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tm
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
June 2007
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT540, MM74HCT541 Rev. 1.3
MM74HCT540, Inverting Octal 3-STATE Buffer
MM74HCT541, Octal 3-STATE Buffer
Features
■
TTL input compatible
■
Typical propagation delay: 12ns
■
3-STATE outputs for connection to system buses
■
Low quiescent current: 80µA
■
Output current: 6mA (Min.)
General Description
The MM74HCT540 and MM74HCT541 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed operation even when driving large
bus capacitances. These circuits achieve speeds com-
parable to low power Schottky devices, while retaining
the low power consumption of CMOS. Both devices are
TTL input compatible and have a fanout of 15 LS-TTL
equivalent inputs.
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for
LS-TTL devices and can be used to reduce power con-
sumption in existing designs.
The MM74HCT540 is an inverting buffer and the
MM74HCT541 is a non-inverting buffer. The 3-STATE
control gate operates as a two-input NOR such that if
either G1 or G2 are HIGH, all eight outputs are in the
high-impedance state.
In order to enhance PC board layout, the MM74HCT540
and MM74HCT541 offers a pinout having inputs and
outputs on opposite sides of the package. All inputs are
protected from damage due to static discharge by diodes
to V
CC
and ground.
Ordering Information
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
Order Number
Package
Number Package Description
MM74HCT540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HCT541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HCT541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 2
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View, MM74HCT540
Top View, MM74HCT541
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 3
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Note:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5 to +7.0V
V
IN
DC Input Voltage –1.5 to V
CC
+1.5V
V
OUT
DC Output Voltage –0.5 to V
CC
+0.5V
I
IK
, I
OK
Clamp Diode Current ±20mA
I
OUT
DC Output Current, per pin ±35mA
I
CC
DC V
CC
or GND Current, per pin ±70mA
T
STG
Storage Temperature Range –65°C to +150°C
P
D
Power Dissipation
Note 2
S.O. Package only
600mW
500mW
T
L
Lead Temperature (Soldering 10 seconds) 260°C
Symbol Parameter Min. Max. Units
V
CC
Supply Voltage 4.5 5.5 V
V
IN
, V
OUT
DC Input or Output Voltage 0 V
CC
V
T
A
Operating Temperature Range –40 +85 °C
t
r
, t
f
Input Rise and Fall Times 500 ns
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 4
DC Electrical Characteristics
V
CC
=
5V ± 10% (unless otherwise specified)
Note:
3. Measured per input. All other inputs at V
CC
or GND.
Symbol Parameter Conditions
T
A
=
25°C
T
A
=
–40
to 85°C
T
A
=
–55
to 125°C
UnitsTyp. Guaranteed Limits
V
IH
Minimum HIGH
Level Input Voltage
2.0 2.0 2.0 V
V
IL
Maximum LOW
Level Input Voltage
0.8 0.8 0.8 V
V
OH
Minimum HIGH
Level Output
Voltage
V
IN
=
V
IH
or V
IL
:
V
|I
OUT
|
=
20µA V
CC
V
CC
– 0.1 V
CC
– 0.1 V
CC
– 0.1
|I
OUT
|
=
6.0mA, V
CC
=
4.5V 4.2 3.98 3.84 3.7
|I
OUT
|
=
7.2mA, V
CC
=
5.5V 5.2 4.98 4.84 4.7
V
OL
Maximum LOW
Level Voltage
V
IN
=
V
IH
or V
IL
:
V
|I
OUT
|
=
20µA 0 0.1 0.1 0.1
|I
OUT
|
=
6.0mA, V
CC
=
4.5V 0.2 0.26 0.33 0.4
|I
OUT
|
=
7.2mA, V
CC
=
5.5V 0.2 0.26 0.33 0.4
I
IN
Maximum Input
Current
V
IN
=
V
CC
or GND ±0.1 ±1.0 ±1.0 µA
I
OZ
Maximum 3-STATE
Output Leakage
Current
V
OUT
=
V
CC
or GND, G
=
V
IH
±0.5 ±5.0 ±10 µA
I
CC
Maximum
Quiescent Supply
Current
V
IN
=
V
CC
or GND, I
OUT
=
0µA 8.0 80 160 µA
V
IN
=
2.4V or 0.5V
(3)
0.6 1.0 1.3 1.5 mA
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 5
AC Electrical Characteristics
MM74HCT540: V
CC
=
5.0V, t
r
=
t
f
=
6ns, T
A
=
25°C, (unless otherwise specified).
AC Electrical Characteristics
MM74HCT540: V
CC
=
5.0V ±10%, t
r
=
t
f
=
6ns (unless otherwise specified).
Note:
4. C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
2 f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
=
C
PD
V
CC
f + I
CC.
Symbol Parameter Conditions Typ.
Guaranteed
Limits Units
t
PHL
, t
PLH
Maximum Output Propagation Delay C
L = 45pF 12 18 ns
tPZL, tPZH Maximum Output Enable Time CL = 45pF, RL = 1kΩ14 28 ns
tPLZ, tPHZ Maximum Output Disable Time CL = 5pF, RL = 1kΩ13 25 ns
Symbol Parameter Conditions
TA = 25°C
TA = –40
to 85°C
TA = –55
to 125°C
UnitsTyp. Guaranteed Limits
tPHL, tPLH Maximum Output
Propagation Delay
CL = 50pF 12 20 25 30 ns
CL = 150pF 22 30 38 45
tPZH, tPZL Maximum Output Enable
Time
RL = 1kΩCL = 50pF 15 30 38 45 ns
CL = 150pF 20 40 50 60
tPHZ, tPLZ Maximum Output Disable
Time
RL = 1kΩ, CL = 50pF 15 30 38 45 ns
tTHL, tTLH Maximum Output Rise
and Fall Time
CL = 50pF 6 12 15 18 ns
CIN Maximum Input
Capacitance
510 10 10 pF
COUT Maximum Output
Capacitance
15 20 20 20 pF
CPD Power Dissipation
Capacitance(4) (per output) G = VCC 12 pF
G = GND 50
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 6
AC Electrical Characteristics
MM74HCT541: VCC = 5.0V, tr = tf = 6ns, TA = 25°C, (unless otherwise specified).
AC Electrical Characteristics
MM74HCT541: VCC = 5.0V ± 10%, tr = tf = 6ns (unless otherwise specified).
Note:
5. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
Symbol Parameter Conditions Typ.
Guaranteed
Limits Units
tPHL, tPLH Maximum Output Propagation Delay CL = 45pF 13 20 ns
tPZL, tPZH Maximum Output Enable Time CL = 45pF, RL = 1kΩ17 28 ns
tPLZ, tPHZ Maximum Output Disable Time CL = 5pF, RL = 1kΩ15 25 ns
Symbol Parameter Conditions
TA = 25°C
TA = –40
to 85°C
TA = –55
to 125°C
UnitsTyp. Guaranteed Limits
tPHL, tPLH Maximum Output
Propagation Delay
CL = 50pF 14 23 29 34 ns
CL = 150pF 17 33 42 49
tPZH, tPZL Maximum Output
Enable Time
RL = 1kΩCL = 50pF 17 30 38 45 ns
CL = 150pF 22 40 50 60
tPHZ, tPLZ Maximum Output
Disable Time
RL = 1kΩ, CL = 50pF 17 30 38 45 ns
tTHL, tTLH Maximum Output Rise
and Fall Time
CL = 50pF 6 12 15 18 ns
CIN Maximum Input
Capacitance
510 10 10 pF
COUT Maximum Output
Capacitance
15 20 20 20 pF
CPD Power Dissipation
Capacitance(5) (per output) G = VCC 12 pF
G = GND 45
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 7
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 8
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 9
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 10
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 11
Rev. I28
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