Integrated Circuit Systems, Inc. ICS9108 CPU Frequency Generator General Description The AV9108 offers a tiny footprint solution for generating two simultaneous clocks. One clock, the REFCLK, is a fixed output frequency which is the same as the input reference crystal (or clock). The other clock, CLK1, can vary between 2 and 120 MHz, with up to 16 selectable preprogrammed frequencies stored in internal ROM. The 1CS9108 is ideal for use in a 3.3V system. It can generate a 66.66 MHz clock at 3.3V. In addition. the ICS9108 provides Features Runs up to 80 MHz at 3.3V 50/50 typical duty cycle at SV +250ps absolute jitter Generates frequencies from 2 to 140 MHz 2 to 32 MHz input reference frequency Up to 16 frequencies stored internally Patented on-chip Phase Locked Loop with VCO for clock generation asymmetrical wave form witha worst case duty cycle of 45/55. Provides reference clock and synthesized clock The ICS9108 has very tight edge control between the CPUs On-chip Joop filter oSops and 2XCPU clock outputs, with a worst case skew of =. Low power 0.8 CMOS technology , e 8-pin or 14-pin DIP or SOIC package The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A mini- mum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitter-free operation. Standard versions for computer motherboard appli- cations are the AV9108-03, AV9108-05 and the ICS9108-10. Custom masked versions, with customized frequencies and features, are available in 6-8 weeks for a small NRE fee. Block Diagram CTT TTS SS SSS SS eS 1 POWER _ I LOOP I PHASE |__| CHARGE eo OUTPUT cL DOWN ; r DETECTOR pump [] PEG & BUFFER y OPUCLK i Y A ! FREQUENCY STORE/ +2 Po Fso +_> PHASE LOCK LOOP 1 E 31 ___>> CONTROL LOGIC OE ___ tk yu! XVICLK +-> ourpuT|_! y REFCLK or Xo t OSCILLATOR | MUX Pl aurFeR) CPUGLK I _ _ oo _!| C-29ICS9108 Pin Configuration FsSo11 \ 6 REFCLK csi 41 44k so FS2 4 2 13 / REFCLK GND 2 7t VOD FS3 743 12 r VDD X1/ICLK J 3 6 [ CLKI AGND | 4 my Clky GND 75 10 fF OE (CLK1) x2 4 5 - FSt1 PD 46 9 [ OE (REFCLK) AV9108-05/-10 XWICLK 4 7 sf xe 8-Pin DIP, SOIC AV9108-03/-11 K-3, K-6 14-Pin DIP, SOIC K-3, K-6 Pin Descriptions for AV9108-03, AV9108-05 and AV9108-10 PIN NUMBER PIN -05/-10/-13 | 03 NAME TYPE DESCRIPTION 1 | 14__|FSO Input Frequency Select 0 for CLK1 (-03 has pull-up). 5 L FS1 Input Frequency Select 1 for CLK1 (-03 has pull-up). 2 FS2 Input Frequency Select 2 for CLK1 (-03 has pull-up). 3 FS3 Input Frequency Select 3 for CLK1 (-03 has pull-up). 4 AGND - Analog GROUND. 2 5 GMD - Digital GROUND. | 6 PD Input POWER-DOWN. Shuts off chip when low. Internal pull-up. 3 7 XIACLK Input CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 14.318 MHz | | system clock. ) 4 T 3 [x2 Output CRYSTAL OUTPUT (No Connect when clock used.). [ 9 OE(REFCLK) _Input OUTPUT ENABLE. Tristates REFCLK when low. Pull-up. _ 10 [OE(CLK1) Input OUTPUT ENABLE. Tristates CLK1 when low. Pull-up. 6 LL CLK! Output CLOCK! Output (see decoding tables). 7 12 VDD : Digital power supply (+3V DC). 8 [3 'REPCLK Output |REFERENCE CLOCK output. Produces a buffered version of the input clock or . crystal frequency (typically 14.318 MHz). C-30ICS9108 Actual Frequencies Decoding Table for AV9108-11 (in MHz) Decoding Table for AV9108-05, 14.318 input F83 | Fs2 | FSi | FSO CLKI J 0, 9 | o | o 16.00 MHz | FS! FSO CLK1 0 | 0 | 0 l 33.39 MHz | 0 0 40.01 MHz 0 | o 1 | 0 50.11 MHz 0 1 50.11 MHz 1 0 I l 80.0] MHz 1 0 66.61 MHz 0 i | o | 0 66.58 MHz | 1 | 1 80.01 MHz 0 1 0 1 100.23 MHz 0 l l 0 60.00 MHz Decoding Table for AV9108-03, 14.318 input yi oa al 4.01 MHz 1 0} 0 I 20.05 MHz FS3 Fs2 ] FSI FSO CLK1 F soe te 0 0 0 0 16.00 MHz 1 | 0 1 I 39.99 Me 0 |! Oo | Oo | L | 39.99 MHz 1 1 0 0! 33.25 MHz | 0 9 1 0 | 50.11 MHz 1 1 0 l 50.11 MHz 1 0 1 1 80.01 MHz 1 I t | oO 30.00 MHz 0 l 0 0 66.58 MHz 1 1 1 | 1 4.01 MHz 0 1 0 1 100.23 MHz 0 1 1 0 8.02 MHz 0 1 1 1 4.01 MHz I 0 0 0 8.02 MHz i 0 0 l 20.00 MHz I 0 1 0 25.06 MHz 1 0 I I 40.01 MHz 1 1 0 0 33.29 MHz 1 1 0 1 50.11 MHz 1 1 1 0 4.01 MHz 1 1 1 I 2.05 MHz Decoding Table for AV9108-10, 14.318 input FS1 FSO CLK} 0 0 25.057 MHz 0 1 33.289 MHz 1 0 40.006 MHz 1 I [50.113 MHz Note: The dash number following ICS9108 must be included when ordering product since it specifies the frequency decoding table being ordered. Decoding options can be created by a simple metal mask change. C-31ICS9108 Frequency Accuracy and Calculation The accuracy of the frequencies produced by the ICS9108 depends on the input frequency and the desired actual output frequency. The formula for calculating the exact frequency is as follows: A Output Frequency = Input Frequency x B where A=2, 3,4... 128, and B=2, 3,4... 32. For example, to calculate the actual output frequency for a video monitor expecting a 44.900 MHz clock and using a 14.318 MHz input clock, the closest A/B ratio is 69/22, which gives an output of 44.906 MHz (within 0.02% of the target frequency). Generally, the [CS9108 can produce frequencies within 0.1% of the desired output. Frequency Transitions Allowable input and Output Frequencies The input frequency should be between 2 and 32 MHz and the A/B ratio should not exceed 24. The output should fall in the range of 2-120 MHz. Output Enable The Output Enable feature tristates the specified output clock pins. This places the selected output pins in a high impedance state to allow for system level diagnostic testing. Power-Down If equipped, the power-down shuts off the specified PLL or entire chip to save current. A few milliseconds are required to reach full functioning speed from a power-down state. Akey ICS9108 feature is the ability to provide glitch-free frequency transitions across its output frequency range. The ICS9108 provides smooth transitions between any of the two groups of eight frequencies (when FS3=0 or FS3=1), so that the device will switch glitch-free between 4-100 MHz and 2-50 MHz. C-32ICS9108 Absolute Maximum Ratings AVDD, VDD referenced to GND .............-. 7V Operating temperature under bias ............... 0C to +70C Storage temperature 2.00... 2. ee eee -65C to + 150C Voltage on I/O pins referenced to GND........... GND -0.5V to VDD +0.5V Power dissipation .........0 2.0.00 eee ee eee 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 5V (Operating Vpp = +4.5V to +5.5V; Ta =0C to 70C unless otherwise stated) DC Characteristics PARAMETER SYMBOL | TEST CONDITIONS MIN TYP | MAX UNITS Input Low Voltage VIL - - 0.8 Vv | Input High Voltage Vin 2.0 : - Vv [Input Low Current fit Vin=0V - 6.0 16 LA Input High Current [om [Vin=Vop -2.0 - 2.0 WA Output Low Voltage VoL Io.=10mA : 0.15 0.40 Vv Output High Voltage, Note 1 Vou Ion=-30mA 2.4 3.25 : Vv Output Low Current, Note 1 ToL VoL=0.8V 22.0 35.0 : mA Output High Current, Note | lou VouH=2.0V - -50.0 {| --35.0 mA Supply Current Icc Unload, 50 MHz - 18.0 | 42.0 mA Supply Current Icc Unload, Logic Inputs 000 j - 38.0 100.0 HA (PD low) Supply Current Icc Unload, Logic Inputs 111 - 14.0 40.0 PA |_@D low) | Pull-up Resistor. Note 1 | Row - | 380.0 700.0 k ohms AC Characteristics | Rise Time 0.8 to 2.0V, Note 1 Tr __[15pf load - 060 | 140 ns Fall Time 2.0 to 0.8V, Note 1 Tr LSpf load - 0.40 1.00 ns Rise Time 20% to 80%, Note 1 Tr 15pf toad - 2.0 35 ns Fall Time 80% to 20%, Note | Te Spf load. - 1.0 2.5 | ons Duty Cycle, Note 1 Dr 15pf load @ 1.4V 45.0 50.0 55.0 | % Jitter, One Sigma, Note | Tiis From 20 to 100 MHz - | 50.0 150.0 _| ps Jitter, One Sigma, Note | Tiis From {4 to 16 MHz 100.0 200.0 ps Jiter, One Sigma, Note | Tiis |From (4 to Below | 0.2 1.0 Go Jitter. Absolute, Note I Tian __|From 20 to 100 MHz -250.0 250.0 ps Jitter, Absolute, Note 1 Tiab From 14 to 16 MHz -500.0 500.0 ps [Jiter, Absolute, Note | Tia __|From 14 to Below _[ 1.0 3.0 Gs : Input Frequency, Note | Fi | 11.0 14.3 19.0 MHz Output Frequency Fo | 2.0 - 120.0 MHz Power-up Time, Note | Tpu - 7.58 18.0 i ms Transition Time, Note I Th [8 to 66.6 MHz - | 66 13.0 | ms Note I: Parameter is guaranteed by design and characterization. Not 100% tested in production. C-33ICS9108 Electrical Characteristics at 3.3V (Operating Vpp = +3.0V to +3.7V; Ta =0C to 70C unless otherwise stated) DC Characteristics PARAMETER | SYMBOL | TESTCONDITIONS | MIN | TYP MAX UNITS Input Low Voltage a - | - 0.20Vpp vl Input High Voltage Vin | opp _! - - Vv Input Low Current In Vin=0V - 2.5 7.0 | pA Input High Current lw Vin=Vpp -2.0 - 2.0 HA Qutput Low Voltage VoL Io .=6mA : 0.15 O11 Vv. Qutput High Voltage Vou _|Ton=-5mA 0.85 0.92 : Vv Output Low Current lo. __|Vor=0.2Vpp | 15.0 22.0 - mA Output High Current lou VoL=0.7Vpp ot -17.0 -10.0 mA Supply Current Icc Unloaded, 50 MHz - 22.0 40.0 mA | Supply Current Icc Unload, Logic Inputs 000 - 13.0 40.0 HA (PD low) Supply Current Iec 'Unload, Logic Inputs 111 - | 4.0 12.0 HA (PD low a i _ | Pull-up Resistor Row - | 550.0 |; 900.0 k ohms AC Characteristics . , Rise Time 20% to 80%, Notel | T, _|15pfload - 22 | 3s ns Fall Time 80% to20% sss) = Te ~_d'A'Spffloadd | 12 2.5 ns Duty Cycle De ___[I5pfload@ 50% |. [0 | as 46.0 60.0 % Jitter, One Sigma Tiis | From 25 to 85 sMHz | 50.0 150.0 ps Jitter, One Sigma Tis [From 14 to 20MHz | __100.0 200.0. | ps. Jitter, One Sigma Tis __|FromidtoBelow | sj 4 10. | 4% Jitter, Absolute Tiab From 25 to 85 MHz 250.0 ee 250.0 ps Jitter, Absolute Tiab From 14 to 20 MHz -500.0 500.0 | ps | Jitter, Absolute __ | _ Tiab From 14 to Below 1.0 3.0 %_ | Input Frequency Fi (3.3 14.3 15.3 MHz | Output Frequency Fo ee 2.0 - $0.0 MHz Power-up Time, Note | Tpu - 7.58 18.0 ms Transition Time, Note 1 Tr 8 to 66.6 MHz > 6.0 13.0 ms Parameter is guaranteed by design and characterization. Ordering Information 1CS9108-05CN8, 1CS9108-05CS8; 1CS9108-10CN8, ICS91808-10CS8; ICS9108-03CN14, ICS9108-03CS14; ICS9108-110N14, ICS9108-11CS14 Example: XXX XXXX -XX M X#W Lead Count & Package Width Lead Count=1, 2 or 3 digits We=.3 SOIC or .6 DIP: None=Standard Width Package Type N=DIP (Plastic); S=SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS. AV=Standard Device; GSP=Genlock Device C-34