LC2MOS Quad 8-Bit DAC
with Separate Reference Inputs
AD7225
Rev. C
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FEATURES
Four 8-bit DACs with output amplifiers
Separate reference input for each DAC
Microprocessor compatible with double-buffered inputs
Simultaneous update of all 4 outputs
Operates with single or dual supplies
Extended temperature range operation
No user trims required
Skinny 24-lead PDIP, CERDIP, SOIC, and SSOP packages
28-lead PLCC package
FUNCTIONAL BLOCK DIAGRAM
V
REF
A
V
REF
B
V
REF
C
V
REF
D
V
DD
LDAC V
SS
AGND DGND
INPUT
LATCH A DAC
LATCH A V
OUT
A
DAC A A
INPUT
LATCH B DAC
LATCH B V
OUT
B
DAC B B
INPUT
LATCH C DAC
LATCH C V
OUT
C
DAC C C
INPUT
LATCH D
CONTROL
LOGIC
DAC
LATCH D V
OUT
D
DAC D D
DATA BUS
DB7
DATA
(8-BIT)
DB0
WR
A1
A2
AD7225
00986-001
Figure 1.
GENERAL DESCRIPTION
The AD7225 contains four 8-bit voltage output digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. Each DAC has a separate
reference input terminal. No external trims are required to
achieve full specified performance for the part.
The double-buffered interface logic consists of two 8-bit
registers per channel—an input register and a DAC register.
Control Input A0 and Control Input A1 determine which input
register is loaded when WR goes low. Only the data held in the
DAC registers determines the analog outputs of the converters.
The double-buffering allows simultaneous update of all four
outputs under control of LDAC. All logic inputs are TTL and
CMOS (5 V) level compatible, and the control logic is speed
compatible with most 8-bit microprocessors.
Specified performance is guaranteed for input reference
voltages from 2 V to 12.5 V when using dual supplies. The part
is also specified for single-supply operation using a reference of
10 V. Each output buffer amplifier is capable of developing 10 V
across a 2 kΩ load.
The AD7225 is fabricated on an all ion-implanted, high speed,
linear-compatible CMOS (LC2MOS) process, which is
specifically developed to integrate high speed digital logic
circuits and precision analog circuitry on the same chip.
PRODUCT HIGHLIGHTS
1. DACs and Amplifiers on CMOS Chip.
The single-chip design of four 8-bit DACs and amplifiers
allows a dramatic reduction in board space requirements
and offers increased reliability in systems using multiple
converters. Its pinout is aimed at optimizing board layout
with all analog inputs and outputs at one end of the
package and all digital inputs at the other.
2. Single- or Dual-Supply Operation.
The voltage-mode configuration of the AD7225 allows
single-supply operation. The part can also be operated with
dual supplies, giving enhanced performance for some
parameters.
3. Versatile Interface Logic.
The AD7225 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. The double-buffered
interface allows simultaneous update of the four outputs.
4. Separate Reference Input for Each DAC.
The AD7225 offers great flexibility in dealing with input
signals, with a separate reference input provided for each
DAC and each reference having variable input voltage
capability.
AD7225
Rev. C | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Terminology ...................................................................................... 8
Circuit Information .......................................................................... 9
Digital-to-Analog Section ........................................................... 9
Op Amp Section ........................................................................... 9
Digital Inputs Section ...................................................................9
Interface Logic Information .......................................................... 10
Ground Management and Layout ................................................ 11
Specification Ranges ...................................................................... 12
Unipolar Output Operation .......................................................... 13
Bipolar Output Operation ............................................................. 14
AGND Bias ...................................................................................... 15
AC Reference Signal ....................................................................... 16
Applications Information .............................................................. 17
Programmable Transversal Filter ............................................. 17
Digital Word Multiplication ..................................................... 18
Microprocesser Interface ............................................................... 19
VSS Generation ................................................................................ 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 23
REVISION HISTORY
3/10—Rev. B to Rev. C
Updated Format .................................................................. Universal
Deleted 28-Terminal Leadless Ceramic Chip Carrier
Package ................................................................................. Universal
Added 24-Lead SSOP Package .......................................... Universal
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Pin Configurations and Function Descriptions
Section ................................................................................................ 6
Added Table 4; Renumbered Sequentially .................................... 6
Changes to Specification Ranges section .................................... 12
Changes to Programmable Transversal Filter Section and
Figure 21 .......................................................................................... 17
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
AD7225
Rev. C | Page 3 of 24
SPECIFICATIONS
VDD = 11.4 V to 16.5 V, VSS = −5 V ± 10%; AGND = DGND = 0 V; VREFx = +2 V to (VDD − 4 V)1
Parameter
, unless otherwise noted. All specifications
TMIN to TMAX, unless otherwise noted.
Table 1.
K, B
Versions2
L, C
Versions2 Unit Conditions/Comments
STATIC PERFORMANCE
Resolution 8 8 Bits
Total Unadjusted Error ±2 ±1 LSB max VDD = 15 V ± 5%, VREF = 10 V
Relative Accuracy ±1 ±1/2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic
Full-Scale Error ±1 ±1/2 LSB max
Full-Scale Temperature Coefficient ±5 ±5 ppm/°C typ VDD = 14 V to 16.5 V, VREF = 10 V
Zero Code Error ±30 ±20 mV max
Zero Code Error Temperature Coefficient ±30 ±30 μV/°C typ
REFERENCE INPUT
Voltage Range 2 to (VDD − 4) 2 to (VDD − 4) V min to V max
Input Resistance 11 11 kΩ min
Input Capacitance3 50 50 pF max Occurs when each DAC is loaded with all 1s
Channel-to-Channel Isolation3 60 60 dB min VREF = 10 V p-p sine wave at 10 kHz
AC Feedthrough3 −70 −70 dB max VREF = 10 V p-p sine wave at 10 kHz
DIGITAL INPUTS
Input High Voltage, VINH 2.4 2.4 V min
Input Low Voltage, VINL 0.8 0.8 V max
Input Leakage Current ±1 ±1 μA max VIN = 0 V or VDD
Input Capacitance3 8 8 pF max
Input Coding Binary Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3 2.5 2.5 V/μs min
Voltage Output Settling Time3 4 4 μs max VREF = 10 V; settling time to ±½ LSB
Digital Feedthrough3 50 50 nV sec typ Code transition all 0s to all 1s
Digital Crosstalk3 50 50 nV sec typ Code transition all 0s to all 1s
Minimum Load Resistance 2 2 kΩ min VOUT = 10 V
POWER SUPPLIES
VDD Range 11.4/16.5 11.4/16.5 V min to V max For specified performance
IDD 10 10 mA max Outputs unloaded; VIN = VINL or VINH
ISS 9 9 mA max Outputs unloaded; VIN = VINL or VINH
SWITCHING CHARACTERISTICS3, 4
t1 50 50 ns min Write pulse width
t2 0 0 ns min Address to write setup time
t3 0 0 ns min Address to write hold time
t4 50 50 ns min Data valid to write setup time
t5 0 0 ns min Data valid to write hold time
t6 50 50 ns min Load DAC pulse width
1 Maximum possible reference voltage.
2 Temperature range is as follows for all versions: −40°C to +85°C.
3 Sample tested at 25°C to ensure compliance.
4 Switching characteristics apply for single-supply and dual-supply operation.
AD7225
Rev. C | Page 4 of 24
SINGLE SUPPLY
VDD = 15 V ± 5%; VSS = AGND = DGND = 0 V; VREFx = 10 V, unless otherwise noted. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter K, B Versions1 L, C Versions1 Unit Conditions/Comments
STATIC PERFORMANCE
Resolution 8 8 Bits
Total Unadjusted Error2 ±2 ±1 LSB max
Differential Nonlinearity2 ±1 ±1 LSB max Guaranteed monotonic
REFERENCE INPUT
Voltage Range 2 to (VDD − 4) 2 to (VDD − 4) V min to V max
Input Resistance 11 11 kΩ min
Input Capacitance3 50 50 pF max Occurs when each DAC is loaded with all 1s
Channel-to-Channel Isolation2, 3 60 60 dB min VREF = 10 V p-p sine wave at 10 kHz
AC Feedthrough2, 3 −70 −70 dB max VREF = 10 V p-p sine wave at 10 kHz
DIGITAL INPUTS
Input High Voltage, VINH 2.4 2.4 V min
Input Low Voltage, VINL 0.8 0.8 V max
Input Leakage Current ±1 ±1 μA max VIN = 0 V or VDD
Input Capacitance3 8 8 pF max
Input Coding Binary Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3 2 2 V/μs min
Voltage Output Settling Time3 4 4 μs max
Digital Feedthrough2, 3 10 10 nV sec typ Code transition all 0s to all 1s
Digital Crosstalk2, 3 10 10 nV sec typ Code transition all 0s to all 1s
Minimum Load Resistance 2 2 kΩ min VOUT = 10 V
POWER SUPPLIES
VDD Range 14.25/15.75 14.25/15.75 V min to V max For specified performance
IDD 10 10 mA max Outputs unloaded; VIN = VINL or VINH
SWITCHING CHARACTERISTICS3
t1 50 50 ns min Write pulse width
t2 0 0 ns min Address to write setup time
t3 0 0 ns min Address to write hold time
t4 50 50 ns min Data valid to write setup time
t5 0 0 ns min Data valid to write hold time
t6 50 50 ns min Load DAC pulse width
1 Temperature range is as follows for all versions: −40°C to +85°C.
2 Sample tested at 25°C to ensure compliance.
3 Switching characteristics apply for single-supply and dual-supply operation.
AD7225
Rev. C | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to AGND −0.3 V, +17 V
VDD to DGND −0.3 V, +17 V
VDD to VSS −0.3 V, +24 V
AGND to DGND −0.3 V, VDD
Digital Input Voltage to DGND −0.3 V, VDD + 0.3 V
VREFx to AGND −0.3 V, VDD + 0.3 V
VOUTx to AGND1 VSS, VDD
Power Dissipation (Any Package) to 75°C 500 mW
Derates Above 75°C by 2.0 mW/°C
Operating Temperature
Commercial (K, L Versions) −40°C to +85°C
Industrial (B, C Versions) −40°C to +85°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
1 Outputs can be shorted to any voltage in the range VSS to VDD provided that
the power dissipation of the package is not exceeded. Typical short-circuit
current for a short to AGND or VSS is 50 mA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7225
Rev. C | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUTB1
VOUTA2
VSS 3
VREFB4
VOUTC
24
VOUTD
23
VDD
22
VREFC
21
VREFA5VREFD
20
AGND 6A0
19
DGND 7A1
18
LDAC 8WR
17
DB7 9DB0
16
DB6 10 DB1
15
DB5 11 DB2
14
DB4 12 DB3
13
AD7225
TOP VI EW
(No t t o Scal e)
00986-002
128 27 26234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CONNECT
V
REF
B
V
REF
A
AGND
NC
DGND
LDAC
DB7
V
REF
C
V
REF
D
A0
NC
A1
WR
DB0
V
SS
V
OUT
A
V
OUT
B
NC
V
OUT
C
V
OUT
D
V
DD
DB6
DB5
DB4
NC
DB3
DB2
DB1
PIN 1
INDENTFIER
12 13 14 15 16 17 18
AD7225
TOP VI EW
(No t t o Scal e)
00986-003
Figure 2. PDIP, SOIC, CERDIP, and SSOP Figure 3. PLCC
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
PDIP, SOIC,
CERDIP, SSOP PLCC
1 2 VOUTB DAC Channel B Voltage Output.
2 3 VOUTA DAC Channel A Voltage Output.
3 4 VSS Negative Power Supply Connection.
4 5 VREFB Reference Voltage Connection for DAC Channel B.
5 6 VREFA Reference Voltage Connection for DAC Channel A.
6 7 AGND Analog Ground Reference Connection.
7 9 DGND Digital Ground Reference Connection.
8 10 LDAC Active Low Load DAC Signal. DAC register data is latched on the rising edge of LDAC.
9 11 DB7 Data Bit 7 (Most Significant Data Bit).
10 12 DB6 Data Bit 6.
11 13 DB5 Data Bit 5.
12 14 DB4 Data Bit 4.
13 16 DB3 Data Bit 3.
14 17 DB2 Data Bit 2.
15 18 DB1 Data Bit 1.
16 19 DB0 Data Bit 0 (Least Significant Data Bit).
17 20 WR Active Low Data Write Signal. Input register data is latched on the rising edge of WR.
18 21 A1 DAC Address Select Pin.
19 23 A0 DAC Address Select Pin.
20 24 VREFD Reference Voltage Connection for DAC Channel D.
21 25 VREFC Reference Voltage Connection for DAC Channel C.
22 26 VDD Positive Power Supply Connection.
23 27 VOUTD DAC Channel D Voltage Output.
24 28 VOUTC DAC Channel C Voltage Output.
N/A 1, 8, 15, 22 NC No Internal Connection.
AD7225
Rev. C | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 15 V, VSS = −5 V, unless otherwise noted.
1.0
–1.0
–0.5
0
0.5
032 64 96 128 160 192 224
TOTAL UNADJUSTED ERROR (LSB)
INP UT CODE
V
REF
x = 10V
00986-004
Figure 4. Channel-to-Channel Matching
Figure 5. Relative Accuracy vs. VREF
Figure 6. Differential Nonlinearity vs. VREF
8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
–60 –40 –20 020 40 60 80 100 120 140
PO WER SUP P LY CURRE NT (mA)
TEMPERATURE (°C)
IDD
ISS
00986-007
Figure 7. Power Supply Current vs. Temperature
5
–5
–4
–3
–2
–1
0
1
2
3
4
–60 –40 –20 020 40 60 80 100 120 140
ZE RO CODE E RROR (mV )
TEMPERATURE (°C)
VOUTA
VOUTB
VOUTC
VOUTD
00986-008
Figure 8. Zero Code Error vs. Temperature
100
90
10
0%
1ms/DIV
300µV
00986-009
Figure 9. Broadband Noise
AD7225
Rev. C | Page 8 of 24
TERMINOLOGY
Total Unadjusted Error
Tota l unadjusted error is a comprehensive specification that
includes full-scale error, relative accuracy, and zero code error.
Maximum output voltage is VREF − 1 LSB (ideal), where 1 LSB
(ideal) is VREF/256. The LSB size varies over the VREF range.
Therefore, the zero code error, relative to the LSB size, increases
as VREF decreases. Accordingly, the total unadjusted error, which
includes the zero code error, also varies in terms of LSB over the
VREF range. As a result, total unadjusted error is specified for a
fixed reference voltage of 10 V.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
allowing for zero code error and full-scale error and is normally
expressed in LSB or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Digital Feedthrough
Digital feedthrough is the glitch impulse transferred to the
output of the DAC due to a change in its digital input code. It is
specified in nV sec and is measured at VREF = 0 V.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one converter (not addressed) due to a change in the digital
input code to another addressed converter. It is specified in nV
sec and is measured at VREF = 0 V.
AC Feedthrough
AC feedthrough is the proportion of reference input signal that
appears at the output of a converter when that DAC is loaded
with all 0s.
Channel-to-Channel Isolation
Channel-to-channel isolation is the proportion of input signal
from the reference of one DAC (loaded with all 1s) that appears
at the output of one of the other three DACs (loaded with all 0s)
The figure given is the worst case for the three other outputs
and is expressed as a ratio in dB.
Full-Scale Error
Full-scale error is defined as
FSE = Measured Value − Zero Code Error − Ideal Value
AD7225
Rev. C | Page 9 of 24
CIRCUIT INFORMATION
DIGITAL-TO-ANALOG SECTION
The AD7225 contains four identical, 8-bit voltage mode digital-
to-analog converters. Each DAC has a separate reference input.
The output voltages from the converters have the same polarity
as the reference voltages, allowing single-supply operation. A novel
DAC switch pair arrangement on the AD7225 allows a refer-
ence voltage range from 2 V to 12.5 V on each reference input.
Each DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS, single-pole, double-throw switches. The
simplified circuit diagram for Channel A is shown in Figure 10.
Note that AGND is common to all four DACs.
V
OUT
A
2R
DB7
2R
DB6
2R
DB5
2R
2R
DB0
RR R
V
REF
A
AGND SHOW N FO R ALL 1s ON DAC
00986-010
Figure 10. Digital-to-Analog Simplified Circuit Diagram
The input impedance at any of the reference inputs is code
dependent and can vary from 11 kΩ minimum to infinity. The
lowest input impedance at any reference input occurs when that
DAC is loaded with Digital Code 01010101. Therefore, it is
important that the reference presents a low output impedance
under changing load conditions. The nodal capacitance at the
reference terminals is also code dependent and typically varies
from 15 pF to 35 pF.
Each VOUTx pin can be considered a digitally programmable
voltage source with an output voltage of
VOUTX = DX × VREFX
where DX is a fractional representation of the digital input code
and can vary from 0 to 255/256.
The output impedance is that of the output buffer amplifier.
OP AMP SECTION
Each voltage mode DAC output is buffered by a unity gain
noninverting CMOS amplifier. This buffer amplifier is capable
of developing 10 V across a 2 kΩ load and can drive capacitive
loads of 3300 pF.
The AD7225 can be operated single or dual supply; operating
with dual supplies results in enhanced performance in some
parameters that cannot be achieved with single-supply opera-
tion. In single-supply operation (VSS = 0 V = AGND), the sink
capability of the amplifier, which is normally 400 μA, is reduced
as the output voltage nears AGND. The full sink capability of
400 μA is maintained over the full output voltage range by tying
VSS to −5 V. This is shown in Figure 11.
Settling time for negative-going output signals approaching
AGND is similarly affected by VSS. Negative-going settling time
for single-supply operation is longer than for dual-supply opera-
tion. Positive-going settling time is not affected by VSS.
500
400
300
200
100
00108642
ISINK (µA)
VOUT (V)
VSS = –5V
VSS = 0V
VDD = + 15V
TA = 25° C
00986-011
Figure 11. Variation of ISINK with VOUT
Additionally, the negative VSS gives more headroom to the
output amplifiers, which results in better zero code perfor-
mance and improved slew rate at the output than can be
obtained in the single-supply mode.
DIGITAL INPUTS SECTION
The AD7225 digital inputs are compatible with either TTL or
5 V CMOS levels. All logic inputs are static protected MOS
gates with typical input currents of less than 1 nA. Internal
input protection is achieved by an on-chip distributed diode
between DGND and each MOS gate. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practi-
cally possible.
AD7225
Rev. C | Page 10 of 24
INTERFACE LOGIC INFORMATION
The AD7225 contains two registers per DAC, an input register
and a DAC register. The A0 and A1 address lines select which
input register accepts data from the input port. When the WR
signal is low, the input latches of the selected DAC are transpa-
rent. The data is latched into the addressed input register on the
rising edge of Table 5
WR. shows the addressing for the input
registers on the AD7225.
Table 5. AD7225 Addressing
A1 A0 Selected Input Register
Low Low DAC A
Low High DAC B
High Low DAC C
High High DAC D
Only the data held in the DAC register determines the analog
output of the converter. The LDAC signal is common to all four
DACs and controls the transfer of information from the input
registers to the DAC registers. Data is latched into all four DAC
registers simultaneously on the rising edge of LDAC. The LDAC
signal is level triggered and therefore the DAC registers can be
made transparent by tying LDAC low (in this case, the outputs
of the converters respond to the data held in their respective
input latches). LDAC is an asynchronous signal and is indepen-
dent of WR. This is useful in many applications. However, in
systems where the asynchronous LDAC can occur during a
write cycle (or vice versa), care must be taken to ensure that
incorrect data is not latched through to the output. If LDAC is
activated prior to the rising edge of WR (or WR occurs during
LDAC), LDAC must stay low for t6 or longer after WR
Table 6. Truth Table
goes high
to ensure correct data is latched through to the output. Table 6
shows the truth table for AD7225 operation. Figure 12 shows
the input control logic for the part; the write cycle timing
diagram is given in Figure 13.
WR LDAC Function
High High No operation. Device not selected.
Low High Input register of selected DAC transparent.
High Input register of selected DAC latched.
High Low All four DAC registers Transparent (that is,
outputs respond to data held in respective
input registers). Input registers are latched.
High
All four DAC registers latched.
Low Low DAC registers and selected input register
transparent output follows input data for
selected channel.
TO INPUT
LATCH A
TO INPUT
LATCH B
TO ALL
DAC LATCHES
TO INPUT
LATCH C
TO INPUT
LATCH D
LDAC
A0
A1
WR
00986-012
Figure 12. Input Control Logic
ADDRESS
DATA IN
LDAC
WR
5V
5V
5V
0V
5V
0V
DATA
VALID
V
INH
V
INL
t2t3
t1
t6
t5
t4
NOTES
1. ALL INP UT SIGNAL RI S E AND FALL T IME S M E AS URE D FROM
10% TO 90% OF 5V.
tR
=
tF
= 20ns OVE R V
DD
RANGE .
2. TIMI NG MEASUREMENT REFERENCE LEVEL I S
3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR,
THEN IT MUST STAY LOW FOR
t6
OR LONGER AFTER WR
GOES HIGH.
V
INH
+ V
INL
2
00986-013
Figure 13. Write Cycle Timing Diagram
AD7225
Rev. C | Page 11 of 24
GROUND MANAGEMENT AND LAYOUT
Because the AD7225 contains four reference inputs that can be
driven from ac sources (see the AC Reference Signal section),
careful layout and grounding is important to minimize analog
crosstalk between the four channels. The dynamic performance
of the four DACs depends on the optimum choice of board
layout. Figure 14 shows the relationship between input fre-
quency and channel-to-channel isolation. Figure 15 shows a
printed circuit board layout that minimizes crosstalk and
feedthrough. The four input signals are screened by AGND.
VREF was limited to between 2 V and 3.24 V to avoid slew rate
limiting effects from the output amplifier during measurements.
–80
–70
–60
–50
–40
–30
20k 50k 100k 200k 500k 1M
ISOLATION (dB)
INP UT FRE QUENCY ( Hz)
V
DD
= +15V
V
SS
= –5V
T
A
= 25° C
V
REF
= 1.24V p-p
00986-014
Figure 14. Channel-to-Channel Isolation
V
OUT
CV
OUT
B
V
OUT
DV
OUT
A
V
DD
V
SS
V
REF
CV
REF
B
V
REF
DV
REF
A
MSB LSB
PI N 1
SYSTEM
GND
DGND
AGND
00986-015
Figure 15. Suggested PCB Layout for AD7225, Component Side (Top View)
AD7225
Rev. C | Page 12 of 24
SPECIFICATION RANGES
For the AD7225 to operate to rated specifications, its input
reference voltage must be at least 4 V below the VDD power
supply voltage. This voltage differential is the overhead voltage
required by the output amplifiers.
The AD7225 is specified to operate over a VDD range from 12 V
± 5% to 15 V ± 10% (that is, from 11.4 V to 16.5 V) with a VSS
of −5 V ± 10%. Operation is also specified for a single 15 V ±
5% VDD supply. Applying a VSS of −5 V results in improved zero-
code error, improved output sink capability with outputs near
AGND, and improved negative-going settling time.
Performance is specified over a wide range of reference voltages
from 2 V to (VDD − 4 V) with dual supplies. This allows a range
of standard reference generators to be used, such as the AD780,
a 2.5 V band gap reference, and the AD584, a precision 10 V
reference. Note that an output voltage range of 0 V to 10 V
requires a nominal 15 V ± 5% power supply voltage.
AD7225
Rev. C | Page 13 of 24
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for each channel of the
AD7225, with the output voltage having the same positive
polarity as VREFx. The AD7225 can be operated single supply
(VSS = AGND) or with positive/negative supplies (see the Op
Amp Section, which outlines the advantages of having negative
VSS). Connections for the unipolar output operation are shown
in Figure 16. The voltage at any of the reference inputs must
never be negative with respect to DGND. Failure to observe this
precaution may cause parasitic transistor action and possible
device destruction. The code table for unipolar output
operation is shown in Table 7.
Note,
( )
( )
== −
256
1
21 8
REFREF VVLSB
V
REF
A V
REF
B V
REF
C V
REF
D V
DD
V
SS
AGND DGND
V
OUT
A
DAC A
V
OUT
B
DAC B
V
OUT
C
DAC C
V
OUT
D
DAC D
DB7
(MSB)
DB0
(LSB)
A1
A2
WR
LDAC
AD7225
00986-016
Figure 16. Unipolar Output Circuit
Table 7. Unipolar Code Table
DAC Latch Contents
Analog Output
MSB LSB
1111 1111
( )
256
255
REF
V+
1000 0001
( )
256
129
REF
V+
1000 0000
( )
2
256
128 REF
REF
V
V+=+
0111 1111
( )
256
127
REF
V+
0000 0001
( )
256
1
REF
V+
0000 0000 0 V
AD7225
Rev. C | Page 14 of 24
BIPOLAR OUTPUT OPERATION
Each of the DACs of the AD7225 can be individually confi-
gured to provide bipolar output operation. This is possible
using one external amplifier and two resistors per channel.
Figure 17 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A (DAC Channel A)
of the AD7225. In this case,
( ) ( )
REFREF
A
OUT V
R
R2
VD
R1
R2
V×
−×
+= 1
1
With R1 = R2
( )
( )
REF
A
OUT VDV
×−=
12
where DA is a fractional representation of the digital word in
Latch A (0 ≤ DA ≤ 255/256).
Mismatch between R1 and R2 causes gain and offset errors and,
therefore, these resistors must match and track over tempera-
ture. The AD7225 can be operated in single supply or from
positive/negative supplies. Table 8 shows the digital code vs.
output voltage relationship for the circuit of Figure 17 with
R1 = R2.
+15V
–15V
V
DD
V
SS
AGND DGND
V
OUT
A
DAC A
AD7225*
V
REF
AR2
V
OUT
R1
V
REF
R1, R2 = 10kΩ ± 0.1%.
*DIGITAL INPUTS OMITTED
FOR CLARITY.
00986-017
Figure 17. Bipolar Output Circuit
Table 8. Bipolar (Offset Binary) Code Table
DAC Latch Contents
Analog Output MSB LSB
1111 1111
( )
128
127
REF
V+
1000 0001
( )
128
1
REF
V+
1000 0000 0 V
0111 1111
( )
128
1
REF
V−
0000 0001
( )
128
127
REF
V−
0000 0000
( )
REFREF VV −=− 1
128
128
AD7225
Rev. C | Page 15 of 24
AGND BIAS
The AD7225 AGND pin can be biased above system ground
(AD7225 DGND) to provide an offset zero analog output
voltage level. Figure 18 shows a circuit configuration to achieve
this for DAC Channel A of the AD7225. The output voltage,
VOUTA, can be expressed as:
VOUTA = VBIAS + DA(VIN)
where DA is a fractional representation of the digital word in
DAC Latch A (0 ≤ DA ≤ 255/256).
VDD
VSS
AGND
VBIAS
VIN
DGND
VOUTA
DAC A
AD7225*
VREFA
*DIGITAL INPUTS OMITTED FOR CLARITY.
00986-018
Figure 18. AGND Bias Circuit
For a given VIN, increasing AGND above system ground reduces
the effective VDD − VREF, which must be at least 4 V to ensure
specified operation. Note that, because the AGND pin is
common to all four DACs, this method biases up the output
voltages of all the DACs in the AD7225. Note that VDD and VSS
of the AD7225 should be referenced to DGND.
AD7225
Rev. C | Page 16 of 24
AC REFERENCE SIGNAL
In some applications, it may be desirable to have ac reference
signals. The AD7225 has multiplying capability within the
upper (VDD − 4 V) and lower (2 V) limits of reference voltage
when operated with dual supplies. Therefore, ac signals need to
be ac-coupled and biased up before being applied to the
reference inputs. Figure 19 shows a sine wave signal applied to
VREFA. For input signal frequencies up to 50 kHz, the output
distortion typically remains less than 0.1%. The typical 3 dB
bandwidth figure for small signal inputs is 800 kHz.
*DIGITAL INPUTS OMITTED FOR CLARITY.
V
DD
V
SS
AGND DGND
V
OUT
A
DAC A
AD7225*
V
REF
A
+15V
+15V
15kΩ
10kΩ
+4V
–4V
REFERENCE
INPUT
00986-019
Figure 19. Applying an AC Signal to the AD7225
AD7225
Rev. C | Page 17 of 24
APPLICATIONS INFORMATION
h
1
1T
X
n
h
2
2T
X
n – 1
h
3
3T
X
n – 2
h
4
4
X
n – 3
FILTER
INPUT
+
y(n)
FILTER
OUTPUT
AD7225
QUAD DAC
+
AD585
SHA
AD7225
QUAD DAC
AD7820
ADC
INPUT
SAMPLES
AM29520
TLC
DELAYED
INPUT
SAMPLES
AD584
REF 10V
V
REF
AM7224
DAC V
OUT
V
REF
V
REF
A
V
OUT
A
h
1
V
REF
A
V
OUT
A
h
2
V
REF
A
V
OUT
A
h
3
V
REF
A
V
OUT
A
h
4
TAP WEIGHTGAIN SET
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
ACCUMULATOR
OUTPUT
FILTER
OUTPUT
00986-020
Figure 20. Programmable Transversal Filter
PROGRAMMABLE TRANSVERSAL FILTER
A discrete time filter can be described by either multiplication
in the frequency domain or by convolution in the time domain:
( ) ( ) ( )
∑
=+−
=ωω=ω N
kknk
nXhyorXHY
11
The convolution sum can be implemented using the special struc-
ture known as the transversal filter (see Figure 21). It consists
of an N-stage delay line with N taps weighted by N coefficients,
the resulting products being accumulated to form the output.
The tap weights or coefficients hk are the nonzero elements of
the impulse response and therefore determine the filter transfer
function. A particular filter frequency response is realized by
setting the coefficients to the appropriate values. This property
leads to the implementation of transversal filters whose fre-
quency response is programmable.
h
1
1T
X
n
h
2
2T
X
n – 1
h
3
3
X
n – 2
h
N
N
X
n – N + 1
h
N – 1
N –1 T
X
n – N
FILTER
INPUT
+
X
n – k + 1
h
k
y
n
= N
k = 1
FILTER
OUTPUT
00986-021
Figure 21. Transversal Filter
A four-tap programmable transversal filter can be implemented
using the AD7225 (see Figure 20). The input signal is first sampled
and converted to allow the tapped delay line function to be
provided by the AM29520. The multiplication of delayed input
samples by fixed, programmable up weights is accomplished by
the AD7225, the four coefficients or reference inputs being set
by the digital codes stored in the AD7226. The resultant products
are accumulated to yield the convolution sum output sample,
which is held by the AD585.
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
00.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
GAIN (d B)
NORM ALIZED FREQ UE NCY ( f /fS)
h1 = 0.117
h2 = 0.417
h3 = 0.417
h4 = 0.417
00986-022
Figure 22. Predicted (Theoretical) Response
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
00.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
GAIN (d B)
FREQUENCY (f/fS)
h1 (DAC A) = 00011110
h2 (DAC B) = 01101011
h3 (DAC C) = 01101011
h4 (DAC D) = 00011110
00986-023
Figure 23. Actual Response
Low-pass, band-pass, and high-pass filters can be synthesized
using this arrangement. The particular up weights needed for
any desired transfer function can be obtained using the standard
Remez exchange algorithm. Figure 22 shows the theoretical
low-pass frequency response produced by a four-tap transversal
filter with the coefficients indicated. Although the theoretical
prediction does not take into account the quantization of the
input samples and the truncation of the coefficients, neverthe-
AD7225
Rev. C | Page 18 of 24
less, there exists a good correlation with the actual performance
of the transversal filter (see Figure 23).
DIGITAL WORD MULTIPLICATION
Because each DAC of the AD7225 has a separate reference input,
the output of one DAC can be used as the reference input for
another. This means that multiplication of digital words can be
performed (with the result given in analog form). For example,
if the output from DAC A is applied to VREFB, then the output
from DAC B, VOUTB, can be expressed as:
VOUTB = DA × DB × VREFA
where DA and DB are the fractional representations of the digital
words in DAC Latch A and DAC Latch B, respectively.
If DA = DB = D, the result is D2 × VREFA.
In this manner, the four DACs can be used on their own or in
conjunction with an external summing amplifier to generate
complex waveforms. Figure 24 shows one such application.
In this case, the output waveform, Y, is represented by
Y = −(x4 + 2x3 + 3x2 + 2x + 4) × VIN
where x is the digital code that is applied to all four DAC
latches.
Figure 24. Complex Waveform Generation
AD7225
Rev. C | Page 19 of 24
MICROPROCESSER INTERFACE
*LINEAR CI RCUIT RY OMI TT E D FOR CLARI TY.
ADDRESS
DECODE
LATCH
EN
AD7225*
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
ADDRESS DATA BUS
8085A/
8088
A15
A8
ALE
AD0
AD7
WR
00986-025
*LINEAR CI RCUIT RY OMI TT E D FOR CLARI TY.
Z-80
A15
A8
D0
D7
AD7225*
WR
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
EN
MREQ
00986-026
Figure 25. AD7225-to-8085A/8088 Interface, Double-Buffered Mode Figure 26. AD7225-to-Z-80 Interface, Double-Buffered Mode
*LINEAR CI RCUIT RY OMI TT E D FOR CLARI TY.
6809/
6502
A15
A0
E OR Φ2
D0
D7
AD7225*
R/W
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
EN
00986-027
*LINEAR CI RCUIT RY OMI TT E D FOR CLARI TY.
68008
A23
A1
D0
D7
AD7225*
A0
A1
DB7
DB0
LDAC
WR
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
EN
AS
R/W
DTACK
00986-028
Figure 27. AD7225-to-6809/6502 Interface, Single-Buffered Mode Figure 28. AD7225-to-68008 Interface, Single-Buffered Mode
AD7225
Rev. C | Page 20 of 24
VSS GENERATION
Operating the AD7225 from dual supplies results in enhanced
performance over single-supply operation on a number of
parameters as previously outlined. Some applications may
require this enhanced performance, but may only have a single
power supply rail available. The circuit of Figure 29 shows a
method of generating a negative voltage using one CD4049,
operated from a VDD of 15 V. Two inverters of the hex inverter
chip are used as an oscillator. The other four inverters are in
parallel and used as buffers for higher output current. The
square wave output is level translated to a negative-going signal,
then rectified and filtered. The circuit configuration shown
provides an output voltage of −5.1 V for current loadings in the
range of 0.5 mA to 9 mA. This satisfies the AD7225 ISS require-
ment over the commercial operating temperature range.
1/6
CD4049AE 1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
510kΩ5.1kΩ
+
0.02µF 47µF
47µF 5V1
–V
OUT
+
+
1N4001 1N4001
510Ω
00986-029
Figure 29. VSS Generation Circuit
AD7225
Rev. C | Page 21 of 24
OUTLINE DIMENSIONS
CONT ROLLING DIMENSI ONS ARE I N INCHES; MILLIME T E R DIME NS IONS
(IN PARENTHES ES) ARE ROUNDE D-OFF I NCH EQUIVALENTS FOR
REFE RE NCE ONLY AND ARE NOT APPROP RIATE FO R US E IN DES IGN.
CORNER LEADS MAY BE CO NFIGURED AS W HOLE OR HAL F LEADS .
COM PLI ANT TO JE DE C S TANDARDS MS-001
071006-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2. 92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
24
112
13
0.100 ( 2.54)
BSC
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
0.210 ( 5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 ( 0 .13)
MIN
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.060 ( 1 .52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 30. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
CONT ROLLING DIMENSI ONS ARE IN I NCHES ; M IL LIM E TER DI M E NS IONS
(IN P ARENTHES ES ) ARE ROUNDED-OFF I NCH EQUIV ALENT S FO R
REFERENCE O NLY AND ARE NO T APP ROPRIATE FOR USE IN DES IGN.
24
112
13
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.09 8 ( 2.49)
MAX
15°
0°
0.320 ( 8 .13)
0.290 ( 7 .37)
0.015 ( 0.38)
0.008 ( 0.20)
SEATING
PLANE
0.200 (5.08)
MAX 1.280 (32.51) M AX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 ( 0.58)
0.014 ( 0.36)
0.100
(2.54)
BSC
0.070 ( 1.78)
0.030 ( 0.76)
0.060 (1.52)
0.015 (0.38)
PIN 1
100808-A
Figure 31. 24-Lead Ceramic Dual In-Line Package [CERDIP]
Narrow Body
(Q-24-1)
Dimensions shown in inches and (millimeters)
AD7225
Rev. C | Page 22 of 24
COM P LIANT T O JEDEC S TANDARDS M O-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(I N P ARE NTHESE S ) ARE ROUNDED- OFF I NCH E QUIV ALENTS FOR
REF E RE NCE ONLY AND ARE NOT AP P ROPRI ATE FOR US E IN DES IG N.
4
526
25
1112 19
18
TOP VIEW
(PINS DOWN)
SQ
0.456 (11.582)
0.450 (11.430)
0.050
(1.27)
BSC
0.048 (1.22)
0.042 (1.07)
0.048 (1. 22)
0.042 (1. 07)
0.495 (12.57)
0.485 (12.32)SQ
0.021 (0.53)
0.013 (0.33) 0.430 (10.92)
0.390 (9.91)
0.032 ( 0.81)
0.026 ( 0.66)
0.120 (3. 04)
0.090 (2. 29)
0.056 (1.42)
0.042 (1.07) 0.020 ( 0. 51)
MIN
0.180 (4.57)
0.165 (4.19)
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
042508-A
Figure 32. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
⋅45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
24 13
12
1
1.27 (0.0500)
BSC
06-07-2006-A
Figure 33. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
AD7225
Rev. C | Page 23 of 24
COMPLIANT TO JEDE C S TANDARDS MO-150- AG
060106-A
24 13
12
1
8.50
8.20
7.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 M IN
0.65 BS C
2.00 M AX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 34. 24-Lead Shrink Small Outline Package [SSOP]
(RS-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Total Unadjusted Error Package Description Package Option
AD7225BQ −40°C to +85°C ±2 LSB 24-Lead CERDIP Q-24-1
AD7225BRS −40°C to +85°C ±2 LSB 24-Lead SSOP RS-24
AD7225BRS-REEL −40°C to +85°C ±2 LSB 24-Lead SSOP RS-24
AD7225BRSZ −40°C to +85°C ±2 LSB 24-Lead SSOP RS-24
AD7225CRS −40°C to +85°C ±1 LSB 24-Lead SSOP RS-24
AD7225CRS-REEL −40°C to +85°C ±1 LSB 24-Lead SSOP RS-24
AD7225CRSZ −40°C to +85°C ±1 LSB 24-Lead SSOP RS-24
AD7225CRSZ-RL −40°C to +85°C ±1 LSB 24-Lead SSOP RS-24
AD7225KN −40°C to +85°C ±2 LSB 24-Lead PDIP N-24-1
AD7225KNZ −40°C to +85°C ±2 LSB 24-Lead PDIP N-24-1
AD7225KP −40°C to +85°C ±2 LSB 28-Lead PLCC P-28
AD7225KP-REEL −40°C to +85°C ±2 LSB 28-Lead PLCC P-28
AD7225KPZ −40°C to +85°C ±2 LSB 28-Lead PLCC P-28
AD7225KR −40°C to +85°C ±2 LSB 24-Lead SOIC_W RW-24
AD7225KR-REEL −40°C to +85°C ±2 LSB 24-Lead SOIC_W RW-24
AD7225KRZ −40°C to +85°C ±2 LSB 24-Lead SOIC_W RW-24
AD7225KRZ-REEL −40°C to +85°C ±2 LSB 24-Lead SOIC_W RW-24
AD7225LN −40°C to +85°C ±1 LSB 24-Lead PDIP N-24-1
AD7225LNZ −40°C to +85°C ±1 LSB 24-Lead PDIP N-24-1
AD7225LP −40°C to +85°C ±1 LSB 28-Lead PLCC P-28
AD7225LP-REEL −40°C to +85°C ±1 LSB 28-Lead PLCC P-28
AD7225LPZ −40°C to +85°C ±1 LSB 28-Lead PLCC P-28
AD7225LPZ-REEL −40°C to +85°C ±1 LSB 28-Lead PLCC P-28
AD7225LR −40°C to +85°C ±1 LSB 24-Lead SOIC_W RW-24
AD7225LR-REEL −40°C to +85°C ±1 LSB 24-Lead SOIC_W RW-24
AD7225LRZ −40°C to +85°C ±1 LSB 24-Lead SOIC_W RW-24
AD7225LRZ-REEL −40°C to +85°C ±1 LSB 24-Lead SOIC_W RW-24
1 To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet.
2 Z = RoHS Compliant Part.
AD7225
Rev. C | Page 24 of 24
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00986-0-3/10(C)