32
35
33
42
LD BBQ_P
BBQ_N
RFOUT
VCC
VTUNE BBI_P
NC
GND
PD RDBK
EXT_VCO BBI_N
1
2
3
8
10
44
45
46
47
48
39
40
41
43
37
38
23
36
34
30
29
28
27
26
25
DATA
CP_OUT
LO_OUTP
CLK
LO_OUTN
REFIN
LE
18
PFD
Charge
Pump
LO Div
6
SDM
24
13
12
6
22
21
16
14
20
19
17
15
9
4
11
7
5
GND
TX Div
Pre
Scaler
N Div
PLL Div
R Div
31
0O
90O
Serial Interface
VCC_TK
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TRF3722
SLWS245B –MAY 2014–REVISED FEBRUARY 2017
TRF3722 Quadrature Modulator with Integrated PLL and VCO
1
1 Features
1• IQ Modulator with Integrated PLL and VCO
• Integer-N/Fractional-N PLL
• Modulator Supports 400 MHz to 4200 MHz
• PLL and VCO Supports 280 MHz to 4100 MHz
• OIP3 at 900 MHz = 31 dBm
• OIP3 at 1800 MHz = 30 dBm
• VCO 1800-MHz Open Loop Phase Noise =
–141 dBc/Hz at 1 MHz Offset
• Independent LO Output Supports divide-by 1/2/4/8
• Modulator Low Power and High Gain Modes
• Multiple Power Down Modes
2 Applications
• Wireless Infrastructure
– CDMA: IS95, UMTS, CDMA2000, TD-SCDMA
– LTE, TD-LTE, LTE Advanced
– TDMA: GSM, EDGE, MC-GSM
• Point-to-Point Microwave, Point-to-Multipoint
Microwave
• Software Defined Radios
• RF Repeaters, Distributed Antenna Systems
3 Description
The TRF3722 is a high performance direct
conversion quadrature modulator with exceptional
linearity and low noise performance. The typical
0.25-V baseband common mode voltage supports
seamless interface with current source DACs. The
device integrates the PLL and VCO to provide the
local oscillator (LO) to the modulator. The PLL and
VCO provides excellent phase noise performance to
satisfy the most stringent transmit communication
requirements. The device also provides additional LO
output for driving a second modulator or down
converting mixer. The modulator features a high gain
mode for a typical 3-dB gain increase and a low
power mode when power optimization is desired.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TRF3722 VQFN (48) 7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Block Diagram
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 9
6.7 Typical Characteristics - Output Power................... 10
6.8 Typical Characteristics - Gain................................. 11
6.9 Typical Characteristics - OIP3 ................................ 12
6.10 Typical Characteristics - OIP2 .............................. 13
6.11 Typical Characteristics - OP1dB........................... 14
6.12 Typical Characteristics - Noise ............................. 15
6.13 Typical Characteristics - Unadjusted CF............... 16
6.14 Typical Characteristics - Unadjusted SBS............ 17
6.15 Typical Characteristics - LO Harmonic ................. 18
6.16 Typical Characteristics - BB Harmonic ................. 20
6.17 Typical Characteristics - RF Output Return Loss . 22
6.18 Typical Characteristics - PLL/VCO ....................... 23
6.19 Typical Characteristics - Current Consumption .... 29
6.20 Typical Characteristics - Power Dissipation.......... 31
7 Parameter Measurement Information ................ 33
7.1 Serial Interface Timing Diagram ............................. 33
8 Detailed Description............................................ 35
8.1 Overview................................................................. 35
8.2 Functional Block Diagram....................................... 35
8.3 Feature Description................................................. 36
8.4 Device Functional Modes........................................ 39
8.5 Register Maps ........................................................ 42
9 Application and Implementation ........................ 55
9.1 Application Information............................................ 55
9.2 Typical Application.................................................. 55
10 Power Supply Recommendations ..................... 58
11 Layout................................................................... 59
11.1 Layout Guidelines ................................................. 59
11.2 Layout Example .................................................... 59
12 Device and Documentation Support................. 60
12.1 Receiving Notification of Documentation Updates 60
12.2 Community Resources.......................................... 60
12.3 Trademarks........................................................... 60
12.4 Electrostatic Discharge Caution............................ 60
12.5 Glossary................................................................ 60
13 Mechanical, Packaging, and Orderable
Information........................................................... 60
4 Revision History
Changes from Revision A (June 2014) to Revision B Page
• Changed 256 MHz to 280 MHz in PLL and VCO Features bullet.......................................................................................... 1
• Changed ESD Ratings table title, updated to current standards ........................................................................................... 4
• Added Typical and footnote 2 to Typical VCO frequency range and Typical output frequency range parameters............... 8
• Changed Figure 1 .................................................................................................................................................................. 9
• Changed location of TRF3722 Application Schematic figure and all associated text to be under Typical Application
section .................................................................................................................................................................................. 55
Changes from Original (May 2014) to Revision A Page
• Changed from 1-page Product Preview to Production........................................................................................................... 1
GND
LD
VCC_DIG
VCC_LO1
GND
NC
BBQ_P
BBQ_N
VCC_MOD1
VCC_MOD2
RFOUT
VCC_MOD3
VCC_MOD4
VCC_TK
VTUNE
NC
BBI_P
NC
GND
GND
GND
GND
GND
GND
GND
PD
RDBK
NC
NC
GND
NC
NC
EXT_VCO
VCC_LO2
VCC_VCO
BBI_N
TRF3722
1
2
3
4
5
6
7
8
9
10
11
12
44
45
46
47
48
39
40
41
42
43
37
38
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
DATA
GND
CP_OUT
VCC_PLL
LO_OUTP
GND
CLK
LO_OUTN
REFIN
LE
GND
GND
3
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5 Pin Configuration and Functions
RGZ Package
48-Pin VQFN
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
BBI_N 29 I BB in-phase input: negative
BBI_P 27 I BB in-phase input: positive
BBQ_N 8 I BB quadrature input: negative
BBQ_P 10 I BB quadrature input: positive
CLK 48 I Serial interface clock input; digital input
CP_OUT 41 O Charge pump output
DATA 47 I Serial interface data input; digital input
EXT_VCO 31 I External local oscillator input
GND 5, 7, 11, 15, 17, 19, 20,
22, 26, 30, 37, 40, 43,
45 Ground
LD 3 O PLL lock detect output
LE 46 I Serial interface latch enable; digital input
LO_OUTN 38 O Local oscillator output: negative
LO_OUTP 39 O Local oscillator output: positive
NC 9, 12, 13, 24, 25, 36 No connect
NC 28 No connect; N/C or ground to paddle
4
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Pin Functions (continued)
PIN I/O DESCRIPTION
NAME NO.
PD 1 I LO Div, TX Div, modulator power down (High = PD)
RDBK 2 O Serial interface internal registers readback output
REFIN 44 I Reference clock input
RFOUT 18 O RF output
VCC_DIG 4 3.3 V digital power supply
VCC_LO1 6 3.3 V TX Div power supply
VCC_LO2 35 3.3 V LO Div power supply
VCC_MOD1 14 3.3 V modulator power supply
VCC_MOD2 16 3.3 V modulator power supply
VCC_MOD3 21 3.3 V modulator power supply
VCC_MOD4 23 3.3 V modulator power supply
VCC_PLL 42 3.3 V PLL power supply
VCC_TK 32 3.3 V or 5 V VCO tank power supply
VCC_VCO 33 3.3 V VCO power supply
VTUNE 34 I VCO control voltage input
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage All VCC except VCC_TK –0.3 +3.6 V
VCC_TK –0.3 +5.5
Digital I/O voltage –0.3 3.6 V
Operating junction temperature –40 150 °C
Storage temperature, Tstg –40 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VCC 3.3 V power-supply voltage 3 3.3 3.6 V
5 V or 3.3 V power-supply voltage, VCC _TK 3 3.3/5 5.5 V
TJOperating junction temperature range –40 125 °C
TAAmbient temperature range –40 85 °C
5
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) TRF3722
UNITRGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 27.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.8 °C/W
RθJB Junction-to-board thermal resistance 4.3 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 °C/W
(1) Powered down output buffer and LO divider.
6.5 Electrical Characteristics
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C. Optimized bias settings as per Table 16.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC PARAMETERS
ICC 3.3 V Supply Current Typical Operating Mode; LO out = Off 328(1) mA
Typical Operating Mode; LO out = On 374 mA
ICC_TK 5 V Supply Current 21 mA
PDISS Total Power Dissipation
Typical Operating Mode; LO out = Off 1.18 W
Typical Operating Mode; LO out = On 1.34 W
Low Power Mode (Mod); LO out = Off 0.91 W
IPD Power Down Current Hardware Power Down 76 mA
Serial interface Power Down 2 mA
RFOUT FREQUENCY
Frequency 400 4200 MHz
IQ MODULATOR ƒLO = 750 MHz
GGain Typical Operating Mode 0.8 dB
High Gain Mode 3.6 dB
Gain Flatness In 300MHz bandwidth –0.5 0.5 dB
OP1dB Output Compression Point 10.2 dBm
OIP3 Output 3rd Order Intercept Point FBB = 4.5, 5.5 MHz 31 dBm
OIP2 Output 2nd Order Intercept Point FBB = 4.5, 5.5 MHz 62 dBm
SBS Unadj. SideBand Suppression –42 dBc
CF Unadj. Carrier Feedthrough –50 dBm
NSDOOutput Noise Spectral Density BB inputs terminated on 50 Ω–159 dBm/Hz
HD2LO LO Second Harmonic Measured at 2 x fLO –49 dBc
HD3LO LO Third Harmonic Measured at 3 x fLO –47 dBc
HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –72 dBc
HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –70 dBc
6
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Electrical Characteristics (continued)
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C. Optimized bias settings as per Table 16.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IQ MODULATOR ƒLO = 900 MHz
GGain Typical Operating Mode 0.8 dB
High Gain Mode 3.6 dB
Gain Flatness In 300MHz bandwidth –0.5 0.5 dB
OP1dB Output Compression Point 10 dBm
OIP3 Output 3rd Order Intercept Point FBB = 4.5, 5.5 MHz 31 dBm
OIP2 Output 2nd Order Intercept Point FBB = 4.5, 5.5 MHz 62.5 dBm
SBS Unadj. Side Band Suppression –42.5 dBc
CF Unadj. Carrier Feed through –50 dBm
NSDOOutput Noise Spectral Density BB inputs terminated on 50 Ω–159 dBm/Hz
HD2LO LO Second Harmonic Measured at 2 x fLO –47 dBc
HD3LO LO Third Harmonic Measured at 3 x fLO –54.5 dBc
HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –65.5 dBc
HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –71.5 dBc
IQ MODULATOR ƒLO = 1800 MHz
GGain Typical Operating Mode 0.3 dB
High Gain Mode 3 dB
Gain Flatness In 300 MHz bandwidth –0.5 0.5 dB
OP1dB Output Compression Point 13 dBm
OIP3 Output 3rd Order Intercept Point fBB = 4.5, 5.5 MHz 29.5 dBm
OIP2 Output 2nd Order Intercept Point fBB = 4.5, 5.5 MHz 57 dBm
SBS Unadj. Side Band Suppression –54.5 dBc
CF Unadj. Carrier Feed through –57 dBm
NSDOOutput Noise Spectral Density BB inputs terminated on 50 Ω–158 dBm/Hz
HD2LO LO Second Harmonic Measured at 2 x fLO –36.5 dBc
HD3LO LO Third Harmonic Measured at 3 x fLO –33.5 dBc
HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –65.5 dBc
HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –73 dBc
RLORF Output Return Loss 6 dB
IQ MODULATOR ƒLO = 2150 MHz
GGain Typical Operating Mode 0.2 dB
High Gain Mode 3 dB
Gain Flatness In 300 MHz bandwidth –0.5 0.5 dB
OP1dB Output Compression Point 11.6 dBm
OIP3 Output 3rd Order Intercept Point FBB = 4.5, 5.5 MHz 30 dBm
OIP2 Output 2nd Order Intercept Point FBB = 4.5, 5.5 MHz 43 dBm
SBS Unadj. Side Band Suppression –43 dBc
CF Unadj. Carrier Feedt hrough –42 dBm
NSDOOutput Noise Spectral Density BB inputs terminated on 50 Ω–157 dBm/Hz
HD2LO LO Second Harmonic Measured at 2 x fLO –40 dBc
HD3LO LO Third Harmonic Measured at 3 x fLO –31 dBc
HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –51 dBc
HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –69 dBc
7
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Electrical Characteristics (continued)
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C. Optimized bias settings as per Table 16.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IQ MODULATOR ƒLO = 2700 MHz
GGain Typical Operating Mode 0 dB
High Gain Mode 2.4 dB
Gain Flatness In 300MHz bandwidth –0.5 0.5 dB
OP1dB Output Compression Point 10.4 dBm
OIP3 Output 3rd Order Intercept Point FBB = 4.5, 5.5 MHz 29.5 dBm
OIP2 Output 2nd Order Intercept Point FBB = 4.5, 5.5 MHz 45.5 dBm
SBS Unadj. Side Band Suppression –33 dBc
CF Unadj. Carrier Feed through –39.6 dBm
NSDOOutput Noise Spectral Density BB inputs terminated on 50 Ω–156 dBm/Hz
HD2LO LO Second Harmonic Measured at 2 x fLO –29 dBc
HD3LO LO Third Harmonic Measured at 3 x fLO –37 dBc
HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –53 dBc
HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –68 dBc
IQ MODULATOR ƒLO = 3600 MHz
G Gain Typical Operating Mode –2 dB
High Gain Mode 0.4 dB
OP1dB Output Compression Point 8.7 dBm
OIP3 Output 3rd Order Intercept Point FBB = 4.5, 5.5 MHz 24.5 dBm
OIP2 Output 2nd Order Intercept Point FBB = 4.5, 5.5 MHz 45.5 dBm
SBS Unadj. Side Band Suppression –31.5 dBc
CF Unadj. Carrier Feed through –39.5 dBm
HD2LO LO Second Harmonic Measured at 2 x fLO –28.4 dBc
HD3LO LO Third Harmonic Measured at 3 x fLO –31.5 dBc
HD2BB Baseband Second Harmonic Measured at fLO ± 2 x fBB –55 dBc
HD3BB Baseband Third Harmonic Measured at fLO ± 3 x fBB –65 dBc
BASEBAND INPUTS
VCM Common Mode Voltage Baseband I/Q input 0 0.25 0.5 V
BWBB Baseband Bandwidth 1 dB Bandwidth 900 MHz
ZinBB Baseband Input Impedance Resistance 5 kΩ
Capacitance 4 pF
REFERENCE OSCILLATOR PARAMETERS
Fref Reference Frequency Max 350 MHz
Reference Input Sensitivity 0.2 3.3 VPP
Zinref Reference Input Impedance Parallel capacitance 2 pF
Parallel resistance 2.2 kΩ
PFD, CP
FPFD PFD Frequency Max, refer to the Typical Application 65 MHz
ICP_OUT Charge Pump Current Max 1.94 mA
In-band Normalized PN Floor Integer Mode –221 dBc/Hz
8
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Electrical Characteristics (continued)
Over recommended operating conditions: VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C. Optimized bias settings as per Table 16.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(2) Divided-down ranges minimum and maximum values are typical but are not specified.
VCO
fVCO Typical VCO frequency range(2) 2050 4100 MHz
KVVCO gain VTUNE = 1.1 V 30 MHz/V
PN
VCO Open Loop Phase Noise;
fVCO = 3600 MHz;
TX Div = Div-by-1;
fOUT = 3600 MHz
VTUNE = 1.1 V
10 kHz –74
dBc/Hz
100 kHz –109
1 MHz –135
10 MHz –152
40 MHz –156
VCO Open Loop Phase Noise;
fVCO = 3600 MHz;
TX Div = Div-by-2;
fOUT = 1800 MHz;
VTUNE = 1.1 V
10 kHz –80
dBc/Hz
100 kHz –115
1 MHz –141
10 MHz –156
40 MHz –158
LO OUTPUT
fOUT Typical output frequency range(2)
Divide by 1 2050 4100
MHz
Divide by 2 1025 2050
Divide by 4 512.5 1025
Divide by 8 256.25 512.5
PLO Output power SE at 1800 MHz, OUTBUF_BIAS = 2 1 dBm
External VCO input Frequency Range 250 4200 MHz
External VCO Input Level –10 0 10 dBm
CLOSE LOOP PLL OR VCO
Integrated Phase Noise
Frac-N; PFD = 15.36 MHz; fOUT =
3532.89 MHz;
Integration BW =1 kHz to 10 MHz; SSB -45.2 dB
Int-N; PFD = 2.56 MHz; fOUT = 1799.68
MHz;
Integration BW = 500 Hz to 20 MHz; SSB -49.8 dB
VCO Close Loop Phase Noise;
fVCO = 3600 MHz;
TX DIV = Div-by-2;
fOUT = 1800 MHz;
Integer Mode, PFD = 2.56MHz
10 kHz –96
dBc/Hz
100 kHz –114
1 MHz –140
10 MHz –156
40 MHz –158
DIGITAL INTERFACE
VIH High Level Input Voltage 2 3.3 V
VIL Low Level Input Voltage 0 0.8 V
VOH High Level Output Voltage Referenced to VCC_DIG 0.8 x VCC V
VOL Low Level Output Voltage Referenced to VCC_DIG 0.2 x VCC V
F1 = FBB1 + LO
F2 = FBB2 + LO
F3rdL = 2F1-F2
F3rdH = 2F2-F1
F2ndL = (FBB2 - FBB1)+LO
F2ndH = (FBB2 + FBB1)+LO
LO
LSB1 = LO - FBB1
LSB2 = LO ± FBB2
FBBn = Baseband Frequency
Fn = RF Frequency
F3rdH/L = 3rd Order Intermodulation Product Frequency (High Side / Low Side)
F2ndH/L = 2nd Order Intermodulation Product Frequency (High Side / Low Side)
LO = Local Oscillator Frequency
LSBn = Lower Sideband Frequency
HD2BB = Baseband second harmonic (High Side / Low Side)
HD3BB = Baseband thrid harmonic (High Side / Low Side)
Desired Signal
Unwanted Sideband
3rd Order IM
2nd Order IM
Freq.
HD2BB
HD3BB
LO + 3FBB1
LO + 3FBB2
LO - 3FBB2
LO - 3FBB1
LO - 2FBB1
LO - 2FBB2
LO + 2FBB2
LO + 2FBB1
9
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6.6 Typical Characteristics
6.6.1 Modulator Output Spectrum
Graphical illustration of the modulator output spectrum with two tones is shown in Figure 1.
Figure 1. Graphical Illustration of Modulator Output Spectrum
Frequency (MHz)
POUT (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D019
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
POUT (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D220
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
POUT (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D219
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
POUT (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D015
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
POUT (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D218
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
10
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6.7 Typical Characteristics - Output Power
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, 500 mVPP, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per
Table 16. Total Pout is two tones combined power.
Figure 2. Total POUT vs Temperature, Typical Operating
Mode Figure 3. Total POUT vs Supply, Typical Operating Mode
Figure 4. Total POUT vs Temperature, High Gain Mode Figure 5. Total POUT vs Supply, High Gain Mode
Figure 6. Total POUT vs Temperature, Low Power Mode Figure 7. Total POUT vs Supply, Low Power Mode
Frequency (MHz)
G (dB)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D008
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
G (dB)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D005
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
G (dB)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D006
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
G (dB)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-10
-8
-6
-4
-2
0
2
4
6
D003
TA = -40qC
TA = 25qC
TA = 85qC
11
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6.8 Typical Characteristics - Gain
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Figure 8. Voltage Gain vs Temperature, Typical Operating
Mode Figure 9. Voltage Gain vs Supply, Typical Operating Mode
Figure 10. Voltage Gain vs Temperature, High Gain Mode Figure 11. Voltage Gain vs Supply, High Gain Mode
Figure 12. Voltage Gain vs Temperature, Low Power Mode Figure 13. Voltage Gain vs Supply, Low Power Mode
Frequency (MHz)
OIP3 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
16
18
20
22
24
26
28
30
32
34
D013
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OIP3 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
16
18
20
22
24
26
28
30
32
34
D014
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
OIP3 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
16
18
20
22
24
26
28
30
32
34
D011
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OIP3 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
16
18
20
22
24
26
28
30
32
34
D012
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
OIP3 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
16
18
20
22
24
26
28
30
32
34
D009
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OIP3 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
16
18
20
22
24
26
28
30
32
34
D010
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
12
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6.9 Typical Characteristics - OIP3
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported OIP3 is minimum of low side and high side.
Figure 14. OIP3 vs Temperature, Typical Operating Mode Figure 15. OIP3 vs Supply, Typical Operating Mode
Figure 16. OIP3 vs Temperature, High Gain Mode Figure 17. OIP3 vs Supply, High Gain Mode
Figure 18. OIP3 vs Temperature, Low Power Mode Figure 19. OIP3 vs Supply, Low Power Mode
Frequency (MHz)
OIP2 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
30
35
40
45
50
55
60
65
70
D025
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OIP2 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
30
35
40
45
50
55
60
65
70
D026
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
OIP2 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
30
35
40
45
50
55
60
65
70
D023
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OIP2 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
30
35
40
45
50
55
60
65
70
D024
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
OIP2 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
30
35
40
45
50
55
60
65
70
D021
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OIP2 (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
30
35
40
45
50
55
60
65
70
D022
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
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6.10 Typical Characteristics - OIP2
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported OIP2 is minimum of low side and high side.
Figure 20. OIP2 vs Temperature, Typical Operating Mode Figure 21. OIP2 vs Supply, Typical Operating Mode
Figure 22. OIP2 vs Temperature, High Gain Mode Figure 23. OIP2 vs Supply, High Gain Mode
Figure 24. OIP2 vs Temperature, Low Power Mode Figure 25. OIP2 vs Supply, Low Power Mode
Frequency (MHz)
OP1dB (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
0
2
4
6
8
10
12
14
16
D031
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OP1dB (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
0
2
4
6
8
10
12
14
16
D032
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
OP1dB (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
0
2
4
6
8
10
12
14
16
D029
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OP1dB (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
0
2
4
6
8
10
12
14
16
D030
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
OP1dB (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
0
2
4
6
8
10
12
14
16
D027
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
OP1dB (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
0
2
4
6
8
10
12
14
16
D028
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
14
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6.11 Typical Characteristics - OP1dB
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C, I/Q frequency (fBB)
5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Figure 26. OP1dB vs Temperature, Typical Operating Mode Figure 27. OP1dB vs Supply, Typical Operating Mode
Figure 28. OP1dB vs Temperature, High Gain Mode Figure 29. OP1dB vs Supply, High Gain Mod
Figure 30. OP1dB vs Temperature, Low Power Mode Figure 31. OP1dB vs Supply, Low Power Mode
Frequency (MHz)
NSD (dBm/Hz)
200 600 1000 1400 1800 2200 2600
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
D049
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
NSD (dBm/Hz)
200 600 1000 1400 1800 2200 2600
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
D050
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
NSD (dBm/Hz)
200 600 1000 1400 1800 2200 2600
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
D047
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
NSD (dBm/Hz)
200 600 1000 1400 1800 2200 2600
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
D048
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
NSD (dBm/Hz)
200 600 1000 1400 1800 2200 2600
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
D045
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
NSD (dBm/Hz)
200 600 1000 1400 1800 2200 2600
-170
-168
-166
-164
-162
-160
-158
-156
-154
-152
-150
D046
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
15
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6.12 Typical Characteristics - Noise
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, TA= 25°C, BB inputs terminated to
50 Ωand 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Figure 32. Noise vs Temperature, Typical Operating Mode Figure 33. Noise vs Supply, Typical Operating Mode
Figure 34. Noise vs Temperature, High Gain Mode Figure 35. Noise vs Supply, High Gain Mode
Figure 36. Noise vs Temperature, Low Power Mode Figure 37. Noise vs Supply, Low Power Mode
Frequency (MHz)
Unadj. CF (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
D038
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
Unadj. CF (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-70
-65
-60
-55
-50
-45
-40
-35
-30
D035
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
Unadj. CF (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-70
-65
-60
-55
-50
-45
-40
-35
-30
D036
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
Unadj. CF (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-70
-65
-60
-55
-50
-45
-40
-35
-30
D033
TA = -40qC
TA = 25qC
TA = 85qC
16
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6.13 Typical Characteristics - Unadjusted CF
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Figure 38. Unadjustable CF vs Temperature,
Typical Operating Mode Figure 39. Unadjustable CF vs Supply,
Typical Operating Mode
Figure 40. Unadjustable CF vs Temperature,
High Gain Mode Figure 41. Unadjustable CF vs Supply, High Gain Mode
Figure 42. Unadjustable CF vs Temperature,
Low Power Mode Figure 43. Unadjustable CF vs Supply, Low Power Mode
Frequency (MHz)
Unadj. SBS (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
D225
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
Unadj. SBS (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
D226
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
Unadj. SBS (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
D223
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
Unadj. SBS (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
D221
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
Unadj. SBS (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
D222
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
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6.14 Typical Characteristics - Unadjusted SBS
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Figure 44. Unadjustable SBS vs Temperature,
Typical Operating Mode Figure 45. Unadjustable SBS vs Supply,
Typical Operating Mode
Figure 46. Unadjustable SBS vs
Temperature, High Gain Mode Figure 47. Unadjustable SBS vs Supply,
High Gain Mode
Figure 48. Unadjustable SBS vs Temperature,
Low Power Mode Figure 49. Unadjustable SBS vs Supply, Low Power Mode
Frequency (MHz)
HD2LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
-20
D055
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD2LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
-20
D203
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
HD2LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
-20
D053
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD2LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
-20
D202
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
HD2LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
-20
D051
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD2LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-60
-55
-50
-45
-40
-35
-30
-25
-20
D201
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
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6.15 Typical Characteristics - LO Harmonic
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Figure 50. LO Second Harmonic vs Temperature,
Typical Operating Mode Figure 51. LO Second Harmonic vs Supply,
Typical Operating Mode
Figure 52. LO Second Harmonic vs Temperature,
High Gain Mode Figure 53. LO Second Harmonic vs Supply,
High Gain Mode
Figure 54. LO Second Harmonic vs Temperature,
Low Power Mode Figure 55. LO Second Harmonic vs Supply,
Low Power Mode
Frequency (MHz)
HD3LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
D061
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD3LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
D206
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
HD3LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
D059
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD3LO (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
D205
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
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Typical Characteristics - LO Harmonic (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Figure 56. LO Third Harmonic vs Temperature,
Typical Operating Mode Figure 57. LO Third Harmonic vs Supply,
Typical Operating Mode
Figure 58. LO Third Harmonic vs Temperature,
High Gain Mode Figure 59. LO Third Harmonic vs Supply,
High Gain Mode
Figure 60. LO Third Harmonic vs Temperature,
Low Power Mode Figure 61. LO Third Harmonic vs Supply,
Low Power Mode
Frequency (MHz)
HD2BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
D209
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
HD2BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
D065
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD2BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
D208
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
HD2BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-80
-75
-70
-65
-60
-55
-50
-45
-40
D063
TA = -40qC
TA = 25qC
TA = 85qC
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6.16 Typical Characteristics - BB Harmonic
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported BB harmonic is from (fBB) 4.5MHz.
Figure 62. BB-HD2 vs Temperature, Typical Operating Mode Figure 63. BB-HD2 vs Supply, Typical Operating Mode
Figure 64. BB-HD2 vs Temperature, High Gain Mode Figure 65. BB-HD2 vs Supply, High Gain Mode
Figure 66. BB-HD2 vs Temperature, Low Power Mode Figure 67. BB-HD2 vs Supply, Low Power Mode
Frequency (MHz)
HD3BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-90
-85
-80
-75
-70
-65
-60
-55
-50
D073
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD3BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-90
-85
-80
-75
-70
-65
-60
-55
-50
D212
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
HD3BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-90
-85
-80
-75
-70
-65
-60
-55
-50
D071
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD3BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-90
-85
-80
-75
-70
-65
-60
-55
-50
D211
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
HD3BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-90
-85
-80
-75
-70
-65
-60
-55
-50
D069
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
HD3BB (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-90
-85
-80
-75
-70
-65
-60
-55
-50
D210
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
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Typical Characteristics - BB Harmonic (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK= 5 V, and TA= 25°C, I/Q frequency (fBB)
4.5 MHz and 5.5 MHz, VCM = 0.25 V, and 4.7 pF series capacitor at RFOUT. Optimized bias settings as per Table 16.
Reported BB harmonic is from (fBB) 4.5MHz.
Figure 68. BB-HD3 vs Temperature, Typical Operating Mode Figure 69. BB-HD3 vs Supply, Typical Operating Mode
Figure 70. BB-HD3 vs Temperature, High Gain Mode Figure 71. BB-HD3 vs Supply, High Gain Mode
Figure 72. BB-HD3 vs Temperature, Low Power Mode Figure 73. BB-HD3 vs Supply, Low Power Mode
S22
Frequency (400 MHz to 4200 MHz)
Frequency (MHz)
RFOUT S22 (dB)
-20
-17.5
-15
-12.5
-10
-7.5
-5
-2.5
0
2.5
5
400 800 1200 1600 2000 2400 2800 3200 3600 4000
D120
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6.17 Typical Characteristics - RF Output Return Loss
Unless specified all plots were created at RFOUT pin using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C
Figure 74. Smith Chart
Figure 75. RFOUT S22 vs Frequency
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-175
-150
-125
-100
-75
-50
-25
500 1k 10k 100k 1M 10M 40M
D091
TA = -40qC
TA = 25qC
TA = 85qC
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-175
-150
-125
-100
-75
-50
-25
500 1k 10k 100k 1M 10M 40M
D092
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-175
-150
-125
-100
-75
-50
-25
500 1k 10k 100k 1M 10M 40M
D089
TA = -40qC
TA = 25qC
TA = 85qC
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-175
-150
-125
-100
-75
-50
-25
500 1k 10k 100k 1M 10M 40M
D090
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-175
-150
-125
-100
-75
-50
-25
1k 10k 100k 1M 10M500 40M
D087
TA = -40qC
TA = 25qC
TA = 85qC
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-175
-150
-125
-100
-75
-50
-25
500 1k 10k 100k 1M 10M 40M
D088
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
23
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6.18 Typical Characteristics - PLL/VCO
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Measured at
LO_OUTP with 50 Ωbias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
Figure 76. Open Loop Phase Noise at 450 MHz vs
Temperature Figure 77. Open Loop Phase Noise at 450 MHz vs Supply
Figure 78. Open Loop Phase Noise at 900 MHz vs
Temperature Figure 79. Open Loop Phase Noise at 900 MHz vs Supply
Figure 80. Open Loop Phase Noise at 1800 MHz vs
Temperature Figure 81. Open Loop Phase Noise at 1800 MHz vs Supply
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D098
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D099
TA = -40qC
TA = 25qC
TA = 85qC
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D096
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D097
TA = -40qC
TA = 25qC
TA = 85qC
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-175
-150
-125
-100
-75
-50
-25
500 1k 10k 100k 1M 10M 40M
D215
450 MHz
900 MHz
1800 MHz
2150 MHz
2700 MHz
3600 MHz
4000 MHz
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D095
TA = -40qC
TA = 25qC
TA = 85qC
24
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Measured at
LO_OUTP with 50 Ωbias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
Figure 82. Open Loop Phase Noise vs Frequency Figure 83. 450 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
Figure 84. 450 MHz Frac-N (Closed Loop Phase Noise) vs
Supply Figure 85. 1800 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
Figure 86. 1800 MHz Frac-N (Closed Loop Phase Noise) vs
Supply Figure 87. 2150 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D104
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
1k 10k 100k 1M 10M500 40M
D105
450MHz, Div8
900MHz, Div4
1800MHz, Div2
3600MHz, Div1
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D102
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D103
TA = -40qC
TA = 25qC
TA = 85qC
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D100
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
500 1k 10k 100k 1M 10M 40M
D101
TA = -40qC
TA = 25qC
TA = 85qC
25
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Measured at
LO_OUTP with 50 Ωbias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
Figure 88. 2150 MHz Frac-N (Closed Loop Phase Noise) vs
Supply Figure 89. 2700 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
Figure 90. 2700 MHz Frac-N (Closed Loop Phase Noise) vs
Supply Figure 91. 3600 MHz Frac-N (Closed Loop Phase Noise) vs
Temperature
Figure 92. 3600 MHz Frac-N (Closed Loop Phase Noise) vs
Supply Figure 93. 450, 900, 1800, 3600 MHz Closed Loop Phase
Noise vs Offset Frequency
Frequency (MHz)
REF Spur (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
D213
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
REF Spur (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
D214
VCC = 3.15,4.75
VCC = 3.30,5.00
VCC = 3.45,5.25
Frequency (MHz)
PFD Spur (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
D108
1 x PFD
2 x PFD
3 x PFD
Frequency (MHz)
PFD Spur (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
D227
PFD = 0.68MHz
PFD = 1.28MHz
PFD = 2.56MHz
Frequency (MHz)
PFD Spur (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
D106
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
PFD Spur (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
D107
VCC = 3.15,4.75
VCC = 3.30,5.00
VCC = 3.45,5.25
26
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Measured at
LO_OUTP with 50 Ωbias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
Figure 94. PFD Spur vs Temperature Figure 95. PFD Spur vs Supply
Figure 96. PFD Spur vs PFD Multiples Figure 97. PFD Spur vs Frequency
Figure 98. 1 x Reference Spur vs Temperature Figure 99. Reference Spur vs Supply
Frequency (MHz) - 1843.2MHz
Frac Spur (dBc)
0.0001 0.001 0.01 0.10.2 0.5 1 2 3 5 10 2020
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
D115
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz) - 3609.6MHz
Frac Spur (dBc)
0.0001 0.001 0.01 0.10.2 0.5 1 2 3 5 10 2020
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
D113
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz) - 1843.2MHz
Frac Spur (dBc)
0.0001 0.001 0.01 0.10.2 0.5 1 2 3 5 10 2020
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
D114
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz) - 61.44MHz
REF Spur (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
D111
1 x REF
2 x REF
3 x REF
Frequency (MHz) - 3609.6MHz
Frac Spur (dBc)
0.0001 0.001 0.01 0.10.2 0.5 1 2 3 5 10 2020
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
D112
TA = -40qC
TA = 25qC
TA = 85qC
27
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Measured at
LO_OUTP with 50 Ωbias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
Figure 100. Reference Spur vs Reference Multiples Figure 101. 3609.6 MHz Integer Boundary Spur vs
Temperature
Figure 102. 3609.6 MHz Integer Boundary Spur vs Supply Figure 103. 1843.2 MHz Integer Boundary Spur vs
Temperature
Figure 104. 1842.2 MHz Integer Boundary Spur vs Supply
V(tune) = 1.1 V
Figure 105. KVCO vs VCO Trim
Frequency (MHz)
LO POUT (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
-1
0
1
2
3
4
5
6
7
8
D117
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
LO Harmonics (dBc)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
D118
2nd Harmonic
3rd Harmonic
5th Harmonic
VCO_TRIM
Frequency (MHz)
0 5 10 15 20 25 30 35 40 45 50 55 60 65
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
D216
VCO_SEL 0
VCO_SEL 1 VCO_SEL 2
VCO_SEL 3
Frequency (MHz)
LO POUT (dBm)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
-2
-1
0
1
2
3
4
5
6
7
8
D116
TA = -40qC
TA = 25qC
TA = 85qC
28
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Typical Characteristics - PLL/VCO (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Measured at
LO_OUTP with 50 Ωbias resistor and 47 pF series capacitor. Modulator section powered down. Reference frequency is set
to 61.44 MHz. Optimized bias settings as per Table 16.
V(tune) = 1.1 V
Figure 106. Frequency vs VCO_TRIM Figure 107. LO Output Power at LO_OUTP vs Temperature
Figure 108. LO Output Power at LO_OUTP vs Supply Figure 109. LO Harmonics at LO_OUTP vs Frequency
Frequency (MHz)
ICC (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
230
232
234
236
238
240
242
244
246
248
250
252
254
256
D232
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
ICC (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
230
232
234
236
238
240
242
244
246
248
250
252
254
256
D233
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
ICC (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
340
348
356
364
372
380
388
396
404
412
420
D230
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
ICC (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
340
348
356
364
372
380
388
396
404
412
420
D231
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
ICC (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
340
348
356
364
372
380
388
396
404
412
420
D228
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
ICC (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
340
348
356
364
372
380
388
396
404
412
420
D229
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
29
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6.19 Typical Characteristics - Current Consumption
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Optimized bias
settings as per Table 16
Figure 110. 3.3V Supply Current vs Temperature, Typical
Operating Mode Figure 111. 3.3V Supply Current vs Supply, Typical
Operating Mode
Figure 112. 3.3V Supply Current vs Temperature, High Gain
Mode Figure 113. 3.3V Supply Current vs Supply, High Gain Mode
Figure 114. 3.3V Supply Current vs Temperature, Low Power
Mode Figure 115. 5V Supply Current vs Supply, Low Power Mode
Frequency (MHz)
ICC_TK (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
26
26.2
26.4
26.6
26.8
27
27.2
27.4
27.6
27.8
28
D234
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
ICC_TK (mA)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
26
26.2
26.4
26.6
26.8
27
27.2
27.4
27.6
27.8
28
D235
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
30
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Typical Characteristics - Current Consumption (continued)
Figure 116. 5V Supply Current vs Temperature, Typical
Operating Mode Figure 117. 5V Supply Current vs Temperature, Typical
Operating Mode
Frequency (MHz)
3.3V PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
D079
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
3.3V PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
D080
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
3.3V PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D077
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
3.3V PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D078
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
3.3V PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D075
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
3.3V PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D076
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
31
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6.20 Typical Characteristics - Power Dissipation
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Optimized bias
settings as per Table 16.
Figure 118. 3.3 V PDISS vs Temperature,
Typical Operating Mode Figure 119. 3.3 V PDISS vs Supply,
Typical Operating Mode
Figure 120. 3.3 V PDISS vs Temperature,
High Gain Mode Figure 121. 3.3 V PDISS vs Supply,
High Gain Mode
Figure 122. 3.3 V PDISS vs Temperature, Low Power Mode Figure 123. 3.3 V PDISS vs Supply, Low Power Mode
Frequency (MHz)
PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
D085
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
D086
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D083
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D084
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
Frequency (MHz)
PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D081
TA = -40qC
TA = 25qC
TA = 85qC
Frequency (MHz)
PDISS (W)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
D082
VCC = 3.15V, 4.75V
VCC = 3.30V, 5.00V
VCC = 3.45V, 5.25V
32
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Typical Characteristics - Power Dissipation (continued)
Unless specified all plots were created using TRF3722EVM, VCC = 3.3 V, VCC_TK = 5 V, and TA= 25°C. Optimized bias
settings as per Table 16.
Figure 124. Total PDISS vs Temperature,
Typical Operating Mode Figure 125. Total PDISS vs Supply, Typical Operating Mode
Figure 126. Total PDISS vs Temperature, High Gain Mode Figure 127. Total PDISS vs Supply, High Gain Mode
Figure 128. Total PDISS vs Temperature, Low Power Mode Figure 129. Total PDISS vs Supply, Low Power Mode
1st Write
clock
pulse
32nd
Write
clock
pulse
tw
CLOCK
DATA
LATCH
ENABLE
REGISTER WRITE
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3 DB29 DB30
DB0 (LSB)
Address Bit0
tsu3
tsu1 tht(CLK)
DB31 (MSB)
t(CL)
t(CH)
tsu2
End of Write
Cycle pulse
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7 Parameter Measurement Information
7.1 Serial Interface Timing Diagram
The TRF3722 features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift register
with seven parallel registers. There are total of three signals that must be applied: the clock (CLK), the serial data
(DATA), and the latch enable (LE). The fouth signal is the read back (RDBK) signal. The serial data (DB0-DB31)
are loaded least significant bit (LSB) first, and read on the rising edge of the CLK. LE is asynchronous to the CLK
signal; at its rising edge, the data in the shift register are loaded into the selected internal register. Figure 130
shows the timing diagram the 4WI. Table 1 lists the 4WI timing for the write operation.
Figure 130. 4WI Writing Timing Diagram
Table 1. 4WI Timing for Write Operation
MIN TYP MAX UNIT
thHold time, data to clock 20 ns
tSU1 Setup time, data to clock 20 ns
tCH Clock low duration 20 ns
tCL Clock High duration 20 ns
tSU2 Setup time, clock to enable 20 ns
tCLK Clock period 50 ns
tWEnable Time 50 ns
tSU3 Setup time, Latch to Data 70 ns
32nd
Write
clock
pulse
1st Read
clock pulse 2nd Read
clock pulse 32nd Read
clock pulse 33rd Read
clock pulse
³(QGRI:ULWH&\FOH´
pulse
ReadBack
Data Bit31
Read
Back
Data
Bit29
Read
Back
Data
Bit1
ReadBack
Data Bit30
ReadBack
Data Bit0
³(QGRI:ULWH&\FOH´
pulse
DB31 (MSB)
1st Write
clock
pulse
tsu1 tht( CLK)
32nd
Write
clock
pulse
DB30DB29
DB2
Address Bit2
DB1
Address Bit1
tsu2 tw
DB0 (LSB)
Address Bit0
CLOCK
DATA
CLOCK
READBACK DATA
REGISTER WRITEREADBACK
td
tsu2
tw
LATCH
ENABLE
T(CL)
T(CH)
LATCH ENABLE
DB3
Address Bit3
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TRF3722 integrates 7 registers: Register 0 (000) to Register 6 (110). Registers 1 through 6 are used to set-up
and control the TRF3722 functionalities, while register 0 is used for the read-back function. Each read-back is
composed by two phases: writing followed by the actual reading of the internal data. This is shown in the timing
diagram in Figure 131.
Figure 131. 4WI Read-Back Timing Diagram
During the writing phase a command is sent to TRF3722 register 0 to set it in read-back mode and to specify
which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is
transferred into the RDBK pin and can be read at the following falling edge (LSB first). The first clock after the LE
goes high (end of writing cycle) is idle and the following 32 clocks pulses will transfer the internal register content
to the RDBK pin. Table 2 shows the Readback timing.
Table 2. 4WI Timing for Readback Timing
MIN TYP MAX UNIT COMMENT
thHold time, data to clock 20 ns
tSU1 Setup time, data to clock 20 ns
tCH Clock low duration 20 ns
tCL Clock High duration 20 ns
tSU2 Setup time, clock to enable 20 ns
tSU3 Setup time, enable to Readback clock 20 ns
tdDelay time, clock to Readback data
output 10
tWEnable Time 50 ns Equals Clock period
t(CLK) Clock period 50 ns
32
35
33
42
LD BBQ_P
BBQ_N
RFOUT
VCC
VTUNE BBI_P
NC
GND
PD RDBK
EXT_VCO BBI_N
1
2
3
8
10
44
45
46
47
48
39
40
41
43
37
38
23
36
34
30
29
28
27
26
25
DATA
CP_OUT
LO_OUTP
CLK
LO_OUTN
REFIN
LE
18
PFD
Charge
Pump
LO Div
6
SDM
24
13
12
6
22
21
16
14
20
19
17
15
9
4
11
7
5
GND
TX Div
Pre
Scaler
N Div
PLL Div
R Div
31
0O
90O
Serial Interface
VCC_TK
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8 Detailed Description
8.1 Overview
TRF3722 integrates a high performance direct conversion quadrature modulator with exceptional linearity and
low noise performance. The modulator which upconverts low frequency baseband signal to high frequency RF
typically operates at 0.25 V common mode. It supports seamless interface with current source DACs. It also
features high gain and low power operating modes. Additionally, TRF3722 integrates PLL and VCO to provide
the local oscillator (LO) to the integrated modulator. The PLL and VCO provides excellent phase noise and
extremely low spurious performance. The device also provides an LO output for driving another modulator or
mixer. TRF3722 supports the use of an external VCO or LO signal.
8.2 Functional Block Diagram
VCO PFD
= x PLL DIV x NINTf f
VCO PFD 25
NFRAC
= x PLL DIV x NINT +
2
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f f
PLL_DIV_SEL
PLL DIV = 2
REF
PFD =
RDIV
f
f
REF
VCO 25
NFRAC
= x PLL DIV x NINT +
RDIV 2
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ç
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f
f
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8.3 Feature Description
8.3.1 RF Output
The RF output is single ended and can drive a 50-Ωload. It can be tuned with the use of an output matching
network to optimize the linearity and return loss performance within a selected band.
8.3.2 Baseband Inputs
The baseband inputs consist of the in-phase signal (I) and the quadrature-phase signals (Q). These I and Q
signals are differential. The baseband lines are nominally biased at 0.25-V common-mode voltage (VCM);
however, the device can operate with a VCM in the range of 0 V to 0.5 V. The baseband input lines are normally
terminated externally 50 Ωon TRF3722 evaluation board, though it is possible to modify this value if necessary
to match to an external filter load impedance requirement.
8.3.3 LO Output
The LO outputs are open collector differential outputs and are biased externally. These differential outputs can
be tuned to optimized output power along with OUTBUF_BIAS register settings. It also is possible to use LO
outputs in single ended mode.
8.3.4 PLL Architecture
Figure 132 illustrates a block diagram of the PLL architecture.
The VCO output frequency (fVCO) is given by Equation 1:
(1)
(2)
(3)
(4)
Where fREF is the reference input frequency, RDIV is the reference divider division ratio and the phase -
frequency detector frequency is fPFD. PLL_DIV_SEL controls the division ratio of the programmable divider (PLL
DIV) before the dual-modulus prescaler (DMP). NINT and NFRAC/225 is the integer and fractional part of the
fractional divider (N.f), respectively. In Integer mode, the fractional setting is ignored and Equation 5 is applied.(5)
The complete feedback divider block consists of a PLL DIV, DMP, and N.f. The prescaler can be programmed as
either a 4/5 or an 8/9. N.f includes an Aand Mdigital counters.
C4
NS
R4
0R
C3
150pF
R3
1.5K
R2
6.49K
C2
2.2nF
C1
150pF
CP_OUT VTUNE
PFD Charge
Pump
LO Div
DMP
4/5 8/9
TX
Quad
Div
N Div
RDIV
Ext
Loop
Filter LO_DIV_SEL
TX_DIV_SEL
PLL DIV
PLL_DIV_SELPRSC_SEL
NINT
Ext VCO/
Ext LO
O°
9O°
VTUNE
CP_OUT
fPFD
fREF fVCO
fLO
fTX
SDM
NFRAC_DIV
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Feature Description (continued)
Figure 132. PLL Architecture
8.3.5 External VCO
An external LO or VCO signal may be applied. If an external LO is used the internal PLL can be powered down.
Alternatively, dividers, phase-frequency detector, and charge pump can remain enabled and may be used to
control the VTUNE of an external VCO. EN_EXTVCO is used to select the internal or external VCO.
8.3.6 Loop Filter
Loop filter design is critical for achieving low closed loop phase noise. Complete modulator performance data has
been measured using integer mode loop filter. The integer mode loop filter was designed considering loop
bandwidth 40 kHz and fPFD 2.56 MHz. Phase margin of 60 degrees was considered. Refer to TRF3722EVM
User’s Guide to obtain the details on TRF3722 loop component calculations. Figure 133 shows integer loop filter.
Figure 133. Integer Loop Filter
C4
330pF
R4
1.1K
C3
330pF
R3
1.1K
R2
1.1K
C2
10nF
C1
1nF
CP_OUT VTUNE
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Feature Description (continued)
Frac-N performance data is obtained using the fractional loop filter shown in Figure 134. 40 kHz loop bandwidth
and 15.36 MHz PFD was considered.
Figure 134. Fractional Loop Filter
8.3.7 Lock Detect
The lock detect signal is generated in the phase frequency detector by comparing the two input signals. When
the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The
precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged
and compared against a reference voltage to generate the lock detect (LD) signal. The number of averages used
is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO
frequency is not locked, LD may pulse high or exhibit periodic behavior.
By default, the internal lock detect signal is made available on the LD terminal. Register bits MUX_CTRL can be
used to control a multiplexer to output other diagnostic signals on the LD output.
VCO, Stepsize TX, Stepsize
PFD
x TX DIV
= =
PLL DIV PLL DIV
f f
f
LO TX
LO DIV x TX DIV x
PLL DIV = Ceiling = Ceiling
3000 MHz 3000 MHz
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è ø
ff
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8.4 Device Functional Modes
8.4.1 Selecting PLL Divider Values
With reference to the PLL architecture illustrated in Figure 132, operation of the PLL requires TX_DIV_SEL /
LO_DIV_SEL, PLL_DIV_SEL, RDIV, NINT, NFRAC and PRSC_SEL bits to be calculated.
a. TX_DIV_SEL / LO_DIV_SEL
The LO to the integrated modulator (ƒTX) and additional LO output (ƒLO) frequency is related to fVCO
according to the following:
ƒTX = fVCO / TX DIV
ƒLO = fVCO / LO DIV
Where TX DIV and LO DIV are related to TX_DIV_SEL and LO_DIV_SEL as:
TX_DIV_SEL / LO_DIV_SEL TX_DIV / LO_DIV FREQUENCY RANGE
TX_DIV_SEL = 0 TX DIV = 1 2050 MHz ≤ƒTX ≤4100 MHz
TX_DIV_SEL = 1 TX DIV = 2 1025 MHz ≤ƒTX ≤2050 MHz
TX_DIV_SEL = 2 TX DIV = 4 512.5 MHz ≤ƒTX ≤1025 MHz
TX_DIV_SEL = 3 TX DIV = 8 256.25 MHz ≤ƒTX ≤512.5 MHz
LO_DIV_SEL = 0 LO DIV = 1 2050 MHz ≤ƒLO ≤4100 MHz
LO_DIV_SEL = 1 LO DIV = 2 1025 MHz ≤ƒLO ≤2050 MHz
LO_DIV_SEL = 2 LO DIV = 4 512.5 MHz ≤ƒLO ≤1025 MHz
LO_DIV_SEL = 3 LO DIV = 8 256.25 MHz ≤ƒLO ≤512.5 MHz
b. PLL_DIV_SEL
Given fVCO, select PLL_DIV_SEL so that the division ratio PLL DIV limits the input frequency to the
prescaler , fDMP, is limited to a maximum of 3000 MHz.
PLL DIV = min(1, 2, 4) such that fDMP ≤3000 MHz
PLL DIV is related to PLL_DIV_SEL according to the following equation:
PLL_DIV = 2PLL_DIV_SEL
This calculation can be restated as Equation 6.
(6)
For both integer and fractional mode it is preferable to operate the fPFD at the highest possible frequency
determined by the required frequency step of the RFOUT or LO_OUT. In Integer mode, select the maximum
fPFD according to Equation 7.
(7)
In Fractional mode, small RF stepsize can be obtained through the fractional divider. In this case, the highest
fPFD frequency should be selected according to the reference clock and system requirements.
VCO
N=
PLL DIV x P
f
f
25
VCO x RDIV
REF
NFRAC = floor NINT x 2
x PLL DIV
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ê ú
ë û
f
f
VCO x RDIV
REF
NINT = floor
x PLL DIV
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f
f
REF
PFD
RDIV = f
f
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c. RDIV, NINT, NFRAC, PRSC_SEL
The remaing PLL parameters are calculated according to the following equations:
The DMP division ratio (P/P+1) can be set to 4/5 or 8/9 through the PRSC_SEL bit. To allow proper
fractional operation, set PRSC_SEL according to:
PRSC_SEL = 0, (P/P+1) = 4/5 for 20 ≤NINT < 72 in integer mode or 23 ≤NINT < 75 in fractional mode.
PRSC_SEL = 1, (P/P+1) = 8/9 for NINT ≥72 in integer mode or NINT ≥75 in fractional mode.
The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode,
the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of
PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum input frequency
(fN) to the digital divider. Use the lower of the possible prescaler divide settings, P = (4,8), as shown by
Equation 8.
(8)
Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fNexceeds 375 MHz,
choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL.
8.4.2 Setup Example for Integer Mode
Suppose the following operating characteristics fractional example are desired for Integer mode operation:
• fREF = 61.44 MHz (reference input frequency)
• Step at RF = 2.56 MHz (RF channel spacing)
• fRF = 1799.68 MHz (RF frequency)
The VCO range is 2050 MHz to 4100 MHz. Therefore:
• LO DIV = 2 (LO_DIV_SEL = 1)
• fVCO = LO DIV × 1799.68 MHz = 3599.36 MHz
In order to keep the frequency of the prescaler below 3000 MHz:
• PLL_DIV = 2 (PLL_DIV_SEL = 1)
The desired stepsize at RF is 2.56 MHz, so:
• fPFD = 2.56 MHz
• fVCO, stepsize = PLL_DIV × fPFD = 5.12 MHz
Using the reference frequency along with the required fPFD gives:
• RDIV = 24
• NINT = 703
NINT ≥75; therefore, select the 8/9 prescaler.
fN= 3599.36 MHz/(2 × 8) = 224.96 MHz < 375 MHz
This example shows that Integer mode operation gives sufficient resolution for the required stepsize.
8.4.3 Integer and Fractional Mode Selection
The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO)
frequency is an integer multiple of fPFD, then select integer mode otherwise select fractional mode. In Integer
mode, the feedback divider ratio is an integer, and the fraction is zero. Thus, bits corresponding to the fractional
control in integer mode are don’t care and fractional divider functionality is disabled.
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In Fractional mode, the accuracy of the final frequency is set by 25-bit resolution. The RF stepsize is fPFD/225
which is less than 1 Hz for fPFD up to 33 MHz. The appropriate fractional control bits in the serial register must be
programmed. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM
values according to the chosen frequency band.
8.4.4 Selecting the VCO and VCO Frequency Control
To achieve a broad frequency tuning range, the TRF3722 integrates multiple VCOs. Each VCO tank uses a bank
of coarse tuning capacitor to bring VCO frequency within a few MHz of the desired value. For a given LO
frequency an appropriate VCO and capacitor array must be selected. The device integrates logic that
automatically selects an appropriate VCO and capacitor array, such that in closed loop V(TUNE) is approximately
equal to the open loop calibration reference voltage set by VCO_CAL_REF. An on-chip temperature sensor
automatically adjusts this reference voltage so that proper lock can be maintained over the temperature range.
The calibration logic is driven by a CAL_CLK signal which is scaled version of the reference frequency according
to CAL_CLK_SEL. For optimum accuracy It is recommended to limit the CAL_CLK frequency to 600 kHz.
When VCO_SEL_MODE is '0', the device automatically selects the VCO and the capacitor array. When
VCO_SEL_MODE is '1', the VCO selected by VCO_SEL is used and the logic automatically selects the capacitor
array. The VCO and capacitor array settings resulting from the calibration can be read from Register 0 - read
back register.
Automatic calibration can be disabled by setting CAL_BYPASS to '1'. In this manual calibration mode, the VCO is
selected through register bits VCO_SEL, while the capacitor array is selected through register bits VCO_TRIM.
Calibration modes are summarized in Table 3.
Table 3. VCO Calibration Modes
CAL_BYPASS VCO_SEL_MODE MAX CYCLES
CAL_CLK VCO CAPACITOR
ARRAY
0 0 46 Automatic
0 1 34 VCO_SEL Automatic
1don't care N/A VCO_SEL VCO_TRIM
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8.5 Register Maps
Table 4. Serial interface Register Summary
Bit Register 1 Register 2 Register 3 Register 4 Register 5 Register 6
Bit0
Register Address Register Address Register Address Register Address Register Address Register Address
Bit1
Bit2
Bit3
Bit4
Bit5
RDIV
NINT
NFRAC
PWD_PLL RSV RSV
Bit6 PWD_CP IB_MOD_GM
Bit7 PWD_VCO
VCO_TRIM
Bit8 PWD_VCO_MUX IB_MOD_LO
Bit9 PWD _DIV124
Bit10 PWD_PRESC
VCO_BIAS
Bit11 RSV
Bit12 PWD_OUTBUF
Bit13 PWD_LO_DIV EN_LOCKDET
Bit14 PWD_TX_DIV VCOBUF_BIAS VCO_TEST_MODE
Bit15 PWD_MOD CAL_BYPASS
Bit16 EN_EXTVCO VCOMUX_BIAS MUX_CTRLBit17 RSV
Bit18 RSV EN_ISOURCE OUTBUF_BIAS
Bit19 REF_INV LD_ANA_PREC ISOURCE_SINKB
Bit20 NEG_VCO RSV ISOURCE_TRIMBit21
ICP
PLL_DIV_SEL CP_TRISTATE
Bit22 VCO_CAL_IB
Bit23 PRSC_SEL SPEEDUP
VCO_CAL_REF LO_DIV_SEL
Bit24 RSV LD_DIG_PREC
Bit25
MOD_ORD LO_DIV_BIAS
Bit26 ICPDOUBLE VCO_SEL VCO_AMPL_CTRL
Bit27
CAL_CLK_SEL
TX_DIV_SEL
Bit28 VCO_SEL_MODE DITH_SEL VCO_VB_CTRL
Bit29 CAL_ACC DEL_SD_CLK TX_DIV_BIAS
Bit30 RSV RSV
Bit31 RSV EN_CAL EN_FRAC_MODE EN_LD_ISOURCE GAIN_CTRL
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8.5.1 Serial interface Register Definition
Table 5. Register 1
Register 1 Bit Name Reset Value Description
Bit0 ADDR<0> 1
Register Address Bits
Bit1 ADDR<1> 0
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 RDIV<0> 1
13-bit Reference Divider Value
(Rmin = 1, Rmax = 8191)
Bit6 RDIV<1> 0
Bit7 RDIV<2> 0
Bit8 RDIV<3> 0
Bit9 RDIV<4> 0
Bit10 RDIV<5> 0
Bit11 RDIV<6> 0
Bit12 RDIV<7> 0
Bit13 RDIV<8> 0
Bit14 RDIV<9> 0
Bit15 RDIV<10> 0
Bit16 RDIV<11> 0
Bit17 RDIV<12> 0
Bit18 RSV 0 Reserved
Bit19 REF_INV 0 Invert Reference Clock Polarity; 1 = use falling edge
Bit20 NEG_VCO 1 VCO polarity control; 1 = negative slope (negative Kv)
Bit21 ICP<0> 0 Program charge pump DC current:
[00000] = 1.94 mA
[11111] = 0.47 mA
[01010] = 0.97 mA
Bit22 ICP<1> 1
Bit23 ICP<2> 0
Bit24 ICP<3> 1
Bit25 ICP<4> 0
Bit26 ICPDOUBLE 0 1 = Set ICP to double the current
Bit27 CAL_CLK_SEL<0> 0 Multiplication or division factor to create VCO calibration clock from
the PFD frequency:
[0000] = Fastest ( Rdiv / 128)
[1111] = Slowest (Rdiv x 128), [1000] = Default (1x Rdiv)
Bit28 CAL_CLK_SEL<1> 0
Bit29 CAL_CLK_SEL<2> 0
Bit30 CAL_CLK_SEL<3> 1
Bit31 RSV 0 Reserved
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CAL_CLK_SEL[3..0]: Set the frequency divider value used to derive the VCO calibration clock from the reference
frequency.
Table 6. CAL_CLK_SEL Scaling Factor Setting
CAL_CLK_SEL Scaling Factor CAL_CLK_SEL Scaling Factor
1111 1/128 0111 NA
1110 1/64 0110 2
1101 1/32 0101 4
1100 1/16 0100 8
1011 1/8 0011 16
1010 1/4 0010 32
1001 1/2 0001 64
1000 1 0000 128
ICP[4..0]: Set the charge pump current.
Table 7. Charge Pump Current Set-Point
ICP[4..0] Current (mA) ICP[4..0] Current (mA)
00 000 1.94 10 000 0.75
00 001 1.76 10 001 0.72
00 010 1.62 10 010 0.69
00 011 1.49 10 011 0.67
00 100 1.38 10 100 0.65
00 101 1.29 10 101 0.63
00 110 1.21 10 110 0.61
00 111 1.14 10 111 0.59
01 000 1.08 11 000 0.57
01 001 1.02 11 001 0.55
01 010 0.97 11 010 0.54
01 011 0.92 11 011 0.52
01 100 0.88 11 100 0.51
01 101 0.84 11 101 0.50
01 110 0.81 11 110 0.48
01 111 0.78 11 111 0.47
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Table 8. Register 2
Register 2 Bit Name Reset Value Description
Bit0 ADDR<0> 0
Register Address Bits
Bit1 ADDR<1> 1
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 NINT<0> 0
PLL N-Divider Value
Bit6 NINT<1> 0
Bit7 NINT<2> 0
Bit8 NINT<3> 0
Bit9 NINT<4> 0
Bit10 NINT<5> 0
Bit11 NINT<6> 0
Bit12 NINT<7> 1
Bit13 NINT<8> 0
Bit14 NINT<9> 0
Bit15 NINT<10> 0
Bit16 NINT<11> 0
Bit17 NINT<12> 0
Bit18 NINT<13> 0
Bit19 NINT<14> 0
Bit20 NINT<15> 0
Bit21 PLL_DIV_SEL<0> 1 Select division ratio of divider in front of prescaler
[00] = 1X, [01] = div2, [10] = div4
Bit22 PLL_DIV_SEL<1> 0
Bit23 PRSC_SEL 1 Select precaler modulus: [0] = 4/5, [1] =8/9
Bit24 RSV 0 Reserved
Bit25 RSV 0
Bit26 VCO_SEL<0> 0 Selects between the four integrated VCOs
[00] = lowest frequency, [11] = highest frequency
Bit27 VCO_SEL<1> 1
Bit28 VCO_SEL_MODE 0 Single VCO auto-calibration mode: [1] = active
Bit29 CAL_ACC<0> 0 Error count during the cap array calibration
[00] = 0, [01] = 1/32, [10] = 1/64, [11] =1/128)
Bit30 CAL_ACC<1> 0
Bit31 EN_CAL 0 Initiate VCO auto-calibration, resets automatically
46
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Table 9. Register 3
Register 3 Bit Name Reset Value Description
Bit0 ADDR<0> 1
Register Address Bits
Bit1 ADDR<1> 1
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 NFRAC<0> 0
Fractional PLL N-Divider
0 to 0.99999 in fractional mode
Bit6 NFRAC<1> 0
Bit7 NFRAC<2> 0
Bit8 NFRAC<3> 0
Bit9 NFRAC<4> 0
Bit10 NFRAC<5> 0
Bit11 NFRAC<6> 0
Bit12 NFRAC<7> 0
Bit13 NFRAC<8> 0
Bit14 NFRAC<9> 0
Bit15 NFRAC<10> 0
Bit16 NFRAC<11> 0
Bit17 NFRAC<12> 0
Bit18 NFRAC<13> 0
Bit19 NFRAC<14> 0
Bit20 NFRAC<15> 0
Bit21 NFRAC<16> 0
Bit22 NFRAC<17> 0
Bit23 NFRAC<18> 0
Bit24 NFRAC<19> 0
Bit25 NFRAC<20> 0
Bit26 NFRAC<21> 0
Bit27 NFRAC<22> 0
Bit28 NFRAC<23> 0
Bit29 NFRAC<24> 0
Bit30 RSV 0 Reserved
Bit31 RSV 0
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Table 10. Register 4
Register 4 Bit Name Reset Value Description
Bit0 ADDR<0> 0
Register Address Bits
Bit1 ADDR<1> 0
Bit2 ADDR<2> 1
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 PWD_PLL 0 Power -down all PLL blocks: (1 = off)
Bit6 PWD_CP 0 Power-down Charge Pump: (1=off)
Bit7 PWD_VCO 0 Power-down VCO: (1=off)
Bit8 PWD_VCO_MUX 0 Power-down VCO Mux blocks: (1=off)
Bit9 PWD _DIV124 0 Power-down the div 1,2,4 in the PLL f/b path: (1=off)
Bit10 PWD_PRESC 0 Power-down Prescaler: (1=off)
Bit11 RSV 1 Reserved
Bit12 PWD_OUTBUF 1 Power-down Ouptut Buffer: (1=off)
Bit13 PWD_LO_DIV 1 Power-down LO divider block: (1=off)
Bit14 PWD_TX_DIV 1 Power-down TX divider block: (1=off)
Bit15 PWD_MOD 1 Power-down modulator block: (1=off)
Bit16 EN_EXTVCO 0 Enable external VCO input buffer: (1 = enabled)
Bit17 RSV 0 Reserved
Bit18 EN_ISOURCE 0 Enable offset current at CP output (frac-n mode only).
Bit19 LD_ANA_PREC<0> 0 Control precision of Analog Lock Detector:
[00] = H/H (High), [01] = L/L (Low), [10] = H/L , [11] = L/L
Bit20 LD_ANA_PREC<1> 0
Bit21 CP_TRISTATE<0> 0 Set the charge pump output in Tristate mode:
[00] = Off, [01] = Down, [10] = Up, [11] = Tristate
Bit22 CP_TRISTATE<1> 0
Bit23 SPEEDUP 0 Enable fast turn on/off time of bias blocks.
Bit24 LD_DIG_PREC 0 Lock detector precision (increases sampling time if set to 1)
Bit25 MOD_ORD<0> 1 Modulator order (1-4). Not used in integer mode
(defaul 3rd order + dither)
Bit26 MOD_ORD<1> 0
Bit27 MOD_ORD<2> 1
Bit28 DITH_SEL 0 Dither Mode: [0] = pseudo-random, [1] = constant
Bit29 DEL_SD_CLK<0> 0 DS modulator clock delay. Frac-n mode only.
[00] = Min delay, [11] = max delay
Bit30 DEL_SD_CLK<1> 1
Bit31 EN_FRAC_MODE 0 Enable Frac-n mode when set to 1
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Table 11. Register 5
Register 5 Bit Name Reset Value Description
Bit0 ADDR<0> 1
Register Address Bits
Bit1 ADDR<1> 0
Bit2 ADDR<2> 1
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 RSV 0 Reserved
Bit6 IB_MOD_GM<0> 0 Adjust modulator bias current gm
Bit7 IB_MOD_GM<1> 1
Bit8 IB_MOD_LO<0> 0 Adjust modulator BB and LO bias current
Bit9 IB_MOD_LO<1> 1
Bit10 VCO_BIAS<0> 0
Adjust VCO bias reference current
Bit11 VCO_BIAS<1> 0
Bit12 VCO_BIAS<2> 0
Bit13 VCO_BIAS<3> 1
Bit14 VCOBUF_BIAS<0> 0 Adjust VCO buffer reference current
Bit15 VCOBUF_BIAS<1> 1
Bit16 VCOMUX_BIAS<0> 0 Adjust VCO Mux reference current
Bit17 VCOMUX_BIAS<1> 1
Bit18 OUTBUF_BIAS<0> 0 Adjust output buffer current
Bit19 OUTBUF_BIAS<1> 1
Bit20 RSV 0 Reserved
Bit21 RSV 1
Bit22 VCO_CAL_IB 0 Bias current for CAL reference voltage: [0] = PTAT, [1] = Constant
Bit23 VCO_CAL_REF<0> 0 VCO calibration reference voltage adjustment
[000] = 0.9 V, [111] = 1.4 V
[011] = recommended = 1.11 V
Bit24 VCO_CAL_REF<1> 0
Bit25 VCO_CAL_REF<2> 1
Bit26 VCO_AMPL_CTRL<0> 0 Adjusts the signal level at the VCO_MUX input:
[00] =max, [11] = min
Bit27 VCO_AMPL_CTRL<1> 1
Bit28 VCO_VB_CTRL<0> 0 Adjusts the VCO core bias voltage:
[00] = 1.2 V, [01] = 1.35 V, [10] = 1.5 V, [11] = 1.65 V
Bit29 VCO_VB_CTRL<1> 1
Bit30 RSV 0 Reserved
Bit31 EN_LD_MON_ISOURCE 1 Enable monitoring of LD to turn on Isource; recommend [0] =
Isource ctrl
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Table 12. Register 6
Register 6 Bit Name Reset Value Description
Bit0 ADDR<0> 0
Register Address Bits
Bit1 ADDR<1> 1
Bit2 ADDR<2> 1
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 RSV 0 Reserved
Bit6 RSV 0
Bit7 VCO_TRIM<0> 0
VCO capacitor array control bits;
used in manual cal mode
Bit8 VCO_TRIM<1> 0
Bit9 VCO_TRIM<2> 0
Bit10 VCO_TRIM<3> 0
Bit11 VCO_TRIM<4> 0
Bit12 VCO_TRIM<5> 1
Bit13 EN_LOCKDET 0 Enable monitor of lock detector output for autocal mode
Bit14 VCO_TEST_MODE 0 Counter mode, measure max and min freq for each VCO
Bit15 CAL_BYPASS 0 Bypass auto-cal; sets VCO_SEL and VCO_TRIM from Serial
interface
Bit16 MUX_CTRL<0> 1 Select signal for test output:
[001] = LD, [010] = NDIV, [100] = RDIV, [110] = A_counter
Bit17 MUX_CTRL<1> 0
Bit18 MUX_CTRL<2> 0
Bit19 ISOURCE_SINKB 0 Offset current polarity
Bit20 ISOURCE_TRIM<0> 0 Adjust Isource bias current in frac-n mode.Bit21 ISOURCE_TRIM<1> 0
Bit22 ISOURCE_TRIM<2> 1
Bit23 LO_DIV_SEL<0> 0 Adjust LO path divider:
[00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8
Bit24 LO_DIV_SEL<1> 0
Bit25 LO_DIV_BIAS<0> 0 Adjust LO divider bias current:
[00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA
Bit26 LO_DIV_BIAS<1> 1
Bit27 TX_DIV_SEL<0> 0 Adjust TX path divider.
Bit28 TX_DIV_SEL<1> 1 [00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8
Bit29 TX_DIV_BIAS<0> 0 Adjust TX divider bias current:
[00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA
Bit30 TX_DIV_BIAS<1> 1
Bit31 GAIN_CTRL 0 Modulator gain control: [0] = Default, [1] = High Gain
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Table 13. READBACK Mode Summary Serial interface Map
Bit Register 0 RDBK
Bit0
Register Address Register Address
Bit1
Bit2
Bit3
Bit4
Bit5 CHIP_ID
N/C
Bit6
Bit7
NU
Bit8
Bit9
Bit10
Bit11
Bit12 R_SAT_ERR
Bit13
COUNT
VCO_TRIM
Bit14
Bit15
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21 VCO_SELBit22
Bit23
Bit24
Bit25
Bit26
Bit27 MUX_COUNT
Bit28 RB_REGBit29
Bit30
Bit31 MUX_COUNT RB_ENABLE
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Table 14. Register 0 (Readback Only)
Register 0 Bit Name Reset Value Description
Bit0 ADDR<0> 0
Register Address Bits
Bit1 ADDR<1> 0
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 CHIP_ID<0> 1 Chip ID
Bit6 CHIP_ID<1> 0
Bit7 NU x
Not Used
Bit8 NU x
Bit9 NU x
Bit10 NU x
Bit11 NU x
Bit12 R_SAT_ERR x R-div saturation error for cal
Bit13 COUNT<0>/NU x
VCO frequency counter high when
MUX_COUNT = 0 and VCO_TEST_MODE = 1
VCO frequency counter low when
MUX_COUNT = 1 and VCO_TEST_MODE = 1
Autocal results for VCO_TRIM and VCO_SEL when
VCO_TEST_MODE = 0
Bit14 COUNT<1>/NU x
Bit15 COUNT<2>/VCO_TRIM<0> x
Bit16 COUNT<3>/VCO_TRIM<1> x
Bit17 COUNT<4>/VCO_TRIM<2> x
Bit18 COUNT<5>/VCO_TRIM<3> x
Bit19 COUNT<6>/VCO_TRIM<4> x
Bit20 COUNT<7>/VCO_TRIM<5> x
Bit21 COUNT<8>/VCO_SEL<0> x
Bit22 COUNT<9>/VCO_SEL<1> x
Bit23 COUNT<10>/VCO_SEL<2> x
Bit24 COUNT<11> x
Bit25 COUNT<12> x
Bit26 COUNT<13> x
Bit27 COUNT<14> x
Bit28 COUNT<15> x
Bit29 COUNT<16> x
Bit30 COUNT<17> x
Bit31 MUX_COUNT x [0] = max freq count, [1] = min freq count
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Table 15. Register RDBK (Write Register for Readback)
RDBK Bit Name Reset Value Description
Bit0 ADDR<0> 0
Register Address Bits
Bit1 ADDR<1> 0
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1
Bit4 ADDR<4> 0
Bit5 N/C 0
Bit6 N/C 0
Bit7 N/C 0
Bit8 N/C 0
Bit9 N/C 0
Bit10 N/C 0
Bit11 N/C 0
Bit12 N/C 0
Bit13 N/C 0
Bit14 N/C 0
Bit15 N/C 0
Bit16 N/C 0
Bit17 N/C 0
Bit18 N/C 0
Bit19 N/C 0
Bit20 N/C 0
Bit21 N/C 0
Bit22 N/C 0
Bit23 N/C 0
Bit24 N/C 0
Bit25 N/C 0
Bit26 N/C 0
Bit27 MUX_COUNT 0 [0] = max freq count, [1] = min freq count
Bit28 RB_REG<0> x Three LSBs of the address for the register that is being read:
[001] = Register 1
[110] = Register 6
Bit29 RB_REG<1> x
Bit30 RB_REG<2> x
Bit31 RB_ENABLE 1 Puts device in Readback mode
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8.5.1.1 BIAS SETTINGS
Optimum TRF7322 bias settings used in the performance measurements are shown in Table 16.
Table 16. Register Settings With Optimized Bias Set Used in the Performance Measurement.
REGISTER BITS TYPICAL OPERATING
MODE [256MHz-2GHz],
INT MODE
TYPICAL OPERATING
MODE [2GHz - 3GHz],
INT MODE
TYPICAL OPERATING
MODE [3GHz -
4.1GHz], INT MODE
LOW POWER MODE,
INT MODE FRACTIONAL MODE
REGISTER 1 RDIV x x x x x
REGISTER 1 REF_INV 0 0 0 0 0
REGISTER 1 NEG_VCO 1 1 1 1 1
REGISTER 1 ICP 0 0 0 0 0
REGISTER 1 ICPDOUBLE 0 0 0 0 0
REGISTER 1 CAL_CLK_SEL 13 13 13 13 15
REGISTER 2 NINT x x x x x
REGISTER 2 PLL_DIV_SEL x x x x x
REGISTER 2 PRSC_SEL x x x x x
REGISTER 2 VCO_SEL x x x x x
REGISTER 2 VCO_SEL_MODE x x x x x
REGISTER 2 CAL_ACC 0 0 0 0 0
REGISTER 2 EN_CAL 1 1 1 1 1
REGISTER 3 NFRAC 0 0 0 0 x
REGISTER 4 PWD_PLL 0 0 0 0 0
REGISTER 4 PWD_CP 0 0 0 0 0
REGISTER 4 PWD_VCO 0 0 0 0 0
REGISTER 4 PWD_VCO_MUX 0 0 0 0 0
REGISTER 4 PWD _DIV124 0 0 0 0 0
REGISTER 4 PWD_PRESC 0 0 0 0 0
REGISTER 4 PWD_OUTBUF 0 0 0 1 0
REGISTER 4 PWD_LO_DIV 0 0 0 1 0
REGISTER 4 PWD_TX_DIV 0 0 0 0 0
REGISTER 4 PWD_MOD 0 0 0 0 0
REGISTER 4 EN_EXTVCO 0 0 0 0 0
REGISTER 4 EN_ISOURCE 0 0 0 0 1
REGISTER 4 LD_ANA_PREC 0 0 0 0 3
REGISTER 4 CP_TRISTATE 0 0 0 0 0
REGISTER 4 SPEEDUP 0 0 0 0 0
REGISTER 4 LD_DIG_PREC 0 0 0 0 0
REGISTER 4 MOD_ORD 5 5 5 5 4
REGISTER 4 DITH_SEL 0 0 0 0 0
REGISTER 4 DEL_SD_CLK 2 2 2 2 0
REGISTER 4 EN_FRAC_MODE 0 0 0 0 1
REGISTER 5 IB_MOD_GM 3 3 2 0 3
REGISTER 5 IB_MOD_LO 0 1 0 0 0
REGISTER 5 VCO_BIAS 15 15 15 15 15
REGISTER 5 VCOBUF_BIAS 2 2 2 2 2
REGISTER 5 OUTBUF_BIAS 2 2 2 0 2
REGISTER 5 VCOMUX_BIAS 2 2 2 2 2
REGISTER 5 VCO_CAL_IB 0 0 0 0 0
REGISTER 5 VCO_CAL_REF 3 3 3 3 3
REGISTER 5 VCO_AMPL_CTRL 0 0 0 0 0
REGISTER 5 VCO_VB_CTRL 3 3 3 3 3
REGISTER 5 EN_LD_ISOURCE 0 0 0 0 0
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Table 16. Register Settings With Optimized Bias Set Used in the Performance Measurement. (continued)
REGISTER BITS TYPICAL OPERATING
MODE [256MHz-2GHz],
INT MODE
TYPICAL OPERATING
MODE [2GHz - 3GHz],
INT MODE
TYPICAL OPERATING
MODE [3GHz -
4.1GHz], INT MODE
LOW POWER MODE,
INT MODE FRACTIONAL MODE
REGISTER 6 VCO_TRIM x x x x x
REGISTER 6 EN_LOCKDET 0 0 0 0 0
REGISTER 6 VCO_TEST_MODE 0 0 0 0 0
REGISTER 6 CAL_BYPASS 0 0 0 0 0
REGISTER 6 MUX_CTRL 1 1 1 1 5
REGISTER 6 ISOURCE_SINKB 0 0 0 0 0
REGISTER 6 ISOURCE_TRIM 4 4 4 4 7
REGISTER 6 LO_DIV_SEL x x x x x
REGISTER 6 LO_DIV_BIAS 2 2 2 0 2
REGISTER 6 TX_DIV_SEL x x x x x
REGISTER 6 TX_DIV_BIAS 1 1 1 0 1
REGISTER 6 GAIN_CTRL 0 0 0 0 0
LO OUTN
RF OUT
LO OUTP
EXT VCO
REFERENCE
CLOCK
LE
DATA
READ BACK
PD
LD
BBI N IN BBI P IN
BBQ N IN BBQ P IN
VTUNE
CP OUT
3.3V
Supply
5V or 3.3V
Supply
VCC_MOD1
VCC_MOD4
VCC_MOD3
VCC_MOD2
VCC_LO1
VCC_DIG
VCC_PLL
VCC_LO_OUT
VCC_LO2
VCC_VCO
VCC_TNK
VCC_MOD4
VCC_MOD1
VCC_MOD2
VCC_VCO
VCC_LO1
VCC_DIG
VCC_PLL
VCC_LO_OUT
VCC_LO2
VCC_MOD3
1K
FB23
C44
1.0uF
C56
0.1nF
1K
FB17
C18
4.7pF
C11
4.7pF
C12 47pF
C62
1.0uF
C42
1.0uF
1K
FB24
1K
FB18
C53
4.7pF
C27
10uF
R41
200
1 2
C54
0.1nF
C48
0.1nF
R26
49.9
1K
FB10
C7 47pF
C38
1.0uF
C60
1.0uF
1K
FB19
C43
1.0uF
C47
0.1nF
R12
49.9
C41
1.0uF
C63
4.7pF
1K
FB20
C64
0.1nF
C32
4.7pF
R13
49.9
R15
49.9
C40
1.0uF
C25
10uF
C46
0.1nF
1K
FB21
C45
0.1nF
C52
1.0uF
C31
4.7pF
1K
FB11
R16
49.9
C37
1.0uF
C39
1.0uF
U1
TRF3722
PD
1
RDBK
2
LD
3
VCC_DIG
4
GND
5
VCC_LO1
6
GND
7
BBQ_N
8
NC1
9
BBQ_P
10
GND
11
NC2
12
NC3 13
VCC_MOD1 14
GND 15
VCC_MOD2 16
GND 17
RFOUT 18
GND 19
GND 20
VCC_MOD3 21
GND 22
VCC_MOD4 23
NC4 24
NC5 25
GND 26
BBI_P 27
NC6 28
BBI_N 29
GND 30
EXT_VCO 31
VCC_TK 32
VCC_VCO 33
VTUNE 34
VCC_LO2 35
NC7 36
GND
37
LO_OUTN
38
LO_OUTP
39
GND
40
PWRPAD
49
CP_OUT
41
VCC_PLL
42
GND
43
REFIN
44
GND
45
LE
46
DATA
47
CLK
48
1K
FB22
1K
FB16
C29
4.7pF
C28
4.7pF
R22
49.9
C55
4.7pF
55
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 135 shows a typical application schematic for the TRF3722.
Figure 135. TRF3722 Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
Table 17 lists the pin termination requirements and interfacing for the circuit.
Table 17. Termination Requirements and Interfacing
PIN NAME DESCRIPTION
47 DATA 4WI data input: digital input, high impedance
2 RDBK Readback output; digital output pins can source or sink up to 8 mA of current
3 LD Lock detector digital output, as configured by MUX_CTRL
8,10,27,29 BBI_P, BBI_N, BBQ_P,
BBQ_N In-phase and quadrature baseband differential baseband signals. Typical 0.25V common mode is
needed
18 RFOUT Modulator RF output: must be ac-coupled and can drive 50 Ωload
31 EXT_VCO External local oscillator input: high impedance, normally ac-coupled. If unused terminate to 50 ohms load
38,39 LO_OUTP, LO_OUTN Local oscillator output: open-collector output. A pull-up resistor is LO_OUT required, normally ac-coupled.
44 REFIN Reference clock input: high impedance, normally ac-coupled
46 LE Serial interface latch enable: digital input, high impedance
48 CLK Serial interface clock input: digital input, high impedance
47 DATA Serial interface data input: digital input, high impedance
50 W50 W
50 W50 W
50 W50 W
50 W50 W
DAC348x / DAC38J8X
TRF3722
S
0/90
~
57
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9.2.2 Detailed Design Procedures: DAC to Modulator Interface Network
Digital-to-analog converter (DAC) can interface directly with the TRF3722 modulator. The common-mode voltage
of the DAC and the modulator baseband inputs should be properly maintained. With the proper interface
network, the common-mode voltage of the DAC can be translated to the proper common-mode voltage of the
modulator. The TRF3722 common-mode voltage is typically 0.25 V, and is ideally suited to interface with the
DAC3482/3484 (DAC348x) and DAC38J8x family. The interface network is shown in Figure 136.
Figure 136. DAC348x Interface with the TRF3722 Modulator
The DAC348x requires a load resistance of 25 Ωper branch to maintain its optimum voltage swing of 1-VPP
differential with a 20-mA max current setting. The load of the DAC is separated into two parallel 50-Ωresistors
placed on the input and output side of the low-pass filter. This configuration provides the proper resistive load to
the DAC while also providing a convenient 50-Ωsource and load termination for the filter.
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9.2.3 Application Curves: DAC34H84 with TRF3722 Modulator Performance
The cascaded combination of the DAC34H84 and TRF3722 modulator yields excellent system parameters
suitable for high-performance applications. Figure 137 and Figure 138 show 152.9 MHz IF adjacent channel
power ratio (ACPR) performance.
• Mode integer
• PFD: 3.2 MHz
• Reference: 153.6 MHz
• LO = 1689.6 MHz
• IF = 152.9 MHz
• RF= 1842.5 MHz
Figure 137. 152.9 MHz IF, DAC34H84 + TRF3722 20 MHz
LTE ACPR
Figure 138. 152.9 MHz IF, 6 Carrier MC-GSM DAC34H84 +
TRF3722 ACPR Performance
10 Power Supply Recommendations
The TRF3722 is powered by supplying a nominal 3.3 V and 5 V. It can also be powered using only 3.3V supply.
Proper RF bypassing should be placed close to each power supply pin. Ground pin connections should have at
least one ground via close to each ground pin to minimize ground inductance. The PowerPAD™ must be tied to
ground, preferably with the recommended ground via pattern to provide a good thermal conduction path to the
alternate side of the board and to provide a good RF ground for the device. (Refer to Layout Guidelines section
for additional information.)
DC Blocking
Capacitor
RF Out
Capacitor
REFIN
RF Out
VCC
Note: Ensure good RF microstrip or stripline
traces are used to connect the external
components to the REFIN, RF and LO output pins
Notes:
1.Ensure all components are connected to a
common RF/DC ground plane with plenty of vias
2. Ensure a low impedance VCC plane is
connected to all VCC terminals
GND
LD
VCC_DIG
VCC_LO1
GND
NC
BBQ_P
BBQ_N
VCC_MOD1
VCC_MOD2
RFOUT
VCC_MOD3
VCC_MOD4
VCC_TK
VTUNE
NC
BBI_P
NC
GND
GND
GND
GND
GND
GND
GND
PD
RDBK
NC
NC
GND
NC
NC
EXT_VCO
VCC_LO2
VCC_VCO
BBI_N
1
2
3
4
5
6
7
8
9
10
11
12
44
45
46
47
48
39
40
41
42
43
37
38
36
35
34
33
32
31
30
29
28
27
26
25
DATA
GND
CP_OUT
VCC_PLL
LO_OUTP
GND
CLK
LO_OUTN
REFIN
LE
GND
GND
25
14
13
15
19
18
16
17
20
21
22
23
24
RF &DC
Bypass
Capacitors
RF &DC
Bypass
Capacitors
Baseband
Terminations
Baseband
Terminations
RF &DC
Bypass
Capacitors
PLL Loop
Filter
RF &DC
Bypass
Capacitors
VCC
VCC
VCC
VCC
VCC
LO Out
59
TRF3722
www.ti.com
SLWS245B –MAY 2014–REVISED FEBRUARY 2017
Product Folder Links: TRF3722
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
Layout of the application board significantly impacts the analog performance of the TRF3722 device. Noise and
high-speed signals should be prevented from leaking onto power-supply terminals or analog signals. The
TRF3722 device is fitted with a ground slug on the back of the package that must be soldered to the printed
circuit board (PCB) ground with adequate ground vias to ensure a good thermal and electrical connection. The
ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground.
Additional ground vias may be added if space allows. Follow these recommendations:
• Place supply decoupling capacitors physically close to the device, on the same side of the board. Isolate
supply terminals with a ferrite bead.
• Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal
lines. Place reference plane vias or decoupling capacitors near any signal line reference transition.
• Power planes should not overlap each other or high-speed signal lines.
• Isolate REFIN routing from loop filter lines, control lines, and other high-speed lines.
11.2 Layout Example
Figure 139. Layout
60
TRF3722
SLWS245B –MAY 2014–REVISED FEBRUARY 2017
www.ti.com
Product Folder Links: TRF3722
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Feb-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TRF3722IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TRF3722
IRGZ
TRF3722IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TRF3722
IRGZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Feb-2017
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TRF3722IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
TRF3722IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Feb-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TRF3722IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6
TRF3722IRGZT VQFN RGZ 48 250 213.0 191.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Feb-2017
Pack Materials-Page 2
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