Wideband, Dual Rx Mixers
with Integrated IF Amplifiers
Data Sheet
ADRF6658
Rev. A Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Wideband, dual-channel, active downconversion mixers
Low distortion, fast settling, IF DGAs
RF input frequency range: 690 MHz to 3.8 GHz
Programmable baluns on RF inputs
For RF = 1950 MHz, IF = 281 MHz, high linearity mode
Voltage conversion gain, including IF filter loss:
−5 dB to +26.5 dB
Input IP3: 29 dBm at minimum DGA gain
Input P1dB: 12 dBm at minimum DGA gain
SSB NF: 13 dB at maximum DGA gain
Output IP3: 40 dBm at maximum DGA gain
Output P1dB: 19 dBm at maximum DGA gain
Channel isolation: 52 dB
Differential and single-ended LO input modes
Differential IF output impedance: 100 Ω
Flexible power-down modes for low power operation
Power-up time after enabling channels: 100 ns, typical
Programmable via a 3-wire serial port interface (SPI)
Single 3.3 V supply
High linearity mode: 440 mA
Low power mode: 260 mA
APPLICATIONS
Cellular base stations and wireless infrastructure receivers
(W-CDMA, TD-SCDMA, WiMAX, GSM, LTE, PCS, DCS, DECT)
Active antenna systems
PTP radio link down converters
Wireless LANs and CATV equipment
GENERAL DESCRIPTION
The ADRF6658 is a high performance, low power, wideband,
dual-channel radio frequency (RF) downconverter with
integrated intermediate frequency (IF) digitally controlled
amplifiers (DGAs) for wideband, low distortion base station
radio receivers.
The dual Rx mixers are doubly balanced Gilbert cell mixers
with high linearity and excellent image rejection. Both mixers
convert 50 Ω RF inputs to open-collector broadband IF outputs.
Internal tunable baluns on the RF inputs enable suppression of
RF signal harmonics and attenuation of out-of-band signals
before the mixer inputs, reducing input reflections and out-of-
band interference signals. A flexible local oscillator (LO)
architecture allows the use of differential or single-ended LO
signals.
The dual-channel IF DGAs are based on the ADL5201 and
ADL5202 and have a fixed, differential output impedance of
100 Ω. The gain is adjustable over a 31.5 dB range with a 0.5 dB
step size via the on-chip SPI, or through independent, 6-bit
parallel ports that support latch functionality. Each channel,
from the mixer inputs to the IF amplifier outputs, together with
an LC interstage band-pass filter, achieves a maximum voltage
conversion gain of 26.5 dB.
Fabricated with the Analog Devices, Inc., high speed SiGe
process, the ADRF6658 is available in a compact, 7 mm ×
7 mm, 48-lead LFCSP package, and operates over the −40°C to
+105°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
MIXA
MIXB
+22dB
ADRF6658
100Ω
+22dB
0dB TO 31.5dB
100Ω
MIX
A
V
DD
AGND
MIX
A
RF
IN
MIX
B
RF
IN
DV
DD
MIX
B
V
DD
LO
IN
+
LO
IN
–
LOV
DD
DATA
MIX
B
OUT+ MIX
B
OUT–
DGA
A
V
DD
IF
B
OUT+
IF
B
OUT–
LE
MIX
A
OUT+ MIX
A
OUT–
IF
A
OUT+
IF
A
OUT–
SDO
B0 TO B5
A0 TO A5
LATCH A
0dB TO 31.5dB
CLK
CONTROL
REGISTERS
LATCH
A
LATCH
B
DGA
A
IN– DGA
A
IN+
DGA
B
IN– DGA
B
IN+
CH
A
EN
CH
B
EN
LATCH B
12223-001
DGA
B
V
DD
ADRF6658 Data Sheet
Rev. A | Page 2 of 31
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Supplemental Information for Mixers and IF DGAs .............. 5
Timing Specifications .................................................................. 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
Dual Mixer Cores ....................................................................... 13
DGA Basic Structure .................................................................. 13
Serial Input Shift Registers ........................................................ 14
Program Modes .......................................................................... 14
Register Maps .................................................................................. 15
Register 0 Through Register 4 .................................................. 18
Register 5 ..................................................................................... 19
Register 6 ..................................................................................... 20
Register 7 ..................................................................................... 21
Register 8 Through Register 12 ................................................ 22
Register 13 ................................................................................... 23
Register 14 ................................................................................... 24
Register 15 ................................................................................... 25
Applications Information .............................................................. 26
Basic Connections ...................................................................... 26
Input Tuning ............................................................................... 26
Register Initialization Sequence ............................................... 26
Standard Register Settings ......................................................... 27
Readback ..................................................................................... 27
Daisy-Chain Mode ..................................................................... 28
IF Filter ........................................................................................ 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
11/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Total Current, Low Power Mode Parameter,
Table 1 ................................................................................................ 4
Change to Figure 4 ........................................................................... 8
Changes to Mixer A Enabled Section and Mixer B Enabled
Section .............................................................................................. 23
Changes to Figure 51 Caption ...................................................... 31
1/15—Revision 0: Initial Version
Data Sheet ADRF6658
Rev. A | Page 3 of 31
SPECIFICATIONS
MIXAVDD = MIXBVDD = DVDD = LOVDD = DGAAVDD = DGABVDD = 3.3 V ± 5%; AGND = 0 V. TA = TMIN to TMAX. The operating
temperature range = −40°C to +105°C. Parameters are measured on a standard test circuit with an IF filter; fRF = 1.95 GHz, RF input
power (PRF) = −10 dBm, fLO = 2.231 GHz, LO input power (PLO) = 0 dBm, and fIF = 281 MHz, using standard register settings. For IP2 and
IP3 measurements, fRF1 = 1.949 GHz and fRF2 = 1.951 GHz, maximum DGA gain, high linearity mode, unless otherwise noted. RSOURCE =
50 Ω, RLOAD = 100 Ω, differential.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
OPERATING CONDITIONS
RF Input Frequency 690 3800 MHz
LO Power Level −6 0 +6 dBm
LO Frequency
690
4100
MHz
CHANNEL CHARACTERISTICS
RF Input Return Loss −12 dB Register 13, Bits[DB12:DB7] programmed
according to RF frequency
IF Output Return Loss −10 dB Within IF filter passband
IF Lower Cutoff Frequency1 10 MHz f−3dB, MIXxOUTy connected to DGAxINy through a
dc block capacitor
IF Upper Cutoff Frequency 520 MHz f−3dB, MIXxOUTy connected to DGAxINy through a
dc block capacitor
Voltage Conversion Gain 26.5 dB Maximum DGA gain
Voltage Conversion Gain −5 dB Minimum DGA gain
Input P1dB
High Linearity Mode 12 dBm Register 13, Bits[DB24:DB22] = 4
Low Power Mode 4 dBm Register 13, Bits[DB24:DB22] = 1
Second Order Input Intercept (IIP2)
49
dBm
P
RF
= 0 dBm per tone, minimum DGA gain, high
linearity mode
Third Order Input Intercept (IIP3) PRF = 0 dBm per tone, minimum DGA gain
High Linearity Mode 29 dBm
Low Power Mode 17 dBm
SSB NF High linearity mode
RF = 855 MHz
12.8
dB
RF = 1950 MHz 13 dB
RF = 3795 MHz 14.4 dB
With a 5 dBm Blocker 25 dB
LO to RF Leakage −30 dBm
LO to IF Leakage −40 dBm
RF to IF Leakage −50 dBc Relative to IF output level
2 LO − 2 RF −55 dBc
3 LO − 3 RF −55 dBc
IF Output and LO Leakage
Intermodulation Spur
−70 −100 dBc fLO = 3.249 GHz, fRF = 3.5 GHz, IF DGA output power
(PIFOUT) = 9 dBm, fSPUR = 237 MHz and 265 MHz
Channel Isolation
52
dB
f
RF
= 1.95 GHz, f
LO
= 2.231 GHz, maximum DGA gain
Mixer V to I Bias Adjustment Effects Register 13, Bits[DB24:DB22] changing from 4 to 1
Amplitude Variation 0.19 dB
Gain Step 0.5 dB
Gain Conformance Error 0.05 dB Any two adjacent steps
Phase Conformance Error 0.5 Degrees Any two adjacent steps
Output P1dB 19 dBm Maximum DGA gain
Output IP3 40 dBm Maximum DGA gain
Differential Output Impedance 100 Ω
Second Harmonic Level −65 dBc At 2 V p-p
Third Harmonic Level −65 dBc At 2 V p-p
ADRF6658 Data Sheet
Rev. A | Page 4 of 31
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, VINH 1.17 3.6 V
Input Low Voltage, VINL −0.5 +0.63 V
Input Current, IINH/IINL ±1 µA
Input Capacitance, C
IN
2
pF
LOGIC OUTPUTS SDO (Pin 32)
Output High Voltage, VOH VLOGIC − 0.4 V VLOGIC selected with Register 5, Bit DB24
Output High Current, I
OH
500
µA
Output Low Voltage, VOL 0.4 V IOL = 500 µA
POWER SUPPLIES
DV
DD
3.15
3.3
3.45
V
MIXAVDD, MIXBVDD, DGAAVDD,
DGABVDD, and LOVDD
DVDD The voltages on these pins must equal DVDD
External IFXOUT± Pull-Up Supply DVDD V
Mixer Current in High Linearity
Mode
80 mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 4
Mixer Current in Low Power Mode 40 mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 1
IF DGA Current 140 mA Per amplifier
Total Current Dual Rx enabled
High Linearity Mode 440 550 mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 4
Low Power Mode 260 mA Mixer V to I bias (Register 13, Bits[DB24:DB22]) = 1
Low Power Sleep Mode 450 1000 µA
Standby Mode 65 mA Both mixers and DGAs in standby mode
TIMING2
Channel Power-Up from Standby
Mode After Changing State of
CHAEN or CHBEN
100
400
ns
From standby mode to normal operation
1 DC-coupled; lower cutoff frequency determined mostly by external components.
2 Not tested in production; guaranteed by characterization.
Data Sheet ADRF6658
Rev. A | Page 5 of 31
SUPPLEMENTAL INFORMATION FOR MIXERS AND IF DGAS
MIXAVDD = MIXBVDD = DVDD = LOVDD = DGAAVDD = DGABVDD = 3.3 V ± 5%; AGND = 0 V. TA = TMIN to TMAX. The operating
temperature range = −40°C to +105°C. Parameters are measured on a standard test circuit with an IF filter; fRF = 1.95 GHz, PRF =
−10 dBm, fLO = 2.231 GHz, and fIF = 281 MHz, using standard register settings, maximum DGA gain, high linearity mode, unless
otherwise noted. For IP2 and IP3 measurements, fRF1 = 1.949 GHz and fRF2 = 1.951 GHz, minimum DGA gain.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
MIXER CHARACTERISTICS
Voltage Conversion Gain 7 dB
Input P1dB
High Linearity Mode
12
dBm
Low Power Mode 4 dBm
Second-Order Input Intercept (IIP2) 55 dBm 0 dBm per tone, minimum DGA gain
Third-Order Input Intercept (IIP3) 0 dBm per tone, minimum DGA gain
High Linearity Mode 29 dBm
Low Power Mode 17 dBm
SSB NF
RF = 1950 MHz 12 dB
LO to RF Leakage −30 dBm
LO to IF Leakage −40 dBm
RF to IF Leakage
−50
dBc
Relative to IF output level
IF DGAs
Voltage Gain 22 dB
Gain Step
0.5
dB
Gain Conformance Error 0.05 dB Any two adjacent steps
Phase Conformance Error 0.5 Degrees Any two adjacent steps
Output P1dB 19 dBm
Output IP3 (OIP3) 40 dBm
Bandwidth 520 MHz
SSB NF 7 dB
Second Harmonic Level −65 dBc At 2 V p-p
Third Harmonic Level −65 dBc At 2 V p-p
ADRF6658 Data Sheet
Rev. A | Page 6 of 31
TIMING SPECIFICATIONS
MIXAVDD = MIXBVDD = DVDD = LOVDD = DGAAVDD = DGABVDD = 3.3 V ± 5%; AG ND = 0 V. 1.8 V and 3.3 V logic levels used. TA = TMIN
to TMAX, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LE Setup Time t1 20 ns
DATA to CLK Setup Time t2 10 ns
DATA to CLK Hold Time t3 10 ns
CLK High Duration t4 25 ns
CLK Low Duration
t
5
25
ns
CLK to LE Setup Time t6 10 ns
LE Pulse Width t7 20 ns
CLK Low to SDO Output Valid t8 20 ns During readback
Timing Diagram
Figure 2. SPI Write Operation Timing Diagram
Figure 3. SPI Readback Operation Timing Diagram
CLK
DATA
LE
LE
DB31 (MSB)
DB30 DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3) DB0 (LS B)
(CONTROL BIT C1)
t1
t
2
t
3
t7
t6
t
4
t
5
DB3
(CONTROL BIT C4)
12223-002
12223-103
CLK
DATA
LE
t
8
READBACK
ADDRESS
READ D ATA
FROM OLD
REGISTER (MSB)
READ D ATA
FROM OLD
REGISTER
READ D ATA
FROM OLD
REGISTER (LSB)
READ D ATA
FRO M NE W
REGISTER
READ D ATA
FRO M NE W
REGISTER (LSB)
SDO
REGISTER 5: NEW DATA
(NEW REGISTER ADDRESS I N RE ADBACK ADDRESS FI E LD)
REGISTER 5: OLD DATA
(OLD REGISTERADDRESS IN RE ADBACK ADDRESS FIE LD) REGI ST ER 5: NEW DATA
(NEW REGISTER ADDRESS I N RE ADBACK ADDRESS FI E LD)
NEXT OPERATION
READ D ATA
FRO M NE W
REGISTER (MSB)
Data Sheet ADRF6658
Rev. A | Page 7 of 31
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
Supply Voltage Pins1 to GND2 −0.3 V to +3.9 V
Supply Voltage Pins1 to DVDD −0.3 V to +0.3 V
Digital Input Output (I/O) Voltage to GND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to DVDD + 0.3 V
RF Input Power 20 dBm
LO Input Power 10 dBm
ESD Ratings
Human Body Model (HBM) 1.5 kV
Field Induced Charged Device Model
(FICDM)
500 V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature
150°C
Thermal Resistance (θJA), with Exposed
Pad Soldered
27.26°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature
40 sec
1 The supply voltage pins include MIXAVDD, DVDD, MIXBVDD, DGABVDD, LOVDD, and
DGAAVDD.
2 GND = AGND = DGND = 0 V
3 The digital I/O pins include LATCHA, CHAEN, CHBEN, LATCHB, B5 to B0, LE, CLK,
DATA, SDO, and A0 to A5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The ADRF6658 is a high performance RF integrated circuit,
and it is ESD sensitive. Take proper precautions for handling
and assembly.
ESD CAUTION
ADRF6658 Data Sheet
Rev. A | Page 8 of 31
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 MIXAVDD Supply for Mixer A. The voltage level on this pin must be equal to that on DVDD. Place decoupling capacitors
to the ground plane as close as possible to this pin.
2 MIXARFIN RF Input for Mixer A. This pin has an input impedance of 50 Ω.
3 AGND Analog Ground. This is a ground return path for MIXAVDD (Pin 1).
4 LATCHA Channel A Latch Buffer Control. This pin controls the latch buffer between the 6-bit parallel control port
(Pin A0 to Pin A5) and the Channel A DGA.
5 CHAEN Channel A Enable. This pin provides external control of the power-down mode for Channel A.
6 CREG Internal Regulator Output. A capacitor of approximately 220 nF must be placed between this output and
ground.
7 DVDD Supply Connection for Digital Circuits. The voltage on this pin ranges from 3.15 V to 3.45 V. Place decoupling
capacitors to the ground plane as close as possible to this pin.
8 CHBEN Channel B Enable. This pin provides external control of the power-down mode for Channel B.
9
LATCH
B
Channel B Latch Buffer Control. This pin controls the latch buffer between the 6-bit parallel control port
(Pin B0 to Pin B5) and the Channel B DGA.
10 AGND Analog Ground. This is a ground return path for MIXBVDD (Pin 12).
11 MIXBRFIN RF Input for Mixer B. This pin has an input impedance 50 Ω.
12 MIXBVDD Supply for Mixer B. The voltage level on this pin must be equal to that on DVDD. Place decoupling capacitors
to the ground plane as close as possible to this pin.
13, 14
MIXBOUT+,
MIXBOUT−
Differential Mixer B Outputs, 300 Ω Impedance. A pull-up inductor must be connected to each of these
output pins. The values of the inductors depend on the IF frequency range.
15 AGND Analog Ground. This is a ground return path for DGABVDD (Pin 18).
16, 17 DGABIN−,
DGABIN+
Differential DGA B Inputs, 300 Ω Impedance.
18
DGA
B
V
DD
Supply for DGA B. The voltage level on this pin must be equal to that on DV
DD
. Place decoupling capacitors
to the analog ground plane as close as possible to this pin.
19, 20, 21,
22, 23, 24
B5, B4, B3, B2,
B1, B0
6-Bit Parallel Control Ports for DGA B.
25, 26 IFBOUT+,
IFBOUT−
Channel B Differential IF Outputs, 100 Ω Resistance from DGA B. Requires a pull-up inductor dependent on
IF frequency.
27
LE
Latch Enable. When the LE input pin goes low, data is clocked into the 32-bit shift register on the CLK rising
edge. Only the last 32 bits are retained. When the LE input pin goes high, the data stored in the shift register
is loaded into one of the 16 registers, the relevant latch being selected by the four LSBs of the 32-bit word.
NOTES
1. CONNECT T HE EXPOSED PAD TO GROUND T HROUG H A
LOW IMP E DANCE PATH, US ING AN ARRAY OF VIAS FROM
THE PAD TO THE P CB GRO UND P LANE.
MIXAVDD
MIXBOUT+ MIXAOUT+
IFAOUT+
IFAOUT–
AGND
LOVDD
SDO
LOIN+
LOIN–
DATA
CLK
LE
IFBOUT–
IFBOUT+
MIXARFIN
AGND
LATCHA
CHAEN
CREG
DVDD
CHBEN
LATCHB
AGND
MIXBRFIN
MIXBVDD
MIXBOUT–
AGND
DGABIN–
DGABIN+
DGABVDD
B5
B4
B3
B2
B1
B0
MIXAOUT–
AGND
DGAAIN–
DGAAIN+
DGAAVDD
A4
A3
A2
A1
A0
A5
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
16
15
14
13
44
45
46
47
48
43
42
41
40
39
38
37
ADRF6658
TOP VIEW
(No t t o Scale)
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
12223-003
Data Sheet ADRF6658
Rev. A | Page 9 of 31
Pin No. Mnemonic Description
28 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
29 DATA Serial Data Input. The serial data input is loaded MSB first with the four LSBs control the destination for the
data. This input is a high impedance CMOS input.
30 LOIN− Complimentary External Local Oscillator Input. In differential LO mode, this pin is one of the input pins of
the differential input and must be ac-coupled. In single-ended LO mode, terminate this pin to ground with a
capacitor.
31 LOIN+ External Local Oscillator Input. In differential LO mode, this pin one of the input pins of the differential input.
In single-ended LO mode, it is the input of the LO signal. AC couple this pin.
32 SDO Serial Data Output. This output is used to read back the register content.
33
LOV
DD
Power Supply for the LO Path. The voltage level on this pin must be equal to that on DVDD. Place
decoupling capacitors to the ground plane as close as possible to this pin.
34 AGND Analog Ground. This is a ground return path for LOVDD (Pin 33).
35, 36 IFAOUT−,
IFAOUT+
Channel A Differential IF Outputs, 100 Ω Resistance from DGA A. Requires a pull-up inductor dependent on
IF frequency.
37, 38, 39,
40, 41, 42
A0, A1, A2, A3,
A4, A5
6-Bit Parallel Control Ports for DGA A.
43 DGAAVDD Supply for DGA A. The voltage level on this pin must be equal to that on DVDD. Place decoupling capacitors
to the analog ground plane as close as possible to this pin.
44, 45 DGAAIN+,
DGAAIN−
Differential DGA A Inputs, 300 Ω Impedance.
46
AGND
Analog Ground. This is a ground return path for DGA
A
V
DD
(Pin 43).
47, 48 MIXAOUT−,
MIXAOUT+
Differential Mixer A Outputs, 300 Ω Impedance. A pull-up inductor must be connected to each of these
output pins. The values of the inductors depend on the IF frequency range.
49 EP Exposed Pad. Connect the exposed pad to ground through a low impedance path, using an array of vias
from the pad to the PCB ground plane.
ADRF6658 Data Sheet
Rev. A | Page 10 of 31
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Power Gain vs. RF Frequency and Balun Codes
Figure 6. RF Input Return Loss vs. Frequency and Balun Codes
Figure 7. Power Conversion Gain vs. RF Frequency for
DGA Gain Code = 0, 32, and 63
Figure 8. Noise Figure vs. RF Frequency and DGA Gain Codes
Figure 9. Input P1dB (IP1dB) vs. RF Frequency, DVDD at Maximum Gain
Figure 10. IP1dB vs. RF Frequency and DVDD at Minimum Gain
0
5
10
15
20
25
30
POWER GAIN (dB)
RF FREQUENCY (GHz)
BALUN CODE 0
BALUN CODE 1
BALUN CODE 2
BALUN CODE 3
BALUN CODE 4
BALUN CODE 5
BALUN CODE 6
BALUN CODE 7
0.51.01.52.02.53.03.54.0
12223-005
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
RF INPUT RETURN LOSS (dB)
FREQUENCY (GHz)
BALUN CODE 0
BALUN CODE 1
BALUN CODE 10
BALUN CODE 11
BALUN CODE 100
BALUN CODE 101
BALUN CODE 110
BALUN CODE 111
12223-006
–20
–15
–10
–5
0
5
10
15
20
25
30
POWER CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
DGA GAIN CODE: 32, +105°C
DGA GAIN CODE: 63, +105°C
DGA GAIN CODE: 32, +25°C
DGA GAIN CODE: 63, +25°C
DGA GAIN CODE: 0, +105°C
DGA GAIN CODE: 0, +25°C
DGA GAIN CODE: 0, –40°C
DGA GAIN CODE: 32, –40°C
DGA GAIN CODE: 63, –40°C
0.51.01.52.02.53.03.54.0
12223-007
10
15
20
25
30
35
40
45
50
NOISE FIGURE (dB)
RF FREQUENCY (GHz)
DGA GAIN CODE: 0, +105°C
DGA GAIN CODE: 32, +105°C
DGA GAIN CODE: 63, +105°C
DGA GAIN CODE: 0, +25°C
DGA GAIN CODE: 32, +25°C
DGA GAIN CODE: 63, +25°C
DGA GAIN CODE: 0, –40°C
DGA GAIN CODE: 32, –40°C
DGA GAIN CODE: 63, –40°C
0.51.01.52.02.53.03.54.0
12223-008
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
IP1dB
A
T MAXIMUM GAIN (dBm)
RF FREQUENCY (GHz)
+105°C 3.6V
+105°C 3.3V
+105°C 3.0V
+25°C 3.6V
+25°C 3.3V
+25°C 3.0V
–40°C 3.6V
–40°C 3.3V
–40°C 3.0V
12223-009
0.51.01.52.02.53.03.54.0
RF FREQUENCY (GHz)
6
8
10
12
14
16
18
IP1dB
A
T MIN GAIN (dBm)
+105°C 3.6V
+105°C 3.3V
+105°C 3.0V
+25°C 3.6V
+25°C 3.3V
+25°C 3.0V
–40°C 3.6V
–40°C 3.3V
–40°C 3.0V
12223-010
Data Sheet ADRF6658
Rev. A | Page 11 of 31
Figure 11. IIP3 vs. RF Frequency
Figure 12. Power Conversion Gain vs. IF Frequency
Figure 13. OIP3 vs. IF Frequency
Figure 14. Channel Isolation
Figure 15. RF Feedthrough at Maximum Gain, Relative to IF Output Level
Figure 16. LO Feedthrough at Maximum Gain, Relative to IF Output Level
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
5
10
15
20
25
30
35
40
II P 3 ( dBm50)
RF FREQ UE NCY (GHz)
II P 3 DG A GAI N CODE: 0 IN TO NE P OW = –25dBm
II P 3 DG A GAI N CODE: 24 IN TONE POW = –15dBm
II P 3 DG A GAI N CODE: 32 IN TONE POW = –10dBm
II P 3 DG A GAI N CODE: 41 IN TONE POW = –5dBm
II P 3 DG A GAI N CODE: 63 IN TO NE P OW = 0dBm
12223-011
150 200 250 300 350 400
IF FREQUENCY (GHz)
POWE R CO NV E RS IO N GAI N ( dBm100)
–70
–60
–50
–40
–30
30
–20
20
–10
10
0
DGA0
DGA24
DGA32
DGA41
DGA63
12223-012
–50
–40
–30
–20
–10
0
10
20
30
40
50
50 100 150 200 250 300 350 400 450 500
OI P 3 ( dBm100)
IF FREQUENCY (MHz)
DGA0 I N TONEPOW = –25dBm +25°C 3. 3V
DGA24 I N TONEP OW = –15dBm +25°C 3. 3V
DGA32 I N TONEP OW = –10dBm +25°C 3. 3V
DGA41 I N TONEP OW = –5dBm +25°C 3. 3V
DGA63 I N TONEP OW = –0dBm +25°C 3. 3V
12223-013
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
10
20
30
40
50
60
70
80
90
100
CHANNEL ISOLATION (dB)
RF FREQ UE NCY (GHz)
CHANNEL A
CHANNEL B
12223-014
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
RF FREQ UE NCY (GHz)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
RF FEE DTHROUGH L E V EL (d Bc)
3.0V 0°C
3.0V + 105°C
3.0V + 25°C
3.0V –40°C
3.0V + 85°C
3.3V 0°C
3.3V + 105°C
3.3V + 25°C
3.3V –40°C
3.3V + 85°C
3.6V 0°C
3.6V + 105°C
3.6V + 25°C
3.6V –40°C
3.6V + 85°C
12223-015
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
LO FEEDTHROUGH LEVEL (dBc)
LO FREQUENCY (GHz)
3.0V 0°C
3.0V + 105°C
3.0V + 25°C
3.0V –40°C
3.0V + 85°C
3.3V 0°C
3.3V + 105°C
3.3V + 25°C
3.3V –40°C
3.3V + 85°C
3.6V 0°C
3.6V + 105°C
3.6V + 25°C
3.6V –40°C
3.6V + 85°C
12223-016
ADRF6658 Data Sheet
Rev. A | Page 12 of 31
Figure 17. IF DGA Output Return Loss Measured Through Balun
Figure 18. IP1dB vs. RF Frequency and V to I Bias
Figure 19. DGA Step Accuracy
Figure 20. Gain Step Response, Maximum Gain to Minimum Gain
Figure 21. Gain Step Response, Minimum Gain to Maximum Gain
Figure 22. Channel Enable Response
IF RETURN LOSS (dB)
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
12223-017
0.51.01.52.02.53.03.54.0
0
2
4
6
8
10
12
14
16
IP1dB (dBm)
RF FREQUENCY (GHz)
BIAS = 0
BIAS = 1
BIAS = 2
BIAS = 3
BIAS = 4
BIAS = 5
12223-018
–1.40
–1.20
–1.00
–0.80
–0.60
–0.40
–0.20
0
0.20
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
DEVI
A
TION (dB)
DGA GAIN CODE
DEVIATION FROM IDEAL LEVEL
STEP ACCURAC Y
12223-019
LATCHx
IFxOUT
12223-020
5ns/DIV
REGISTER 14, A5 TO A0 OR B5 TO B0
IFxOUT
12223-021
5ns/DIV
CHxEN
IFxOUT
12223-022
10ns/DIV
Data Sheet ADRF6658
Rev. A | Page 13 of 31
THEORY OF OPERATION
DUAL MIXER CORES
The ADRF6658 provides two double balanced active mixers
based on the Gilbert cell design. The RF inputs, LO inputs, and
IF outputs of the mixers are all differential, providing maximum
usable bandwidth at the input and output ports. The mixers are
designed for a 50 Ω input impedance and a 300 Ω output
impedance, with external RF chokes connected to the supply.
Mixer RF Inputs
At the RF input of each channel (MIXARFIN and MIXBRFIN) of
the ADRF6658, a tunable balun converts the single-ended input
signal into differential form, to be fed into the mixer section.
The tuning of the balun is controlled by the two sets of register
bits: RF balun input cutoff (CIN) in Register 13, Bits[DB12:DB10],
and RF balun output cutoff (COUT) in Register 13, Bits[DB9:DB7].
Mixers Bias Circuit
A band gap reference circuit generates the reference currents
used by mixers. The bias current for the LO circuit of the
mixers can be programmed via the mixer LO IBIAS bits in
Register 13, Bits[DB26:DB25].
RF Voltage to Current (V to I) Converter
The differential RF input signal, created in the internal balun
from the external, single-ended RF signal provided to the
MIXARFIN or MIXBRFIN pin, is applied to a V to I converter that
converts the differential input voltage to output currents. The
V to I converter provides a 50 Ω input impedance. The V to I
section bias current can be adjusted up or down using the mixer
V to I IBIAS bits in Register 13, Bits[DB24:DB22]. Adjusting the
current up improves IIP3 and P1dB input, but degrades the SSB
NF. Adjusting the current down improves the SSB NF but
degrades IIP3 and the input P1dB. The conversion gain remains
nearly constant over a wide range of mixer V to I IBIAS settings,
allowing the device to be adjusted dynamically without
affecting the conversion gain. A setting of 3 or 4 provides a
good trade-off of IP3 and SSB NF.
Mixer Power-Down
It is possible to power down either mixer by programming the
relevant bits. For Channel A, program the Mixer A enable bit
(Bit DB5 in Register 13). For Channel B, program the Mixer B
Enable bit (Bit DB4 in Register 13). The mixers can be powered
down independently.
Mixer Output
The mixer load uses a pair of 150 Ω resistors connected to the
positive supply. This provides a 300 Ω differential output resistance,
which matches the input impedance of the internal IF DGA
block. Pull the mixer outputs to the positive supply externally
using a pair of RF chokes, or by using an output transformer
with the center tap connected to the positive supply. The mixer
outputs are dc-coupled, and they can operate up to
approximately 500 MHz into a 300 Ω load.
DGA BASIC STRUCTURE
In each channel, the ADRF6658 has a built-in, variable gain
DGA. Each amplifier consists of a digitally controlled, passive
attenuator of a 300 Ω differential input impedance followed by a
highly linear transconductance amplifier with feedback. The
output impedance of the gain amplifier is 100 Ω, differentially.
The input impedance of the DGA block matches the output
impedance of the internal mixer.
The gain of each amplifier can be programmed independently,
either via the DGA control bits in the serial control registers, or
via an external, 6-bit parallel port. The choice of serial or
parallel control is determined by the DGA control select bit, Bit
DB22 in Register 7. Programming this bit to 0 allows the gain to
be set by programming Register 14 (Bits[DB17:DB12] for
Channel A, or Bits[DB11:DB6] for Channel B). When the DGA
Control Select bit is set to 1, the gain is set by the binary value
applied to the 6-bit, external parallel control interface (Pin A5
through Pin A0 for Channel A, or Pin B5 through Pin B0 for
Channel B).
Figure 23. Simplified Schematic
Input System
The dc voltage level at the inputs of each amplifier is set to
approximately 1.1 V by two independent internal voltage
reference circuits. These reference circuits are not accessible and
cannot be adjusted.
Power down each amplifier by setting Bit DB5 and Bit DB4.in
Register 14. When powered down, the total current of each
amplifier reduces to 10 μA (typical). The dc level at the inputs
remains at approximately 1.6 V, regardless of the state of
Bit DB5 and Bit DB4 in Register 14.
+22dB 100Ω
EXTERNAL
CONTROL
PARALLEL
PORT LATCH
CONTROL
LATCH
DGA
CONTROL
SELECT
REGISTER 7
VIN+
VIN–
VOUT+
VOUT–
ATTENUATOR
0dB TO 31.5d B +22dB
300Ω
MUX
INTERNAL
CONTROL
REGISTER 14
12223-040
ADRF6658 Data Sheet
Rev. A | Page 14 of 31
Output Amplifier
The gain of the output amplifier is set to 22 dB when driving
a 100 Ω load. The input resistance of this amplifier is set to
300 Ω in matched condition, and its output resistance is set to
100 Ω. If the load resistance is different from 100 Ω, use the
following equations to determine the resulting gain and
input/output resistances:
AV = 0.15 × (3800)/RL
RIN = (3800 + RL)/(1 + 0.15 × RL)
S21 (Gain) = 2 × RIN/(RIN + 300) × AV
ROUT = (2000 + RS)/(1 + 0.09 × RS)
where:
Av is the voltage gain.
RL is the load resistance.
RIN is the input resistance.
S21 is the insertion gain.
ROUT is the output resistance.
Note that at the maximum attenuation setting, RS, as seen by
the output amplifier, is the output resistance of the attenuator,
which is 300 Ω. However, at minimum attenuation, RS is the
source resistance connected to the DGA inputs of the device.
The dc current to the outputs of each amplifier is supplied
through two external chokes. The inductance of the chokes and
the resistance of the load, in parallel with the output resistance
of the device, adds a low frequency pole to the response. The
parasitic capacitance of the chokes adds to the output capacitance
of the device. This total capacitance, in parallel with the load
and output resistance, sets the high frequency pole of the
device. Generally, the larger the inductance of the choke, the
higher its parasitic capacitance. Therefore, this trade-off must
be considered when the value and type of the choke are
selected.
For an operation frequency of 45 MHz to 500 MHz when
driving a 100 Ω load, 1.2 μH chokes with a self resonant
frequency (SRF) of 375 MHz or higher are recommended (such
as the 0805AF-122XJRB from Coilcraft). If higher value chokes
are used, gain peaking may occur at the low frequency end of
the pass band due to ac-coupling in the internal feedback path
of the amplifier. The supply current of each amplifier takes
about 80 mA through the two chokes combined in high linearity
mode (Register 13, Bits[DB24:DB22] = 4). The current increases
with temperature at approximately 2.5 mA per 10°C.
Gain Control
The gain of each amplifier can be adjusted using the parallel
control interface or the SPI. The gain step size is 0.5 dB. Each
amplifier has a maximum gain of +22 dB (Code 0) to −9.5 dB
(Code 63). LATCHA or LATCHB must be at or transitioned to
logic high after programming through the parallel or serial
interface for the gain change to take effect.
The NF of each amplifier is approximately 4 dB at the maxi-
mum gain setting, relative to a 300 Ω source. This represents
approximately 22.5 nV√Hz noise referred to the amplifier
output. The NF increases as the gain is reduced, and this increase
is equal to the reduction in gain. The linearity of the device
measured at the output is first-order independent of the gain
setting. From −4 dB to +22 dB gain, OIP3 is approximately
40 dBm into a 100 Ω load at 281 MHz (+1 dBm per tone). At
gain settings below −4 dB, OIP3 drops to approximately 28 dBm.
SERIAL INPUT SHIFT REGISTERS
Data is clocked into the 32-bit shift register on each rising edge
of CLK, MSB first. Data transfers from the shift register to one
of sixteen latches on the rising edge of LE. The destination latch
is determined by the state of the four control bits (C4, C3, C2,
and C1) in the shift register. As shown in Figure 2, these are the
four LSBs: DB3, DB2, DB1, and DB0. See Table 6 for the truth
table for these bits. Figure 27 through Figure 42 describe the
function of the control registers in the ADRF6658. The Register
Maps section summarizes how to program the latches.
PROGRAM MODES
Table 6 and Figure 27 through Figure 42 show how to set up the
program modes in the ADRF6658.
Table 6. Truth Table for Control Bits C4, C3, C2, and C1
Control Bits
Register
C4 C3 C2 C1
0 0 0 0 Register 0 (R0)
0 0 0 1 Register 1 (R1)
0 0 1 0 Register 2 (R2)
0 0 1 1 Register 3 (R3)
0 1 0 0 Register 4 (R4)
0 1 0 1 Register 5 (R5)
0 1 1 0 Register 6 (R6)
0 1 1 1 Register 7 (R7)
1 0 0 0 Register 8 (R8)
1 0 0 1 Register 9 (R9)
1
0
1
0
Register 10 (R10)
1 0 1 1 Register 11 (R11)
1 1 0 0 Register 12 (R12)
1 1 0 1 Register 13 (R13)
1 1 1 0 Register 14 (R14)
1 1 1 1 Register 15 (R15)
Data Sheet ADRF6658
Rev. A | Page 15 of 31
REGISTER MAPS
Figure 24. Register Summary (Register 0 Through Register 5)
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
000 0 0
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 C3(0) C2(0) C1(0)
C4(0)
0
0
0
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
000 0 0
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
C4(0)
0
0
0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
000 0 0
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(0)
C4(0)
0
0
0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
000 0 0
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(1)
C4(0)
0
0
0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
110 0 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(0)
C4(0)
1
0
0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
RA10 0 0 SDL
RESERVEDCONTROL BITS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(1)
C4(0)
RA2
RA3
RA4
RESERVED
SDO LEVEL
READBACK
ADDRES
12223-041
ADRF6658 Data Sheet
Rev. A | Page 16 of 31
Figure 25. Register Summary (Register 6 Through Register 10)
REGISTER 6
REGISTER 7
REGISTER 8
REGISTER 9
REGISTER 10
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
0 0 0 0 0
CONTROL BITS
0DCS 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 C3(1) C2(1) C1(1)
C4(0)
000
DGA CONTROL
SELECT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
0 0 0 0 0
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(0)
C4(1)
000
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
0 0 0 00
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
C4(1)
000
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
0 0 0 0 0
RESERVED
RESERVED
RESERVED
CONTROL
BITS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(0)
C4(1)
000
12223-042
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
00 1 0 0
CONTROL BITS
0 0 0 DCE 0 0 1 0 LOS 0 0 1 0 PLB 0 PLI 0 0 0 0 C3(1) C2(1) C1(0)
C4(0)
0
0
1
DAISY-CHAIN EN
PU LO BIAS
RESERVED
PU LO IN
RESERVED RESERVED RESERVED
LOIN STANDBY
Data Sheet ADRF6658
Rev. A | Page 17 of 31
Figure 26. Register Summary (Register 11 Through Register 15)
REGISTER 11
REGISTER 12
REGISTER 13
REGISTER 14
REGISTER 15
DB31 DB30 DB29DB28DB27DB26DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
000 0 0
RESERVED
RESERVED
CONTROL
BITS
0 0 0 0 0 0 0 0 0 00000 0 0 0 00 0 C3(0) C2(1) C1(1)
C4(1)
0
0
0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22DB21DB20DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
00000
CONTROL
BITS
00 0 0 0 0 0 0 0 0 00 0 0 0 0 00 0 0C3(1) C2(0) C1(0)
C4(1)
0
0
0
RESERVED
DB31 DB30 DB29 DB28DB27DB26DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16DB15DB14DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
00 MB5 MB4 MB3
CONTROL BITS
MB2 MB1 MR4 MR3 MR2 MR1 MC5 MC4 MC3 MC2 MC1 IC3 IC2 IC1 OC3 OC2 OC1 0 MAE MBE C3(1) C2(0) C1(1)
C4(1)
0
0
0
RESERVED
MIXER
LO
IBIAS
MIXER
V TO I
IBIAS
MIXER
V TO I
RDAC
MIXER
V TO I
CDAC
RF BALUN RFBALUN
MIXER A
ENABLE
MIXER B
ENABLE
CUT OFF
INPUT CUT OFF
OUTPUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
10 0 1 0
CONTROL BITS
0 0 1 0 0 0 AG6 AG5 AG4 AG3 AG2 AG1 BG6 BG5 BG4 BG3 BG2 BG1 DAEDBEC3(1) C2(1) C1(0)
C4(1)
0
0
1
DGA A
GAIN DGA B
GAIN
DGA A
ENABLE
DGA B
ENABLE
RESERVED
DGA LOW
POWER MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
00 1 0 0
CONTROL BITS
00 0 0 0 0 0 DLP 0 MSB 0 0 0 0 0 0 0 0 0 1 C3(1) C2(1) C1(1)
C4(1)
0
1
0
RESERVED RESERVED
MIXER STANBDY
RESERVED
12223-043
ADRF6658 Data Sheet
Rev. A | Page 18 of 31
REGISTER 0 THROUGH REGISTER 4
Program Register 0 through Register 4 with the assigned values as shown in the register maps, Figure 27 through Figure 31.
Figure 27. Register 0 (R0), Hexadecimal Code = 0x00000010
Figure 28. Register 1 (R1), Hexadecimal Code = 0x00000001
Figure 29. Register 2 (R2), Hexadecimal Code = 0x00000002
Figure 30. Register 3 (R3), Hexadecimal Code = 0x00000003
Figure 31. Register 4 (R4), Hexadecimal Code = 0x38000004
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
CONTROL
BITS
000 0000000000 0000001 C3(0) C2(0) C1(0)
C4(0)
0
0
0
RESERVED
12223-144
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
CONTROL
BITS
000 0000000000 0000000 C3(0) C2(0) C1(1)
C4(0)
0
0
0
RESERVED
12223-145
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
CONTROL
BITS
000 0000000000 0000000 C3(0) C2(1) C1(0)
C4(0)
0
0
0
RESERVED
12223-146
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
CONTROL
BITS
000 0000000000 0000000 C3(0) C2(1) C1(1)
C4(0)
0
0
0
RESERVED
12223-147
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
11000
RESERVED
CONTROL
BITS
000 0000000000 0000000 C3(1) C2(0) C1(0)
C4(0)
1
0
0
12223-148
Data Sheet ADRF6658
Rev. A | Page 19 of 31
REGISTER 5
Control Bits
Program Register 5 by setting Bits[C4:C1] to 0101. Figure 32
shows the input data format for programming this register.
Readback Address
The readback address bits, Bits[DB31:DB28], determine which
register content is read on the SDO output. Readback
functionality is explained in the Readback section.
SDO Output Level
Bit DB24 changes the logic level of the SDO output. When
programmed to 0, the SDO output is compatible with a 1.8 V
logic. When set to 1, the SDO output uses 3.3 V as the high
level.
Figure 32. Register 5 (R5)
DB31 DB30 DB29DB28DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
RA100 0 SDL
RESERVEDCONTROL BITS
0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0)C1(1)
C4(0)
RA2
RA3
RA4
RESERVED
SDO LEVEL
SDLSDO OUTPUT
LOGICLEVEL
01.8V
1 3.3V
READBACK
ADDRESS
RA2RA1READBACKADDRESS
0 0 REGISTER 0
01 REGISTER 1
10 REGISTER 2
1 1 REGISTER 3
00 REGISTER4
0 1 REGISTER 5
REGISTER 14
11
REGISTER 15
RA4RA3
0 0
0
0
0
0
0
1
0
0
0
1
1
1
REGISTER 6
REGISTER 7
1 0
1 1
0
01
10 0 REGISTER 8
0 1 REGISTER 9
1 0 REGISTER 10
1 1 REGISTER 11
0 0 REGISTER 12
1
1
1
1
1
0
0
0
0
1REGISTER 13
0 1
1 0
1
11
1
12223-044
ADRF6658 Data Sheet
Rev. A | Page 20 of 31
REGISTER 6
Control Bits
Program Register 6 by setting Bits[C4:C1] to 0110. Figure 33
shows the input data format for programming this register.
Daisy-Chain Enable
To enable daisy-chain mode for programming multiple devices,
set Bit DB20 to 1. This feature is described in detail in the
Daisy-Chain Mode section. Programming this bit to 0 disables
this feature.
Local Oscillator Input Buffer Standby Mode
Bit DB15 controls the standby mode of the buffer on the LO
input when both channels are disabled by pins CHAEN and
CHBEN. In this case, if the LOIN standby bit is programmed to
0, the buffer on the LO input is in low power mode. When this
bit is set to 1 while both channels are disabled, the buffer on the
LO input works in normal mode, ensuring a shorter time of
return to normal operation mode after any of the channels are
enabled.
Bit DB8 controls the power up of the LO buffer. If DB8 is set to
0, the LO buffer is disabled.
Bit DB10 provides direct control of the LO buffer power modes.
Set this bit to 1 for normal mode, and 0 for standby mode.
In normal operation mode, the LO input buffer typically
consumes about 20 mA. In standby mode, this current is
reduced to 6 mA.
Figure 33. Register 6 (R6)
12223-150
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
00 1 0 0
CONTROL BITS
0 0 0 DCE 0 0 1 0 LOS 0 0
1
0 PLB 0 PLI 0 0 0 0 C3(1) C2(1) C1(0)
C4(0)
0
0
1
DAISY CHAIN EN
PU LO BIAS
RESERVED
PU LO IN
DCEDAISY-CHAIN
ENABLE
0 DISABLED
1 ENABLED
RESERVED RESERVED RESERVED
LOS LOINBUFFER
0
LOW POWER MODE
1
ENABLED FOR NORMAL OPERATION
STANDBY
LOIN STANDBY
PU LO BIAS POWER UP LO
0
DISABLED
1
ENABLED FOR NORMAL OPERATION
BUFFER BIAS (BAND-GAP)
PU LO INPOWER-UP LO
0
DISABLED
1
ENABLED FOR NORMAL OPERATION
BUFFER
Data Sheet ADRF6658
Rev. A | Page 21 of 31
REGISTER 7
Control Bits
Program Register 7 by setting Bits[C4:C1] to 0111. Figure 34
shows the input data format for programming this register.
DGA Control Select
Bit DB22 selects the mode of control for the IF DGA. When this
bit is programmed to 0, the gain of each DGA block is set by
value of the relevant fields in Register 14: Bits[DB17:DB12] set
the DGA A gain for Channel A, and Bits[DB11:DB6] set the
DGA B gain for Channel B. When Bit DB22 in Register 7 is set
to 1, the gain is controlled by the external parallel ports: Pin A5
through Pin A0 for Channel A, and Pin B5 through Pin B0 for
Channel B.
Figure 34. Register 7 (R7)
RESERVED
RESERVED
DB31DB30 DB29 DB28 DB27 DB26 DB25DB24DB23DB22DB21DB20DB19DB18DB17 DB16DB15DB14DB13DB12 DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
000 0 0
CONTROLBITS
0DCS0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0C3(1)C2(1) C1(1)
C4(0)
0
0
0
DCSDGA CONTROL
SELECT
0 GAIN SET BYSPIREGISTER
1GAIN SET BYEXTERNAL PINS
DGA CONTROL
SELECT
12223-046
ADRF6658 Data Sheet
Rev. A | Page 22 of 31
REGISTER 8 THROUGH REGISTER 12
Program Register 8 through Register 12 with the assigned values as shown in the register maps, Figure 35 through Figure 39.
Figure 35. Register 8 (R8), Hexadecimal Code = 0x00000008
Figure 36. Register 9 (R9), Hexadecimal Code = 0x00000009
Figure 37. Register 10 (R10), Hexadecimal Code = 0x0000000A
Figure 38. Register 11 (R11), Hexadecimal Code = 0x0000000B
Figure 39. Register 12 (R12), Hexadecimal Code = 0x0000000C
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
RESERVED
CONTROL
BITS
000 00000000 00 0000000 C3(0) C2(0) C1(0)
C4(1)
0
0
0
12223-047
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
RESERVED
CONTROL
BITS
0000000000 000 0000000 C3(0) C2(0) C1(1)
C4(1)
0
0
0
12223-048
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
RESERVED
CONTROL
BITS
000 0000000000 0000000 C3(0) C2(1) C1(0)
C4(1)
0
0
0
12223-049
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
RESERVED
CONTROL
BITS
000 0000000000 0000000 C3(0) C2(1) C1(1)
C4(1)
0
0
0
12223-050
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000
RESERVED
CONTROL
BITS
000 0000000000 0000000 C3(1) C2(0) C1(0)
C4(1)
0
0
0
12223-051
Data Sheet ADRF6658
Rev. A | Page 23 of 31
REGISTER 13
Control Bits
Program Register 13 by setting Bits[C4:C1] to 1101. This
register controls the built in phase-locked loop (PLL)
synthesizer. Figure 40 shows the input data format for
programming this register.
Mixer LO Bias Current
Bits[DB26:DB25] set the value of the bias current of the mixer
LO inputs.
Mixer V to I Converter Bias Current
Bits[DB24:DB22] set the value of the V to I converter bias
current (IBIAS) used on the mixer LO input.
Mixer V to I CDAC
Bits[DB17:DB13] set the value of CDAC bits that determines
the capacitance component in the distortion correction circuit.
These bits optimize the linearity correction in the mixer V to I
converter as a function of RF frequency.
RF Balun Input Cutoff
Bits[DB12:DB10] select the input cutoff frequency of the balun
on the RF mixer input.
RF Balun Output Cutoff
Bits[DB9:DB7] select the output cutoff frequency of the balun
on the RF mixer input.
Mixer A Enabled
Bit DB5 powers up or switches off the mixer in Channel A. This
option enables power saving if the mixer is not being used in
the circuit.
Switching off Mixer A changes the supply current for this mixer
from 80 mA to 5 mA.
Mixer B Enabled
Bit DB4 powers up or switches off the mixer in Channel B. This
option enables power saving if the mixer is not being used in
the circuit.
Switching off Mixer B changes the supply current for this mixer
from 80 mA to 5 mA.
Figure 40. Register 13 (R13)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00MB5MB4MB3
CONTROL BITS
MB2MB10000MC5MC4MC3MC2MC1IC3IC2IC1OC3OC2OC10MAEMBE C3(1) C2(0) C1(1)
C4(1)
0
0
0
RESERVED RESERVED
MIXER
LO
IBIAS
MIXER
V TO I
IBIAS
MIXER
V TO I
CDAC
RF BALUN
INPUT
CUT OFF
RF BALUN
OUTPUT
CUT OFF
MIXER A
ENABLE
MIXER B
ENABLE
MBE MIXER B
ENABLED
0 DISABLED
1 ENABLED
MAE MIXER A
ENABLED
0 DISABLED
1 ENABLED
IC3 IC2 IC1 RF BALUN INPUT CU T-OFF
000
001
010
011
100
101
110
111
OC3 OC2 OC1 RF BALUN OUTPUT CUT-OFF
000
001
010
011
100
101
110
111
MB4 MIXER LO
BIAS CURRENT
MB5
0
0
1
1
0
1
0
1
200µA
300µA
500µA
700µA
MB3 MB2 MB1
0011.0mA
0101.5mA
0111.7mA
1002.0mA
1012.3mA
1 1 0 RESERVED
1 1 1 RESERVED
0010.5mA
MIXER VOLTAGE-TO-CURRENT
CONVERTER BIAS CURRENT
MC3 MC2 MC1
0011
0102
0113
... ... ... ...
10129
11030
11131
0000
MIXER VOLTAGE-TO-CURRENT
CDAC
MC4
0
0
0
...
1
1
1
0
MC5
0
0
0
...
1
1
1
0
12223-052
ABOVE 1.78GHz
ABOVE 1.78GHz
1.40GHz TO 1.78GHz
1.18GHz TO 1.40GHz
1.03GHz TO 1.18GHz
0.91GHz TO 1.03GHz
0.84GHz TO 0.91GHz
0.77GHz TO 0.84GHz
BELOW 0.77GHz
1.40GHz TO 1.78GHz
1.18GHz TO 1.40GHz
1.03GHz TO 1.18GHz
0.91GHz TO 1.03GHz
0.84GHz TO 0.91GHz
0.77GHz TO 0.84GHz
BELOW 0.77GHz
ADRF6658 Data Sheet
Rev. A | Page 24 of 31
REGISTER 14
Control Bits
Program Register 14 by setting Bits[C4:C1] to 1110. This
register controls the built in PLL synthesizer. Figure 41 shows
the input data format for programming this register.
DGA Channel A Gain Control
Bits[DB17:DB12] set the gain in the DGA block in Channel A if
the DGA control select bit (DCS, Register 7, Bit DB22) bit is 0.
The gain is set by the value of the programmed attenuator in the
DGA block in Channel A. The maximum value of the gain is
+22 dB, and the minimum value is −9.5 dB. Figure 41 shows the
corresponding values of the programmed gain and the binary
word written to Bits[DB17:DB12]. LATCHA must be at logic
low for the gain to change, and the new gain value is latched
into the DGA when LATCHA goes high.
DGA Channel A Gain Control
Bits[DB11:DB6] set the gain in the DGA block in Channel B if
the DCS bit (Register 7, Bit DB22) bit is 0. The gain is set by the
value of the programmed attenuator in the DGA block in
Channel B. The maximum value of the gain is +22 dB, and the
minimum value is −9.5 dB. Figure 41 shows the corresponding
values of the programmed gain and the binary word written to
Bits[DB11:DB6].
DGA Channel A Enable
Bit DB5 powers up or powers down the DGA block in
Channel A. To reduce the device power consumption, power
down the DGA block in Channel A if not in use.
DGA Channel B Enable
Bit DB4 powers up or powers down the DGA block in Channel B.
To reduce the device power consumption, power down the
DGA block in Channel B if not in use.
Figure 41. Register 14 (R14)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10 0 1 0
CONT ROL BITS
0 0 1 0 0 0 AG6 AG5 AG4 AG3 AG2 AG1 BG6 BG5 BG4 BG3 BG2 BG1 DAE DBE C3(1) C2(1) C1(0)
C4(1)
0
0
1
DGA A
GAIN DGA B
GAIN
DAE
DIGITAL LY CONTROL LED GAIN
AMPL IFIER IN CHANNEL A— ENABL E
0DISABLED
1ENABLED
DBE
DIGITAL LY CONTROL LED GAIN
AMPL IFIER IN CHANNEL B— ENABL E
0DISABLED
1ENABLED
AG1 DIGI T ALL Y CONTROL LED GAIN
AMPL IFIER IN CHANNEL A— GAIN VALUE
AG2
0
0
1
1
0
1
0
1
22.0dB
21.5dB
21.0dB
–9.5dB
AG3
0
0
0
1
AG4
0
0
0
1
AG5
0
0
0
1
AG6
0
0
0
1
1
1 1 20.5dB0000
GAIN DECREAS ED BY 0.5dB STEP
RESERVED
...
1...
0...
–9.0dB
...
1
...
1
...
1
...
BG1
DIGITAL LY CONTROL LED GAIN
AMPL IFIER IN CHANNEL B— GAIN VALUE
BG2
0
0
1
1
0
1
0
1
22.0dB
21.5dB
21.0dB
–9.5dB
BG3
0
0
0
1
BG4
0
0
0
1
BG5
0
0
0
1
BG6
0
0
0
1
1
1 1 20.5dB0000
GAIN DECREAS ED BY 0 .5 d B STE P
...
1...
0...
–9.0dB
...
1
...
1
...
1
...
DGA A
ENABLE
DGA B
ENABLE
12223-053
Data Sheet ADRF6658
Rev. A | Page 25 of 31
REGISTER 15
Control Bits
Program Register 15 by setting Bits[C4:C1] to 1111. This
register controls the built in DGA block.
Figure 42 shows the input data format for programming this
register.
DGAs—Low Power Mode
When set to 1, Bit DB16 enables the DGA low power mode.
When programmed to 0, both DGA blocks work in normal
mode.
In normal mode, the typical current used by each DGA block is
approximately 140 mA. In low power mode, this current
reduces to 23 mA.
Mixer Standby Mode
DB14 determines whether a mixer enters a low power mode or
completely shuts off when the channel is disabled using
Register 13, Bits DB4 and DB5. When DB14 is 0, the mixer is
powered down. When DB14 is 1, the mixer stays in a low power
mode. The band gap reference for the mixer bias circuit remains
on in either case.
Figure 42. Register 15 (R15)
12223-159
DGA LOW
POWER MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0
00 1 0 0
CONTROL BITS
0 0 0 0 0 0 0 DLP 0 MSB 0 0 0 0 0 0 0 0 0 1 C3(1) C2(1) C1(1)
C4(1)
0
1
0
RESERVED RESERVED
MIXERSTANBDY
MODE
RESERVED
DLPDIGITALLY CO NTROLL ED GAIN
0DISABLED
1ENABLED
AMPLI F I ERS— LOW PO W ER MO DE
MSM M IXER STANDBY M ODE
0MIXER TURNE D OFF W HE N CHANNE L ENABLE = 0
1MIXER IN LOW POW ER W HEN CHANNEL ENABLE = 0
ADRF6658 Data Sheet
Rev. A | Page 26 of 31
APPLICATIONS INFORMATION
Figure 43. Basic Connections
BASIC CONNECTIONS
The basic connections for the ADRF6658 are shown in Figure 43.
INPUT TUNING
Conversion gain and input return loss can be optimized for an
input frequency range
IIP3 Optimization
Input IP3 can be optimized by writing to the Mixer CDAC bits
(Register 13, Bits[DB17:DB13]). Examples of optimum settings
are listed in Table 7.
Table 7. IIP3 Optimization Settings
RF
Frequency
(MHz)
CDAC, Bits[DB17:DB13]
(Decimal Value)
IIP3 for IF DGA at
Minimum Gain
(dBm)
750 26 36
900 25 32
1950 12 29
2700 10 25
3800 3 26
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after applying correct voltages to the supply
pins, the ADRF6658 registers load in the following sequence:
1. Register 15
2. Register 14
3. Register 13
4. Register 12
5. Register 11
6. Register 10
7. Register 9
8. Register 8
9. Register 7
10. Register 6
11. Register 5
12. Register 4
13. Register 3
14. Register 2
15. Register 1
16. Register 0
IF
A
OUT+
IF
A
OUT–
1µF
3.3V
3.3V
1µF
C13
0.1µF
C16
1µF
C17
1µF
1µF
3.3V
1µF
C14
0.1µF
1µF
3.3V 1µF IN2
IN
OUT2
IF FILTER
OUT
C10
0.1µF
3.3V
3.3V
C9
0.1µF
C7
0.1µF
3.3V
C8
0.1µF
3.3V
C5
0.1µF
3.3V
C6
0.1µF
C15
0.1µF
1µF
3.3V 1µF IN
IN2
OUT
IF FILTER
OUT2
C12
0.1µF
C19
1µF
C18
1µF
MIXA
MIXB
+22dB
ADRF6658
100Ω
+22dB
0dB TO 31.5dB
100Ω
MIX
A
V
DD
AGND
RF
IN
A
RF
IN
BMIX
B
RF
IN
MIX
A
RF
IN
C
REG
DV
DD
MIX
B
V
DD
LO
IN
+
LO
IN
–
LOV
DD
DATA
MIX
B
OUT+ MIX
B
OUT–
DGA
A
V
DD
IF
B
OUT+
IF
B
OUT–
LE
MIX
A
OUT+ MIX
A
OUT–
SDO
B0 TO B5
A0 TO A5
LATCH A
0dB TO 31.5dB
CLK
CONTROL
REGISTERS
LATCH
A
LATCH
A
LATCH
B
LATCH
B
DGA
A
IN– DGA
A
IN+
DGA
B
IN– DGA
B
IN+
CH
A
EN
CH
B
EN
LATCH B
DGA
B
V
DD
SPI
INTERFACE
12 816 1713 14 918
43
36
35
32
29
28
27
25
26
44455
47
481
33
2
31
30
11
6
4 7
6
B
A
6
37 42
19 24
24 TO 19
3, 10, 15, 34, 46, EP
MUX
MUX
12223-143
Data Sheet ADRF6658
Rev. A | Page 27 of 31
STANDARD REGISTER SETTINGS
Figure 44. Register Settings for Standard Test Configuration
Figure 45. Timing Diagram for Readback Operation
READBACK
The address of the register that is read back is written to the
readback address in Register 5, Bits[DB31:DB28].
After initialization of the device, the readback address stores a
number from 0 to 15, depending on the value written to
Bits[DB31:DB28] in Register 5. If the readback is performed
after initialization but before a new value is written to the
readback address field, the data read on the serial data output
pin (the SDO pin) during the time of next write to the device
(for example, during a new value write to Register 5) is the data
stored in the register pointed to by the previous value of the
readback address field. This is shown in Figure 45.
The data from new Register N, where N = 0 to 15, is available
on the SDO output during the next write operation to the
device after setting the correct register number by programming
the readback address (Bits[DB31:DB28] in Register 5), as shown
in Figure 45. To read the register values without changing the
device settings, write a special no operation (NOP) command to
the device. The format for this command is all zeros (0x00000000).
Writing all zeros to Register 0 does not change any settings in
this register due to the internal detection circuit, but allows the
clock signal to be provided to the device so that readback can be
performed.
12223-261
CLK
DATA
LE
READBACK
ADDRESS
REGIST ER 5 : OL D DATA
(O L D REG ISTER ADDRESS IN READBACK ADDRESS FI E LD)
NEXT OPERATION
READ DATA
FROM OLD
REGI ST ER ( MSB)
READ DATA
FROM OLD
REGISTER
READ DATA
FROM OLD
REGI ST ER ( LSB)
READ DATA
FRO M NE W
REGI ST ER ( MSB)
READ DATA
FRO M NE W
REGISTER
READ DATA
FRO M NE W
REGI ST ER ( LSB)
REGI ST ER 5: NEW DATA
(NEW REGI ST ER ADDRESS IN READBACK ADDRESS FI E LD)
REGI ST ER 5: NEW DATA
(NEW REGI ST ER ADDRESS IN READBACK ADDRESS FI E LD)
SERIAL DATA
OUTPUT
12223-060
ADRF6658 Data Sheet
Rev. A | Page 28 of 31
DAISY-CHAIN MODE
In a system with one controller using the SPI for programming
multiple devices, a dedicated signal for selecting a chip is used
to address each device. In the ADRF6658, the function of chip
select input is performed by the LE pin. As the number of
devices increases, so does the number of lines used for device
selection. Additionally, as both clock and data lines are routed
from the controller outputs to the relevant inputs of each
device, the layout become more complex. Using more outputs
on the controlling device for the simple selection of different
devices may become unacceptable due to the limited number of
the controller outputs. In extreme situations, in a system with a
numerous devices, additional controllers may be necessary to
assure the correct addressing of each device.
To simplify the system, an alternative solution is the daisy-chain
function, enabled by programming Bit DB20 in Register 6 of the
ADRF6658. The daisy-chain function allows propagation of the
signal through a string of slave devices, saving multiple outputs
of the controller as well as simplifying the layout by removing
multiple selection lines. The daisy chain also removes the necessity
of connecting the data input of each slave device directly to the
controller data output. To use the daisy chain, all slave devices
must use the same SPI protocol.
Figure 46shows a traditional solution using multiple signals for
selecting each device; Figure 47 shows a system using a daisy chain.
Writing to N independent devices in a traditional system
demands programming each of the devices in sequence. As each
write operation ends at a different time, so do the changes to the
device settings. This may be a drawback for applications requiring
synchronized changes to multiple devices. When using daisy-chain
functionality, all slave devices must be programmed at the same
time. To write to selected devices only, write an NOP command
(0x00000000) to the devices requiring unchanged configuration.
This command does not change any internal register settings
of the device to which it is written.
Figure 46. System with Traditional Multiple Chip Select
Figure 47. System with Daisy-Chain Functionality
CONTROLLER
(MICROCONTROLLER,
DSP)
DEV. 1
CLK
DATA
LE
SDO
DEV. 2
DEV. 3
CLK
DATA OUT
LE1
LE2
LE3
DATA IN
CLK
DATA
LE CLK
DATA
LE
12223-061
SDO
SDO
12223-062
CONTROLLER
(MICROCONTROLLER,
DSP)
CLK
DATA OUT
LE
DATA IN
DEV. 1
CLK
DATA
LE
DEV. 2
DEV. 3
CLK
DATA
LE CLK
DATA
LE
SDO
SDO
SDO
Data Sheet ADRF6658
Rev. A | Page 29 of 31
Writing to a single, 32-bit register in each of the N devices with
daisy chain functionality enabled is possible by writing N × 32 bits
while the LE signal is kept low, then raising the LE signal. As
new register settings are written to the device on the rising edge of
the LE signal, the programmed register in multiple devices are
updated at the same time. Figure 48 shows the timing diagram
for writing to multiple devices.
During readback on a single device, the data available on the
SDO output shows the content of the registers which addresses
are currently stored in the readback address fields of the relevant
devices. In daisy-chain mode, the data is written to or read from
all the devices in sequence, as shown in Figure 49.
The data from the new Register M, where M = 0 to 15, is available
on the SDO output during the next write operation to the device
after setting the correct register number by programming the read-
back address (Bits[DB31:DB28] in Register 5), as shown in
Figure 49. To avoid changing the register settings when read-
back is performed, an NOP command (0x00000000) can be
used as the next operation.
Figure 48. Timing Diagram for Writing to Multiple Devices Using Daisy-Chain Functionality for N Devices
Figure 49. Timing Diagram for Readback from Multiple Devices Using Daisy-Chain Functionality for N Devices
CLK
DATA
LE
DEVI CE 1 D ATA
DEVI CE N D ATA
LE
12223-064
12223-065
CLK
DATA
LE
READBACK
ADDRESS
IN DEV ICE N
READBACK
ADDRESS
IN DEV ICE 1
... ... ... ...
SDO
DEVICE N: REG ISTER 5
(NEW RE ADBACK ADDRESS)
OLD REG ISTER ADDRESS IN READBACK ADDRESS FI EL D
DEVICE N NEW REGISTER ADDRESS IN RE ADBACK ADDRESS FI E LD
DEVICE N
NEW REGISTER ADDRESS IN RE ADBACK ADDRESS FI E LD
DEVICE 1
OLD REG ISTER ADDRESS IN READBACK ADDRESS FI EL D
DEVICE 1
READ DATA
DEVICE N, OLD REG ISTER READ DATA
DEVICE N, NEW REG ISTER READ DATA
DEVICE 1, NEW REGI STER
READ DATA
DEVICE 1, O LD REGI STER
DEVICE N: NEXT OPERATION DEVICE 1: NEXT O PERATION
DEVICE 1: REGI ST ER 5
(NEW RE ADBACK ADDRESS)
ADRF6658 Data Sheet
Rev. A | Page 30 of 31
IF FILTER
The IF filter used in the ADRF6658 evaluation is of a fifth order
Butterworth design, shown in Figure 50, with a center frequency of
281 MHz and a bandwidth of 200 MHz.
The filter design is optimized to produce the best flatness and
stop-band rejection at the presence of device parasitics, using
standard Electronic Industries Association (EIA) E24 values,
also known as standard 5% values.
Figure 50. IF Filter
DGAAIN+MIXAOUT+
L14
150nH
L12
120nH
L10
82nH C14
3.9pF
C12
3.3pF
C10
6.8pF
C18
11pF
L18
27nH
C16
13pF
L16
24nH
DGAAIN–
MIXAOUT–
L15
150nH
L13
120nH
L11
82nH C15
3.9pF
C13
3.3pF
C11
6.8pF
C19
11pF
L19
27nH
C17
13pF
L17
24nH
12223-066
Data Sheet ADRF6658
Rev. A | Page 31 of 31
OUTLINE DIMENSIONS
Figure 51. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADRF6658BCPZ −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP], Tray CP-48-5
ADRF6658BCPZ-RL7 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel CP-48-5
EV-ADRF6658SD1Z Evaluation Board
1 Z = RoHS Compliant Part.
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTI ON DESCRIPTI ONS
SECTION OF THIS DATA SHEET.
COM P LI ANT T O JE DE C S TANDARDS M O-220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
PIN 1
INDICATOR
4.25
4.10 SQ
3.95
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0. 05 MAX
0.02 NO M
0.20 M IN
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
10-15-2015-B
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12223-0-11/15(A)
