Philips Semiconductors eee eee eee ee ee ee ee Universal LCD driver for low multiplex Product specification PCF8566 rates CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 Power-on reset 6.2 LCD bias generator 6.3 LCD voltage selector 6.4 LCD drive mode waveforms 6.5 Oscillator 6.6 Internal clock 6.7 External clock 6.8 Timing 6.9 Display latch 6.10 Shift register 6.11 Segment outputs 6.12 Backplane outputs 6.13 Display RAM 6.14 Data pointer 6.15 Subaddress counter 6.16 Output bank selector 6.17 Input bank selector 6.18 Blinker 7 I2C-BUS DESCRIPTION 7.1 Bit transfer 7.2 Start and stop conditions 7.3 System configuration 7.4 Acknowledge 7.5 PCF8566 |?C-bus controller 76 Input filters 7.7 [2C-bus protocol 78 Command decoder 7.9 Display controller 7.10 Cascaded operation 1998 May 04 8 9 10 11 12 13 14 15 15.1 15.2 15.2.1 15.2.2 15.3 15.3.1 15.3.2 15.3.3 16 17 18 LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION CHIP DIMENSIONS AND BONDING PAD LOCATIONS PACKAGE OUTLINES SOLDERING Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO and VSO Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURGHASE OF PHILIPS |2?@ COMPONENTSPhilips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 1 FEATURES e Single-chip LCD controller/driver e Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing Selectable display bias configuration: static, Yo or 14 e Internal LCD bias generation with voltage-follower buffers e 24 segment drives: up to twelve 8-segment numeric characters; up to six 15-segment alphanumeric characters; or any graphics of up to 96 elements 24x 4-bit RAM for display data storage e Auto-incremented display data loading across device subaddress boundaries e Display memory bank switching in static and duplex drive modes e Versatile blinking modes e LCD and logic supplies may be separated e 2.5 to 6 V power supply range e Low power consumption e Power saving mode for extremely low power consumption in battery-operated and telephone applications e |2C-bus interface TTL/CMOS compatible Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers e May be cascaded for large LCD applications (up to 1536 segments possible) e Cascadable with the 40 segment LCD driver PCF8576C Optimized pinning for single plane wiring in both single and multiple PCF8566 applications e Space-saving 40 lead plastic very small outline package (VSO40; SOT 158-1) e No external components required (even in multiple device applications) Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION 2 GENERAL DESCRIPTION The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) having low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 24 segments and can easily be cascaded for larger LCD applications. The PCF8566 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I@C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF8566P DIP40 | plastic dual in-line package; 40 leads (600 mil) SOT129-1 PCF8566T VSO40_ | plastic very small outline package; 40 leads SOT158-1 1998 May 04Product specification Philips Semiconductors Universal LCD driver for low multiplex rates PCF8566 4 BLOCK DIAGRAM EseooOw cv IV OV 8y 2 YALNNOOD ssayuqqv ans YALNIOd Vivd YOLOATAS SLIG Xx ve YOLOATAS NV WvVd NV INdLno AW1dSI0 LNdNI YALSIDAY LAIHS HOLV1 AV1dSIG SLAdLNO LNANDAS AVIdSIC OF O} ZI 2S 10S weiBelp yooig 1614 ovS OL YATIOULNOO SHIL14 sna-9 41 ANdNI Yaqd00sd0 GQNVAWOOS YOLVTIIOSO YATIOYULNOO AW1dSI0 YSyNI1a ONIALL 99S849d YOLVYANAD svld do1 YW + YOLOATAS ADVLION qo1 SLAdLNO ANV1dNOvVa OLY SLY vy &b Edd |}dd edd Odd vds TOS SS, 9SO ONAS M19 a1, dda 1998 May 04Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates 5 PINNING SYMBOL PIN DESCRIPTION SDA 1 [2C-bus data input/output spa [1 U [40] 823 SCL 2 [2C-bus clock input/output set [2] faa] s22 SYNC 3 cascade synchronization ___ input/output SYNC [3 | [38] $21 CLK 4 external clock input/output ouk [4 | [37] s20 Vpp 5 positive supply voltage Vpp [6] 36] sig OSC 6 oscillator input osc [6 | 35] 818 AO 7 ao [7] [34] S17 Al 8 l2C-bus subaddress inputs Marc rag] si6 A2 9 SAO 10 |2C-bus slave address bit 0 input ve [9 32] sts Vss 11 logic ground sao [10] 31] S14 Viep 12 |LCD supply voltage Veg [11] PCF8566 [30] sis BPo 13 Vip [12] 29] $12 BPe 4 LCD backplane outputs BPo [13] 28] s11 BP1 15 Bre [14] 27] sto BP3 16 ap [i 5] 80 SO to $23 | 17 to 40 | LCD segment outputs aps [16] [25] $8 so [17 24] 87 si [18] [23] s6 s2 [19] [22] $5 s3 [20] [21] 84 MGG382 Fig.2 Pin configuration. 1998 May 04 5Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 6 FUNCTIONAL DESCRIPTION The PCF8566 is a versatile peripheral device designed to interface any microprocessor to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to 4 backplanes and up to 24 segments. The display configurations possible with the PCF8566 depend on the number of active backplane outputs required; a selection of display configurations is given in All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.3. The host microprocessor/microcontroller maintains the two-line |2C-bus communication channel with the PCF8566. The internal oscillator is selected by tying OSC (pin 6) to Vgg. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (Vpp, Vsg and Vi cp) and Table 1. to the LCD panel chosen for the application. Table 1 = Selection of display configurations ACTIVE NUMBER OF 14-SEGMENT BACKPLANE SEGMENTS 7-SEGMENT NUMERIC ALPHANUMERIC DOT MATRIX OUTPUTS 4 96 12 digits + 12 indicator | 6 characters + 12 indicator 96 dots (4 x 24) symbols symbols 3 72 9 digits + 9 indicator 4 characters + 16 indicator 72 dots (3 x 24) symbols symbols 2 48 6 digits + 6 indicator 3 characters + 6 indicator 48 dots (2 x 24) symbols symbols 1 24 3 digits + 3 indicator 1 character + 10 indicator 24 dots symbols symbols Vpp trise i R< 2c bus Vpp | Yicp 5 12 HOST _ SDA 1 17 to 40] 24 segment drives >) LCD PANEL MICRO- PROCESSOR/ -SCLI, PcFes6s (up to 96 MICRO- OSG [a bacanes > elements) CONTROLLER 6 13 to 16] 4 backplanes 7 8 9 10 11 AO |A1 |A2 |SA0!Vog MGG385 Fig.3 Typical system configuration. 1998 May 04Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates 6.1 Power-on reset 6.3. LCD voltage selector At power-on the PCF8566 resets to a defined starting The LCD voltage selector coordinates the multiplexing of condition as follows: the LCD according to the selected LCD drive configuration. The operation of the voltage selector is 1. All backplane outputs are set to Vpp controlled by MODE SET commands from the command 2. All segment outputs are set to Vop decoder. The biasing configurations that apply to the 3. The drive mode 1 : 4 multiplex with sbias is selected preferred modes of operation, together with the biasing 4. Blinking is switched off characteristics as functions of Vop = Vpp Vicp and the 5. Input and output bank selectors are reset (as defined resulting discrimination ratios (D), are given in Table 2. in Table 5) A practical value of Vo, is determined by equating Votirms) The |2C-bus interface is initialized with a defined LCD threshold voltage (Vin), typically when the LCD exhibits approximately 10% contrast. In the static 7. The data pointer and the subaddress counter are P drive mode a suitable choice is Vop > 3 Vin. Multiplex drive cleared. ratios of 1: 3 and 1: 4 with % bias are possible but the discrimination and hence the contrast ratios are smaller (/3 = 1.732 for 1:3 multiplex or /21/3 = 1.528 for 6.2 LCD bias generator 1: 4 multiplex). The advantage of these modes is a reduction of the LCD full scale voltage Vo, as follows: Data transfers on the I?C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. The full-scale LCD voltage (Vop) is obtained from Vpp Vicp. The LCD voltage may be temperature 1:3 multiplex (Vybias): compensated externally through the Vi cp supply to pin 12. Fractional LCD biasing voltages are obtained from an Vop ~ SEV sours) = 2.449V internal voltage divider of three series resistors connected between Vpp and Vicp. The centre resistor can be switched out of circuit to provide a bias voltage level for Vop = 4/3/3V the 1: 2 multiplex configuration. off (rms) 1:4 multiplex (Vebias): = 2.309V off (rms) off(rms) These compare with Vop = 3 Vottrmsy when Vabias is used. Table 2 Preferred LCD drive modes: summary of characteristics LCD DRIVE MODE | Gon oura ion yee ye D = youn Static (1 BP) static (2 levels) 0 1 oo 1: 2 MUX (2 BP) \% (3 levels) [2/4 = 0.354 410/4 = 0.791 JB = 2.236 1: 2 MUX (2 BP) 1% (4 levels) V = 0.333 J5/3 = 0.745 JB = 2.236 1: 3 MUX (3 BP) 4 (4 levels) Yq = 0.333 JB/9 = 0638 /33/3 = 1915 1:4 MUX (4 BP) 1 (4 levels) Ve = 0.333 /3/3 = 0577 B= 1732 1998 May 04 7Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 6.4 LCD drive mode waveforms The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.4. When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The PCF8566 allows use of \% or g bias in this mode as shown in Figs 5 and 6. The backplane and segment drive waveforms for the 1 : 3 multiplex drive mode (three LCD backplanes) and for the 1 : 4 multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively. ~ Tirame Vpp = LCD segments BPo VicD Vpp (on) Shy VLcD = Vpp = Sn41 VLcD (a) waveforms at driver Vop state 1 9 At any instant (t): Vetate 1(t) = Vg,(t) - Vepo(t) Von(rms) = Yo Vop (rms) ~ op Vop Vetate 2(4) = Vsn 4 (9 Vepolt) state 2 0 Voti(rms) = 9 V Vop (b) resultant waveforms at LCD segment MGG392 Fig.4 Static drive mode waveforms: Vop = Vpp Vico. 1998 May 04 8Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates + Ttrame Vpp _ T | LCD segments BPO (Vpp + Vicb)/2 ' ] f Vicp Vpp Ps 2 BP1 (Vpp + Vicp)/2 \ VLcp _ Vpp Sn VLcD Vpp Sn+1 Vicp (a) waveforms at driver Vv OO op | | At any instant (t): Vop/2 , Vetate 1(0 = Vsp (0) Vepolt) state 1 0 Von(rms) = Vopyi0 = 0.791Vo5 Vop/2 | 4 ~Vop Vstate 2(0 = Vgq{t) Vapi (0 Vv - Oo = Vop Vott(rms) = Ne = 0.354V gn Vop/2 ee state 2 0 _ | I Vop/2 -Vop (b) resultant waveforms MGG394 at LCD segment Fig.5 Waveforms for 1 : 2 multiplex drive mode with % bias: Vop = Vpp - Vicp. 1998 May 04 9Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 BPO BP1 Sn41 state 1 state 2 Vpp - Vop/3 Vpp - 2Vop/38 J Tirame ~ ! | Vicp Vpp = Vop/3 Vpp = 2Vop/3 _ VLcD Vpp Vpp - Vop Vpp - 2Vop/3 _ VLcp _ sl ] pL Vpp Vpp - Vop/3 Vpp - 2Vop/3 _ LCD segments 4 state 1 state 2 VLcD (a) waveforms at driver WVop/3 Vop/3 0 Vop/3 -2Vop/3 -V op WVop/3 Vop/3 0 Vop/3 -2Vo5)/3 -Vop (b) resultant waveforms at LCD segment At any instant (t): Vetate 1(t) = Vg,(t) - Vepo(t) Vv Von(tms) = os = 0.745V on Vetate 2(t) = Vg, (t) - Vep1() V, Voti(rms) = = = 0.333Vo5 MGG393 Fig.6 Waveforms for 1 : 2 multiplex drive mode with 1 bias: Vop = Vop Vip. 1998 May 04 10Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 BPO BP1 BP2 Sn+4 Sn+2 state 1 state 2 Vop 2Vop/3 V Tirame > Vpp LCD segments OS PS Von ~ 2Vop/3 | 0ee Vicp 4 state 1 Vp Vpp- Vop/3 VicD VicD Vpp _ Vpp - Vop/3 Vpp - 2Vop/3 _ Vicp Pt RN Yop - aves LS ee VD Vv Von/3 woe TI | 1 }e. Vpp Vpp - Vop/3 Vpp - 2Vop/3 Vicp | I Vpp Vpp - Vop/3 _ Vpp - 2Vop/3 _ VicD (a) waveforms at driver /3 _ 4 0 op Vop/3 -2V5p/3 op Vop Vop 2Vop/3 V /3 At any instant (t): Vetate 1() = Vg, (t) - Vepo(t) Vv Von(rms) = GPV38 = 0.638 Vp Vetate a(t) = Vg.(t) - Vepitt) op 0 Vop/3 op -2Vop/3 Vop Fig.7 Waveforms for 1 : 3 multiplex drive mode: Vop = Vpp Vico. V Vott(rms) = = = 0.333V gy (b) resultant waveforms at LCD segment MGG395 1998 May 04Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 BPO BP1 BP2 BP3 Sn41 Sn+2 Sn+3 state 1 state 2 Vpp Vpp - Vop/3 Vpp - 2Vop/3 _ Tirame Pr VicD Vpp Vpp = Vop/3 Vpp = 2Vop/3 _ Vicp _ Vpp Vpp = Vop/3 Vpp = 2Vop/3 _ VicD Vpp Vpp = Vop/3 Vpp - 2Vop/3 VicD Vop - 2Vop/3 VicD op Ju. JUD L, Vbb Vpp - Vop/3_ Vpp - 2Vop/3 _ VLcD Vbb Vpp - Vop/3 Vpp - 2Vop/3 _ VicD e000 state 1 Pry T1660 LCD segments Vpb Vpp - Vop/3 Vpp - 2Vop/3 _ Vicp (a) waveforms at driver Vop Vop/3 Vop/3 0 Vop/3 NV op/3 Vop Vop WNVop/3 Vop/3 0 Vop/3 -Vop/3 Vop (b) resultant waveforms at LCD segment At any instant (t): Vetate 1(t) = Vg,(t) - Vepo(t) Vv Von(rms) = +8 = 0.577Vop Vstate 200 = Ven () Vapi V Voff(rms) = = = 0.333Vop MGG396 Fig.8 Waveforms for 1 : 4 multiplex drive mode: Vop = Vop Vico. 1998 May 04 12Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 6.5 Oscillator The internal logic and the LCD drive signals of the PCF8566 or PCF8576 are timed either by the built-in oscillator or from an external clock. The clock frequency (fc_k) determines the LCD frame frequency and the maximum rate for data reception from the |2C-bus. To allow I?C-bus transmissions at their maximum data rate of 100 KHZ, fe_x should be chosen to be above 125 kHz. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 6.6 Internal clock When the internal oscillator is used, OSC (pin 6) should be tied to Vgs. In this case, the output from CLK (pin 4) provides the clock signal for cascaded PCF8566s and PCF8576s in the system. 6.7 External clock The condition for external clock is made by tying OSC (pin 6) to Vpp; CLK (pin 4) then becomes the external clock input. 6.8 Timing The timing of the PCF8566 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal SYNC maintains the correct timing relationship between the PCF8566s in the system. The timing also generates the LCD frame frequency which it derives as an integer multiple of the clock frequency (Table 3). The frame frequency is set by MODE SET commands when internal clock is used, or by the frequency applied to pin 4 when external clock is used. Table 3. LCD frame frequencies NOMINAL PCF8566 MODE frrame frrame (Hz) Normal mode foik/2880 64 Power saving mode fotk/480 64 The ratio between the clock frequency and the LCD frame frequency depends on the mode in which the device is operating. In the power saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power dissipation. 1998 May 04 13 The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the |2C-bus. When a device is unable to digest a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2@C-bus but no data loss occurs. 6.9 Display latch The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM. 6.10 Shift register The shift register serves to transfer display information from the display RAM to the display latch while previous data are displayed. 6.11 Segment outputs The LCD drive section includes 24 segment outputs SO to $23 (pins 17 to 40) which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with the data resident in the display latch. When less than 24 segment outputs are required the unused segment outputs should be left open-circuit. 6.12 Backplane outputs The LCD drive section includes four backplane outputs BPO to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs can be left open. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode BPO and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.13 Display RAM The display RAM is a static 24 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on state of the corresponding LCD segment; similarly, a logic 0 indicates the off state.Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 24 segments operated with respect to backplane BPO (see Fig.9). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. When display data are transmitted to the PCF8566 the display bytes received are stored in the display RAM according to the selected LCD drive mode. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.10; the RAM filling organization depicted applies equally to other LCD types. With reference to Fig.10, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1:3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. Inthe 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. 6.14 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored starting at the display RAM address indicated by the data pointer thereby observing the filling order shown in Fig.10. The data pointer is automatically incremented according to the LCD configuration chosen. Thatis, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode). 6.15 Subaddress counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to AO, Ai and A2 (pins 7, 8, and 9). AO, A1 and A2 should be tied to Vsg or Vpp. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are being sent to the display RAM, automatic wrap-over to the next PCF8566 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. display RAM bits (columns) / backplane outputs (BP) Fig.9 display RAM addresses (rows)/segment outputs (S) 19 20 a1 22 23 MGG389 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs. 1998 May 04 14Product specification Philips Semiconductors Universal LCD driver for low multiplex rates PCF8566 (peBueyoun 1g Byep = X) SNG-Oz| EU} JeAo pey|lusues) eyep Agidsip pue Jepso Bulli} WY Ae|dsip epoww eAlp InoAe| GO] Ueemjeg sdiysuolejey o}BiI4 ves > laa cc! OTR _D dd OWA PY) 4s 7 6 qa}z eda aa P| xeydqynu eo yo}! da K-53 1 | e]o ada . f . ----------------------------} | J ----- zag oda v-t tu] u Pe Au, x x xle dd OQ PD x 6 912 zi da g xediyjnuu 8 p dd; +t ag 5 t e Q]/o Ad eS OO Ug [i}-z +s ech otu L+u u u ogg fe) ~ 144s wee ee ee ew ee ee ee ee SS SO: Clllke,.,eeo>rmns - - - - = u e+S x x x x]/e da OTK 2_Y x x x x12Z ae PL +s xe[diyjnu da 6 q/t aq p 8 t ero Ad as GSN |] oe eee eee bts Zi etu |] gtu }+u] ou ~ fe ju oda s == oo -- rr _o+t's x x x x x x x x] dad) KOPN x x x x x x x x |Z 1 as | s+ Ug x x x x x x x xl L oaq ue olyeys u da p 8 6 } e q |o}o ag SB D-re's ast asw |__| | | te . bets tts itu gtu Gtu ytu etu otu L+u u oda u pe7-** 8 aydq Aejdsip peyiwsues} Japso Burj Wy Aeidsip seue|dyoeq qa7 sjuawBes q97 @pow eAUp 15 1998 May 04Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 6.16 Output bank selector This selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. In 1:4 multiplex, all RAM addresses of bit 0 are the first to be selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex, bits 0 then 1 are selected and, in the static mode, bit 0 is selected. The PCF8566 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of bit O contents. In the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 6.17 Input bank selector The input bank selector loads display data into the display RAM according to the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using the BANK SELECT command. The input bank selector functions independently of the output bank selector. Table 4 _ Blinking frequencies 6.18 Blinker The display blinking capabilities of the PCF8566 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, as shown in Table 4. An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1: 2 LCD drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the BLINK command. Inthe 1:3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit E at the required rate using the MODE SET command. NORMAL OPERATING POWER-SAVING NOMINAL BLINKING FREQUENCY BLINKING MODE MODE RATIO MODE RATIO fotink (HZ) Off - - blinking off 2 Hz feik/92 160 fetk/15360 2 1 Hz feLK/184320 feLK/30720 1 0.5 Hz fo_K/368640 fe_x/61440 0.5 1998 May 04 16Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 7 [C-BUS DESCRIPTION The |?C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 7.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 7.3. System configuration A device generating a message is a transmitter, a device receiving a message is a receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. 7.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is not limited. Each byte is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. SDA I | data line I stable; I | data valid I | change | | allowed | of data | MBA607 Fig.11 Bit transfer. 1998 May 04 17Philips Semiconductors Product specification Universal LCD driver for low multiplex rates rccrT conc -- | --- | -- SDA / \ SDA | l Te l | __. __ SCL i \ / \ / SCL 1S | 1 PY START condition STOP condition Fig.12 Definition of START and STOP conditions. SDA TT | | | | MASTER SLAVE MASTER TRANSMITTER / RECEIVER TRANSMITTER / TRANSM er TRANSMITTER / RECEIVER RECEIVER RECEIVER MBAG05 Fig.13 System configuration. START clock pulse for condition acknowledgement SCL FROM MASTER TN S\N Se _- SVS DATA OUTPUT \I 7" BY TRANSMITTER } I s DATA OUTPUT \ / BY RECEIVER MBA606 - 1 Fig.14 Acknowledgement on the |2C-bus. 1998 May 04 18Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 7.5 PCF8566 I?C-bus controller The PCF8566 acts as an I2C-bus slave receiver. It does not initiate |@C-bus transfers or transmit data to an |2C-bus master receiver. The only data output from the PCF8566 are the acknowledge signals of the selected devices. Device selection depends on the |2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs AO, A1 and A2 are normally left open-circuit or tied to Vgg which defines the hardware subaddress 0. In multiple device applications AO, A1 and A2 are left open-circuit or tied to Vgg or Vpp according to a binary coding scheme such that no two devices with a common |2C-bus slave address have the same hardware subaddress. In the power-saving mode it is possible that the PCF8566 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCF8566 forces the SCL line LOW until its internal operations are completed. This is Known as the clock synchronization feature of the I2C-bus and serves to slow down fast transmitters. Data loss does not occur. 7.6 = Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.7. 2C-bus protocol Two |2C-bus slave addresses (0111110 and 0111111) are reserved for PCF8566. The least-significant bit of the slave address that a PCF8566 will respond to is defined by the level tied at its input SAO (pin 10). Therefore, two types of PCF8566 can be distinguished on the same |2C-bus which allows: 1. Upto 16 PCF8566s on the same |2C-bus for very large LCD applications The use of two types of LCD multiplex on the same I2C-bus. 1998 May 04 19 The |2C-bus protocol is shown in Fig.15. The sequence is initiated with a START condition (S) from the |2C-bus master which is followed by one of the two PCF8566 slave addresses available. All PCF8566s with the corresponding SAO level acknowledge in parallel the slave address but all PCF8566s with the alternative SAO level ignore the whole l2C-bus transfer. After acknowledgement, one or more command bytes (m) follow which define the status of the addressed PCF8566s. The last command byte is tagged with a cleared most-significant bit, the continuation bit C. The command bytes are also acknowledged by all addressed PCF8566s on the bus. After the last command byte, a series of display data bytes (n) may follow. These display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data are directed to the intended PCF8566 device. The acknowledgement after each byte is made only by the (AO, A1, A2) addressed PCF8566. After the last display byte, the I@C-bus master issues a STOP condition (P). 7.8 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most-significant bit position (see Fig.16). When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If the bit is reset, it indicates the last command byte of the transfer. Further bytes will be regarded as display data. The five commands available to the PCF8566 are defined in Table 5,Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 acknowledge by all addressed acknowledge by AO, Al and A2 w selected R/W POF 8566s PCF8566 only - slave address _ TTT 1 Ss TT TTT I TTT TTT od 04141114 1/AJo;/Alc COMMAND A DISPLAY DATA A| P 0 | | | | | | | | | | | | | | | | 4 A LA A 1 byte L_ m 21 byte(s) n 20 byte(s) update data pointers and if necessary, MGG390 subaddress counter Fig.15 |@C-bus protocol. 0 = last command 1 =commands continue MSB LSB TT T TT CG REST OF OPGODE | | | | 4 MGG388 Fig.16 General format of command byte. 1998 May 04 20Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates Table 5 Definition of PCF8566 commands COMMAND/OPCODE OPTIONS DESCRIPTION Mode set Cc 1 Oo |} LP] E B | M1 | MO see Table 6 defines LCD drive mode see Table 7 defines LCD bias configuration see Table 8 defines display status; the possibility to disable the display allows implementation of blinking under external control see Table 9 defines power dissipation mode Load data pointer C 0 0 P4 | P3 | P2 | P1 | PO see Table 10 five bits of immediate data, bits P4 to PO, are transferred to the data pointer to define one of twenty-four display RAM addresses Device select C 1 1 0 0 A2 | Ai | AO see Table 11 three bits of immediate data, bits AO to A2, are transferred to the subaddress counter to define one of eight hardware subaddresses Bank select Cc 1 1 1 1 0 0 see Table 12 defines input bank selection (storage of arriving display data) see Table 13 defines output bank selection (retrieval of LCD display data) the BANK SELECT command has no effect in 1:3 and 1: 4 multiplex drive modes Blink Cc 1 1 1 0 A | BF1| BFOo see Table 14 defines the blinking frequency see Table 15 selects the blinking mode; normal operation with frequency set by bits BF1 and BFO, or blinking by alternation of display RAM banks. Alternation blinking does not apply in 1 : 3 and 1: 4 multiplex drive modes Table 6 LCD drive mode LCD DRIVE MODE BIT M1 BIT Mo Static (1 BP) 0 1 1: 2 MUX (2 BP) 1 0 1: 3 MUX (3 BP) 1 1 1:4 MUX (4 BP) 0 0 1998 May 04 21Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates Table 7 LCD bias configuration Table 15 Blink mode selection LCD BIAS BIT B BLINK MODE BITA Vabias 0 Normal blinking 0 Vobias 1 Alternation blinking 1 Table 8 Display status 7.9 Display controller DISPLAY STATUS BITE The display controller executes the commands identified ; by the command decoder. It contains the status registers Disabled (blank) 0 of the PCF8566 and coordinates their effects. Enabled 1 The controller is also responsible for loading display data Table 9 Power dissipation mode into the display RAM as required by the filling order. MODE BIT LP 7.10 Cascaded operation Normal mode 0 In large display configurations, up to 16 PCF8566s can be Power-saving mode 1 distinguished on the same |2C-bus by using the 3-bit Table 10 Load data pointer BITS | pa | ps | p2 | Pi | Po 5-bit binary value of 0 to 23 Table 11 Device select BITS | ao | at | a2 3-bit binary value of 0 to 7 Table 12 Input bank selection STATIC 1:2 MUX BIT 1 RAM bit 0 RAM bits 0, 1 0 RAM bit 2 RAM bits 2, 3 1 Table 13 Output bank selection STATIC 1:2 MUX BIT O RAM bit 0 RAM bits 0, 1 0 RAM bit 2 RAM bits 2, 3 1 Table 14 Blinking frequency BLINK FREQUENCY BIT BF1 BIT BFO Off 0 0 2Hz 0 1 1 Hz 1 0 0.5 Hz 1 1 1998 May 04 22 hardware subaddress (AO, Ai and A2) and the programmable |2C-bus slave address (SAO). It is also possible to cascade up to 16 PCF 8566s. When cascaded, several PCF8566s are synchronized so that they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8566s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (Fig.17). The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8566s. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the definition of a multiplex mode when PCF8566s with differing SAO levels are cascaded). SYNC is organized as an input/output pin; the output section being realized as an open-drain driver with an internal pull-up resistor. A PCF8566 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF8566 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8576 are shown in Fig.18. The waveforms are identical with the parent device PCF8576. Cascade ability between PCF8566s and PCF8576s is possible, giving cost effective LCD applications.Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates I I I Vpp_|YLCD 5 12 spa], SCLI5 17 to 40 [24 segment drives > SVNC LCD PANEL SYNC], _ pcF8s66 CLIK 4 (up to 1536 Osc] , 13 to 16 - elements) 7 8 9 10 11 BPO to BP3 AO [AT ]A2 [SA0]|Vgg Pereveult) VLcD Vpp ; R< tise 2 Chus Vpp VicpD 5 12 HOST SDAI, MICRO- SCL 2 17 to 40 | 24 segment drives > PROCESSOR/ SYNG MIGRO- 3 PCF8566 CONTROLLER CLK 4 osc Ps 13 to 16 4 backplanes BPO to BP3 7 8 9 10 11 Tasos Ao [At |a2 [Sao] Ves Vss Fig.17 Cascaded PCF8566 configuration. 1998 May 04 23Philips Semiconductors Universal LCD driver for low multiplex rates BP1 (1/2 bias) BP1 (1/3 bias) SYNC BP2 SYNC BP3 SYNC Fig.18 Synchronization of the cascade for the various PCF8566 drive modes. |< | Tirame 1 = ] ~ trame ~=_| | (a) static drive mode. a 7 _ | 1 __| U (b) 1: 2 multiplex drive mode. U (c) 1:3 multiplex drive mode. Pr, | * a! U (d) 1: 4 multiplex drive mode. MBE535 For single plane wiring of PCF8566s, see Chapter Application information. 1998 May 04 24 Product specification PCF8566Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT Vop supply voltage 0.5 +7 Vv Vicp LCD supply voltage Vop - 7 Vop Vv Vi input voltage (SCL, SDA, AO to A2, OSC, CLK, SYNC and SAO) | Vss0.5 |Vpp + 0.5 | V Vo output voltage (SO to S23 and BPO to BP3) Vicp- 9.5 |Vpp + 0.5 |V I DC input current - +20 mA lo DC output current - +25 mA Ipp; Iss; ILep | Vpp; Vss or Vicp current - +50 mA Prot power dissipation per package - 400 mW Po power dissipation per output - 100 mW Tstg storage temperature 65 +150 C 9 HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is advised to take handling precautions appropriate to handling MOS devices (see Handling MOS devices). 1998 May 04 25Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 10 DC CHARACTERISTICS Vgs = 0 V; Vpp = 2.5 to 6 V; Vicp = Vpp 2.5 to Vpp 6 V; Tamb = 40 to +85 C; unless otherwise specified. SYMBOL PARAMETER ConpiTIONS | MIN. | TYP. | MAX. | UNIT Supplies Vop operating supply voltage 2.5 - 6 Vv Viep LCD supply voltage Vpp - 6 - Vpp - 2.5] V Ipp operating supply current foLk = 200 kHz; note 1 - 30 90 HA (normal mode) ILp power saving mode supply current | Vpp =3.5 V; Vicp = 0 V; |- 15 40 HA fe_k = 35 kHz; AO, Al and A2 tied to Vgg; note 1 Logic Vit LOW level input voltage Vgs - 0.3Vpp Vv Vin HIGH level input voltage 0.7Vpp - Vop Vv Voi LOW level output voltage lo=OmA - - 0.05 Vv Vou HIGH level output voltage lo=OmA Vpp 0.05 | - Vv lout LOW level output current VoL =1V; Vpp =5 V 1 - - mA (CLK and SYNC) lou HIGH level output current (CLK) Vou =4V; Vpp =5 V - - -1 mA loL2 LOW level output current VoL =0.4V; Vpp=5V {3 - - mA (SDA and SCL) lu leakage current Vi = Vss or Vpp - - +1 HA (SAO, CLK, OSC, Ao, A1, A2, SCL and SDA) loa pull-down current Vi=1V;Vpp =5V 15 50 150 HA (AO, A1, A2 and OSC) Rousync _ | pull-up resistor (SYNC) 15 25 60 kQ Viet power-on reset level note 2 - 1.3 2 Vv tow tolerable spike width on bus - - 100 ns Ci input capacitance note 3 - - 7 pF LCD outputs Vep DC voltage component Cpp = 35 nF - +20 - mV (BPO to BP3) Vs DC voltage component (SO to $23) | Cg = 5 nF - +20 - mV Zep output impedance (BPO to BP3) Vicp = Vpp 5 V; note 4 | 1 5 kQ Zs output impedance (SO to $23) Vicp= Vpp-5 V; note 4 |- 3 7 kQ Notes 1. Outputs open; inputs at Vgg or Vpp; external clock with 50% duty factor; |@C-bus inactive. Resets all logic when Vpp < Vrer. 2 3. Periodically sampled, not 100% tested. 4 Outputs measured one at a time. 1998 May 04 26Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 11 AC CHARACTERISTICS Vgs = 0 V; Vpp = 2.5 to 6 V; Vicp = Vpp 2.5 to Vpp 6 V; Tamp = 40 to +85 C; unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT foik oscillator frequency (normal mode) |Vpp=5V;note2 | 125 200 315 kHz foLKLp oscillator frequency (power saving Vpp = 3.5 V 21 31 48 kHz mode) teLKH CLK HIGH time 1 - - ys teLKL CLK LOW time 1 - - ys tpsync SYNC propagation delay - - 400 ns tsynecL SYNC LOW time 1 - - ys tpiep driver delays with test loads Vicp=Vpp-5V |- - 30 ys I2?C-bus tur bus free time 4.7 - - ys THD: STA START condition hold time 4 - - us tlow SCL LOW time 4.7 - - ys tHiGH SCL HIGH time 4 - - ys tsu; STA START condition set-up time 4.7 - - ys (repeated start code only) tHD: DAT data hold time 0 - - ys tsu: DAT data set-up time 250 - - ns tr rise time - - 1 us tf fall time - - 300 ns tsu; sto STOP condition set-up time 4.7 - - ys Notes 1. All timing values referred to Vj and Vj, levels with an input voltage swing of Vgg to Vpp. 2. Atfork < 125 kHz, I@C-bus maximum transmission speed is derated. 1.5kQ Vpp (2%) CLK 3.3 kO SDA, SCL (pin 4) ++ -5Vpp (pins 1, 2) p (2%) p ; SYNC 8:8 k Vv (pins) (2%) pp BPO to BP3 80 to $23 (pins 13 to 16) (pins 17 to 40) Fig.19 Test loads. lload * 15 HA MGG387 1998 May 04 27Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 tcLK 1CLKH *| |" ICLKL \ fo7Vpp CLK 0.3Vpp 0.7Vpp SYNC tpSYNC >| * + _ tsyncL"| | / 0.5V BPO to BP3 t Vpp=5 V $0 to $23 | Ypp ) \ 0.5V tp_cp >" t MGG391 Fig.20 Driver timing waveforms. tBuF tlow 4 SCL {<t | tHD:STA tr tHD;DAT tHIGH Tgu:DAT SDA " tsu:sTA st MGA728 Fig.21 |@C-bus timing waveforms. tgu:sto 1998 May 04 28Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 MGG397 40 Ipp (uA) 30 TV YA 85C 20 Zr a LE 10 Z| 0 0 2 4 6 8 Vpp (Y) a. Normal mode; Vicp = 0 V; external clock = 200 kHz. MGG398 24 Ipb (HA) 2 16 LA LL ZX +85 C 0 2 4 6 8 Vpp () b. Low power mode; Vicp = 0 V; external clock = 35 kHz. Fig.22 Typical supply current characteristics. MGG399 Rep (kQ) 0 2 4 6 8 Vpp (V) a. Backplane output impedance BPO to BP3 (Rep); Vop = V; Tamb = 40 to +85 C. MGG400 Rg (kQ) LN wow +85 C] / if | 6 8 Vpp (VY) b. Segment output impedance SO to S23 (Rs); Vpp = 5 V. Fig.23 Typical characteristics of LCD outputs. 1998 May 04 29PCF8566 Product specification "$99G849d eBeyoed jo Bunim eurld ajBuis pz 6i4 Universal LCD driver for low multiplex rates 12 APPLICATION INFORMATION Philips Semiconductors 99800 SLNAWD4S SANV1dyOva Wy ----------------- ves eg ----------------- os | | , szs [2] oz} zzS s {| foz} S ses {zz| l6t}- 928 ss {zz| 61} 2s oes {ez} lai} szs 9s {ez| fai} ts les fre! [Zi}- v2S 1s {re| [Zi 0S zes {s2| it] eda gs {sz} fot} ed@ ses {22| ist] ta 6s -{22| fst} Lda ves [22] rt] 2d Hnoup-uado ors {Z| rt} 2da ses {z2| fet] Odd 1s fze| fet} oda ges ez| fet} zis Se et] G1, Les [ae] rt} els [oe] rE SS, ses [ie] OL vis fe] fot} ovsS 6es [ze| 6 sis fze| [6 }- ev ors [aa] 8 91s ee fe} iv is fre rz] Lis [re] Zz + ov evs {se| 2] sis {se| is 980 evs [pe] rs] sis {ae r=] dd, rvs 25] Ea ozs {Z| [+] 19 srs {ae g bes 26] fe] NAS ovs [ee] z zzs [se] fz] 10s Zvs [or| : ees [or] r] vas do1, | SSA ada 10 ONAS 70S vas 30 1998 May 04Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates 13 CHIP DIMENSIONS AND BONDING PAD LOCATIONS 2.5 mm(1) y Lae] 8&5 8 8 &@ | 8&8 8 & 8 & AAAI | Eee | BP1 ! s9 | BP2 Si0 | BPO si | Vicb $12 | Lo 2.91(1) S13 oo ott mm $14 SAO S15 PCF8566 [9] | a2 $16 Al S17 AO $18 [6] | osc 26] [27] Be] Eo] fe AMAHE [or] S > N <x a oO x a MBH783 o 8 8 8 8 a 3 lz 3 8 Y (1) Typical value. Pad size: 120 x 120 um Chip area: 7.27 mm. The numbers given in the small squares refer to the pad numbers. Fig.25 Bonding pad locations. 1998 May 04 31Philips Semiconductors Product specification Universal LCD driver for low multiplex PCF8566 rates Table 16 Bonding pad locations (dimensions in mm) All x/y coordinates are referenced to centre of chip, (see Fig.25). PAD NUMBER SYMBOL x y PIN 1 SDA 200 1235 1 2 SCL 400 1235 2 3 SYNG 605 1235 3 4 CLK 856 1235 4 5 Vop 1062 1235 5 6 Osc 1080 1025 6 7 AO 1080 825 7 8 Al 1080 625 8 9 A2 1080 425 9 10 SAO 1080 225 10 11 Vss 1080 -25 11 12 Vip 1080 347 12 13 BPO 1080 547 13 14 BP2 1080 747 14 15 BP1 1080 947 15 16 BP3 1074 1235 16 17 So 874 1235 17 18 $1 674 1235 18 19 $2 474 1235 19 20 $3 274 1235 20 21 $4 274 1235 21 22 $5 474 1235 22 23 S6 674 1235 23 24 $7 874 1235 24 25 $8 1074 1235 25 26 S89 1080 765 26 27 $10 1080 565 27 28 $11 1080 365 28 29 $12 1080 165 29 30 $13 1080 35 30 31 $14 1080 235 31 32 $15 1080 435 32 33 $16 1080 635 33 34 $17 1080 835 34 35 $18 1080 1035 35 36 $19 1056 1235 36 37 $20 830 1235 37 38 $21 630 1235 38 39 $22 430 1235 39 40 $23 230 1235 40 1998 May 04 32Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 14 PACKAGE OUTLINES DIP40: plastic dual in-line package; 40 leads (600 mil) $OT129-1 ~~ seating plane od i, | > el : = z io ME b 40 | ie a4 My A pin 1 index py -_ - - | Yh E 1 20 0 5 10mm Leora tiaii td scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Az a) (1) z UNIT | way. | min. | max. b by c D E e ey L Me My w max. 1.70 0.53 0.36 52.50 1441 3.60 15.80 17.42 mm 47 | 051 | 40 | 444 | 038 | 023 | 51.50] 137 | 254 | 124 | 365 | 15.24 | 15.90 | 9254 | 225 : 0.067 | 0.021 0.014 | 2.067 0.56 0.14 0.62 0.69 inches | 0.19 |) 0.020 | 0.16 | go45 | 0.015 | 0.009 | 2.028 | 054 | 919 | 269 | g 42 | o6o | o63 | %01 | 0.089 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 92-44-44 SOT129-1 051G08 MO-015AJ a os Oldd 1998 May 04 33Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 VSO40: plastic very small outline package; 40 leads SOT158-1 D | a (As) re Lp f |~< | - detail X 0 5 10 mm Lo 1 | 1 1 scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A 4 2) 4 UNIT | ax. | At Ao | Ag bp c pM | @) | e He L Lp Q Vv w y z | 9 0.3 2.45 0.42 | 0.22 | 15.6 7.6 12.3 1.7 1.15 0.6 mm | 2.70) 91 | 225 | %5 | a30 | 014] 152] 75 |%76*| 1148] 225) 15 | 105] 92 | OT | OT | og | 50 . 0.012 | 0.096 0.017 |0.0087] 0.61 | 0.30 0.48 0.067 | 0.045 0.024 o inches | 0.11 | 9994 | 0.089 | -9'9| 0.012 0.0055] 0.60 | 0.29 | 9-93 | o.46 | 9-989 | 0.059 | 0.041 | 9-008 | 9.004 | 0.004 | g gia Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUEDATE IEC JEDEC EIAJ 92-44-44 SOT158-1 oe 95-01-24 1998 May 04 34Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 15 SOLDERING 15.1. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook 1C26; Integrated Circuit Packages (order code 9398 652 90011). 15.2 DIP 15.2.1 SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tgig max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.2.2 REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 15.3. SOand VSO 15.3.1 REFLOW SOLDERING Reflow soldering techniques are suitable for all SO and VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 May 04 35 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 15.3.2 WAVE SOLDERING Wave soldering techniques can be used for all SO and VSO packages if the following conditions are observed: e A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. e The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3.3 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.