Industrial Power & Control
EiceDRIVER™
High voltage gate driver IC
datasheet
<Revision 2.5>, 21.01.2013
6ED family - 2nd generation
3 phase 600 V gate drive IC
6ED003L06-F2
6ED003L02-F2
EiceDRIVER™
Edition 21.01.2013
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
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EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 3 <Revision 2.5>, 21.01.2013
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 2.5>, 21.01.2013
p. 8
revised Figure 1
p. 20
revised Figure 8
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Last Trademarks Update 2010-10-26
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 4 <Revision 2.5>, 21.01.2013
Table of Contents
1 Overview ............................................................................................................................................. 7
2 Blockdiagram ...................................................................................................................................... 8
3 Pin configuration, description, and functionality ........................................................................... 9
3.1 Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) .................................................................. 9
3.2 EN (Gate Driver Enable, Pin 10) ........................................................................................................ 10
3.3 FAULT (Fault Feedback, Pin 8) ......................................................................................................... 10
3.4 ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) ......................................................... 11
3.5 VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ...................................................................... 11
3.6 VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) ............................................. 11
3.7 LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) ............................... 11
4 Electrical Parameters ....................................................................................................................... 12
4.1 Absolute Maximum Ratings ............................................................................................................... 12
4.2 Required operation conditions ........................................................................................................... 13
4.3 Operating Range ................................................................................................................................ 13
4.4 Static logic function table ................................................................................................................... 14
4.5 Static parameters ............................................................................................................................... 14
4.6 Dynamic parameters .......................................................................................................................... 16
5 Timing diagrams............................................................................................................................... 17
6 Package ............................................................................................................................................. 19
6.1 PG-DSO-28 ........................................................................................................................................ 19
6.2 PG-TSSOP-28 .................................................................................................................................... 20
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 5 <Revision 2.5>, 21.01.2013
List of Figures
Figure 1 Typical Application ............................................................................................................................... 8
Figure 2 Block diagram for 6ED003L06-F2 / 6ED003L02-F2 ............................................................................ 8
Figure 3 Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2 ................................................................... 9
Figure 4 Input pin structure............................................................................................................................... 10
Figure 5 Input filter timing diagram ................................................................................................................... 10
Figure 6 EN pin structures ................................................................................................................................ 10
Figure 7 FAULT pin structures ......................................................................................................................... 11
Figure 8 Timing of short pulse suppression ..................................................................................................... 17
Figure 9 Timing of internal deadtime ................................................................................................................ 17
Figure 10 Enable delay time definition ............................................................................................................... 17
Figure 11 Input to output propagation delay times and switching times definition ............................................. 18
Figure 12 Operating areas.................................................................................................................................. 18
Figure 13 ITRIP-Timing ...................................................................................................................................... 18
Figure 14 Package drawing ................................................................................................................................ 19
Figure 15 PCB reference layout ......................................................................................................................... 19
Figure 16 Package drawing ................................................................................................................................ 20
Figure 17 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint20
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 6 <Revision 2.5>, 21.01.2013
List of Tables
Table 1 Members of 6ED family – 2nd generation ............................................................................................. 7
Table 2 Pin Description ..................................................................................................................................... 9
Table 3 Abs. maximum ratings ........................................................................................................................ 12
Table 4 Required Operation Conditions .......................................................................................................... 13
Table 5 Operating range ................................................................................................................................. 13
Table 6 Static parameters ............................................................................................................................... 14
Table 7 Dynamic parameters .......................................................................................................................... 16
Table 8 Data of reference layout ..................................................................................................................... 20
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 7 <Revision 2.5>, 21.01.2013
EiceDRIVER™
3 phase 600 V gate drive IC
1 Overview
Main features
Thin-film-SOI-technology
Maximum blocking voltage +600V
Separate control circuits for all six drivers
CMOS and LSTTL compatible input (negative logic)
Signal interlocking of every phase to prevent cross-conduction
Detection of over current and under voltage supply
externally programmable delay for fault clear after over current
detection
Product highlights
Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology
'shut down' of all switches during error conditions
Typical applications
Home appliances
Fans, pumps
General purpose drives
Product family
Table 1 Members of 6ED family – 2nd generation
Sales Name
high side control input
HIN1,2,3 and LIN1,2,3
typ. UVLO-
Thresholds
Bootstrap
diode
6ED003L06-F2 / 6ED003L02-F2
negative logic
11.7 V / 9.8 V
No
Description
The devices are full bridge drivers to control power devices like MOS-transistors or IGBTs in 3-phase systems
with a maximum blocking voltage of +600 V. Based on the used SOI-technology there is an excellent
ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic
latch-up may occur at all temperatures and voltage conditions.
The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down
to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic and an over-
current detection. The over-current level is adjusted by choosing the resistor value and the threshold level at pin
ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut down of all six switches. An
error signal is provided at the FAULT open drain output pin. The blocking time after over-current can be
adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore,
the resistor RRCIN is optional. The typical output current can be given with 165 mA for pull-up and 375 mA for pull
down. Because of system safety reasons a 310 ns interlocking time has been realised. The function of input EN
can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1).
PG-DSO28
PG-TSSOP28
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 8 <Revision 2.5>, 21.01.2013
Figure 1 Typical Application
2 Blockdiagram
Figure 2 Block diagram for 6ED003L06-F2 / 6ED003L02-F2
VCC
FAULT
LIN1,2,3
EN
RCIN
ITRIP
VSS
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
COM
To Load
VSS
EN
R
RCIN
C
RCIN
HIN1,2,3
HIN1,2,3
LIN1,2,3
FAULT
VCC
DC-Bus
R
Sh
5V
VCC
LO1
LO2
LO3
COM
VSS
SET
DOMINANT
LATCH
S
R
Q
UV-
DETECT
BIAS NETWORK / VDD2
DEADTIME &
SHOOT-THROUGH
PREVENTION z
DEADTIME &
SHOOT-THROUGH
PREVENTION
DEADTIME &
SHOOT-THROUGH
PREVENTION
DELAY
DELAY
DELAY
VSS / COM
LEVEL-
SHIFTER
VSS / COM
LEVEL-
SHIFTER
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
Gate-
Drive
Gate-
Drive
>1
INPUT NOISE
FILTER
LIN3
INPUT NOISE
FILTER
HIN3
INPUT NOISE
FILTER
LIN2
INPUT NOISE
FILTER
HIN2
INPUT NOISE
FILTER
LIN1
VS3
HO3
VB3
BIAS NETWORK / VB3
COMPAR
ATOR
HV LEVEL-SHIFTER
+ REVERSE-DIODE
LATCH
UV-
DETECT
VS2
HO2
VB2
BIAS NETWORK - VB2
COMPAR
ATOR
HV LEVEL-SHIFTER
+ REVERSE-DIODE
LATCH
UV-
DETECT
VS1
HO1
VB1
BIAS NETWORK - VB1
COMPAR
ATOR
HV LEVEL-SHIFTER
+ REVERSE-DIODE
LATCH
UV-
DETECT
Gate-
Drive
INPUT NOISE
FILTER
HIN1
FAULT
>1
RCIN
VDD2
IRCIN
ITRIP INPUT NOISE
FILTER
INPUT NOISE
FILTER
EN
Gate-
Drive
Gate-
Drive
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 9 <Revision 2.5>, 21.01.2013
Pin configuration, description, and functionality
Figure 3 Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2
Table 2 Pin Description
Symbol
Description
VCC
Low side power supply
VSS
Logic ground
/HIN1,2,3
High side logic input
/LIN1,2,3
Low side logic input
/FAULT
Indicates over-current and under-voltage (negative logic, open-drain output)
EN
Enable I/O functionality (positive logic)
ITRIP
Analog input for over-current shut down, activates FAULT and RCIN to VSS
RCIN
External RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR)
COM
Low side gate driver reference
VB1,2,3
High side positive power supply
HO1,2,3
High side gate driver output
VS1,2,3
High side negative power supply
LO1,2,3
Low side gate driver output
nc
Not connected
2.1 Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7)
The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 4 and Figure 5.
VCC1 28VB1
HIN12 27HO1
HIN23 26VS1
HIN34 25
LIN15 24VB2
LIN26 23HO2
LIN37 22VS2
FAULT8 21
ITRIP9 20VB3
EN10 19HO3
RCIN11 18VS3
VSS12 17
COM13 16LO1
LO314 15LO2
nc
nc
nc
UZ=10.5V
INPUT NOISE
FILTER
Vcc
Schmitt-Trigger
SWITCH LEVEL
VIH; VIL
LINx
HINx
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 10 <Revision 2.5>, 21.01.2013
Figure 4 Input pin structure
An internal pull-up of about 75 k (negative logic) pre-biases the input during supply start-up and a ESD zener
clamp is provided for pin protection purposes. The zener diodes are therefore designed for single pulse stress
only and not for continuous voltage stress over 10V.
Figure 5 Input filter timing diagram
It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1 µs.
The 6ED-F2 driver IC provide additionally a shoot through prevention capability which avoids the simultaneous
on-state of two channels of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of
a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe state. Please
refer to the application note AN-Gatedrive-6ED2-1 for a detailed description.
A minimum dead time insertion of typ. 310 ns is also provided, in order to reduce cross-conduction of the
external power switches.
2.2 EN (Gate Driver Enable, Pin 10)
The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW
logic level. The internal structure of the pin is given in Figure 6. The switching levels of the Schmitt-Trigger are
here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. There is an internal
pull down resistor (75 k), which keeps the gate outputs off in case of broken PCB connection.
Figure 6 EN pin structures
2.3 /FAULT (Fault Feedback, Pin 8)
/Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 7). The pin is
active (i.e. forces LOW voltage level) when one of the following conditions occur:
Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the
supply voltage condition returns in the normal operation range (please refer to VCC pin description for
more details).
Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and
RCIN input is released (please refer to ITRIP pin).
LIN
HIN
HIN
LIN
HO
LO
high
low
on off on
tFILIN tFILIN
off on off
LO
HO
VZ= 10.5 V
INPUT NOISE
FILTER
EN IEN+, IEN-
VEN,TH+,
VEN,TH-
6ED family – 2nd generation
FAULT >1 from uv-detection
VCC
RON,FLT
VDD
from ITRIP-Latch
6ED family –
2nd generation
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 11 <Revision 2.5>, 21.01.2013
Figure 7 /FAULT pin structures
2.4 ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11)
The 6ED family – 2nd generation provides an over-current detection function by connecting the ITRIP input with
the motor current feedback. The ITRIP comparator threshold (typ 0.44 V) is referenced to VSS ground. A input
noise filter (typ. tITRIPMIN = 230 ns) prevents the driver to detect false over-current events.
Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault
feedback at /FAULT pin. RCIN input/output pin is used to determine the reset time of the fault condition. As
soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The
capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon
as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 5.2 V, the fault condition releases and the driver
returns operational following the ontrol input pins according to section 2.1. Please refer to AN-Gatedrive-6ED2-1
for details on setting RCIN time constant.
2.5 VCC, VSS and COM (Low Side Supply, Pin 1, 12,13)
VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input
logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is
referenced to COM ground. COM ground is floating respect to VSS ground with a maximum range of operation
of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VCCUV+ is present.
The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below VCCUV- = 9.8 V.
This prevents the external power switches from critically low gate voltage levels during on-state and therefore
from excessive power dissipation. Please consult the individual output characteristic of the driven transistor.
2.6 VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28)
VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VCC.
The device operating area as a function of the supply voltage is given in Figure 12. Details on bootstrap supply
section and transient immunity can be found in application note AN-Gatedrive-6ED2-1.
2.7 LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT
and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs, while high
side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs. In particular, after an under voltage
condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the respective high side
output, while after a under voltage condition of the VCC supply, the low side outputs switch to the state of their
respective inputs.
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 12 <Revision 2.5>, 21.01.2013
3 Electrical Parameters
3.1 Absolute Maximum Ratings
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (Ta=25°C)
Table 3 Abs. maximum ratings
Parameter
Symbol
Min.
Max.
Unit
High side offset voltage(Note 1) DSO28
TSSOP28
VS
VCC-VBS-6
600
180
V
High side offset voltage (tp<500ns, Note 1)
VCC -VBS – 50
–
High side offset voltage(Note 1) DSO28
TSSOP28
VB
VCC – 6
620
200
High side offset voltage (tp<500ns, Note 1)
VCC – 50
–
High side floating supply voltage (VB vs. VS) (internally clamped)
VBS
-1
20
High side output voltage (VHO vs. VS)
VHO
-0.5
VB + 0.5
Low side supply voltage (internally clamped)
VCC
-1
20
Low side supply voltage (VCC vs. VCOM)
VCCOM
-0.5
25
Gate driver ground
VCOM
-5.7
5.7
Low side output voltage (VLO vs. VCOM)
VLO
-0.5
VCCOM + 0.5
Input voltage /LIN, /HIN, EN, ITRIP
VIN
-1
10
FAULT output voltage
VFLT
-0.5
VCC + 0.5
RCIN output voltage
VRCIN
-0.5
VCC + 0.5
Power dissipation (to package) Note 2 DSO28
TSSOP28
PD
–
–
1.3
0.6
W
Thermal resistance DSO28
(junction to ambient, see section 5) TSSOP28
Rth(j-a)
–
–
75
165
K/W
Junction temperature
TJ
–
125
°C
Storage temperature
TS
- 40
150
offset voltage slew rate (Note 3)
dVS/dt
50
V/ns
Note :The value for ESD immunity is 1.0kV (Human Body Model). ESD immunity for pins inside the low side (i.e. VCC, /HINx, /LINx, FAULT,
EN, RCIN, ITRIP, VSS, COM, LOx) and ESD immunity for pins inside each high side itself (i.e. VBx, HOx, VSx) is guaranteed up to 1.5kV
(Human Body Model).
Note 1 : Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by design /
characterization. External bootstrap diode is mandatory. Refer to application note.
Note 2: Consistent power dissipation of all outputs. All parameters inside operating range.
Note 3: Not subject of production test, verified by characterisation
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 13 <Revision 2.5>, 21.01.2013
3.2 Required operation conditions
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (Ta = 25°C)
Table 4 Required Operation Conditions
Parameter
Symbol
Min.
Max.
Unit
High side offset voltage (Note 1) DSO28
TSSOP28
VB
7
620
200
V
Low side supply voltage (VCC vs. VCOM) DSO28
TSSOP28
VCCOM
10
25
3.3 Operating Range
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (Ta = 25°C)
Table 5 Operating range
Parameter
Symbol
Min.
Max.
Unit
High side floating supply offset voltage
VS
VCC -
VBS -1
500
V
High side floating supply offset voltage (VB vs. VCC, statically)
VBCC
-1.0
500
High side floating supply voltage (VB vs. VS, Note 1)
VBS
13
17.5
High side output voltage (VHO vs. VS)
VHO
10
VBS
Low side output voltage (VLO vs. VCOM)
VLO
0
VCC
Low side supply voltage
VCC
13
17.5
Low side ground voltage
VCOM
-2.5
2.5
Logic input voltages /LIN, /HIN, EN, ITRIP (Note 2)
VIN
0
5
FAULT output voltage
VFLT
0
VCC
RCIN input voltage
VRCIN
0
VCC
Pulse width for ON or OFF (Note 3)
tIN
1
–
µs
Ambient temperature
Ta
-40
95
°C
Note 1 : Logic operational for VB (VB vs. VSS) > 7,0V
Note 2 : All input pins (/HINx, /LINx) and EN, ITRIP pin are internally clamped (see abs. maximum ratings)
Note 3 : In case of input pulse width at /LINx and /HINx below 1µs the input pulse may not be transmitted properly
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 14 <Revision 2.5>, 21.01.2013
3.4 Static logic function table
VCC
VBS
RCIN
ITRIP
ENABLE
FAULT
LO1,2,3
HO1,2,3
<VCCUV–
X
X
X
X
0
0
0
15V
<VBSUV–
X
0
3.3 V
High imp
/LIN1,2,3
0
15V
15V
<3.2 V
0
3.3 V
0
0
0
15V
15V
X
> VIT,TH+
3.3 V
0
0
0
15V
15V
> VRCIN,TH
0
3.3 V
High imp
/LIN1,2,3
/HIN1,2,3
15V
15V
> VRCIN,TH
0
0
High imp
0
0
3.5 Static parameters
VCC = VBS = 15V unless otherwise specified. (Ta=25°C)
Table 6 Static parameters
Parameter
Symbol
Values
Unit
Test condition
Min.
Typ.
Max.
High level input voltage
VIH
1.7
2.1
2.4
V
Low level input voltage
VIL
0.7
0.9
1.1
EN positive going threshold
VEN,TH+
1.9
2.1
2.3
EN negative going threshold
VEN,TH-
1.1
1.3
1.5
ITRIP positive going threshold
VIT,TH+
380
445
510
mV
ITRIP input hysteresis
VIT,HYS
45
70
RCIN positive going threshold
VRCIN,TH
-
5.2
6.4
V
RCIN input hysteresis
VRCIN,HYS
-
2.0
-
Input clamp voltage
(/HIN, /LIN, EN, ITRIP)
VIN,CLMAP
9
10.3
12
IIN = 4mA
Input clamp voltage at high impedance
(/HIN, /LIN)
VIN,FLOAT
-
5.3
5.8
controller output
pin floating
High level output voltage LO1,2,3
HO1,2,3
VOH
-
-
VCC -0.7
VB -0.7
VCC -1.4
VB -1.4
IO = 20mA
Low level output voltage LO1,2,3
HO1,2,3
VOL
-
-
VCOM+
0.2
VS+ 0.2
VCOM+
0.6
VS + 0.6
IO = -20mA
VCC and VBS supply undervoltage positive
going threshold
VCCUV+
VBSUV+
11
11.7
12.5
VCC and VBS supply undervoltage negative
going threshold
VCCUV–
VBSUV–
9.5
9.8
10.8
V
VCC and VBS supply undervoltage lockout
hysteresis
VCCUVH
VBSUVH
1.2
1.9
-
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 15 <Revision 2.5>, 21.01.2013
Table 6 Static parameters
Parameter
Symbol
Values
Unit
Test condition
Min.
Typ.
Max.
High side leakage current betw. VS and VSS
ILVS+
-
1
12.5
µA
VS = 600V
High side leakage current betw. VS and VSS
ILVS+
1
-
10
-
TJ = 125°C,
VS = 600V
High side leakage current between VSx and
VSy (x=1,2,3 and y=1,2,3)
ILVS–
1
-
10
-
TJ = 125°C
VSx - VSy = 600V
Quiescent current VBS supply (VB only)
IQBS1
-
210
400
µA
HO=low
Quiescent current VBS supply (VB only)
IQBS2
-
210
400
HO=high
Quiescent current VCC supply (VCC only)
IQCC1
-
1.1
1.8
mA
VLIN=float.
Quiescent current VCC supply (VCC only)
IQCC2
-
1.3
2
VLIN=0, VHIN=3.3 V
Input bias current
ILIN+
-
70
100
µA
VLIN=3.3 V
Input bias current
ILIN-
-
110
200
µA
VLIN=0
Input bias current
IHIN+
-
70
100
VHIN=3.3 V
Input bias current
IHIN-
-
110
200
VHIN=0
Input bias current (ITRIP=high)
IITRIP+
45
120
VITRIP=3.3 V
Input bias current (EN=high)
IEN+
-
45
120
VENABLE=3.3 V
Input bias current RCIN (internal current
source)
IRCIN
2.8
VRCIN = 2 V
Mean output current for load capacity
charging in range from 3 V (20%) to 6 V
(40%)
IO+
120
165
-
mA
CL=10 nF
Peak output current turn on (single pulse)
IOpk+
1
240
RL = 0 , tp <10 µs
Mean output current for load capacity
discharging in range from 12 V (80%) to 9 V
(60%)
IO-
250
375
-
CL=10 nF
Peak output current turn off (single pulse)
IOpk-
1
420
RL = 0 , tp <10 µs
RCIN low on resistance of the pull down
transistor
Ron,RCIN
-
40
100
VRCIN=0.5 V
FAULT low on resistance of the pull down
transistor
Ron,FLT
-
45
100
VFAULT=0.5 V
1
Not subject of production test, verified by characterisation
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 16 <Revision 2.5>, 21.01.2013
3.6 Dynamic parameters
VCC = VBS = 15 V, VS = VSS = VCOM unless otherwise specified. (TA=25°C)
Table 7 Dynamic parameters
Parameter
Symbol
Values
Unit
Test condition
Min.
Typ.
Max.
Turn-on propagation delay
ton
400
530
800
ns
VLIN/HIN = 0 or 3.3 V
Turn-off propagation delay
toff
360
490
760
Turn-on rise time
tr
-
60
100
VLIN/HIN = 0 or 3.3 V
CL = 1 nF
Turn-off fall time
tf
-
26
45
Shutdown propagation delay ENABLE
tEN
-
780
1100
VEN=0
Shutdown propagation delay ITRIP
tITRIP
400
670
1000
VITRIP=1 V
Input filter time ITRIP
tITRIPMIN
155
230
380
Propagation delay ITRIP to FAULT
tFLT
-
420
700
Input filter time at LIN/HIN for turn on and off
tFILIN
120
300
-
VLIN/HIN = 0 & 3.3 V
Input filter time EN
tFILEN
300
600
-
Fault clear time at RCIN after ITRIP-fault,
(CRCin=1nF)
tFLTCLR
1.0
1.9
3.0
ms
VLIN/HIN = 0 & 3.3 V
VITRIP = 0
Dead time
DT
150
310
-
ns
VLIN/HIN = 0 & 3.3 V
Matching delay ON, max(ton)-min(ton), ton
are applicable to all 6 driver outputs
MTON
-
20
100
external dead time
> 500 ns
Matching delay OFF, max(toff)-min(toff), toff
are applicable to all 6 driver outputs
MTOFF
-
40
100
external dead time
>500 ns
Output pulse width matching. Pwin-PWout
PM
40
100
PWin > 1 µs
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 17 <Revision 2.5>, 21.01.2013
4 Timing diagrams
Figure 8 Timing of short pulse suppression
Figure 9 Timing of internal deadtime
Figure 10 Enable delay time definition
HIN/LIN
HIN/LIN
HO/LO
HO/LO
low
tIN < tFILIN
tIN
tIN > tFILIN
tIN
tFILIN
HIN/LIN
HIN/LIN
HO/LO
HO/LO
high
tIN < tFILIN
tIN
tIN > tFILIN
tIN
tFILIN
LIN1,2,3
HIN1,2,3
HO1,2,3
LO1,2,3
12 V
3V
3V
12V
2.5V 2.5V
DT DT
LO1,2,3
tEN
3V
HO1,2,3
EN
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 18 <Revision 2.5>, 21.01.2013
Figure 11 Input to output propagation delay times and switching times definition
Figure 12 Operating areas
Figure 13 ITRIP-Timing
LIN1,2,3
HIN1,2,3
HO1,2,3
LO1,2,3
1.65V 1.65V
12V
3V 3V
12V
PWOUT
ton toff
trtf
PWIN
ONOFF ON
Recommended
Area
ON Forbidden
Area ON ON
Recommended
Area
ON OFF
20
17.5
13
11.7
9.8
vCC
vBS
t
IC STATE
VCCMAX , VBSMAX
VCCUV+, VBSUV+
VCCUV-, VBSUV-
V
RCIN
ITRIP
1V
FAULT
Any
output
VRCIN,TH
0.1V
0.1V
tFLTCLR
0.5V
tFLT
tITRIP 3V
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 19 <Revision 2.5>, 21.01.2013
5 Package
5.1 PG-DSO-28
Figure 14 Package drawing
Dimensions
80.0 80.0 1.5 mm³
therm [W/mK]
Material
FR4
0.3
Metal (Copper)
70µm
388
Figure 15 PCB reference layout
EiceDRIVER(TM)
6ED003L06-F2, 6ED003L02-F2
datasheet 20 <Revision 2.5>, 21.01.2013
5.2 PG-TSSOP-28
Footprint for Reflow soldering
e = 0.65
A = 6.10
L = 1.30
B = 0.40
Figure 16 Package drawing
Figure 17 PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
Table 8 Data of reference layout
Dimensions
Material
Metal (Copper)
76.2 114.3 1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG