MB39C001PVB - Fujitsu Limited

DS04-27243-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP For Power Supply Applications

(Switching FET Integrated DC/DC Converter)

1ch PFM/PWM Synchronous

Rectification Step-down Regulator

MB39C001

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■DESCRIPTION

The MB39C001 is a synchronous rectification type of single-channel, step-down DC/DC converter IC using current

mode control.

The MB39C001 integrates s witching FETs , an oscillator , error amplifier , voltage detector, and a ref erence voltage

generator in a 18-pin BCC package. The required external components are only a coil and decoupling capacitors.

The MB39C001 is small in size , and can achieve a DC/DC con verter highly effective in the full load r ange , and it

is the best for internal power supplies for portable devices such as cellular phones, PDAs and DSC.

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■FEATURES

• High efficiency : 96% Max

• Quiescent current : 20 µA (in PFM mode)

• Output current (DC/DC) : 600 mA Max

• Input voltage range : 2.5 V to 5.5 V

• Oscillation frequency : 1.0 MHz (in PWM mode)

• No flyback diode needed

• Low dropout operation : 100% on-duty support

(Continued)

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■PACKAGE

18-pin plastic BCC

(LCC-18P-M05)

MB39C001

(Continued)

• High-precision reference voltage generator integrated : 1.25 V ± 2% (with no load)

• Output voltage select function integrated : Capable of selecting internal setting (3 bits) or

external setting

• Built-in switching FETs : PMOS 0.43 Ω (Typ) , NMOS 0.32 Ω (Typ)

• Current mode control providing quick transition response to inputs/loads

• Built-in temperature protection function

• Low consumption current at shutdown mode : 1 µA or less

• Built-in undervoltage lockout protection circuit (UVLO) : Circuit actuation voltage of 2.3 V (Typ)

• Small pack age : BCC-18P

MB39C001

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■PIN ASSIGNMENT

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■PIN DESCRIPTION

Pin No. Symbol I/O Description

1, 2 LX1, LX2 O Inductor connection output terminals. Connect mutually and use the LX1

and LX2 terminal. They enter the high impedance state at shutdown.

3VRSELI

Reference voltage switch terminal. (Refer (2) “Setting output voltages”

in ■ APPLICATION NOTES)

4 OUT I Output voltage feedback terminal.

5 VREF O Reference voltage (1.25 V) output terminal.

6 POWER GOOD O POWERGOOD circuit output terminal.

An N-ch MOS open-drain circuit is connected.

7 VREFIN I Error amplifier (ErrorAmp) noninverting input terminal.

8AGNDControl block ground terminal.

9 CNT I Control input terminal (L : Shutdown, H : Normal operation ) .

10 AVDD Control block power-supply terminal.

11 VSET3 I Output voltage setting terminal. (Refer (2) “Setting output voltages” in

■ APPLICATION NOTES)

12 VSET2 I

13 VSET1 I

14, 15 DVDD1, DVDD2 Drive block power-supply terminal.

16 VSEL I Output voltage switch terminal. (Refer (2) “Setting output voltages” in

■ APPLICATION NOTES.)

17, 18 DGND1, DGND2 Drive block ground terminal.

DVDD2

VSEL

DGND1

DGND2

12345

LX1 LX2 VRSEL OUT VREF

14 13 12 11

DVDD1 VSET1

MB39C001

VSET2 VSET3

AVDD

CNT

AGND

VREFIN

POWER GOOD

(TOP VIEW)

LCC-18P-M05

MB39C001

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■I/O TERMINAL EQUIVALENT CIRCUIT DIAGRAM

∗

AVDD

OUT

AVDD

DVDD1

DVDD2 AVDD

AGND

DGND1

DGND2

LX1

LX2 VREF

POWER GOOD

VRSEL,

VSET1,

VSET2,

VSET3,

VSEL

AGND

VREFIN

AGND

CNT

AGND

* : ESD protection element

MB39C001

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■BLOCK DIAGRAM

−

7 3 8 1718

15 1410

VSEL

VSET1

VSET2

VSET3

VREF

POWER GOOD 6

OUT

CNT 9

VIN

ERR

Amplifier

Iout

Comparator

AVDD DVDD2 DVDD1

LX1

LX2LVOUT

DGND1DGND2AGNDVRSELVREFIN

1.25 V

Ref

SELECT

DET

PFM/PWM

Logic

Control

To each block

MB39C001

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■FUNCTIONS

About the Current Mode

Conventional voltage mode control compares the voltage (Vc) obtained by applying negative feedback to the

output voltage using the ErrAmp with the reference triangular waveform (Vtri) to control the on-duty cycle, thereby

regulating the output voltage.

Current mode control uses the oscillator (rectangular wa vef orm generator) , and the v oltage (VIDET) obtained b y

applying I-V conversion to the current which flows into SW FET, and uses them in place of the triangular waveform.

Current-mode control compares the voltage (Vc) obtained by applying negative feedback to the output voltage

using the ErrAmp with VIDET to control the on-duty cycle, thereby regulating the output voltage.

Function of Each Block

• PFM/PWM Logic Control Circuit

This circuit controls the synchronous rectification of inter nal P-channel MOS FET and N-channel MOS FET

at the frequency (1 MHz), set by the internal oscillator (rectangular wavefor m oscillator) dur ing normal oper-

ation. Under light loads, the circuit performs intermittent (burst) operation.

The precaution of the penetration current caused b y synchronous rectification and the re v erse current flowing

during discontinuous operation are performed to this circuit.

• Iout Comparator Circuit

This circuit detects the current (ILX) flowing from the internal P-channel MOS FET to the external inductor.

The circuit compares the output of ErrAmp with VIDET, obtained by applying I-V conversion to the ILX peak current

(IPK), and approaches the PFM/PWM Logic Control circuit to turn off the internal P-channel MOS FET.

−

VIN VIN

Vtri

VIDET

tON

tOFF

Vtri

SR-FF

Voltage mode control model Current mode control model

Oscillator

Note : The above models illustrate principles of operation; they are slightly different from actual

operations of the IC.

MB39C001

• ErrAmp phase compensation circuit

This circuit compares reference voltages such as VREF with output voltages. The IC contains a phase com-

pensation circuit and adjusted for the best operation of this IC , and it is eliminating the need for nominating a

phase compensation circuit and adding an external component for phase compensation.

•VREF circuit

A high-accuracy reference voltage is generated by a BGR (band gap reference) circuit. The output voltage is

1.25 V (Typ).

• SELECT circuit

This circuit is used to select a pre-set output voltage. The voltage can be set by changing the division resistance

value at the earlier stage of the ErrAmp.

•DET circuit

This circuit monitors the OUT ter minal voltage. When that voltage reaches the output set voltage, the open-

drain output at the POWER GOOD terminal is turned on.

• Protection circuit

An over temperature protection circuit is bu ilt in the IC as a protection circuit.

The over temperature protection circuit turns off both of the N-channel and P-channel SW FETs when the

junction temperature reaches 135°C.

Also , when the junction temperature f alls to 110 °C, the ov er temperature protection circuit operates normally.

Although the IC has no overcurrent protection circuit as a dedicated circuit, it uses current mode control for

v oltage control, and thus the peak-current value is monitored and controlled at any time . (The maximum peak-

current value is 1 A.)

MB39C001

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■ABSOLUTE MAXIMUM RATINGS

* : The package is mounted on a 10x10-cm square, dual sided epoxy board.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

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■RECOMMENDED OPERATING CONDITIONS

* : The output possible current can be tends to decrease when the voltage difference between the power supply

v oltage (VIN) and DC/DC con v erter output voltage (VOUT) is small. This is because of an effect of slope compen-

sation; it does not lead to the breakdown of the device. If it is the using condition which suppresses the output

current, it is possible to use it also with “VIN-VOUT<0.7 V”.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Condition Ratings Unit

Min Max

Power supply voltage VIN AVDD, DVDD1, and DVDD2

terminals 7V

Input voltage VI

OUT terminal −0.3 VDD + 0.3

CNT, VSEL, VSET1, VSET2,

VSET3, and VRSEL terminals −0.3 VDD + 0.3

VREFIN terminal −0.3 VDD + 0.3

POWER GOOD pull-up voltage VIPG 7V

LX voltage VLX LX1/LX2 terminal −0.3 VDD + 0.3 V

LX peak current IPK LX1/LX2 terminal 1.3 A

Power dissipation PDTa ≤ + 25 °C540* mV

Operating ambient temperature Ta −40 + 85 °C

Storage temperature TSTG − 55 + 125 °C

Parameter Symbol Condition Values Unit

Min Typ Max

Power supply voltage VIN AVDD, DVDD1, and

DVDD2 terminals 2.5 3.7 5.5 V

VREFIN voltage VRIN — 0.3 — 0.7 V

LX current ILX VIN – VOUT ≥ 0.7 V* — — 600 mA

POWERGOOD current IPG ———1mA

MB39C001

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■ELECTRICAL CHARACTERISTICS

(Unless otherwise specified , VIN = 3.7 V, CNT = 3.7 V, VSET1 = VSET2 = 0 V, VSET3 = VSEL = 3.7 V,

VRSEL = 0 V, Ta = +25°C)

* : Standard design value

(Continued)

Parameter Symbol Pin No. Condition Values Unit

Min Typ Max

DC/DC

converter

block

Reference voltage VREF 5VREF = 0 mA 1.21 1.25 1.29 V

Input current IREFIN 7 VREFIN = 0.6 V, VRSEL = 3.7 V −100 −40 nA

Output voltage VOUT

Load current = −200 mA*l1.764 1.8 1.836 V

Input stability Line 2.5 V < DVDD = AVDD < 5.5 V*2

Load current = 0 mA 40 mV

Load stability Load −200 mA > Load current >

−600 mA 20 mV

OUT terminal

Input impedance ROUT OUT = 2.0 V 1.01 MΩ

LX peak current IPK

1, 2 OUT = 90%1A

Oscillation

frequency fosc 0.8 1.0 1.2 MHz

fSHORT OUT = 0 V 100 170 240 kHz

Rise delay time tPG 680 µs

SW PMOS-FET

ON resistor RPMOS

1, 2

LX1 + LX2 = −100 mA 0.43 Ω

SW NMOS-FET

ON resistor RNMOS LX1 + LX2 = 100 mA 0.32 Ω

SW FET leak

current ILEAK 1µA

Output

voltage

select

block

Input threshold

voltage VTH 3,9,11,

12,13,16 CNT, VSEL, VSET1, VSET2,

VSET3, VRSEL terminal 0.3 1.0 1.5 V

Input current II

9 CNT terminal 01µA

3,11,12,

13,16 VSEL, VSET1, VSET2, VSET3,

VRSEL terminal 0.1 1 µA

Protection

circuit

block

Over temperature

protection (junc-

tion temperature)

TOTPH 4135*  °C

TOTPL 110*  °C

UVLO

threshold voltage VTHH

4, 10,

14, 15

2.3 V

VTHL 2.15 V

UVLO hysteresis

width VHYS 0.15 V

MB39C001

(Continued)

(Unless otherwise specified , VIN = 3.7 V, CNT = 3.7 V, VSET1 = VSET2 = 0 V, VSET3 = VSEL = 3.7 V,

VRSEL = 0 V, Ta = +25°C)

* : Standard design value

*1 : Refer (2) “Setting output voltages” in ■ APPLICATION NOTES.)

*2 : The minimum VIN value is 2.5 V or “output voltage setting value + 0.4 V”, either high one.

*3 : Detection to the output voltage setting value by VSET1 to VSET3. Refer (2) “Setting output voltages”

in ■ APPLICATION NOTES.)

*4 : The sum of the currents flowing to the AVDD terminal, DVDD1 terminal, and DVDD2 terminal.

*5 : Current consumption at a duty cycle of 100% (with the main SW FET full-on). The SW FET gate drive current

is not included because of a full-on state (not perf orming SW operation). And, the load current is not similarly

included.

Parameter Symbol Pin No. Condition Values Unit

Min Typ Max

POWER

GOOD

circuit

block

Threshold voltage VTHHPG

4, 6 *3 86 90 94 %

VTHLPG 84 88 92 %

Hysteresis width VHYSPG 2%

Output voltage VOL 6POWER GOOD = 25 µA0.1 V

Output current IOH POWER GOOD = 5.5 V  1µA

General

Power supply current

at shutdown IVDD1

10, 14,

CNT = 0 V, All circuits = OFF*4 1µA

Power supply current

on standby IVDD2 Load current = 0 mA 20 35 µA

Power supply current

during operation IVDD3 VOUT = 90% or OUT = 1.62 V*5300 400 µA

MB39C001

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■TYPICAL OPERATING CHARACTERISTICS

(The following characteristics are provided for setup reference purposes only; they are not guaranteed

characteristics.)

(Continued)

100

500.1 1 10 100 1000

VIN = 2.7 V

VIN = 3.7 V

VIN = 4.5 V Ta = +25 °C

L = 3.3 µH

C = 10 µF

VOUT = 1.8 V

100

500.1 1 10 100 1000

VIN = 2.7 V

VIN = 3.7 V

VIN = 4.5 V Ta = +25 °C

L = 3.3 µH

C = 10 µF

VOUT = 2.5 V

100

500.1 1 10 100 1000

VIN = 4.5 V

VIN = 3.7 V

Ta = +25 °C

L = 3.3 µH

C = 10 µF

VOUT = 3.3 V

Ta = +25 °C

VIN = 3.7 V

VOUT = 1.8 V

1.84

1.82

1.80

1.78

1.76

1.74 0 100 200 300 400 500 600

Conversion efficiency vs. Load current Conversion efficiency vs. Load current

Conversion efficiency η

ηη

η (%

Conversion efficiency η

ηη

η (%

Load current IOUT (mA) Load current IOUT (mA)

Conversion efficiency vs. Load current Output voltage vs. Load current

Conversion efficiency η

ηη

η (%

Output voltage VOUT (V)

Load current IOUT (mA) Load current IOUT (mA)

MB39C001

(Continued)

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.702.0 3.0 4.0 5.0 6.0

IOUT = 0 A

IOUT = 600 mA

Ta = +25 °C

VOUT = 1.8 V

1.30

1.28

1.26

1.24

1.22

1.20−50 −25 0 25 50 75 100

IOUT = 0 A

IOUT = 600 mA

VIN = 3.7 V

VOUT = 1.8 V

1.2

1.1

1.0

0.9

0.8 23456

Ta = +25 °C

VOUT = 1.8 V

IOUT = 600 mA

1.2

1.1

1.0

0.9

0.8−50 −25 0 25 50 75 100

VIN = 3.7 V

IOUT = 600 mA

Output voltage vs. Power supply voltage Reference voltage vs. Ambient temperature

Output voltage VOUT (V)

Reference voltage VREF (V)

Power supply voltage VIN (V) Ambient temperature Ta ( °

°°

°C)

Oscillation frequency vs. Power supply voltage Oscillation frequency vs. Ambient temperature

Oscillation frequency fosc (MHz)

Power supply voltage VIN (V) Ambient temperature Ta ( °

°°

°C)

MB39C001

(Continued)

023 4 5 6

Ta = +25 °C

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 0 A

0−50 −25 0 25 50 75 100

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 0 A

1.2

1.0

0.8

0.6

0.4

0.2

0.00.0 0.2 0.4 0.80.6 1.0

Ta = +25 °C

VIN = 3.7 V

IOUT = 200 mA

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0 23456

Ta = +25 °C

Pch

Nch

Power supply current vs.

Power supply voltage Power supply current vs.

Ambient temperature

Power supply current IIN (µ

µµ

µA)

Power supply current IIN (µ

µµ

µA)

Power supply voltage VIN (V) Ambient temperature Ta ( °

°°

°C)

Oscillation frequency −

−−

− VREFIN voltage SW FET ON resistance vs.

Power supply voltage

Oscillation frequency fosc (MHz)

SW FET ON resistance R (ON) (Ω

ΩΩ

Ω)

VREFIN voltage (V) Power supply voltage VIN (V)

MB39C001

(Continued)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0−50 −25 0 25 50 75 100

VIN = 3.7 V

VIN = 2.5 V

VIN = 5.5 V

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0−50 −25 0 25 50 75 100

VIN = 2.5 V

VIN = 3.7 V

VIN = 5.5 V

−50 −25 0 25 50 7585 100 125

600

500

400

300

200

100

210

540

Pch SW FET ON resistance vs.

Ambient temperature Nch SW FET ON resistance vs.

Ambient temperature

Pch SW FET ON resistance RP (ON) (Ω

ΩΩ

Ω)

Nch SW FET ON resistance RN (ON) (Ω

ΩΩ

Ω)

Ambient temperature Ta ( °

°°

°C) Ambient temperature Ta ( °

°°

°C)

Power dissipation vs.

Ambient temperature

Power dissipation PD (mW)

Ambient temperature Ta ( °

°°

°C)

MB39C001

(Continued)

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 0 mA to 600 mA

VOUT 200 mV/div

IOUT 0.5 A/div

20 µs/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 200 mA to 600 mA

20 µs/div

VOUT 200 mV/div

IOUT 0.5 A/div

Output waveforms at load sudden changes

MB39C001

(Continued)

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 100 mA to 600 mA

VOUT 200 mV/div

IOUT 0.5 A/div

20 µs/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 600 mA

VOUT 20 mV/div

400 ns/div

VLX 2 V/div

ILX 0.5 A/div

Output waveforms at load sudden changes

Switching waveforms (continuous operation)

MB39C001

(Continued)

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 100 mA

VOUT 100 mV/div

VLX 2 V/div

ILX 0.5 A/div

2 µs/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 600 mA

VOUT 1 V/div

ILX 0.5 A/div

VCNT 2 V/div

20 µs/div

Switching waveforms (during burst operation)

CNT terminal response characteristics

MB39C001

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■TYPICAL OPERATING CHARACTERISTICS MEASUREMENT CIRCUIT

Note : The above components are recommended parts confirmed by Fujitsu to operate normally.

COMPONENT ITEM Specification Vendor Parts No.

R1 Resistor 1 MΩssm PFR05Q-105-D-1

C2 Ceramic condenser 4.7 µF TDK C2012JB1A475K

C5 Ceramic condenser 0.01 µF TDK C1608JB1H103K

C1 Ceramic condenser 10 µF TDK C2012JB0J106M

L1 Inductor 3.3 µH TDK VLF4012AT-3R3M

ssm : SUSUMU CO., LTD.

TDK : TDK Corporation

VDD

VOUT

VIN

GND

DGND1, DGND2

LX1, LX2

DVDD1, DVDD2

AVDD

OUT

VRSEL

VSET1 to VSET3

CNT

AGND

VDD VDD

× 3

lOUT

C5 Load current

MB39C001

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■APPLICATION NOTES

(1) Selection of components

• Selection of external inductor

The design of the inductor is basically unnecessary. This IC is designed to operate efficiently with a 3.3 µH

inductor.

Select the inductor whose rated saturation current is larger than the LX peak current in the oper ating conditions,

and select the inductor whose DC resistance is as low as possible (150 mΩ or less is recommended) .

The LX peak current value (IPK) is obtained from the following formula :

L : External inductor value

IOUT : Load current

VIN : Power supply voltage

VOUT : Output setting voltage

D : Switching on-duty cycle ( = VOUT / VIN)

fosc : Switching frequency (fixed at 1 MHz)

Example : Peak current maximum value (IPK) : At VIN = 3.7 V, VOUT = 1.8 V, IOUT = 0.6 A, L = 3.3 µH.

• Selection of I/O condenser

• Select the DVDD input condenser whose equivalent series resistance (ESR) is low in particular, to suppress

the loss by ripple currents.

• Better line regulation and load regulation characteristics can be obtained by adding an input condenser im-

mediately close to AVDD. Although the appropriate capacitance may be different depending on the layout

design, the reference range for selection is from , 1000 pF to 0.01 µF.

• The output condenser should also have low equivalent series resistance (ESR). The ripple current of the

fluctuation portion of the inductor current, it flows into the output condenser. The ripple voltage is the product

of this fluctuation portion and ESR, it is generated at the output. The output capacitance significantly affects

the stability of operation as a DC/DC conver ter. In principle, an output condenser of about 10 µF is recom-

mended. If there is a problem with the ripple v oltage , y ou can work around the problem b y selecting one with

large capacitance.

• Condenser types

Selecting ceramic condenser for both of input and output is effective for reduction in ESR and size. Since

power supply circuits are heat generators, you should avoid using ceramic condenser which have an F tem-

perature characteristic (-80% to +20%). You should use those with a B characteristic (± 10% to ± 20%) or the like.

Avoid using normal electrolytic condenser as their ESR is high.

Tantalum condenser are effective for reduction in ESR but are very dangerous as they have a disadvantage,

they establish a short mode if a failure occurs. When using a Tantalum condenser, choose one with a fuse.

IPK = IOUT + VIN − VOUT •D•1 = IOUT + (VIN − VOUT) • VOUT

Lfsw2 2 • L • fsw • VIN

IPK = IOUT + (VIN − VOUT) • VOUT = 0.6 A + (3.7 V − 1.8 V) • 1.8 V := 0.74 A

2 • L • fsw • VIN 2 • 3.3 µH • 1 MHz • 3.7 V

MB39C001

(2) Setting output voltages

When output voltages are set in advance, only treat the control terminals as shown in the table below. Any

additional component such as a voltage dividing resistor is not required.

As VSET1 to VSET3, VSEL, and VRSEL ter minals have built-in pull-down equal circuits, their level is equal to

“L” when opened.

Note : For a circuit configuration example, refer (1) “Setting 1.8-V output using the internal reference voltage”

in ■ APPLICATION EXAMPLES.

•

••

• Output voltage setting table 1

X : Don’t care

To set arbitrary voltages other than abo v e, set VRSEL to “H” and apply v oltage to VREFIN. The v oltage applied

to VREFIN is supplied either from external or by dividing VREF using a resistor. The output voltage using

VREFIN with VREF resistor-divided is obtained from the following formula :

(VREFIN voltage : × 1.25 Refer (4) “VREFIN terminal in ■ NOTES ON CIRCUIT DESIGN”.

Note : For a circuit configur ation e xample, refer (2) “Supplying the VREF terminal voltage to the ref erence v oltage

external input (VREFIN) after resistor voltage division and setting the VOUT voltage to 1.25 V with VOUT setting

gain doubled” in ■ APPLICATION EXAMPLES.

The output voltage is determined by the resistor ratio. Select the resistance value so that the current flowing

through the resistor does not exceed the rated VREF current (1 mA) .

VSET1 VSET2 VSET3 VSEL VRSEL VOUT

LLLX

1.1 V

H L L L 0.8 V

H L L H 1.2 V

L H L X 1.3 V

H H L L 1.1 V

H H L H 1.5 V

L L H L 1.1 V

L L H H 1.8 V

H L H X 2.5 V

L H H X 2.8 V

H H H X 3.3 V

VOUT = (Output voltage setting value) • Kv Kv = R8 •1.25

R7 + R8 0.6

R7 + R8

MB39C001

•

••

• Output voltage setting table 2

X : Don’t care

(3) About conversion efficiency

The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit.

The total loss (PLOSS) of the DC/DC converter is roughly divided as follows :

PLOSS = PCONT + PSW + PC

PCONT : Control system circuit loss (The power used f or this IC to operate, including the the gate driving power

for internal SW FETs)

PSW : Switching loss (The loss caused during switching of the IC's internal SW FETs)

PC : Continuity loss (The loss caused when currents flo w through the IC's internal SW FETs and external

circuits )

The IC's control circuit loss (PCONT) is extremely small, which is about 1 mW (IIN = 300 µA) * , at VIN = 3.7 V.

As the IC contains FETs which can switch faster with smaller power , the continuity loss (PC) is more predominant

as the loss during heavy-load oper ation than the control circuit loss (PCONT) and switching loss (P SW) .

Further the continuity loss (PC) is divided roughly, into the loss by internal SW FET ON-resistance and by external

inductor series resistance.

PC = IOUT2 • (RDC + D • RONp + (1 − D) • RONn)

D : Switching on-duty cycle ( = VOUT / VIN)

RONp : Internal Pch SW FET ON resistance

RONn : Internal Nch SW FET ON resistance

RDC : External inductor series resistance

IOUT = Load current

VSET1 VSET2 VSET3 VSEL VRSEL VOUT (Output voltage setting value ×

× ×

× Kv)

LLLX

1.1 V × Kv

H L L L 0.8 V × Kv

H L L H 1.2 V × Kv

L H L X 1.3 V × Kv

H H L L 1.1 V × Kv

H H L H 1.5 V × Kv

L L H L 1.1 V × Kv

L L H H 1.8 V × Kv

H L H X 2.5 V × Kv

L H H X 2.8 V × Kv

H H H X 3.3 V × Kv

MB39C001

The above for mula indicates that it is impor tant to reduce RDC as much as possible to improve efficiency by

selecting components.

* : The loss is caused during continuous operation. When the load is light, the IC perf orms burst operation, thereby

further suppressing the loss (IIN = about 30 µA with no load). The mode is changed depending on the peak

current value Ipk flowing into SW FETs, at a threshold value of about 150 mA.

(4) Power dissipation and temperature examination

The IC is so efficient that no examination is required in most cases. But if the IC is used at a low po wer supply

voltage, heavy load, high output voltage, or high temperature, it requires further examination for higher efficiency .

The internal loss (P) is roughly obtained from the following formula :

P = IOUT2 • (D • RONp + (1 − D) • RONn)

D : Switching on-duty cycle ( = VOUT / VIN)

RONp : Internal Pch SW FET ON resistance

RONn : Internal Nch SW FET ON resistance

IOUT = Load current

The loss e xpressed by the abo v e f ormula is mainly contin uity loss. The internal loss includes the switching loss

and the control circuit loss as well but they are so small compared to the continuity loss they can be ignored.

In this IC with RONp greater than RONn, the larger the on-duty cycle, the greater the loss.

When assuming VIN = 3.7 V, Ta = 70 °C, VOUT = 1.8 V, and IOUT = 0.6 A, for example, RONp = 0.48 Ω and

RONn = 0.39 Ω according to the graph “SW FET ON resistance vs. Ambient temperature”. The IC's internal

loss P is 156 mW. According to the graph “Power dissipation vs. ambient temperature”, the power dissipation

at an ambient temperature Ta of 70 °C is 300 mW and the internal loss is smaller than the power dissipation.

(5) Transient response

The IC contains an optimized version of ErrAmp, providing favorable transient response characteristics.

The response characteristics such as response time, overshoot, and undershoot, are checked usually by chang-

ing suddenly IOUT, with VIN and VOUT left constant.

(6) Example of designing board layout

For stable operation, the IC requires the optimized design of board layout.

Pay attention to the following points during layout design.

• Connect the GND terminals (AGND, DGND1, DGND2) and power terminals (AVDD, DVDD1, DVDD2) imme-

diately near the IC.

• Place the DVDD input condenser (C2) near DVDD and DGND. If the power supply or ground plains exists on

any other board layer, place TH (through hole) close to the condenser terminal.

• Place the AVDD input condenser (C5) near AVDD and AGND. If the power supply or ground plains exists on

any other board layer, place TH (through hole) close to the condenser terminal.

MB39C001

• Place the GND side terminal of the output condenser (C1) as near DGND of the IC and the GND side terminal

of the input condenser (C2). If the ground plains exists on any other board layer, place TH close to the GND

side terminal of the condenser . For wiring to OUT, start close to the VOUT side terminal of the output condenser

(CI). Note that the OUT ter minal is highly sensitive and should be wired as apar t from the wir ing of the LX

terminal of the IC.

• Large currents flow among the input condenser (C2, C5), output condenser (C1), external inductor (L1), and

this IC . Place these components near the IC , to minimiz e the loop area made up of these components. Also,

mount these components on the same layer and wire them without using any TH. Wire these nets using as

bold, short, and straight patterns (plains layout is advisable).

• For the IC mounted layer, provide a ground plane.

Recommended layout drawing (with only important wiring)

VIN TH

GND

VOUT

MB39C001

■

■■

■NOTES ON CIRCUIT DESIGN

(1) GND Potential

Connect AGND and DGND to GND of the power supply circuit, so that they have equal potential.

(2) Control input terminals

• The voltages applied to the CNT, VSET1 to VSET3, VSEL, and VRSEL terminals must not exceed the absolute

maximum rating (VDD + 0.3 V). Applying a voltage exceeding the absolute maximum rating may cause

per manent damage to the LSI. If it is inevitable, inser t a resistor of about 20 kΩ between a ter minal of the

controller (such as a CPU) and the control terminal of the IC. This prevents a latch-up to some extent.

Note : Finally, judge right or wrong of the adoption after confirming it is unquestionable under y our system require-

ments as permanent measure.

• The CNT terminal has no internal pull-down resistor function (while the VSET1 to VSET3, VSEL, and VRSEL

hav e one). If the terminal of the controller (such as the CPU) connected to the CNT terminal can enter a high

impedance state an unpredictable malfunction may occur. To prevent this, a pull-down resistor (of about

1 MΩ) should be connected to the CNT terminal.

• If the fall time of the CNT terminal is long, the output (VOUT) may cause an overshoot when the load is light.

Be careful not to let the rise time and fall time exceed 500 µs.

(3) Power supply input

• If the rise time or fall time of the supply voltage (VIN) is long, a malfunction ma y occurs. Be careful not to let

the rise time and fall time exceed 100 ms.

• If the pow er supply v oltage fluctuates around the UVLO detection v oltage (between 2.15 and 2.3 V) when the

power supply is turned on or shut off. The output is stopped by under-voltage and restarted by restored voltage

repeatedly and there is a possibility that chattering is generated in VOUT. Although the UVLO detection v oltage

has a hysteresis of 0.15 V, fluctuation over 0.15 V cannot be suppressed. Be careful to prevent the supply

voltage from going up and down near UVLO.

• If the CNT terminal becomes "L" from "H" when the supply voltage (VIN) becomes lower than the output voltage

(VOUT), the IC may cause a latch-up by the action of an external inductor. Although this is an operating condition

unintended for normal use, it can occur frequently when the power supply voltage is shut off with light loads.

Even if a latch-up occurs by nor mal shutdown, the latch-up is cleared when the power supply voltage goes

below 0.8 V. Therefore, there are few things which become problem, when the power supply is turned back

on again. If the power supply is turn ed back on with the power supply voltage exceeding 0.8 V, the IC may

be broken by an excessive current due to a latch-up. This problem can be worked around by either of the

following two methods :

•When the CNT terminal becomes "L" from "H" as the power supply voltage goes down, be sure to lower

the power supply voltage to 0.8 V or less before turning the power supply back on again.

•Add a Schottky barrier diode as shown in the latch-up preventive circuit example.

Note, however, that this work around adversely affects the regulation or conversion efficiency when the

application uses an e xtremely small load current. When selecting the Schottky barrier diode, pa y attention

to the following points :

Reverse current [IR]

Select a diode whose reverse current is smaller than the load current. (If a diode whose reverse current

is greater than the load current is adopted, the output voltage (VOUT) is raised b y the reverse current,

and the regulation deteriorates.

MB39C001

Forward voltage [VF]

The forward voltage must be smaller than the voltage triggering latch-up. Select a diode whose forward

voltage is about 0.5 V or less.

Non repetitive peak surge current [IFSM]

Select a diode whose non repetitiv e peak surge current is greater than the peak re v erse current. The

peak current is different depending on the operating conditions; the reference value is 1 A to 3 A.

Latch-up preventive circuit example

(4) VREFIN terminal

When the VREFIN ter minal is used, the switching frequency is lowered if the VREFIN voltage is 0.5 V or less.

When the load current (IOUT) is 100 mA or less, the VREFIN voltage should fa ll within the range of 0.5 to 0.7 V.

The VREFIN voltage can be between 0.3 and 0.7 V if the switching frequency lowered is acceptable when the

load current (IOUT) is 100 mA or less.

(5) POWER GOOD terminal

The POWER GOOD terminal always monitors the OUT terminal voltage, with no exception, even when the

output voltage is changed by switching the ter minals such as VSET1 to VSET3 and VSEL. When the output

voltage rises slowly with heavy loads, the PO WER GOOD terminal become "H" until the output voltage becomes

90% of the setting voltage.

Be careful when using the POWER GOOD ter minal to reset a load circuit which uses a CPU. Be careful that

the POWER GOOD ter minal temporarily becomes “H” level when dynamically changing the voltage, thereby

resetting the circuit accidentally at an unintended timing.

(6) Output overcurrent protection

This IC uses current mode control which provides a cer tain level of overcurrent protection. If LX is connected

to VDD or GND, or V OUT is connected to GND with an extremely low resistor of 0.1 Ω or less , the IC may not be

protected from overcurrents and it is break down.

The IC is apt to break down, when the inductance element of the short-circuit route is large or when the output

v oltage is high. To prev ent the IC from breaking due to a short-circuit, it is advisable to insert a resistor of about

1 kΩ between the OUT terminal and VOUT.

AVDD DVDD1 DVDD2

LX1

LX2

OUT

AGND DGND1 DGND2

VIN

VOUT

8 17 18

1514

Schottky barrier diode

for latch-up prevention

MB39C001

■

■■

■APPLICATION EXAMPLES

(1) Output setting of 1.8 V by reference voltage use of internal

(2) Supplying the VREF terminal voltage to the reference voltage external input (VREFIN) after resistor

voltage division, the VOUT voltage is set to 1.25 V by the OUT setting gain twice

18178

10 14 15

0.01 µF

AVDD DVDD1 DVDD2

VSET1

VSET2

VSET3

VSEL

CNT

VRSEL

POWER GOOD

OUT

LX1

LX2

VREF

VREFIN

AGND DGND1 DGND2

1 MΩ

20 kΩ

CPU

4.7 µFVIN

VOUT

3.3 µHC1

10 µF

1 MΩAPLI

18178

10 14 15

0.01 µF

AVDD DVDD1 DVDD2

VSET1

VSET2

VSET3

VSEL

CNT

VRSEL

POWER GOOD

OUT

LX1

LX2

VREF

VREFIN

AGND DGND1 DGND2

1 MΩ

100 kΩ

20 kΩ

CPU

4.7 µFVIN

VOUT

3.3 µHC1

10 µF

APLI

VOUT = (Output voltage setting value ) × VREFIN

0.6

= 1.2 • VREFIN = 2 × R8 VREF

0.6 R7 +

+ R8

= 2 × 100 k × 1.25 = 1.25 V

100 k +

+ 100 k

MB39C001

(3) Supplying an external voltag e to the reference voltag e external input (VREFIN), the VOUT vol tage is se t

by the VOUT setting gain triple

The components for the above example are listed below.

TDK : TDK Corporation

ssm : SUSUMU CO., LTD.

Component Part name Specification Manufacturer Model name

L1 Inductor 3 .3 µH20% RDC = 120 mΩTDK VLF4012AT-3R3M

C1 Ceramic condenser 10 µF20% 6.3 V TDK C2012JB0J106M

C2 Ceramic condenser 4.7 µF10% 10 V TDK C2012JB1A475K

C5 Ceramic condenser 0.0 1 µF10% 50 V TDK C1608JB1H103K

R1 Resistor 1 MΩ0.5%ssm PFR05Q-105-D-1

R2 Resistor 20 kΩ0.5%ssm RR0816P-203-D

R6 Resistor 1 MΩ0.5%ssm PFR05Q-105-D-1

R7 Resistor 100 kΩ0.5%ssm RR0816P-104-D

R8 Resistor 100 kΩ0.5%ssm RR0816P-104-D

18178

10 14 15

0.01 µF

AVDD DVDD1 DVDD2

VSET1

VSET2

VSET3

VSEL

CNT

VRSEL

POWER GOOD

OUT

LX1

LX2

VREF

VREFIN

AGND DGND1 DGND2

1 MΩ

20 kΩ

CPU

DAC

4.7 µFVIN

VOUT

3.3 µHC1

10 µF

APLI

VOUT = (Output voltage setting value ) × VREFIN

0.6

= 1.8 • VREFIN = 3 × VREFIN

0.6

MB39C001

■

■■

■NOTES ON USE

1. Do not exceed maximum ratings.

Using the LSI beyond maximum ratings may generate a parasitic transistor, resulting in permanent damage to

the LSI due to a latch-up . The LSI should be used under the recommended operating conditions and e xceeding

any of the recommended conditions may adversely affect LSI reliability.

2. Use under recommended operating conditions.

The recommended operating conditions are reommended values that guarantee the normal operation of the LSI.

The v alues of electrical characteristics are guaranteed when the LSI is used under the recommended operating

conditions with each parameter falling in the specified range.

3. Take measures against static electricity.

• Containers for semiconductors must be antistatic or conductive.

• When storing or carrying a printed circuit board with components mounted, put it in a conductive bag or

container.

• The work table, tools, and measuring instruments must be properly grounded.

• The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.

4. Do not apply a negative voltage.

Applying a negative voltage of − 0.3 V or less to an LSI may generate a parasitic transistor , resulting malfunction.

■

■■

■ORDERING INFORMATION

Model Package Remarks

MB39C001PVB 18-pin plastic BCC

(LCC-18P-M05)

MB39C001

■

■■

■PACKAGE DIMENSIONS

18-pin plastic BCC

(LCC-18P-M05)

Unit : mm (inches)

Note : Parenthesized values are reference values.

2003 FUJITSU LIMITED C18058S-c-1-1

0.05(.002)

2.70±0.10

2.40±0.10

(.094±.004)

0.45±0.05

0.075±0.025

(.003±.001)

(.018±.002)

(Stand off)

0.45(.018)

TYP.

2.31(.090)

1.90(.075)

REF

2.01(.079)

TYP

TYP.

0.45(.018)

1.35(.053)

2.28(.090)

"A" "B"

"C"

1510

15 10

0.28±0.06

(.011±.002)

0.36±0.06

(.014±.002)

C0.10(.004)

0.25±0.06

(.010±.002)

0.25±0.06

(.010±.002)

Details of "B" part Details of "C" partDetails of "A" part

(.106±.004)

REF

TYP

INDEX AREA

MIN.

0.14(.006)

(Mount height)

(.011±.002)

0.28±0.06

(.014±.002)

0.36±0.06

0.90(.035)

REF

MB39C001

■

■■

■EVALUATION BOARD SPECIFICATIONS

The MB39C001 e valuation board is a surf ace-mounting board of a single-channel down-con v ersion circuit. The

output v oltage can be set by s witch of each SW (*1), and supplies the current of up to 600 mA at a po wer supply

voltage from 2.5 V to 5.5 V (*2).

*1 : For setting the output voltage, refer (2) "Setting output voltages" in ■ APPLICATION NOTES.

*2 : The current can be supplied when “VIN - V OUT ≥ 0.7 V”. It can be supplied ev en “VIN - V OUT < 0.7 V” when under

operating conditions in which the output current is suppressed.

• Terminal Description

• Switch Description

• Setup and checkup

(1) Setup

Connect the pow er supply terminal of the power supply to VIN, VCTL, and CNT and its ground terminal to GND.

Connect the OUT side to the required loading device or measuring instrument.

Set SW1 (VSEL) and SW4 (VSET3) to ON; SW2 (VSET1), SW3 (VSET2), and SW5 (VRSEL) to OFF. (Set the

output to 1.8 V using the internal reference voltage.)

(2) Checkup

Supply power to VIN. The IC is working normally when the OUT voltage is 1.8 V (Typ) .

Symbol Function

VIN Power supply terminal.

VIN = 2.5 V to 5.5 V (3.7 V Typ)

OUT DC/DC converter output terminal.

VCTL Power supply terminal for mode setting SW.

Connect with VIN and use it.

CNT Power control terminal.

VCNT = 0 V to 0.3 V : Shutdown

VCNT = 1.5 V to VIN : Normal operation

POWER_GOOD Fixed at “L” ( = 0 V) , when the OUT voltage reaches the output setting voltage.

VREF Reference voltage output terminal.

VREFIN External reference voltage input terminal.

When an external reference voltage is used, this terminal supplies it.

GND DC/DC converter ground terminal.

AGND MB39C001 ground terminal.

SW Name FUNCTION Remarks

1 VSEL Output voltage setting

For details on each setting, refer (2) "Setting output

voltages" in ■ APPLICATION NOTES.

2 VSET1 Output voltage setting

3 VSET2 Output voltage setting

4 VSET3 Output voltage setting

5 VRSEL Reference voltage setting

MB39C001

• On-board Component Layout

123456

SW1 AGND

N. C

VRSEL

VSEL

VSET3

VSET2

VSET1

CNT

VREFIN

POWER_GOOD

M1 C5 R8

VREF

VCTL

VIN

GND

OUT

Top side (Top View)

Bottom side (Top View)

MB39C001

Board Layout

Top Side (Layer1) In Side VIN & GND (Layer2)

Inside GND (Layer3) Bottom Side (Layer4)

MB39C001

• Connection Diagram

• Parts List

• Ordering Information

Symbol Part name Model name Specification Package Manufacturer Remarks

L1 Inductor VLF4012AT-3R3M 3.3 µH,

RDC = 120 mΩSMD TDK

C1 Ceramic capacitor C2012JB0J106M 10 µF (6.3 V) 2012 TDK

C2 Ceramic capacitor C2012JB1A475K 4.7 µF (10 V) 2012 TDK

C3 Ceramic capacitor C1608JB1H104K 0.1 µF (50 V) 1608 TDK

C4 

Not mounted

C5 Ceramic capacitor C1608JB1H103K 0.01 µF (50 V) 1608 TDK

R6 Resistor PFR05Q-105-D-1 1 MΩ ± 0.5%1005 ssm

R7 Resistor RR0816P-104-D 100 kΩ ± 0.5%1608 ssm

R8 Resistor RR0816P-104-D 100 kΩ ± 0.5%1608 ssm

SW Switch DMS-6H 6 poles MATSUKYU

Terminal pins WT-2-1 WT-2-1 MacEight

TDK : TDK Corporation

ssm : SUSUMU CO., LTD.

MATSUKYU : Matsukyu Co., Ltd.

MacEight : MacEight Co., Ltd.

EV board part No. EV board version No. Remarks

MB39C001EVB-01 MB39C001EV Board Rev.2.0

18178

10 14 15

0.01 µF

100 kΩ

3.3 µHC1

10 µF

4.7 µF

SW3

SW4

SW1

SW5

0.1 µF

MB39C001

AGND

GND

POWER GOOD

OUT

IOUT

1 MΩ

VREF

VREFIN

SW2

VCTL

VIN

IIN

CNT

MB39C001

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0405

 FUJITSU LIMITED Printed in Japan