FUJITSU SEMICONDUCTOR DATA SHEET DS04-27712-1E ASSP For Power Supply Applications (Secondary Battery) Lithium Ion Battery Pack Control IC MB3838A DESCRIPTION The MB3838A is a lithium-ion battery pack control IC for 3/4-cell series lithium-ion battery packs in notebook PCs with 12.6 V/16.8 V charging system, and is designed to control charging and discharging by detecting over-charge, over-discharge, and over-current conditions. When the IC detects an over-discharge of the lithium-ion battery, advance warning signal is sent before shutting off discharge. This function enables data in the notebook PCs memory to be saved to the hard disk. After the over-discharge is detected and after inputting the PDWN signal (state of quasi-over-discharge) , current consumption becomes 0 A to cut all biases of IC. Therefore, even if the battery pack is left for a long term, use by the re-charge is enabled. Moreover, because charge and discharge control FET can be turned off by remote on function at the battery pack unit, the output short-circuit by the misoperation can be prevented. In addition, because it provides with the reference voltage power supply for the A/D converter and the VDD regulator, and the cell voltage monitor and the current monitor function are built-in, the remainder amount monitoring system with built-in battery pack can be easily composed. PACKAGE 24-pin plastic SSOP (FPT-24P-M03) MB3838A FEATURES * * * * * * * * * Power supply voltage range : 6.5 V to 25 V High-precision over-charge detection voltage : 4.325 V 0.025 V Circuit current consumption after over-discharge detection : 0 A (Typ) Built-in reference voltage power supply and VDD regulator Built-in cell voltage monitor and current monitor function Built-in quasi-over-discharge function Built-in advance warning function to prevent over-discharge output Built-in remote on/off function Built-in over-current detection function with two-stage delay time : VTH1 = 110 mV7 ms (Typ) : VTH2 = 300 mV 500 s (Typ) * Built-in 0 V cell charge return function 2 MB3838A PIN ASSIGNMENT (TOP VIEW) OCV 1 24 AOUT2 COUT 2 23 D1 BAT4 3 22 D2 COVT 4 21 D3 BAT3 5 20 AOUT1 CPDT 6 19 SEL BAT2 7 18 VS COCT 8 17 VCC BAT1 9 16 OUTON DOUT 10 15 VDD VIS 11 14 VREF GND 12 13 PDWN (FPT-24P-M03) 3 MB3838A PIN DESCRIPTIONS 4 Pin no. Symbol I/O Descriptions 1 OCV I Discharge/charge state detection terminal 2 COUT O P-ch MOS FET control terminal for charge control (Open collector) 3 BAT4 I Battery connection terminal 4 COVT 5 BAT3 I 6 CPDT 7 BAT2 I 8 COCT 9 BAT1 I Battery connection terminal 10 DOUT O P-ch MOS FET control output terminal for discharge control switch (CMOS output) 11 VIS I Current detection terminal 12 GND 13 PDWM I Power down signal input terminal 14 VREF O Reference voltage output terminal 15 VDD O VDD regulator output terminal 16 OUTON I Remote-on signal input terminal 17 VCC Power supply terminal 18 VS O Battery voltage monitor and power down advance warning signal output terminal 19 SEL I 3-cell/4-cell switch terminal At "L" level input : 3-cell mode At "H" level input : 4-cell mode 20 AOUT1 O Cell voltage monitor output terminal 21 D3 I Cell voltage and current monitor mode switch signal input terminal 22 D2 I Cell voltage and current monitor mode switch signal input terminal 23 D1 I Cell voltage and current monitor mode switch signal input terminal 24 AOUT2 O Current monitor output terminal Condenser connection terminal for setting over-charge detection delay time Battery connection terminal Condenser connection terminal for setting over-discharge detection delay time Battery connection terminal Condenser connection terminal for setting over-current detection delay time Ground terminal VIS 11 GND 12 BAT1 9 BAT2 7 BAT3 5 Gain change bias ON/OFF AOUT2 24 D1 D2 D3 AOUT1 23 22 21 20 [Decoder block] 3-bit decoder Multiplexer 2.75 V 2% - - - - + 4.325 V 0.6% + - VTH2 VTH1 - + - + Delay Latch2 time (23 ms) reset VCC - OCV > 0.3 V DOUT 10 COUT 2 COCT 8 Delay time (7 ms) (500 s) 4 Reset Latch1 COVT Latch3 6 CPDT Power down delay time (20 s) OCV 1 600 Reference voltage power supply 5V 1% VDD regulator 5V 2% ON/OFF [Remote on circuit block] VCC [Over-discharge detection block PF output and Power fail block] delay time (2 s) Reset [Over-current detection block] [Cell voltage monitor block] x1 x1 [Current monitor block] 50 m/10 mV + - x 48/x125 100 k 100 k 100 k x1 + - [Cell switch circuit block] [Over-charge detection block] SEL 19 [Cell voltage input block] [Cell voltage amp block] + - BAT4 3 x1 + 100 k - VCC 17 13 PDWN 16 OUTON 18 VS 15 VDD 14 VREF MB3838A BLOCK DIAGRAM 5 MB3838A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition VCC Power supply voltage Rating Unit Min Max 28 V Input voltage VI BAT4, BAT3, OCV, PDWN, OUTON terminal 28 V Collector output voltage VO COUT terminal 28 V Output current IO DOUT, COUT terminal (DC) 2 mA Peak output current IOP DOUT, COUT terminal Duty = tON/t 2/Duty mA Power dissipation PD Ta +25 C 740* mW Operating ambient temperature Ta -30 +85 C TSTG -55 +125 C Storage temperature * : When mounted on a 10cm square epoxy double-sided. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATION CONDITIONS Parameter Power supply voltage Symbol Condition VCC Output current OCV terminal outside resistor Condenser for setting delay time VI IO Unit Min Typ Max 6.5 16.8 25 V 0 25 V VIS terminal -0.3 +0.3 V SEL terminal 0 VCC V D1, D2, D3 terminal 0 VDD V VREF terminal -600 0 A VDD terminal -10 0 mA VS terminal -10 0 mA OCV, PDWN, OUTON terminal Input voltage Value ROCV 470 COVT 0.068 F CPDT 1.0 F COCT 1800 pF WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB3838A ELECTRICAL CHARACTERISTICS Parameter Detection voltage Over-charge Detection Block Over-discharge Detection Block and Power Fail Block Symbol VTH Pin No. Ta = +25 C, 2, 3, Each cell voltage 5, 7, 9 Ta = 0 C to +70 C 4.300 4.325 4.350 V 4.280 4.325 4.370 V 0.14 0.20 0.26 V 0.1 0.5 A 11.5 23 34.5 ms Hysteresis width VH 2, 3, 5, 7, 9 Input current IIN 2, 3, Each cell voltage = 5, 7, 9 4.2 V Delay time tD 2 COVT = 0.068 F Output voltage VOL 2 COUT = 1 mA 0.75 1.0 V Output leak current ILEAK 2 COUT = 18 V 0 0.5 A Detection voltage VTH 3, 5, 7, 9, 10 2.695 2.75 2.805 V VS output delay time tD1 18 CPDT = 1.0 F 1 2 3 s Power-down delay time tD2 10 CPDT = 1.0 F 10 20 30 s Input threshold voltage VTH 2.0 3.5 5.0 V Input current IIN 13 PDWN terminal, PDWN = 5 V 50 100 A VTH1 11 VIS terminal voltage 88 110 132 mV VTH2 11 VIS terminal voltage 240 300 360 mV tD1 10 COCT = 1800 pF, VTH2 > VIS > VTH1 4 7 10 ms tD2 10 COCT = 1800pF, VIS > VTH2 250 500 750 s IIN 11 VIS = 0 V 0 A VOL 10 DOUT terminal, DOUT = 1 mA 1.0 V VOH 10 DOUT terminal, DOUT = -0.4 mA VCC - 0.4 V Delay time Input current Each cell voltage PDWN terminal, 10, 13 Each cell voltage = 2V Detection voltage Over-current Detection Block Condition (Ta = +25 C, VCC = OCV = 16.8 V) Value Unit Min Typ Max Output voltage (Continued) 7 MB3838A Parameter Input current in over-charging Cell Voltage Input Block Reference Voltage Block VDD Regulator Block Cell Voltage Monitor Block Short cell detection voltage Symbol Pin No. IIN 3, 5, 7, 9 VTH Condition Each cell voltage = 4.5 V Cell voltage = 3.6 V 2, 3, (Except for mea5, 7, 9 surement cell) , COUT = "L" "H" (Ta = +25 C, VCC = OCV = 16.8 V) Value Unit Min Typ Max 22.5 45 67.5 A 0.6* V VREF 14 VREF = -0.1 mA, Ta = +25 C 4.95 5.00 5.05 V VREF 14 VREF = -0.1 mA, Ta = 0 C to +70 C 4.90 5.00 5.10 V Input stable range LINE 14 VCC = 6.5 V to 25 V, VREF = -0.1 mA 5 10 mV Output voltage VDD 15 VDD = -1 mA 4.90 5.00 5.10 V Input stable range LINE 15 VCC = 6.5 V to 25 V, VDD = -1 mA 10 50 mV Load stable range LOAD 15 VDD = -1 mA to -10 mA 20 80 mV Input current IIN 3, 5, 7, 9 Each cell voltage = 4V 0.1 0.3 A Voltage gain AV 20 Each cell voltage = 2.0 V to 4.4 V 0.98 1.0 1.02 V/V Output offset voltage VOF 20 -20 0 +20 mV Output source current ISOURCE 20 AOUT1 = 3.6 V -10 -5 mA ISINK 20 AOUT1 = 3.6 V 40 80 A VOH 20 VDD - 0.3 VDD V VOL 20 0 0.2 V Output voltage Output sink current Output voltage * : Standard design value (Continued) 8 MB3838A Parameter Symbol Pin No. IIN 11 VIS = 0 V AV1 24 AV2 -10 A D1 = 5 V, D2 = 0 V, D3 = 5 V 45.6 48 50.4 V/V 24 D1 = 0 V, D2 = 0 V, D3 = 5 V 121 125 129 V/V VOF1 24 D1 = 5 V, D2 = 0 V, D3 = 5 V -100 0 100 mV VOF2 24 D1 = 0 V, D2 = 0 V, D3 = 5 V -230 0 230 mV VOS1 24 D1 = 5 V, D2 = 5 V, D3 = 5 V 1.85 2.0 2.15 V VOS2 24 D1 = 5 V, D2 = 5 V, D3 = 0 V 1.65 2.0 2.35 V VOS1D 24 D1 = 5 V, D2 = 0 V, D3 = 5 V -50 0 50 mV VOS2D 24 D1 = 0 V, D2 = 0 V, D3 = 5 V -100 0 100 mV ISOURCE 24 AOUT2 = 3.6 V -10 -5 mA ISINK 24 AOUT2 = 3.6 V 40 80 A VO1 24 VIS = 0 V, D1 = 5 V, D2 = 0 V, D3 = 5 V 1.85 2.0 2.15 V VO2 24 VIS = 0 V, D1 = 0 V, D2 = 0 V, D3 = 5 V 1.65 2.0 2.35 V VOH 24 VDD - 0.3 VDD V VOL 24 0 0.2 V Input current IIN 21, 22, 23 D1 = D2 = D3 = 5 V 50 100 A Input threshold voltage VTH 21, 22, 23 0.8 1.4 2.0 V Output delay time after switching tDO 20, 24 250 500 s Input current Voltage gain Output offset voltage Output voltage at input short mode Current Monitor Block Output change at input short mode Output source current Output sink current Output voltage Decoder Block Condition (Ta = +25 C, VCC = OCV = 16.8 V) Value Unit Min Typ Max (Continued) 9 MB3838A (Continued) Symbol Pin No. Input current IL 19 "L" level input voltage VIL 19 "H" level input voltage VIH 19 Input threshold voltage VTLH 1 Input current IIN Input resistance in power down Parameter Cell Switch Circuit Block Remote on Circuit Block 0 1 A 0 0.3 x VCC V 0.7 x VCC VCC V OCV terminal 0.8 1.4 2.0 V 1 OCV terminal, OCV = 18 V 10 20 A RIN 1 OCV terminal 480 600 720 Input threshold voltage VTH 16 OUTON terminal 1.2 1.8 2.4 V Input current IIN 16 OUTON terminal, OUTON = 18 V 0.1 0.5 A Output voltage VOH 18 VS terminal, VS = -4 mA V Output current IO 18 VS terminal, VS = 0 V -30 -11 mA ILEAK 18 VS terminal, VS = 0 V, Each cell voltage = 2V -0.5 0 A ICC1 17 VCC = 16.8 V, OUTON = 0 V normal mode 120 170 A ICC2 17 VCC = 11.6 V, OUTON = 0 V normal mode 100 145 A ICC3 17 VCC = 16.8 V, OUTON = 0 V monitor mode 600 860 A 17 VCC = 6 V, OCV = 0 V Over-discharge shutoff mode 0 A Output leak current General Power supply current ICC4 10 Condition (Ta = +25 C, VCC = OCV = 16.8 V) Value Unit Min Typ Max SEL = 0 V to VCC VCC - 1.0 VCC - 0.4 MB3838A TYPICAL CHARACTERISTICS Power Supply Current vs. Power Supply Voltage (3-cell mode) 200 180 160 140 120 100 80 60 40 20 0 600 2 4 6 8 10 12 14 16 18 20 400 0 2 4 6 8 10 12 14 16 Power supply voltage VCC (V) Power Supply Current vs. Power Supply Voltage (monitor mode) Reference Voltage vs. Power Supply Voltage 300 200 100 0 0 3-cell mode state, SEL = 0 V, Ta = +25 C, BAT4 = BAT3 = VCC, B4 cell voltage = 0 V, B3 cell voltage = B2 cell voltage = B1 cell voltage Power supply voltage VCC (V) 4-cell mode state, SEL = VCC, Ta = +25 C, BAT4 = VCC, B4 cell voltage = B3 cell voltage = B2 cell voltage = B1 cell voltage, D1 = D2 = D3 = 5 V 500 200 180 160 140 120 100 80 60 40 20 0 Reference voltage VREF (V) 0 Power supply current ICC (A) 4-cell mode state, SEL = VCC, Ta = +25 C, BAT4 = VCC, B4 cell voltage = B3 cell voltage = B2 cell voltage = B1 cell voltage 2 4 6 8 10 12 14 16 18 20 18 20 6 5 Ta = +25 C VREF = -0.1 mA 4 3 2 1 0 0 5 10 15 20 25 30 Power supply voltage VCC (V) Power supply voltage VCC (V) Over-charge Detection Voltage vs. Operating Ambient Temperature Over-charge detection voltage VTH (V) Power supply current ICC (A) Power supply current ICC (A) Power Supply Current vs. Power Supply Voltage (4-cell mode) 4.400 4.380 4.360 4.340 4.320 4.300 4.280 4.260 4.240 4.220 4.200 -40 B4 cell representative, BAT4 = VCC, BAT3 = 12.6 V, BAT2 = 8.4 V, BAT1 = 4.2 V -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) (Continued) 11 MB3838A Over-discharge Detection Block PF Output Delay Time Over-charge Detection Block Delay Time Ta = +25C 10 1 0.1 100 1000 10000 10 Warning output delay time tD (s) Delay time tD (ms) 100 1 0.1 0.01 0.001 0.0001 100000 Capacitor for setting delay time COVT (pF) Delay time tD1, tD2 (ms) Power failure permission signal wait time tD (s) 1 0.1 0.01 0.1 0.1 100 Ta = +25 C 0.001 0.01 1 10 Over-current Detection Delay Time 10 0.01 0.0001 0.001 Capacitor for setting warning output time CPDT (F) Over-discharge Detection Block Power Down Delay Time 100 Ta = +25C 1 10 tD1 VTH1 = 110 mV Ta = +25 C 10 1 tD2 VTH2 = 300 mV 0.1 0.01 100 Capacitor for setting power failure permission signal wait time CPDT (F) 1000 10000 Capacitor for setting delay time COCT (pF) Reference voltage VREF (V) Reference Voltage vs. Load Current 6 Ta = +25 C VCC = 16.8 V 5 4 3 2 1 0 0 -5 -10 -15 -20 -25 -30 -35 -40 Load current IREF (mA) (Continued) 12 MB3838A (Continued) VDD Regulator Output Voltage vs. Power Supply Voltage Ta = +25 C VCC = 16.8 V 5 4 3 2 1 0 0 -5 -10 -15 -20 -25 -30 -35 -40 VDD regulator output voltage VDD (V) 6 6 5 Ta = +25 C VDD = -1 mA 4 3 2 1 0 0 5 10 15 20 25 30 Power supply voltage VCC (V) Load current IDD (mA) Power Dissipation vs. Operating Ambient Temperature 600 Power dissipation PD (mW) VDD regulator output voltage VDD (V) VDD Regulator Output Voltage vs. Load Current 540 500 400 300 200 100 0 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) 13 MB3838A FUNCTIONAL DESCRIPTION (1) Over-charge Detection Block This block monitors the each cell voltage during battery charging. As shown in figure1, When the any cell voltage rises above the over-charge detection voltage (4.325 V Typ) , an open collector of COUT terminal (pin 2) turns off after delay time (23 ms Typ) by the condenser (COVT) connected with COVT terminal (pin 4) and GND, and the COUT terminal (pin 2) becomes "H" level. Then the external charge control P-ch MOS FET is turned off and the battery charge stops. When all the cells voltage in over-charge detection status falls below the over-charge release voltage (4.125 V Typ) , the COUT terminal (pin 2) is set to "L" level after delay time (2 s : at COVT = 0.068 F) , and the external charge control P-ch MOS FET is turned on. Also, as shown in Figure 2, IC does not enter the state of the overcharge detection when the cell voltages lower more than the over-charge detection voltages in delay time (23 ms Typ) even if the cell voltage becomes more than the over-charge detection voltage. (2) Cell Voltage Input Block As shown in Figure 1 and 2, when the external charge control P-ch MOS FET in over-charge detection state is turned off, at the same time, the cell voltage input block SW that rose above the over-charge detection level is turned on. The cell voltage input current is lowered to the cell and the cell with high voltage lowers. When the cell voltage becomes below the over-charge release voltage (4.125 V Typ) , cell voltage input block SW is turned off. (3) Over-discharge Detection Block and Power Fail Block As shown in Figure 5, when the voltage of any cell falls below the over-discharge detection voltage (2.75 V Typ) , the output P-ch MOS FET of VS terminal (pin 18) is turned off after VS output delay time (2 s Typ) by the condenser (CPDT) connected with the CPDT terminal (pin 6) and GND. Then, after power down delay time (20 s Typ) by condenser (CPDT) connected with the CPDT terminal (pin 6) and GND, the DOUT terminal (pin 10) becomes "H" level. The discharge is stopped by turning off the external discharge control P-ch MOS FET. The OCV terminal (pin 1) is set to "L" level by stopping discharge, and at that time this IC's bias source is turned off perfectly and would be a power down mode. To return from that mode carry out charge operation or set the OCV terminal (pin 1) to "H" level. (4) Over-current Detection Block As shown in figure 6, when the VIS terminal (pin 11) voltage for the current detection rises above 110 mV (Typ) , it is judged the over-current. And after delay time (7 ms Typ) by condenser (COCT) connected with the COCT terminal (pin 8) and GND, the DOUT terminal (pin 10) becomes "H" level, and discharge is stopped the turning off the external discharge control P-ch MOS FET. Moreover, when the discharge current is large, as shown in figure 7, if the VIS terminal (pin 11) voltage rises above 300 mV (Typ) . And after delay time (500 s Typ) by condenser (COCT) connected with the COCT terminal (pin 8) and GND, the DOUT terminal (pin 10) becomes "H" level, and discharge is stopped by turning off the external discharge control P-ch MOS FET. Further, when the over-current is detected, output P-ch MOS FET of the VS terminal (pin 18) is turned off. The OCV terminal (pin 1) becomes "L" level by stopping discharge, and the bias source of this IC enters the down state of turning off power completely. To return from that mode carry out charge operation or set the OCV terminal (pin 1) to "H" level. (5) Cell Voltage Monitor Block As shown in decoder block function table, the battery cell which monitors it is switched, each cell voltage is converted into the voltage value of the GND standard, and generates to the AOUT1 terminal (pin 20) . 14 MB3838A (6) Current Monitor Block External resistor RS voltage drop by the current which flows to the battery cell is detected with the VIS terminal (pin 11) . The voltage gain is switched as shown in the decoder block function table, and generates to the AOUT2 terminal (pin 24) . Because the offset by which the VIS terminal voltage outputs 2 V to the AOUT2 terminal (pin 24) at 0 V is set, the current value of charge and discharge both direction can be monitored. (7) Reference Voltage Block The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V Typ) from the voltage supplied from the power supply terminal (pin 17) , and it is used to set the voltage of IC internal circuit. Moreover, the reference voltage is possible to use as a reference voltage of the A/D converter such as microprocessor, because it can supply a load current of up to 600 A to an external device through the VREF terminal. (8) VDD Regulator Block The VDD regulator block is a series regulator that generates a voltage (5.0 V Typ) steady from the reference voltage block output voltage, and it is used to the power supply of IC's internal logic circuit etc. Moreover, the voltage is possible to use as a power-supply voltage such as microprocessor, because it can supply a load current of up to 10 mA to an external device through VDD terminal (pin 15) . (9) Decoder Block The cell voltage and the current monitor can be switched by inputting the signal at the VDD level or the GND level to D1, D2, D3 terminals (pin 23, 22, 21 ) . Decoder Block Function Table D1 D2 D3 Cell voltage monitor (AOUT1 output) Current monitor (AOUT2 output) L L L OFF OFF L L H B1 cell 125 times mode L H L B2 cell 125 times mode L H H B3 cell 125 times mode H L L B4 cell 125 times mode H L H B1 cell 48 times mode H H L B2 cell 125 times input short mode H H H B3 cell 48 times input short mode (10) Cell Switch Circuit Block 4 cells and 3 cells modes can be switched by inputting the signal at the VCC level or the GND level to the SEL terminal (pin 19) . Cell Switch Circuit Block Function Table SEL Mode Operation Function L 3 cells mode The over-discharge detection of the B4 cell and the short cell detection function is turned off, and the other functions operate. H 4 cells mode All functions operate. 15 MB3838A (11) Remote on Circuit Block The VS terminal (pin 18) output P-ch MOS FET is turned on in a usual state that the over-discharge and the over-current are not detected. The VS terminal output P-ch MOS FET is turned off in the state of the power down. The COUT terminal (pin 2) and the DOUT terminal (pin 10) are made "L" level by setting the OUTON terminal (pin 16) to "L" level, and the external charge and discharge control P-ch MOS FET is turned on. When the OUTON terminal (pin 16) is made "H" level, the open collector of the COUT terminal (pin 2) is turned off, the DOUT terminal (Pin 10) is set "H" level, and the external charge and discharge control P-ch MOS FET is turned off. At this time, because the pull-up resistor is connected with the OCV terminal (pin 1) side, the COUT terminal voltage becomes a voltage on the OCV terminal (pin 1) side. Further, the OUTON terminal (pin 16) becomes "H" level and the over-charge, the over-discharge detection function, and the voltage-current monitor function operate in the state to turn off the charge and discharge because IC is operating. 16 MB3838A SETTING METHOD Over-charge Detection Block Delay Time Setting Method When the over-charge is detected, condenser (COVT) connected with the COVT terminal (pin 4) begins to be charged, the COVT terminal voltage rises. It is possible to set at the delay time to turn off the open collector output of the COUT terminal (pin 2) by the threshold voltage of the COVT terminal (pin 4) . Over-charge detection block delay time : tD [s] =: 0.338 x COVT [F] VS Output Delay Time Setting Method When the over-discharge is detected, condenser (CPDT) connected with the CPDT terminal (pin 6) begins to be charged, the CPDT terminal voltage rises. The delay time to turn off P-ch MOS FET of the VS terminal (pin 18) voltage by the threshold voltage of the CPDT terminal (pin 6) can be set. VS output delay time : tD1 [s] =: 2.0 x CPDT [F] Power down Delay Time Setting Method When the over-discharge is detected, re-charge to condenser (CPDT) which connected with the CPDT terminal (pin 6) begins after turning off P-ch MOS FET of the VS terminal (pin 18) . The CPDT terminal voltage rises, and it is possible to set at the delay time becoming to "H" level the DOUT terminal (pin 10) voltage by the threshold voltage of the CPDT terminal (pin 6) . Power down delay time : tD2 [s] =: 20.0 x CPDT [F] The DOUT terminal (pin 10) becomes "H" level and after the discharge is prohibited, the circuit current becomes 0 to turn off all internal circuits of IC by the OCV terminal (pin 1) becomes "L" level. The time constant is considered with the condenser in note PC connected with the OCV terminal (pin 1) . Repetition of the return and power down are prevented by the change of the cell voltage by the discharge time constant of the CPDT terminal (pin 6) . It is necessary to limit to the condenser connected with the OCV terminal (pin 1) on note PC side as much as the next formula by the CPDT value. The OCV terminal external condenser : COCV [F] < 2200 x CPDT [F] Over-current Detection Block Delay Time Setting Method In this case of the over-current is detected (VTH2 > VIS > VTH1) , the charge begins condenser (COCT) which connected with the COCT terminal (pin 8) . The COCT terminal voltage rises, and it is possible to set at the delay time becoming to "H" level the DOUT terminal (pin 10) voltage by the threshold voltage of the COCT terminal (pin 8) . Over-current Detection Block Delay Time : tD1 [s] =: 3.89 x COCT [F] When the over-current is detected (VIS > VTH2) , the charge begins condenser (COCT) which connected with the COCT terminal (pin 8) . The COCT terminal voltage rises, it is possible to set at the delay time becoming to "H" level the DOUT terminal (pin 10) voltage by the threshold voltage of the COCT terminal (pin 8) . Over-current Detection Block Delay Time : tD2 [s] =: 0.28 x COCT [F] 17 MB3838A Voltage Gain and Output Offset Voltage Formula <Voltage monitor block> AOUT11 - AOUT12 * Voltage gain : AV = (V/V) , Output offset voltage : VOF = AOUT11 - AV x 4.4 (V) 2.4 (AOUT11 : At cell voltage 4.4 V, AOUT12 : AOUT1 terminal voltage at cell voltage 2 V) <Current monitor block 48 times mode> AOUT21 - AOUT22 * Voltage gain : AV1 = (V/V) , Output offset voltage : VOF1 = 2 - (AOUT21 - 0.042 x AV1) (V) 0.063 (AOUT21 : VIS = 42 mV, AOUT22 : AOUT2 terminal voltage at VIS = -21 mV) <Current monitor block 125 times mode> AOUT21 - AOUT22 * Voltage gain : AV2 = (V/V) , Output offset voltage : VOF2 = 2 - (AOUT21 - 0.016 x AV2) (V) 0.024 (AOUT21 : VIS = 16 mV, AOUT22 : AOUT2 terminal voltage at VIS = -8 mV) Output change at Input short mode * Output change : VOSD = VOS - VO (V) (VO : AOUT2 terminal voltage at 0 V, VOS : AOUT2 terminal voltage at input short mode) 18 MB3838A OPERATE TIMING CHART 1. Over-charge Detection Block and Cell voltage input Block * Other cells are states that VTH is not exceeded, and the voltage decreases because of the cell voltage input current and self-discharge. VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell1 Cell voltage input current Cell2 Cell1 Cell2 (45 A) (0 A) (45 A) (0 A) (VDD) COVT terminal (2 V) (0.7 V) COUT terminal tD (23 ms) tD (2 s) Figure 1 As shown in Figure 1, when either of the cell voltage rises above the over-charge detection voltage (4.325 V Typ) during charging. After delay time (23 ms Typ) by condenser (COVT) connected with the COVT terminal (pin 4) and GND, the open-collector of the COUT terminal (pin 2) turns off, becomes "H" level, and the external charge control P-ch MOS FET is turned off. At this time, the cell voltage input block SW turns on, and throws the cell voltage input current on the cell. When all cells voltage which entered the state of the over-charge detection falls below the over-charge release voltage (4.125 V Typ) , the cell voltage input block SW is turned off, and the COVT terminal (pin 4) voltage begins to decrease. After delay time (2 s : at COVT = 0.068 F) , the COUT terminal (pin 2) becomes "L" level, and the external charge control P-ch MOS FET is turned on. When either of the cell voltage entered the state of the over-charge detection becomes below the over-charge release voltage (4.125 V Typ) , the cell voltage input block SW of the cell turns off. 19 MB3838A * State that voltage decreased because of the cell voltage input current and self-discharge after charge. VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell voltage input current (45 A) (0 A) (VDD) COVT terminal (2 V) (0.7 V) COUT terminal tD (23 ms) tD (2 s) Ffigure 2 As shown in Figure 2, if the cell voltage rises above the over-charge detection voltage (4.325 V Typ) during charging, and it has lowered more than the over-charge detection voltage (4.325 V Typ) while it is delay time (23 ms Typ) by condenser (COVT) is connected with the COVT terminal (pin 4) and GND, it does not enter the state of the over-charge detection. When the cell voltage rises above the over-charge detection voltage (4.325 V Typ) , at the same time, if the condenser (COVT) connected with the COVT terminal (pin 4) and GND has passed delay time (23 ms Typ) , the open-collector of the COUT terminal (pin 2) turns off, it becomes "H" level, and the external charge control Pch MOS FET is turned off. At this time, the cell voltage input block SW turns on and flows the cell voltage input current on the cell. When all the cell voltages which entered the state of the over-charge detection falls below the over-charge release voltage (4.125 V Typ) , the cell voltage input block SW is turned off, and the COVT terminal (pin 4) voltage begins to decrease. After delay time (2 s : at COVT = 0.068 F) , the COUT terminal (pin 2) becomes "L" level, and the external charge control P-ch MOS FET is turned on. Further, when either of cell voltage entered the state of the over-charge detection falls below the over-charge release voltage (4.125 V Typ) , the cell voltage input block SW of the cell turns off. 20 MB3838A * After detecting the over-charge, it is a state which changes into "L" to "H" to "L" as for the OUTON terminal voltage. VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell voltage input current (45 A) (0 A) (VDD) COVT terminal (2 V) (0.7 V) COUT terminal OUTON terminal DOUT terminal OCV terminal (0 V) VS terminal (0 V) tD (23 ms) Figure 3 As shown in Figure 3, after detecting the over-charge while charging the cell, when the OUTON terminal (pin 16) becomes "L" level to "H" level, the DOUT terminal (pin 10) becomes "H" level, and the OCV terminal (pin 1) becomes "L" level by turning off the external discharge control P-ch MOS FET. All the cell voltages which entered the state of the over-charge detection have fallen below the over-charge release voltage (4.125 V Typ) , after delay time (2 s : at COVT = 0.068 F) , when the OUTON terminal (pin 16) becomes "H" level to "L" level, the COUT terminal (pin 2) becomes "L" level (The open collector output is a On state) , and the external charge control P-ch MOS FET is turned on. At this time, when the OCV terminal (pin 1) becomes "L" level to "H" level, the DOUT terminal (pin 10) becomes "L" level, and the external charge control P-ch MOS FET is turned on. 21 MB3838A 2. Over-charge Detection Block, Discharge Detection Block, and Cell voltage input Block * Discharge after over-charge detection, Over-charge detection by re-charge, Re-discharged state. discharge start discharge start charge start VTH (4.325 V) Cell voltage VH (0.2 V) (4.125 V) Cell voltage input current (45 A) (0 mA) (VDD) COVT terminal (2 V) COUT terminal OCV terminal (VCC) VTH (VCC - 0.3 V) tD (23 ms) tD (23 ms) Figure 4 As shown in Figure 4, if the cell voltage while charging the cell rises above the over-charge detection voltage (4.325 V Typ) and condenser (COVT) connected with the COVT terminal (pin 4) and GND has passed delay time (23 ms Typ) . The COUT terminal becomes "H" level by turning off the open-collector of the COUTterminal (pin 2) and the external charge control P-ch MOS FET is turned off, and it enters the state of the over-charge detection. In the state of the over-charge detection, when the charge is stopped, and the discharge is begun, the OCV terminal (pin 1) voltage decreases because of the body diode voltage for the external charge control P-ch MOS FET. When the potential difference voltage between VCC-OCV terminal becomes 300 mV or more, the COUT terminal (pin 2) becomes "L" level, the external charge control P-ch MOS FET is turned on, and the cell voltage input block SW turns off. Further, even if the cell voltage does not fall below the over-charge release voltage (4.125 V Typ) , the overcharge by the re-charge is detected. 22 MB3838A 3. Over-discharge Detection Block and Power failure Circuit Block * After over-discharge detection, State that "H" level signal is not inputted to the PDWN terminal. charge start Cell voltage VTH (2.75 V) (3 V) CPDT terminal PDWN terminal 0V DOUT terminal OCV terminal 0V OUTON terminal 0V VS terminal 0V tD1 (2 s) tD2 (20 s) Internal bias : off tD1 (2 s) Figure 5 As shown in Figure 5, when either of cell voltage falls below the over-discharge detection voltage (2.75 V Typ) , if the VS output delay time (2 s Typ) passed by condenser (CPDT) connected with the CPDT terminal (pin 6) and GND, P-ch MOS FET of the VS terminal (pin 18) is turned off. After that, when the power down delay time (20 s Typ) passed by condenser (CPDT) , the DOUT terminal (pin 10) becomes "H" level, and the discharge is stopped by turning off the external discharge control P-ch MOS FET. By the discharge having stopped, the OCV terminal (pin 1) becomes "L" level, and the source of the bias in IC is completely turned off. 23 MB3838A If the cell voltage will not return more than the over-discharge detection voltage (2.75 V Typ) in the power down delay time or less (20 s Typ) , it is judged the state of the over-discharge. When the OCV terminal (pin 1) becomes "H" level, the DOUT terminal (pin 10) becomes "L" level, and also the VS terminal (pin 18) becomes "H" level with the external discharge control P-ch MOS FET turned on. At this time, as long as cell voltage remains below the over-discharge detection voltage (2.75 V Typ) , after the VS output delay time (2 s Typ) by condenser (CPDT) , P-ch MOS FET of the VS terminal (pin 18) is turned off again. But the VS terminal (pin 18) becomes "H" level when the cell voltage will become more than the overdischarge detection voltage (2.75 V Typ) in the power down delay time or less (20 s Typ) , and it is not judged the state of the over-discharge. 24 MB3838A 4. Over-Current Detection Block * State that discharge current is comparatively small as over-current (VTH2 > VIS > VTH1) . charge start (0.3 V) VIS terminal (0.11 V) 0V (3 V) COUT terminal DOUT terminal VS terminal 0V tD (7 ms) Internal bias : off Figure 6 As shown in Figure 6, if the VIS terminal (pin 11) voltage by external resistor RS becomes 110 mV or more, it charges condenser (COCT) connected with the COCT terminal (pin 8) and GND. If the OCV terminal voltage returns to the level of the battery voltage while it is delay time (7 ms Typ) , it is not judged the over-current. It is judged the over-current, the DOUT terminal (pin 10) becomes "H" level when the VIS terminal voltage by external resistor RS becomes 110 mV or more, and delay time (7 ms Typ) by condenser (COCT) connected with the COCT terminal (pin 8) and GND passed, and the external discharge control P-ch MOS FET is turned off again. The OCV terminal (pin 1) becomes "L" level by the discharge having stopped, and turns off the source of the bias in IC completely. The DOUT terminal (pin 10) becomes "L" level because it makes the OCV terminal (pin 1) "H" level and the VS terminal (pin 18) also becomes "H" level. 25 MB3838A * State that discharge current is large as over-current (VIS > VTH2) . charge start (0.3 V) VIS terminal (0.11 V) 0V (3 V) COCT terminal DOUT terminal VS terminal 0V tD (500 s) Internal bias : off Figure 7 As shown in Figure 7, when the potential difference voltage between the VIS terminal (pin 11) and the GND terminal (pin 12) by external resistor RS becomes 110 mV or more, it charges condenser (COCT) connected with the COCT terminal (pin 8) and GND. If the OCV terminal voltage returns to the level of the battery voltage while it is delay time (7 ms Typ) , it is not judged the over-current. The potential difference between the VIS terminal (pin 11) and the GND terminal (pin 12) by external resistor RS becomes 300 mV or more, and when delay time (500 s Typ) by condenser (COCT) connected with the COCT terminal (pin 8) and GND passes, it is judged the over-current. And the DOUT terminal (pin 10) becomes "H" level, and the external discharge control P-ch MOS FET is turned off, the VS terminal (pin 18) becomes "L" level and the OCV terminal (pin 1) also becomes "L" level. At this time, turns off the source of the bias in IC completely. The DOUT terminal (pin 10) becomes "L" level because it makes the OCV terminal (pin 1) "H" level and the VS terminal (pin 18) also becomes "H" level. 26 MB3838A OTHER NOTES About the output voltage of the VREF terminal and the VDD terminal The VREF terminal (pin 14) outputs 5 V (Typ) , and the VDD terminal (pin 15) outputs 5 V (Typ) in the state usually. The VREF terminal (pin 14) and the VDD terminal (pin 15) become 0 V when the over-discharge of the battery is detected, and it enters the state of power down. At this time, the voltage applied to the VDD terminal (pin 15) is output as for the VREF terminal (pin 14) because it is short-circuited with an internal switch during the VREF terminal (pin 14) and VDD terminal (pin 15) when the voltage is applied from the outside to the VDD terminal (pin 15) About the operation at a low voltage If case of the cell voltage becomes extremely unbalanced and one cell or some cells become short (under 0.6 V Typ) , the COUT terminal (pin 2) is set "H" level (The open-collector output is a Off state) by the short cell detection function. However, the short cell detection function is invalidated when the VCC terminal (pin 17) voltage falls below 4.2 V (Typ) , and the COUT terminal (pin 2) is set "L" level in the state of 1.4 V or more (Typ) in the OCV terminal (pin 1) voltage. About the VS terminal Because it enters the state that the interdiction of the over-charge protection function cannot be done if it is charged through the body diode of internal P-ch MOS FET connected with the VS terminal (pin 18) , be careful please not to apply the voltage more than the VCC terminal voltage to the VS terminal. About the electrostatic charge Because this IC achieves making of the battery long-lived, the function to assume Icc = 0 A at power down is built-in this IC. Attention enough so as not to cause the malfunction by applying static electricity to need the charger for the return is necessary. We recommend making low impedance with the condenser etc. to prevent the static electricity noise from invading each input terminal of IC. Please arrange the condenser which uses such a purpose in very nearby of IC. Terminal processing in 3 cells mode This IC corresponds to the battery of 3 cells series connection and 4 cells series connection. Please be short-circuited of the B4 cell input because protection functions other than the over-charge detection function are invalidated at 3 cells mode. * Terminal processing in 3 cells mode BAT4 BAT3 Cell 3 SEL BAT2 Cell 2 BAT1 Cell 1 GND 27 MB3838A I/O EQUIVALENT CIRCUIT Reference Voltage Block VDD Regulator Block VCC 17 VDD VDD - + 14 VREF ESD protection element 625 k 15 VDD 1.8 M 600 k GND GND 12 Over-charge Detection Block Over-discharge Detection Block and Power Fail Block VDD PDWN 13 2 COUT VCC VDD 100 k 2 k COVT 4 1 k GND 10 DOUT 20 k CPDT 6 GND Over-current Detection Block Cell Voltage Input Block VDD BAT4 3 VTH1 VTH2 - 100 k x1 100 k x1 100 k x1 100 k x1 + BAT3 5 - + 2 k VIS 11 BAT2 7 GND COCT 8 BAT1 9 GND (Continued) 28 MB3838A (Continued) Remote on Circuit Block Cell Switch Circuit Block VCC VCC 500 OCV 1 600 OUTON 16 2 k SEL 19 GND GND VS 18 Cell Voltage Monitor Block VCC D1 23 D2 22 D3 21 GND 100 k 100 k 100 k 100 k 100 k 100 k AOUT1 20 Current Monitor Block 4 k 500 k/192 k VIS + - GND 4 k 24 AOUT2 500 k/192 k 29 30 BG B1 B2 B3 Li ION Battery B1 Cell B2 Cell B3 Cell B4 Cell B4 R1A 10 m C9 0.1 F C10 1 F R12 100 k M1 C8 0.1 F 1 k 1 k R2 1 k R3 R4 1 k R5 10 R6 R11 1 M C1 0.1 F C2 0.1 F C3 0.1 F C4 0.1 F R13 100 k C12 4700 pF C11 3300 pF M2 R14 1 M M4 R21 10 k M5 R22 10 k C5 0.1 F C13 0.1 F R8 1 M Temp_meas C6 4.7 F R15 10 k R20 330 k C7 4.7 F PDWN 13 VREF 14 Vcc_meas. R19 12 k M3 R18 62 k 12 GND 11 VIS VDD 15 OUTON 16 9 BAT1 10 DOUT VCC 17 VS 18 SEL 19 AOUT1 20 D3 21 D2 22 D1 23 AOUT2 24 8 COCT 7 BAT2 6 CPDT 5 BAT3 4 COVT 3 BAT4 2 COUT 1 OCV IC1 MB3838A R7 470 C14 0.1 F C16 0.1 F C17 0.1 F 10 TEST -ENTRY 9 VPP 8 WP Vcc1 18 SCL 19 SDA 20 PORT0 11 PORT1 12 PORT2 13 PORT3 14 Vcc2 15 SALAVE 17 -ADDRESS POWON 16 7 CAN00 6 AN03 5 Vss 4 AN02 3 AN01 2 AN00 1 Avref IC2 MB39F101 D1 R17 4.7 k GND CLOCK DATA Note PC side C15 0.1 F R16 4.7 k POW SC VS BAT+ MB3838A APPLICATION EXAMPLE MB3838A RARTS LIST COMPONENT ITEM SPECIFICATION VENDOR PARTS No. IC1 IC FUJITSU MB3838A IC2 IC FUJITSU MB39F101 M1, M2 FET VDS = -30 V TOSHIBA TPC8107 M3 FET VDS = -30 V NEC 2SJ463A M4, M5 FET VDS = 50 V NEC PA602T D1 Diode VF = 0.37 V (Max) , IF = 1 mA ROHM RB751V-40 C1, C2, C3, C4, C5 C8, C9, C13, C14 C15, C16, C17 C6, C7 C10 C11 C12 Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser 0.1 F 0.1 F 0.1 F 4.7 F 1 F 3300 pF 4700 pF 50 V (10%) 50 V (10%) 50 V (10%) 10 V (10%) 25 V (10%) 50 V (10%) 50 V (10%) TDK TDK TDK TDK TDK TDK TDK C1608JB1H104K C1608JB1H104K C1608JB1H104K C2012JB1A475K C3216JB1E105K C1608JB1H332K C1608JB1H472K R1A R2, R3, R4, R5 R6 R7 R8, R11, R14 R12, R13 R15, R21, R22 R20 R16, R17 R18 R19 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 10 m 1 k 10 470 1 M 100 k 10 k 330 k 4.7 k 62 k 12 k 1 W, 1% 1/16 W, 0.5% 1/16 W, 0.5% 1/16 W, 0.5% 1/10 W, 5% 1/16 W, 0.5% 1/16 W, 0.5% 1/16 W, 0.5% 1/16 W, 0.5% 1/16 W, 0.5% 1/16 W, 0.5% KOA ssm ssm ssm KYOCERA ssm ssm ssm ssm ssm ssm SL1TTE10LOF RR0816P102D RR0816P100D RR0816P471D CR10-105J RR0816P104D RR0816P103D RR0816P334D RR0816P472D RR0816P623D RR0816P123D Note : TOSHIBA NEC ROHM TDK KOA ssm KYOCERA : TOSHIBA CORPORATION : NEC corporation : ROHM CO., LTD : TDK Corporation : KOA Corporation : SUSUMU CO., LTD. : KYOCERA Corporation. 31 MB3838A USAGE PRECAUTIONS * Printed circuit board ground lines should be set up with consideration for common impedance. * Take appropriate static electricity measures. * Containers for semiconductor materials should have anti-static protection or be made of conductive material. * After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. * Work platforms, tools, and instruments should be properly grounded. * Working personnel should be grounded with resistance of 250 k to 1 M between body and ground. * Do not apply negative voltages. The use of negative voltages below -0.3 V may create parasitic transistors on LSI lines, which can cause malfunction. ORDERING INFORMATION Part number MB3838APFV 32 Package 24-pin plastic SSOP (FPT-24P-M03) Remarks MB3838A PACKAGE DIMENSION Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) MAX) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 24-pin plastic SSOP (FPT-24P-M03) 0.170.03 (.007.001) *17.750.10(.305.004) 24 13 *2 5.600.10 7.600.20 (.220.004) (.299.008) INDEX Details of "A" part +0.20 1.25 -0.10 +.008 .049 -.004 (Mounting height) 0.25(.010) 1 "A" 12 0~8 +0.08 0.65(.026) 0.24 -0.07 +.003 .009 -.003 0.13(.005) M 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) (Stand off) 0.10(.004) C 2003 FUJITSU LIMITED F24018S-c-4-5 Dimensions in mm (inches) Note : The values in parentheses are reference values. 33 MB3838A FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0409 2004 FUJITSU LIMITED Printed in Japan