DS04-27712-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP For Power Supply Applications (Secondary Battery)
Lithium Ion Battery Pack Control IC
MB3838A
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■DESCRIPTION
The MB3838A is a lithium-ion battery pac k control IC f or 3/4-cell series lithium-ion battery packs in notebook PCs
with 12.6 V/16.8 V charging system, and is designed to control charging and discharging by detecting over-charge,
over-discharge, and over-current conditions.
When the IC detects an over-discharge of the lithium-ion battery, adv ance w arning signal is sent bef ore shutting
off discharge. This function enables data in the notebook PCs memory to be saved to the hard disk.
After the ov er-discharge is detected and after inputting the PD WN signal (state of quasi-o ver-discharge) , current
consumption becomes 0 µA to cut all biases of IC.
Therefore, even if the battery pack is left for a long term, use by the re-charge is enabled.
Moreov er, because charge and discharge control FET can be turned off b y remote on function at the battery pack
unit, the output short-circuit by the misoperation can be prevented.
In addition, because it provides with the reference voltage power supply for the A/D converter and the VDD
regulator, and the cell v oltage monitor and the current monitor function are built-in, the remainder amount moni-
toring system with built-in battery pack can be easily composed.
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■PACKAGE
24-pin plastic SSOP
(FPT-24P-M03)
MB3838A
2
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■FEATURES
• Power supply voltage range : 6.5 V to 25 V
• High-precision over-charge detection voltage : 4.325 V ± 0.025 V
• Circuit current consumption after over-discharge detection : 0 µA (Typ)
• Built-in reference voltage power supply and VDD regulator
• Built-in cell voltage monitor and current monitor function
• Built-in quasi-over-discharge function
• Built-in advance warning function to prevent over-discharge output
• Built-in remote on/off function
• Built-in over-current detection function with two-stage delay time : VTH1 = 110 mV→7 ms (Typ)
: VTH2 = 300 mV→ 500 µs (Typ)
• Built-in 0 V cell charge return function
MB3838A
3
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■■
■PIN ASSIGNMENT
AOUT2
AOUT1
SEL
VS
VCC
OUTON
VDD
VREF
PDWN
D1
D2
D3
OCV
BAT3
CPDT
BAT2
COCT
BAT1
DOUT
VIS
GND
COUT
BAT4
COVT
24
20
19
18
17
16
15
14
13
23
22
21
1
5
6
7
8
9
10
11
12
2
3
4
(TOP VIEW)
(FPT-24P-M03)
MB3838A
4
■
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■PIN DESCRIPTIONS
Pin no. Symbol I/O Descriptions
1 OCV I Discharge/charge state detection terminal
2COUTO
P-ch MOS FET control terminal for charge control
(Open collector)
3 BAT4 I Battery connection terminal
4COVTCondenser connection terminal for setting over-charge detection delay
time
5 BAT3 I Battery connection terminal
6CPDTCondenser connection terminal for setting over-discharge detection delay
time
7 BAT2 I Battery connection terminal
8COCTCondenser connection terminal for setting over-current detection delay
time
9 BAT1 I Battery connection terminal
10 DOUT O P-ch MOS FET control output terminal for discharge control switch
(CMOS output)
11 VIS I Current detection terminal
12 GND Ground terminal
13 PDWM I Power down signal input terminal
14 VREF O Reference voltage output terminal
15 VDD O VDD regulator output terminal
16 OUTON I Remote-on signal input terminal
17 VCC Power supply terminal
18 VS O Battery voltage monitor and power down advance warning signal output
terminal
19 SEL I 3-cell/4-cell switch terminal
At “L” level input : 3-cell mode
At “H” level input : 4-cell mode
20 AOUT1 O Cell voltage monitor output terminal
21 D3 I Cell voltage and current monitor mode switch signal input terminal
22 D2 I Cell voltage and current monitor mode switch signal input terminal
23 D1 I Cell voltage and current monitor mode switch signal input terminal
24 AOUT2 O Current monitor output terminal
MB3838A
5
■
■■
■BLOCK DIAGRAM
VCC
[Cell switch circuit block] [Over-charge detection block]
[Cell voltage input block]
DOUT COUT OCV
VREF
VDD
VS
OUTON
PDWN
CPDTCOVTCOCTD1 D2 D3 AOUT1
SEL
BAT4
BAT3
BAT2
BAT1
GND
VIS
+
−
2.75 V
±2%
4.325 V
±0.6%
Latch2
Delay
time
(23 ms)
Reference
voltage
power supply
5 V ± 1 %
VDD regulator
5 V ± 2 %
PF output
delay
time
(2 s)
Power down
delay time
(20 s)
Delay
time
(7 ms)
(500 µs)
Multiplexer
3-bit
decoder
VCC − OCV > 0.3 V
VCC
Latch1
Latch3
VTH1
VTH2
50 m/10 mV
48/ 125
××
600 Ω
100 kΩ
100 kΩ
100 kΩ
100 kΩ
×1
×1
×1
×1
+
−
+
−
+
−
+
−
−
+
−
+
−
−
−
−
+
+
−
6482021222324
11
12
9
7
5
3
19
17 10 2 1
14
15
18
16
13
ON/OFF
[Remote on circuit block]
[Current monitor block]
[Over-current detection block]
[Cell voltage amp block]
Reset
Reset
reset
[Over-discharge detection block
and Power fail block]
AOUT2
Gain
change
bias
ON/OFF
[Cell voltage monitor block]
[Decoder block]
MB3838A
6
■
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■ABSOLUTE MAXIMUM RATINGS
* : When mounted on a 10cm square epoxy double-sided.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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■RECOMMENDED OPERATION CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Condition Rating Unit
Min Max
Power supply voltage VCC 28 V
Input voltage VIBAT4, BAT3, OCV, PDWN,
OUTON terminal 28 V
Collector output voltage VOCOUT terminal 28 V
Output current IODOUT, COUT terminal (DC) 2mA
Peak output current IOP DOUT, COUT terminal Duty = tON/t 2/Duty mA
Power dissipation PDTa ≤ +25 °C740* mW
Operating ambient temperature Ta −30 +85 °C
Storage temperature TSTG −55 +125 °C
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply voltage VCC 6.5 16.8 25 V
Input voltage VI
OCV, PDWN,
OUTON terminal 025 V
VIS terminal −0.3 +0.3 V
SEL terminal 0 VCC V
D1, D2, D3 terminal 0 VDD V
Output current IO
VREF terminal −600 0µA
VDD terminal −10 0mA
VS terminal −10 0mA
OCV terminal outside resistor ROCV 470 Ω
Condenser for setting delay
time
COVT 0.068 µF
CPDT 1.0 µF
COCT 1800 pF
MB3838A
7
■
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■ELECTRICAL CHARACTERISTICS (Ta = +25 °C, VCC = OCV = 16.8 V)
(Continued)
Parameter Sym-
bol Pin
No. Condition Value Unit
Min Typ Max
Over-charge
Detection Block
Detection voltage VTH 2, 3,
5, 7, 9
Ta = +25 °C,
Each cell voltage 4.300 4.325 4.350 V
Ta = 0 °C to +70 °C 4.280 4.325 4.370 V
Hysteresis width VH2, 3,
5, 7, 9 0.14 0.20 0.26 V
Input current IIN 2, 3,
5, 7, 9 Each cell voltage =
4.2 V 0.1 0.5 µA
Delay time tD2COVT = 0.068 µF 11.5 23 34.5 ms
Output voltage VOL 2COUT = 1 mA 0.75 1.0 V
Output leak
current ILEAK 2COUT = 18 V 00.5µA
Over-discharge
Detection Block
and Power Fail
Block
Detection voltage VTH 3, 5,
7, 9,
10 Each cell voltage 2.695 2.75 2.805 V
VS output delay
time tD1 18 CPDT = 1.0 µF 123s
Power-down
delay time tD2 10 CPDT = 1.0 µF 102030s
Input threshold
voltage VTH 10, 13 PDWN terminal,
Each cell voltage =
2 V 2.0 3.5 5.0 V
Input current IIN 13 PDWN terminal,
PDWN = 5 V 50 100 µA
Over-current
Detection Block
Detection voltage VTH1 11 VIS terminal
voltage 88 110 132 mV
VTH2 11 VIS terminal
voltage 240 300 360 mV
Delay time tD1 10 COCT = 1800 pF,
VTH2 > VIS > VTH1 4710ms
tD2 10 COCT = 1800pF,
VIS > VTH2 250 500 750 µs
Input current IIN 11 VIS = 0 V 0µA
Output voltage VOL 10 DOUT terminal,
DOUT = 1 mA 1.0 V
VOH 10 DOUT terminal,
DOUT = −0.4 mA VCC − 0.4 V
MB3838A
8
(Ta = +25 °C, VCC = OCV = 16.8 V)
* : Standard design value
(Continued)
Parameter Sym-
bol Pin
No. Condition Value Unit
Min Typ Max
Cell Voltage
Input Block
Input current in
over-charging IIN 3, 5,
7, 9 Each cell voltage =
4.5 V 22.5 45 67.5 µA
Short cell
detection voltage VTH 2, 3,
5, 7, 9
Cell voltage = 3.6 V
(Except for mea-
surement cell) ,
COUT = “L” → “H”
0.6* V
Reference
Voltage Block
Output voltage VREF 14 VREF = −0.1 mA,
Ta = +25 °C4.95 5.00 5.05 V
VREF 14 VREF = −0.1 mA,
Ta = 0 °C to +70 °C4.90 5.00 5.10 V
Input stable
range LINE 14 VCC = 6.5 V to 25 V,
VREF = −0.1 mA 510mV
VDD Regulator
Block
Output voltage VDD 15 VDD = −1 mA 4.90 5.00 5.10 V
Input stable
range LINE 15 VCC = 6.5 V to 25 V,
VDD = −1 mA 10 50 mV
Load stable
range LOAD 15 VDD = −1 mA to
−10 mA 20 80 mV
Cell Voltage
Monitor Block
Input current IIN 3, 5,
7, 9 Each cell voltage =
4 V 0.1 0.3 µA
Voltage gain AV20 Each cell voltage =
2.0 V to 4.4 V 0.98 1.0 1.02 V/V
Output offset
voltage VOF 20 −20 0 +20 mV
Output source
current ISOURCE 20 AOUT1 = 3.6 V −10 −5mA
Output sink
current ISINK 20 AOUT1 = 3.6 V 40 80 µA
Output voltage VOH 20 VDD − 0.3 VDD V
VOL 20 00.2V
MB3838A
9
(Ta = +25 °C, VCC = OCV = 16.8 V)
(Continued)
Parameter Sym-
bol Pin
No. Condition Value Unit
Min Typ Max
Current Monitor
Block
Input current IIN 11 VIS = 0 V −10 µA
Voltage gain AV1 24 D1 = 5 V, D2 = 0 V,
D3 = 5 V 45.6 48 50.4 V/V
AV2 24 D1 = 0 V, D2 = 0 V,
D3 = 5 V 121 125 129 V/V
Output offset
voltage
VOF1 24 D1 = 5 V, D2 = 0 V,
D3 = 5 V −100 0 100 mV
VOF2 24 D1 = 0 V, D2 = 0 V,
D3 = 5 V −230 0 230 mV
Output voltage at
input short mode
VOS1 24 D1 = 5 V, D2 = 5 V,
D3 = 5 V 1.85 2.0 2.15 V
VOS2 24 D1 = 5 V, D2 = 5 V,
D3 = 0 V 1.65 2.0 2.35 V
Output change at
input short mode
VOS1D 24 D1 = 5 V, D2 = 0 V,
D3 = 5 V −50 0 50 mV
VOS2D 24 D1 = 0 V, D2 = 0 V,
D3 = 5 V −100 0 100 mV
Output source
current ISOURCE 24 AOUT2 = 3.6 V −10 −5mA
Output sink
current ISINK 24 AOUT2 = 3.6 V 40 80 µA
Output voltage
VO1 24 VIS = 0 V, D1 = 5 V,
D2 = 0 V, D3 = 5 V 1.85 2.0 2.15 V
VO2 24 VIS = 0 V, D1 = 0 V,
D2 = 0 V, D3 = 5 V 1.65 2.0 2.35 V
VOH 24 VDD − 0.3 VDD V
VOL 24 00.2V
Decoder Block
Input current IIN 21,
22,
23 D1 = D2 = D3 = 5 V 50 100 µA
Input threshold
voltage VTH 21,
22,
23 0.8 1.4 2.0 V
Output delay time
after switching tDO 20,
24 250 500 µs
MB3838A
10
(Continued)
(Ta = +25 °C, VCC = OCV = 16.8 V)
Parameter Sym-
bol Pin
No. Condition Value Unit
Min Typ Max
Cell Switch
Circuit Block
Input current IL19 SEL = 0 V to VCC 01µA
“L” level input
voltage VIL 19 00.3 × VCC V
“H” level input
voltage VIH 19 0.7 × VCC VCC V
Remote on
Circuit Block
Input threshold
voltage VTLH 1 OCV terminal 0.8 1.4 2.0 V
Input current IIN 1OCV terminal,
OCV = 18 V 10 20 µA
Input resistance
in power down RIN 1 OCV terminal 480 600 720 Ω
Input threshold
voltage VTH 16 OUTON terminal 1.2 1.8 2.4 V
Input current IIN 16 OUTON terminal,
OUTON = 18 V 0.1 0.5 µA
Output voltage VOH 18 VS terminal,
VS = −4 mA VCC − 1.0 VCC − 0.4 V
Output current IO18 VS terminal,
VS = 0 V −30 −11 mA
Output leak
current ILEAK 18
VS terminal,
VS = 0 V,
Each cell voltage =
2 V
−0.5 0 µA
General Power supply
current
ICC1 17 VCC = 16.8 V,
OUTON = 0 V
normal mode 120 170 µA
ICC2 17 VCC = 11.6 V,
OUTON = 0 V
normal mode 100 145 µA
ICC3 17 VCC = 16.8 V,
OUTON = 0 V
monitor mode 600 860 µA
ICC4 17
VCC = 6 V,
OCV = 0 V
Over-discharge
shutoff mode
0 µA
MB3838A
11
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■TYPICAL CHARACTERISTICS
(Continued)
200
180
160
140
120
100
80
60
40
20
00 2 4 6 8 10 12 14 16 18 20
200
180
160
140
120
100
80
60
40
20
00 2 4 6 8 10 12 14 16 18 20
600
500
400
300
200
100
00 2 4 6 8 10 12 14 16 18 20
6
5
4
3
2
1
00 5 10 15 20 25 30
Ta = +25 °C
VREF = −0.1 mA
4.400
4.380
4.360
4.340
4.320
4.300
4.280
4.260
4.240
4.220
4.200
−40 −20 0 +20 +40 +60 +80 +100
Power Supply Current vs.
Power Supply Voltage (4-cell mode)
Power supply current ICC (µA)
Power supply voltage VCC (V)
Power Supply Current vs.
Power Supply Voltage (3-cell mode)
Power supply current ICC (µA)
Power supply voltage VCC (V)
Power Supply Current vs.
Power Supply Voltage (monitor mode)
Power supply current ICC (µA)
Power supply voltage VCC (V)
Reference Voltage vs.
Power Supply Voltage
Reference voltage VREF (V)
Power supply voltage VCC (V)
Over-charge Detection Voltage vs.
Operating Ambient Temperature
Over-charge detection voltage
VTH (V)
Operating ambient temperature Ta ( °C)
4-cell mode state, SEL = VCC,
Ta = +25 °C, BAT4 = VCC,
B4 cell voltage = B3 cell voltage =
B2 cell voltage = B1 cell voltage
3-cell mode state, SEL = 0 V,
Ta = +25 °C,
BAT4 = BAT3 = VCC,
B4 cell voltage = 0 V,
B3 cell voltage = B2 cell voltage =
B1 cell voltage
4-cell mode state, SEL = VCC,
Ta = +25 °C, BAT4 = VCC,
B4 cell voltage = B3 cell
voltage = B2 cell voltage =
B1 cell voltage,
D1 = D2 = D3 = 5 V
B4 cell representative,
BAT4 = VCC,
BAT3 = 12.6 V,
BAT2 = 8.4 V,
BAT1 = 4.2 V
MB3838A
12
(Continued)
100
10
1
0.1100 1000 10000 100000
Ta = +25°C10
1
0.1
0.001
0.01
0.0001 0.001 0.01 0.1 1 10
Ta = +25°C
100
10
1
0.01
0.1
0.0001 0.001 0.01 0.1 1 10
Ta = +25 °C100
10
1
0.01
0.1
100 1000 10000
Ta = +25 °C
tD1
VTH1 = 110 mV
tD2
VTH2 = 300 mV
6
5
00−5−10 −15 −20 −25 −30 −35 −40
2
1
3
4
Ta = +25 °C
VCC = 16.8 V
Over-charge Detection Block Delay Time
Delay time tD (ms)
Capacitor for setting delay time COVT (pF)
Over-discharge Detection Block
PF Output Delay Time
Warning output delay time
tD (s)
Capacitor for setting warning output time
CPDT (µF)
Over-discharge Detection Block
Power Down Delay Time
Power failure permission
signal wait time tD (s)
Capacitor for setting power failure permission
signal wait time CPDT (µF)
Over-current Detection Delay Time
Delay time tD1, tD2 (ms)
Capacitor for setting delay time COCT (pF)
Reference Voltage vs. Load Current
Reference voltage VREF (V)
Load current IREF (mA)
MB3838A
13
(Continued)
6
5
00−5−10 −15 −20 −25 −30 −35 −40
2
1
3
4
Ta = +25 °C
VCC = 16.8 V
6
5
0
2
1
3
4
0 5 10 15 20 25 30
Ta = +25 °C
VDD = −1 mA
600
500
540
0
200
100
300
400
−40 −20 +20 +40 +60 +80 +1000
Power Dissipation vs.
Operating Ambient Temperature
Power dissipation PD (mW)
Operating ambient temperature Ta ( °C)
VDD Regulator Output Voltage vs.
Power Supply Voltage
VDD regulator output voltage
VDD (V)
Power supply voltage VCC (V)
VDD Regulator Output Voltage vs.
Load Current
VDD regulator output voltage
VDD (V)
Load current IDD (mA)
MB3838A
14
■
■■
■FUNCTIONAL DESCRIPTION
(1) Over-charge Detection Block
This bloc k monitors the each cell voltage during battery charging. As shown in figure1, When the any cell voltage
rises above the over-charge detection voltage (4.325 V Typ) , an open collector of COUT terminal (pin 2) turns
off after delay time (23 ms Typ) by the condenser (COVT) connected with COVT terminal (pin 4) and GND, and
the COUT terminal (pin 2) becomes “H” le vel. Then the e xternal charge control P-ch MOS FET is turned off and
the battery charge stops.
When all the cells voltage in over-charge detection status falls below the over-charge release voltage (4.125 V
Typ) , the COUT ter minal (pin 2) is set to “L” level after delay time (2 s : at COVT = 0.068 µF) , and the external
charge control P-ch MOS FET is turned on. Also, as shown in Figure 2, IC does not enter the state of the o ver-
charge detection when the cell voltages lower more than the over-charge detection voltages in delay time (23
ms Typ) even if the cell voltage becomes more than the over-charge detection voltage.
(2) Cell Voltage Input Block
As shown in Figure 1 and 2, when the external charge control P-ch MOS FET in over-charge detection state is
tur ned off, at the same time, the cell voltage input block SW that rose above the over-charge detection level is
turned on.
The cell voltage input current is lowered to the cell and the cell with high voltage lowers. When the cell voltage
becomes below the over-charge release voltage (4.125 V Typ) , cell voltage input block SW is turned off.
(3) Over-discharge Detection Block and Power Fail Block
As shown in Figure 5, when the v oltage of any cell falls below the over-discharge detection voltage (2.75 V Typ) ,
the output P-ch MOS FET of VS terminal (pin 18) is turned off after VS output delay time (2 s Typ) by the
condenser (CPDT) connected with the CPDT terminal (pin 6) and GND. Then, after pow er do wn delay time (20 s
Typ) by condenser (CPDT) connected with the CPDT terminal (pin 6) and GND, the DOUT terminal (pin 10)
becomes “H” level. The discharge is stopped by turning off the external discharge control P-ch MOS FET.
The OCV terminal (pin 1) is set to “L” le vel b y stopping discharge, and at that time this IC’ s bias source is turned
off perfectly and would be a power down mode. To return from that mode carry out charge operation or set the
OCV terminal (pin 1) to “H” level.
(4) Over-current Detection Block
As shown in figure 6, when the VIS terminal (pin 11) voltage f or the current detection rises above 110 mV (Typ) ,
it is judged the over-current. And after delay time (7 ms Typ) by condenser (COCT) connected with the COCT
terminal (pin 8) and GND, the DOUT terminal (pin 10) becomes “H” le vel, and discharge is stopped the turning
off the external discharge control P-ch MOS FET.
Moreover, when the discharge current is large, as shown in figure 7, if the VIS terminal (pin 11) voltage rises
abov e 300 mV (Typ) . And after dela y time (500 µs Typ) b y condenser (COCT) connected with the COCT terminal
(pin 8) and GND, the DOUT ter minal (pin 10) becomes “H” level, and discharge is stopped by tur ning off the
external discharge control P-ch MOS FET.
Further, when the over-current is detected, output P-ch MOS FET of the VS terminal (pin 18) is turned off . The
OCV ter minal (pin 1) becomes “L” level by stopping discharge, and the bias source of this IC enters the down
state of turning off power completely . To return from that mode carry out charge operation or set the OCV terminal
(pin 1) to “H” level.
(5) Cell Voltage Monitor Block
As shown in decoder block function table, the battery cell which monitors it is switched, each cell voltage is
converted into the voltage value of the GND standard, and generates to the AOUT1 terminal (pin 20) .
MB3838A
15
(6) Current Monitor Block
External resistor RS v oltage drop by the current which flows to the battery cell is detected with the VIS terminal
(pin 11) . The voltage gain is switched as shown in the decoder block function tab le, and generates to the AOUT2
terminal (pin 24) . Because the offset by which the VIS terminal voltage outputs 2 V to the AOUT2 terminal (pin
24) at 0 V is set, the current value of charge and discharge both direction can be monitored.
(7) Reference Voltage Block
The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V Typ) from the
v o ltage supplied from the power supply terminal (pin 17) , and it is used to set the voltage of IC internal circuit.
Moreover, the reference voltage is possible to use as a reference voltage of the A/D conver ter such as micro-
processor , because it can supply a load current of up to 600 µA to an external device through the VREF terminal.
(8) VDD Regulator Block
The VDD regulator block is a series regulator that generates a voltage (5.0 V Typ) steady from the reference
voltage block output voltage, and it is used to the power supply of IC’s inter nal logic circuit etc. Moreover, the
voltage is possible to use as a power-supply voltage such as microprocessor, because it can supply a load
current of up to 10 mA to an external device through VDD terminal (pin 15) .
(9) Decoder Block
The cell v oltage and the current monitor can be switched b y inputting the signal at the VDD le vel or the GND le v el
to D1, D2, D3 terminals (pin 23, 22, 21 ) .
(10) Cell Switch Circuit Block
4 cells and 3 cells modes can be switched by inputting the signal at the VCC level or the GND level to the SEL
terminal (pin 19) .
Decoder Block Function Table
D1 D2 D3 Cell voltage monitor
(AOUT1 output) Current monitor
(AOUT2 output)
LLL OFF OFF
L L H B1 cell 125 times mode
L H L B2 cell 125 times mode
L H H B3 cell 125 times mode
H L L B4 cell 125 times mode
H L H B1 cell 48 times mode
H H L B2 cell 125 times input short mode
H H H B3 cell 48 times input short mode
Cell Switch Circuit Block Function Table
SEL Mode Operation Function
L 3 cells mode The over-discharge detection of the B4 cell and the short cell detection
function is turned off, and the other functions operate.
H 4 cells mode All functions operate.
MB3838A
16
(11) Remote on Circuit Block
The VS ter minal (pin 18) output P-ch MOS FET is turned on in a usual state that the over-discharge and the
over-current are not detected. The VS terminal output P-ch MOS FET is turned off in the state of the power down.
The COUT ter minal (pin 2) and the DOUT terminal (pin 10) are made “L” level by setting the OUTON terminal
(pin 16) to “L” level, and the external charge and discharge control P-ch MOS FET is turned on.
When the OUTON terminal (pin 16) is made “H” le v el, the open collector of the COUT terminal (pin 2) is turned
off, the DOUT ter minal (Pin 10) is set “H” level, and the exter nal charge and discharge control P-ch MOS FET
is turned off.
At this time, because the pull-up resistor is connected with the OCV ter minal (pin 1) side, the COUT terminal
voltage becomes a voltage on the OCV terminal (pin 1) side.
Further, the OUTON terminal (pin 16) becomes “H” level and the over-charge, the over-discharge detection
function, and the voltage-current monitor function operate in the state to turn off the charge and discharge
because IC is operating.
MB3838A
17
■
■■
■SETTING METHOD
Over-charge Detection Block Delay Time Setting Method
When the over-charge is detected, condenser (COVT) connected with the COVT terminal (pin 4) begins to be
charged, the COVT ter minal voltage r ises. It is possible to set at the delay time to tur n off the open collector
output of the COUT terminal (pin 2) by the threshold voltage of the COVT terminal (pin 4) .
Over-charge detection block delay time : tD [s] := 0.338 × COVT [µF]
VS Output Delay Time Setting Method
When the over-discharge is detected, condenser (CPDT) connected with the CPDT terminal (pin 6) begins to be
charged, the CPDT terminal v oltage rises. The delay time to turn off P-ch MOS FET of the VS terminal (pin 18)
voltage by the threshold voltage of the CPDT terminal (pin 6) can be set.
VS output delay time : tD1 [s] := 2.0 × CPDT [µF]
Power down Delay Time Setting Method
When the over-discharge is detected, re-charge to condenser (CPDT) which connected with the CPDT terminal
(pin 6) begins after tur ning off P-ch MOS FET of the VS terminal (pin 18) . The CPDT ter minal voltage rises,
and it is possible to set at the delay time becoming to “H” level the DOUT terminal (pin 10) voltage by the threshold
voltage of the CPDT terminal (pin 6) .
Power down delay time : tD2 [s] := 20.0 × CPDT [µF]
The DOUT terminal (pin 10) becomes “H” le vel and after the discharge is prohibited, the circuit current becomes
0 to turn off all internal circuits of IC by the OCV terminal (pin 1) becomes “L” level.
The time constant is considered with the condenser in note PC connected with the OCV terminal (pin 1) .
Repetition of the return and power down are prevented by the change of the cell voltage by the discharge time
constant of the CPDT terminal (pin 6) .
It is necessar y to limit to the condenser connected with the OCV terminal (pin 1) on note PC side as much as
the next formula by the CPDT value.
The OCV terminal external condenser : COCV [µF] < 2200 × CPDT [µF]
Over-current Detection Block Delay Time Setting Method
In this case of the over-current is detected (VTH2 > VIS > VTH1) , the charge begins condenser (COCT) which
connected with the COCT terminal (pin 8) . The COCT terminal voltage rises, and it is possible to set at the
delay time becoming to “H” level the DOUT terminal (pin 10) voltage by the threshold voltage of the COCT
terminal (pin 8) .
Over-current Detection Block Delay Time : tD1 [s] := 3.89 × COCT [µF]
When the over-current is detected (VIS > VTH2) , the charge begins condenser (COCT) which connected with the
COCT terminal (pin 8) . The COCT terminal voltage rises, it is possib le to set at the delay time becoming to “H”
level the DOUT terminal (pin 10) voltage by the threshold voltage of the COCT terminal (pin 8) .
Over-current Detection Block Delay Time : tD2 [s] := 0.28 × COCT [µF]
MB3838A
18
Voltage Gain and Output Offset Voltage Formula
<Voltage monitor block>
• Voltage gain : AV = (V/V) , Output offset voltage : VOF = AOUT11 − AV × 4.4 (V)
(AOUT11 : At cell voltage 4.4 V, AOUT12 : AOUT1 terminal voltage at cell voltage 2 V)
<Current monitor block 48 times mode>
• Voltage gain : AV1 = (V/V) , Output offset voltage : VOF1 = 2 − (AOUT21 − 0.042 × AV1) (V)
(AOUT21 : VIS = 42 mV, AOUT22 : AOUT2 terminal voltage at VIS = −21 mV)
<Current monitor block 125 times mode>
• Voltage gain : AV2 = (V/V) , Output offset voltage : VOF2 = 2 − (AOUT21 − 0.016 × AV2) (V)
(AOUT21 : VIS = 16 mV, AOUT22 : AOUT2 terminal voltage at VIS = −8 mV)
Output change at Input short mode
• Output change : VOSD = VOS − VO (V)
(VO : AOUT2 terminal voltage at 0 V, VOS : AOUT2 terminal voltage at input short mode)
AOUT11 − AOUT12
2.4
AOUT21 − AOUT22
0.063
AOUT21 − AOUT22
0.024
MB3838A
19
■
■■
■OPERATE TIMING CHART
1. Over-charge Detection Block and Cell voltage input Block
• Other cells are states that VTH is not exceeded, and the voltage decreases because of the cell voltage input
current and self-discharge.
Figure 1
As shown in Figure 1, when either of the cell voltage rises above the over-charge detection voltage (4.325 V
Typ) during charging. After delay time (23 ms Typ) by condenser (COVT) connected with the CO VT terminal (pin
4) and GND, the open-collector of the COUT terminal (pin 2) turns off, becomes “H” level, and the external
charge control P-ch MOS FET is turned off.
At this time, the cell voltage input block SW turns on, and throws the cell voltage input current on the cell.
When all cells v oltage which entered the state of the over-charge detection falls below the o ver-charge release
voltage (4.125 V Typ) , the cell voltage input block SW is turned off, and the CO VT terminal (pin 4) voltage begins
to decrease. After delay time (2 s : at COVT = 0.068 µF) , the COUT terminal (pin 2) becomes “L” level, and the
external charge control P-ch MOS FET is turned on.
When either of the cell voltage entered the state of the over-charge detection becomes below the over-charge
release voltage (4.125 V Typ) , the cell voltage input block SW of the cell turns off.
VTH
(4.325 V)
VH (0.2 V)
(4.125 V)
(VDD)
tD (23 ms) tD (2 s)
(2 V)
(0.7 V)
(45 µA)
(0 µA)
(45 µA)
(0 µA)
Cell voltage
Cell voltage input
current
Cell1
Cell2
COVT terminal
COUT terminal
Cell1
Cell2
MB3838A
20
• State that voltage decreased because of the cell voltage input current and self-discharge after charge.
Ffigure 2
As shown in Figure 2, if the cell voltage rises above the over-charge detection voltage (4.325 V Typ) during
charging, and it has lowe red more than the over-charge detection voltage (4.325 V Typ) while it is delay time
(23 ms Typ) by condenser (COVT) is connected with the COVT ter minal (pin 4) and GND, it does not enter the
state of the over-charge detection.
When the cell voltage rises above the over-charge detection voltage (4.325 V Typ) , at the same time, if the
condenser (COVT) connected with the COVT terminal (pin 4) and GND has passed delay time (23 ms Typ) , the
open-collector of the COUT ter minal (pin 2) turns off, it becomes “H” level, and the exter nal charge control P-
ch MOS FET is turned off.
At this time, the cell voltage input block SW turns on and flows the cell voltage input current on the cell.
When all the cell voltages which entered the state of the over-charge detection falls below the over-charge
release voltage (4.125 V Typ) , the cell voltage input block SW is turned off, and the CO VT terminal (pin 4) voltage
begins to decrease. After delay time (2 s : at COVT = 0.068 µF) , the COUT ter minal (pin 2) becomes “L” level,
and the external charge control P-ch MOS FET is turned on.
Fur ther, when either of cell voltage entered the state of the over-charge detection falls below the over-charge
release voltage (4.125 V Typ) , the cell voltage input block SW of the cell turns off.
VTH
(4.325 V)
VH (0.2 V)
(4.125 V)
(VDD)
tD (23 ms) tD (2 s)
(2 V)
(0.7 V)
(45 µA)
(0 µA)
Cell voltage
Cell voltage input
current
COVT terminal
COUT terminal
MB3838A
21
• After detecting the over-charge, it is a state which changes into “L” to “H” to “L” as for the OUTON terminal
voltage.
Figure 3
As shown in Figure 3, after detecting the over-charge while charging the cell, when the OUTON ter minal (pin
16) becomes “L” le vel to “H” le vel, the DOUT terminal (pin 10) becomes “H” level, and the OCV terminal (pin 1)
becomes “L” level by turning off the external discharge control P-ch MOS FET.
All the cell voltages which entered the state of the over-charge detection have fallen below the over-charge
release v oltage (4.125 V Typ) , after delay time (2 s : at COVT = 0.068 µF) , when the OUTON terminal (pin 16)
becomes “H” level to “L” level, the COUT terminal (pin 2) becomes “L” level (The open collector output is a On
state) , and the external charge control P-ch MOS FET is turned on. At this time, when the OCV terminal (pin
1) becomes “L” le v el to “H” le v el, the DOUT terminal (pin 10) becomes “L” le v el, and the e xternal charge control
P-ch MOS FET is turned on.
VTH
(4.325 V)
VH (0.2 V)
(4.125 V)
(45 µA)
(0 µA)
(VDD)
(2 V)
(0.7 V)
(0 V)
(0 V)
tD (23 ms)
Cell voltage
Cell voltage input
current
COVT terminal
COUT terminal
OUTON terminal
DOUT terminal
OCV terminal
VS terminal
MB3838A
22
2. Over-charge Detection Block, Discharge Detection Block, and Cell voltage input Block
• Discharge after over-charge detection, Over-charge detection by re-charge, Re-discharged state.
Figure 4
As shown in Figure 4, if the cell voltage while charging the cell r ises above the over-charge detection voltage
(4.325 V Typ) and condenser (COVT) connected with the CO VT terminal (pin 4) and GND has passed delay time
(23 ms Typ) . The COUT terminal becomes “H” le vel by turning off the open-collector of the COUTterminal (pin
2) and the external charge control P-ch MOS FET is turned off, and it enters the state of the over-charge detection.
In the state of the over-charge detection, when the charge is stopped, and the discharge is begun, the OCV
terminal (pin 1) v oltage decreases because of the body diode v oltage f or the e xternal charge control P-ch MOS
FET. When the potential difference voltage between VCC-OCV ter minal becomes 300 mV or more, the COUT
terminal (pin 2) becomes “L” le v el, the e xternal charge control P-ch MOS FET is turned on, and the cell voltage
input block SW turns off.
Fur ther, even if the cell voltage does not fall below the over-charge release voltage (4.125 V Typ) , the over-
charge by the re-charge is detected.
VTH
(4.325 V)
VH (0.2 V)
(4.125 V)
(45 µA)
(0 mA)
(VDD)
(2 V)
(VCC)
VTH
(VCC − 0.3 V)
tD (23 ms) tD (23 ms)
Cell voltage
Cell voltage
input current
COVT terminal
COUT terminal
OCV terminal
discharge
start charge
start
discharge
start
MB3838A
23
3. Over-discharge Detection Block and Power failure Circuit Block
• After over-discharge detection, State that “H” level signal is not inputted to the PDWN terminal.
Figure 5
As shown in Figure 5, when either of cell v oltage f alls belo w the ov er-discharge detection v oltage (2.75 V Typ) ,
if the VS output dela y time (2 s Typ) passed by condenser (CPDT) connected with the CPDT terminal (pin 6) and
GND, P-ch MOS FET of the VS terminal (pin 18) is turned off.
After that, when the pow er down dela y time (20 s Typ) passed by condenser (CPDT) , the DOUT terminal (pin 10)
becomes “H” level, and the discharge is stopped by tur ning off the external discharge control P-ch MOS FET.
By the discharge having stopped, the OCV terminal (pin 1) becomes “L” level, and the source of the bias in IC
is completely turned off.
VTH (2.75 V)
(3 V)
0 V
0 V
0 V
0 V
tD1 (2 s) tD2 (20 s) tD1 (2 s)
Cell voltage
CPDT terminal
PDWN terminal
DOUT terminal
OCV terminal
OUTON terminal
VS terminal
↓ charge start
Internal bias : off
MB3838A
24
If the cell v oltage will not return more than the ov er-discharge detection v oltage (2.75 V Typ) in the pow er down
delay time or less (20 s Typ) , it is judged the state of the over-discharge.
When the OCV terminal (pin 1) becomes “H” le vel, the DOUT terminal (pin 10) becomes “L” le vel, and also the
VS terminal (pin 18) becomes “H” level with the external discharge control P-ch MOS FET turned on.
At this time, as long as cell v oltage remains belo w the o ver-discharge detection v oltage (2.75 V Typ) , after the
VS output delay time (2 s Typ) by condenser (CPDT) , P-ch MOS FET of the VS terminal (pin 18) is tur ned off
again. But the VS ter minal (pin 18) becomes “H” level when the cell voltage will become more than the over-
discharge detection voltage (2.75 V Typ) in the power down delay time or less (20 s Typ) , and it is not judged
the state of the over-discharge.
MB3838A
25
4. Over-Current Detection Block
• State that discharge current is comparatively small as over-current (VTH2 >
>>
> VIS >
>>
> VTH1) .
Figure 6
As shown in Figure 6, if the VIS terminal (pin 11) voltage by external resistor RS becomes 110 mV or more, it
charges condenser (COCT) connected with the COCT terminal (pin 8) and GND.
If the OCV ter minal voltage returns to the level of the battery voltage while it is delay time (7 ms Typ) , it is not
judged the over-current.
It is judged the over-current, the DOUT ter minal (pin 10) becomes “H” level when the VIS terminal voltage by
e x ternal resistor RS becomes 110 mV or more, and delay time (7 ms Typ) by condenser (COCT) connected with
the COCT terminal (pin 8) and GND passed, and the external discharge control P-ch MOS FET is turned off again.
The OCV ter minal (pin 1) becomes “L” level by the discharge having stopped, and turns off the source of the
bias in IC completely.
The DOUT terminal (pin 10) becomes “L” le vel because it makes the OCV terminal (pin 1) “H” level and the VS
terminal (pin 18) also becomes “H” level.
0 V
tD (7 ms)
(3 V)
(0.3 V)
(0.11 V)
0 V
VIS terminal
COUT terminal
DOUT terminal
VS terminal
↓ charge start
Internal bias : off
MB3838A
26
• State that discharge current is large as over-current (VIS >
>>
> VTH2) .
Figure 7
As shown in Figure 7, when the potential difference voltage between the VIS terminal (pin 11) and the GND
terminal (pin 12) by e xternal resistor RS becomes 110 mV or more, it charges condenser (COCT) connected with
the COCT terminal (pin 8) and GND.
If the OCV ter minal voltage returns to the level of the battery voltage while it is delay time (7 ms Typ) , it is not
judged the over-current.
The potential difference between the VIS ter minal (pin 11) and the GND ter minal (pin 12) by exter nal resistor
RS becomes 300 mV or more, and when dela y time (500 µs Typ) by condenser (COCT) connected with the COCT
ter minal (pin 8) and GND passes, it is judged the over-current. And the DOUT ter minal (pin 10) becomes “H”
le vel, and the e xternal discharge control P-ch MOS FET is turned off, the VS terminal (pin 18) becomes “L” le vel
and the OCV terminal (pin 1) also becomes “L” level. At this time, turns off the source of the bias in IC completely .
The DOUT terminal (pin 10) becomes “L” le vel because it makes the OCV terminal (pin 1) “H” level and the VS
terminal (pin 18) also becomes “H” level.
0 V
tD (500 µs)
(3 V)
(0.3 V)
(0.11 V)
0 V
VIS terminal
COCT terminal
DOUT terminal
VS terminal
↓ charge start
Internal bias : off
MB3838A
27
■
■■
■OTHER NOTES
About the output voltage of the VREF terminal and the VDD terminal
The VREF terminal (pin 14) outputs 5 V (Typ) , and the VDD ter minal (pin 15) outputs 5 V (Typ) in the state
usually. The VREF terminal (pin 14) and the VDD terminal (pin 15) become 0 V when the over-discharge of the
battery is detected, and it enters the state of power down. At this time, the voltage applied to the VDD terminal
(pin 15) is output as for the VREF ter minal (pin 14) because it is short-circuited with an inter nal switch during
the VREF terminal (pin 14) and VDD terminal (pin 15) when the voltage is applied from the outside to the VDD
terminal (pin 15)
About the operation at a low voltage
If case of the cell v oltage becomes extremely unbalanced and one cell or some cells become short (under 0.6 V
Typ) , the COUT terminal (pin 2) is set “H” level (The open-collector output is a Off state) by the shor t cell
detection function. However, the short cell detection function is invalidated when the VCC terminal (pin 17)
v oltage falls below 4.2 V (Typ) , and the COUT terminal (pin 2) is set “L” lev el in the state of 1.4 V or more (Typ)
in the OCV terminal (pin 1) voltage.
About the VS terminal
Because it enters the state that the interdiction of the over-charge protection function cannot be done if it is
charged through the body diode of internal P-ch MOS FET connected with the VS terminal (pin 18) , be careful
please not to apply the voltage more than the VCC terminal voltage to the VS terminal.
About the electrostatic charge
Because this IC achieves making of the battery long-lived, the function to assume Icc = 0 µA at power down is
built-in this IC.
Attention enough so as not to cause the malfunction by applying static electricity to need the charger for the
return is necessary.
We recommend making low impedance with the condenser etc. to prevent the static electricity noise from invading
each input terminal of IC.
Please arrange the condenser which uses such a purpose in very nearby of IC.
Terminal processing in 3 cells mode
This IC corresponds to the battery of 3 cells series connection and 4 cells series connection.
Please be short-circuited of the B4 cell input because protection functions other than the ov er-charge detection
function are invalidated at 3 cells mode.
BAT4
BAT3
BAT2
BAT1
GND
SEL
Cell 3
Cell 2
Cell 1
• Terminal processing in 3 cells mode
MB3838A
28
■
■■
■I/O EQUIVALENT CIRCUIT
(Continued)
17
12
VDD
VREF
VCC
GND
625 kΩ
14
15
GND
VDD
1.8 MΩ
600 kΩ
VDD
−
+
2
4
VDD
COVT
GND
2 kΩ
COUT
6
13
10
VCC
VDD
GND
CPDT
100 kΩ
20 kΩ
1 kΩ
PDWN
DOUT
11 2 kΩ
8
COCT
VIS
VDD
GND
+
+
−
−
VTH1
VTH2
100 kΩ
100 kΩ
100 kΩ
100 kΩ×1
×1
×1
×1
3
5
7
9
GND
BAT4
BAT3
BAT2
BAT1
Reference Voltage Block VDD Regulator Block
Over-charge Detection Block Over-discharge Detection Block and Power Fail Block
Over-current Detection Block Cell Voltage Input Block
ESD
protection
element
MB3838A
29
(Continued)
1
18
16
600 Ω
500 Ω
VCC
GND
OCV
VS
OUTON
19
GND
VCC
SEL 2 kΩ
20
23
22
21 100 kΩ100 kΩ
100 kΩ100 kΩ
100 kΩ
100 kΩ
VCC
D1
D2
D3
GND
AOUT1
−
+24
GND
VIS 4 kΩ
4 kΩ
500 kΩ/192 kΩ
500 kΩ/192 kΩ
AOUT2
Remote on Circuit Block Cell Switch Circuit Block
Cell Voltage Monitor Block
Current Monitor Block
MB3838A
30
■
■■
■APPLICATION EXAMPLE
R11
1 MΩ
R12
100 kΩ
10 Ω
1 kΩ
1 kΩ
1 kΩ
1 kΩ
R13
100 kΩ
R15
10 kΩ
R8
1 MΩ
R16
4.7 kΩ
R14
1 MΩR7
470 Ω
M1 M2
R6
B4
B3
B2
BG
B1
R5
R4
R3
R2
C4
0.1 µF
C3
0.1 µF
C2
0.1 µF
C1
0.1 µF
C10
1 µF
C8
0.1 µF
C9
0.1 µFC7
4.7 µFC6
4.7 µF
C14
0.1 µF
C16
0.1 µF
C17
0.1 µF
C5
0.1 µF
C15
0.1 µF
R1A
10 mΩ
C11
3300 pF
4700 pF
C12
R18
62 kΩ
R19
12 kΩ
R20
330 kΩR22
10 kΩ
R21
10 kΩ
M3
M4 M5
D1
VS
BAT+
SC
POW
DATA
CLOCK
GND
IC2
MB39F101
IC1
MB3838A
Vcc_meas. Temp_meas
1
2
3
4
5
6
7
8
9
10
11
12
OCV
COUT
BAT4
COVT
BAT3
CPDT
BAT2
COCT
BAT1
DOUT
VIS
GND
24
23
22
21
20
19
18
17
16
15
14
13
AOUT2
D1
D2
D3
AOUT1
SEL
VS
VCC
OUTON
VDD
VREF
PDWN
1
2
3
4
5
6
7
8
9
10
Avref
AN00
AN01
AN02
Vss
AN03
CAN00
WP
VPP
TEST
-ENTRY
20
19
18
17
16
15
14
13
12
11
SDA
SCL
Vcc1
SALAVE
-ADDRESS
POWON
Vcc2
PORT3
PORT2
PORT1
PORT0
C13
0.1 µF
R17
4.7 kΩ
Note PC side
B4 Cell
B3 Cell
B2 Cell
B1 Cell
Li ION
Battery
MB3838A
31
■
■■
■RARTS LIST
Note : TOSHIBA : TOSHIBA CORPORATION
NEC : NEC corporation
ROHM : ROHM CO., LTD
TDK : TDK Corporation
KOA : KOA Corporation
ssm : SUSUMU CO., LTD.
KYOCERA : KYOCERA Corporation.
COMPONENT ITEM SPECIFICATION VENDOR PARTS No.
IC1 IC FUJITSU MB3838A
IC2 IC FUJITSU MB39F101
M1, M2 FET VDS = −30 V TOSHIBA TPC8107
M3 FET VDS = −30 V NEC 2SJ463A
M4, M5 FET VDS = 50 V NEC µPA602T
D1 Diode VF = 0.37 V (Max) , IF = 1 mA ROHM RB751V-40
C1, C2, C3, C4, C5
C8, C9, C13, C14
C15, C16, C17
C6, C7
C10
C11
C12
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
0.1 µF
0.1 µF
0.1 µF
4.7 µF
1 µF
3300 pF
4700 pF
50 V (10%)
50 V (10%)
50 V (10%)
10 V (10%)
25 V (10%)
50 V (10%)
50 V (10%)
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C1608JB1H104K
C1608JB1H104K
C1608JB1H104K
C2012JB1A475K
C3216JB1E105K
C1608JB1H332K
C1608JB1H472K
R1A
R2, R3, R4, R5
R6
R7
R8, R11, R14
R12, R13
R15, R21, R22
R20
R16, R17
R18
R19
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
10 mΩ
1 kΩ
10 Ω
470 Ω
1 MΩ
100 kΩ
10 kΩ
330 kΩ
4.7 kΩ
62 kΩ
12 kΩ
1 W, 1%
1/16 W, 0.5%
1/16 W, 0.5%
1/16 W, 0.5%
1/10 W, 5%
1/16 W, 0.5%
1/16 W, 0.5%
1/16 W, 0.5%
1/16 W, 0.5%
1/16 W, 0.5%
1/16 W, 0.5%
KOA
ssm
ssm
ssm
KYOCERA
ssm
ssm
ssm
ssm
ssm
ssm
SL1TTE10LOF
RR0816P102D
RR0816P100D
RR0816P471D
CR10-105J
RR0816P104D
RR0816P103D
RR0816P334D
RR0816P472D
RR0816P623D
RR0816P123D
MB3838A
32
■
■■
■USAGE PRECAUTIONS
•
••
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply negative voltages.
The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
malfunction.
■
■■
■ORDERING INFORMATION
Part number Package Remarks
MB3838APFV 24-pin plastic SSOP
(FPT-24P-M03)
MB3838A
33
■
■■
■PACKAGE DIMENSION
24-pin plastic SSOP
(FPT-24P-M03)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) MAX) .
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F24018S-c-4-5
7.75±0.10(.305±.004)
5.60±0.10 7.60±0.20
(.220±.004) (.299±.008)
*1
*2
0.10(.004)
112
1324
0.65(.026) –0.07
+0.08
0.24
.009 +.003
–.003 M
0.13(.005)
INDEX
0.17±0.03
(.007±.001)
"A"
0.25(.010)
0.10±0.10
(.004±.004)
(Stand off)
Details of "A" part
(Mounting height)
1.25 +0.20
–0.10
–.004
+.008
.049
0~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10(.004)
MB3838A
FUJITSU LIMITED
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F0409
2004 FUJITSU LIMITED Printed in Japan
