High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
1 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date
2.0
2.1
Initial issue with new naming rule
Add a new 32L WSON –8x8mm package
Jan.26, 2005
Aug.12, 2005
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
2 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
GENERAL DESCRIPTION
The CS18LV40963 is a high performance, high speed, and super low power CMOS Static
Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of
2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of 0.50uA and maximum
access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW
chip enable (/CE) and active LOW output enable (/OE) and three-state output drivers.
The CS18LV40963 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV40963 is available in JEDEC standard 32-pin
sTSOP 1 -8x13.4 mm, TSOP 1 -8x20mm, TSOP 2 -400mil, SOP -450 mil and WSON –8x8mm
packages.
.
FEATURES
Low operation voltage : 2.7 ~ 3.6V
Ultra low power consumption : 3mA＠1MHz (Max.) operating current
0.50 uA (Typ.) CMOS standby current
High speed access time : 55/70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
Product Family
Product Family Operating
Temp
Standby (Typ. )
(Vcc = 3.0V) Vcc. Range Speed (ns) Package Type
32L SOP
32L STSOP 1
0~70oC
0.50 uA
32L TSOP 1
32L TSOP 2
32L WSON
CS18LV40963
-40~85oC 1.0 uA
2.7~3.6 55/70
Dice
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
3 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
4 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
PIN DESCRIPTIONS
Name
Type Function
A0 – A18 Input Address inputs for selecting one of the 524,288 x 8 bit words in the RAM
/CE Input
/CE is active LOW. Chip enables must be active when data read from or
write to the device. If either chip enable is not active, the device is
deselected and in a standby power down mode. The DQ pins will be in
high impedance state when the device is deselected.
/WE Input
The Write enable input is active LOW. It controls read and write
operations. With the chip selected, when /WE is HIGH and /OE is LOW,
output data will be present on the DQ pins, when /WE is LOW, the data
present on the DQ pins will be written into the selected memory location.
/OE Input
The output enable input is active LOW. If the output enable is active
while the chip is selected and the write enable is inactive, data will be
present on the DQ pins and they will be enabled. The DQ pins will be in
the high impedance state when /OE is inactive.
DQ0~DQ7 I/O These 8 bi-directional ports are used to read data from or write data into
the RAM.
Vcc Power Power Supply
Gnd Power Ground
NC No connection
TRUTH TABLE
MODE /CE /WE /OE DQ0~7 Vcc Current
Standby H X X High Z ICCSB, ICCSB1
Output Disabled L H H High Z ICC
Read L H L DOUT I
CC
Write L L X DIN I
CC
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
5 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter Rating Unit
VTERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V
TBIAS Temperature Under Bias -40 to +125 OC
TSTG Storage Temperature -60 to +150 OC
PT Power Dissipation 1.0 W
IOUT DC Output Current 30 mA
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE
Range Ambient Temperature Vcc
Commercial 0~70oC 2.7V ~ 3.6V
Industrial -40~85oC 2.7V ~ 3.6V
1. Overshoot : Vcc +2.0V in case of pulse width ≦20ns.
2. Undershoot : - 2.0V in case of pulse width ≦20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol Parameter Conditions MAX. Unit
CIN Input Capacitance VIN=0V 6 pF
CDQ Input/Output Capacitance VI/O=0V 8 pF
1. This parameter is guaranteed and not tested.
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
6 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
Parameter
Name Parameter Test Conduction MIN TYP(1) MAX Unit
VIL Guaranteed Input Low
Voltage (2)
-0.5 0.8
V
VIH Guaranteed Input High
Voltage (2)
2.0 Vcc+0.2
V
IIL Input Leakage Current VCC=MAX, VIN=0 to VCC -1 1
uA
IOL Output Leakage
Current
VCC=MAX, /CE=VIN, or
/OE=VIN , VIO=0V to VCC
-1 1
uA
VOL Output Low Voltage
VCC=MAX, IOL = 2mA 0.4
V
VOH Output High Voltage VCC=MIN, IOH = -1mA 2.4 V
ICC Operating Power
Supply Current
/CE=VIL, IDQ=0mA, F=FMAX
(3) 30
mA
ICCSB Standby Supply - TTL /CE=VIH, IDQ=0mA, 1
mA
ICCSB1 Standby Current
-CMOS
/CE≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V
0.5 5
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or
tester notice are included.
3. Fmax = 1/tRC.
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC)
Parameter Name Parameter Test Conduction MIN TYP MAX Unit
VDR VCC for Data Retention /CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V 1.5 V
ICCDR Data Retention Current /CE≧VCC-0.2V, VCC=1.5V
VIN≧VCC-0.2V or VIN≦0.2V 0.3 2 uA
TCDR Chip Deselect to Data
Retention Time 0 ns
tR Operation Recovery
Time
See Retention Waveform
t
RC (1) ns
1. Read Cycle Time.
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
7 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS
Input Pulse Levels Vcc/0V WAVEFORMS INPUTS OUTPUTS
Input Rise and Fall Times 5ns MUST BE STEADY MUST BE STEADY
Input and Output Timing
Reference Level 0.5Vcc
Output Load See FIGURE 1A
and 1B
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY CENTER LINE IS HIGH
IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A FIGURE 1B
667Ω
TERMINAL EQUIVALENT
OUTPUT 1.73V
GND
V
CC
5ns 5ns
10%
90% 90%
10%
ALL INPUT PULSES
FIGURE 2
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
8 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V )
< READ CYCLE >
55 -70 JEDEC
Parameter
Name
Parameter
Name
Description
MIN MAX MIN MAX
Unit
tAVAX t
RC Read Cycle Time 55 70 ns
tAVQ V t
AA Address Access Time 55 70 ns
tELQV t
CO Chip Select Access Time (/CE) 55 70 ns
tGLQV t
OE Output Enable to Output Valid 25 35 ns
tELQX t
LZ Chip Select to Output Low Z (/CE) 10 10 ns
tGLQX t
OLZ Output Enable to Output in Low Z 5 5 ns
tEHQZ t
CHZ Chip Deselect to Output in High Z
(/CE)
0 20 0 25 ns
tGHQZ t
OHZ Output Disable to Output in High Z 0 20 0 25 ns
tAXOX t
OH Out Disable to Address Change 10 10 ns
SWITCHING WAVEFORMS (READ CYCLE)
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
9 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for
a given device and from device to device interconnection.
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V )
< WRITE CYCLE >
55 -70 JEDEC
Parameter
Name
Parameter
Name
Description
MIN MAX MIN MAX
Unit
tAVAX t
WC Write Cycle Time
55 70 ns
tE1LWH t
CW Chip Select to End of Write
45 60 ns
tAVW L t
AS Address Setup Time
0 0 ns
tAVW H t
AW Address Valid to End of Write
45 60 ns
tWLWH t
WP Write Pulse Width
40 50 ns
tWHAX t
WR Write Recovery Time (/CE, /WE)
0 0 ns
tWLQZ t
WHZ Write to Output in High Z
20 20 ns
tDVWH t
DW Data to Write Time Overlap
25 30 ns
tWHDX t
DH Data Hold from Write Time
0 0 ns
tWHOX t
OW End of Write to Output Active
5 5 ns
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
10 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
SWITCHING WAVEFORMS (WRITE CYCLE)
High Speed Super Low Power SRAM
512K Word By 8 Bit CS18LV40963
11 Rev. 2.1
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. A write occurs during the overlap(tWP) of low /CE and low /WE. A write begins at the
latest transition among /CE goes low. A write ends at the earliest transition when /CE
goes high and /WE goes high. The tWP is measured from the beginning of the write to
the end of write.
2. tCW is measured from the /CE going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. TWR applied in case a
write ends as /CE or /WE going high.
ORDER INFORMATION
Note: Package material code “R” meets ROHS
