11486-812 - ON Semiconductor L.L.C.

IAmerican Microsystems, Inc., reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

1.0 Features

• Fully compatible with FS6370 (EEPROM-based) and

FS6377 (register-based) devices.

• Three on-chip PL Ls with Referenc e an d Fee dback

Dividers set by internal ROM look-up table

• Four independently programmable muxes and post

dividers

• Selectable po wer -do wn of PLLs and shutd o wn of

output clock drivers

• Tristate outputs for board testing

• Can be optimized for reference clock (instead of

crystal) input

• 5V to 3.3V operation

• Commercial (FS6372) and industrial (FS6372i) tem-

perature ranges

2.0 Description

The FS6372 is a CMOS clock generator IC designed to

minimize cost and component count in a variety of elec-

tronic systems. Three phase-locked loops feeding four

muxes and post di viders pro vide a high degree of f lexibil-

ity.

Figure 1: Pin Configuration

116

VSS

SELECT

VSS

XIN

XOUT/REFIN

VDD n/c

CLK_D

VSS

CLK_C

CLK_B

VDD

CLK_A

VDD

FS6372-xx

16-pin (0.150”) SOIC

Figure 2: Block Diagram

ROM

Power Down

Control

Post

Divider C

Post

Divider B

FS6372

Post

Divider A

CLK_A

CLK_B

CLK_C

Reference

Oscillator PLL A

PLL B

XOUT

XIN

PLL C

Post

Divider D

CLK_D

SELECT

Mux

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

Table 1: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = T hree-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN TYPE NAME DESCRIPTION

1 P VSS Ground

2DI

USELECT Selects diff erent devic e funct i on (refer to specific variation of FS6372-xx for details )

3DI

UPD Power-Down Input

4 P VSS Ground

5 AI XIN Crystal Oscillator Input

6 AO XOUT / REFIN Crystal Oscillator Output / Reference Clock Input

7DI

UOE Output Enable Input

8 P VDD Power Supply (5V to 3.3V)

9 - N/C No Connect

10 DO CLK_D D Clock Output

11 P VSS Ground

12 DO CLK_C C Clock Output

13 DO CLK_B B Cl ock Output

14 P VDD Power Supply (5V t o 3.3V)

15 DO CLK_A A Cl ock Output

16 P VDD Power Supply (5V t o 3.3V)

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

3.0 Electrical Specifications

Table 2: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER SYMBOL MIN. MAX. UNITS

Supply Voltage, dc (VSS = ground) VDD VSS-0.5 7 V

Input Voltage, dc VIVSS-0.5 VDD+0.5 V

Output Voltage, dc VOVSS-0.5 VDD+0.5 V

Input Clamp Current, dc (V I < 0 or VI > V DD)I

IK -50 50 mA

Output Clamp Current, dc (VI < 0 or VI > VDD)I

OK -50 50 mA

Storage Temperature Range (non-condensing) TS-65 150 °C

Ambient Temperature Range, Under Bias TA-55 125 °C

Junction Temperature TJ150 °C

Lead Temperature (soldering, 10s) 260 °C

Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage res ulting in a loss of functi onality or performance may occur if this devi ce is subjected to a high-energy elec-

trostatic discharge.

Table 3: Operating Conditions

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

5V ± 10% 4.5 5 5.5

Supply Voltage VDD 3.3V ± 10% 3 3.3 3.6 V

Commercial 0 70

Ambient Operating Temperature Range TAIndustrial -40 85 °C

Crystal Resonator Frequency fXIN 527MHz

Crystal Resonator Load Capacitanc e CXL Paral l el resonant , A T cut 18 pF

Output Driver Load Capacitance CL15 pF

AMERICAN MICROSYSTEMS, INC.

March 2002

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

Table 4: DC Electrical Specifications

Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

Supply Current, Dynamic, with

Loaded Outputs IDD VDD = 5.5V, fCLK = 50MHz, CL = 15pF 43 mA

Supply Current, Static IDDL VDD = 5.5V, device powered down 0.3 mA

Power-Down, Output Enable Pins (PD, OE)

VDD = 5.5V 3.85 VDD+0.3

High-Level Input V olt age VIH VDD = 3.6V 2.52 VDD+0.3 V

VDD = 5.5V VSS-0.3 1.65

Low-Level Input V oltage VIL VDD = 3.6V VSS-0.3 1.08 V

VDD = 5.5V 2.20

Hysteresis Voltage Vhys VDD = 3.6V 1.44 V

High-Level Input Current IIH -1 1 µA

Low-Level Input Current (pul l-up) IIL VIL = 0V -20 -36 -80 µA

Select (SELECT)

VDD = 5.5V 2.4 VDD+0.3

High-Level Input V olt age VIH VDD = 3.6V 2.0 VDD+0.3 V

VDD = 5.5V VSS-0.3 0.8

Low-Level Input V oltage VIL VDD = 3.6V VSS-0.3 0.8 V

High-Level Input Current IIH -1 1 µA

Low-Level Input Current (pul l-up) IIL -20 -36 -80 µA

Crystal Oscillator Feedback (XIN)

VDD = 5.5V 2.9

Threshold Bias Voltage VTH VDD = 3.6V 1.7 V

VDD = 5.5V 54 µA

High-Level Input Current IIH VDD = 5.5V, oscillator powered down 5 15 mA

Low-Level Input Current IIL VDD = 5.5V -25 -54 -75 µA

Crystal Loadi ng Capaci tance * CL(xtal) As seen by an external crystal connected to XIN and

XOUT 18 pF

Input Loading Capacitance * CL(XIN) As seen by an external clock driver on XOUT; XIN

unconnected 36 pF

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

Table 5: DC Electrical Specifications, continued

Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Crystal Oscillator Drive (XOUT)

High-Level Output Sourc e Current I OH VDD = V(XIN) = 5.5V, VO = 0V 10 21 30 mA

Low-Level Output Sink Current IOL VDD = 5.5V, V(XIN) = 0V, VO = 5.5V -10 -21 -30 mA

Clock Outputs (CLK_A, CLK_B, CL K_C, CLK_D)

High-Level Output Sourc e Current I OH VO = 2.4V -125 mA

Low-Level Output Sink Current IOL VO = 0.4V 23 mA

zOH VO = 0.5VDD; output drivi ng hi gh 29

Output Impedance zOL VO = 0.5VDD; output drivi ng l ow 27 Ω

Tristate Output Current IZ-10 10 µA

Short Circuit S ource Current * ISCH VDD = 5.5V, VO = 0V; shorted for 30s, max. -150 mA

Short Circuit S i nk Current * ISCL VDD = VO = 5.5V, shorted for 30s, max. 123 m A

Figure 3: CLK_A, CLK_B, CL K_C, CLK_D Clock Outputs

Low Drive Current (mA) High Drive Current (mA)

Voltage

(V) MIN. TYP. MAX. Voltage

(V) MIN. TYP. MAX.

0 0 0 0 0 -87 -112 -150

0.2 9 11 12 0.5 -85 -110 -147

0.5 22 25 29 1 -83 -108 -144

0.7 29 34 40 1.5 -80 -104 -139

1 39 46 55 2 -74 -97 -131

1.2 44 52 64 2.5 -65 -88 -121

1.5 51 61 76 2.7 -61 -84 -116

1.7 55 66 83 3 -53 -77 -108

2 60 73 92 3.2 -48 -71 -102

2.2627797 3.5-39-62-92

2.5 65 81 104 3.7 -32 -55 -85

2.7 65 83 108 4 -21 -44 -74

3 66 85 112 4.2 -13 -36 -65

3.5 67 87 117 4.5 0 -24 -52

4 68 88 119 4.7 -15 -43

4.5 69 89 120 5 0 -28

5 91 121 5.2 -11

5.5 123 5.5 0

-200

-150

-100

-50

100

150

- 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Output Current (mA)

MIN

TYP

MAX

The data in this table represents nominal characterization data only.

AMERICAN MICROSYSTEMS, INC.

March 2002

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

Table 6: AC Timing Specifications

Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK

(MHz) MIN. TYP. MAX. UNITS

Overall

VDD = 5.5V 0.8 150

Output Frequency * fOVDD = 3.6V 0.8 100 MHz

VDD = 5.5V 40 230

VCO Frequency * fVCO VDD = 3.6V 40 170 MHz

VO = 0. 5V to 4.5V ; CL = 15pF 1.9

Rise Time * trVO = 0. 3V to 3.0V ; C L = 15pF 1.6 ns

VO = 4. 5V to 0.5V ; CL = 15pF 1.8

Fall Time * tfVO = 3.0V to 0. 3V; CL = 15pF 1.5 ns

Tristate Enable Delay * tPZL, tPZH 18ns

Tristate Disable Delay * tPLZ, tPHZ 18ns

Clock Stabilization Time * tSTB Output active from power-up, via PD pin 100 µs

Clock Outputs (PLL A clock via CLK_A pin)

Duty Cycle * Ratio of pulse width (as measured from rising edge to next

falling edge at 2.5V) to one clock period 100 45 55 %

On rising edges 500µs apart at 2.5V relative to an ideal

clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,

No other PLLs active 100 45

Jitter, Long Term (σy(τ)) * tj(LT) On rising edges 500µs apart at 2.5V relative to an ideal

clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,

all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) 50 165 ps

From rising edge to the next rising edge at 2.5V, CL=15pF,

fXIN=14.318MHz, NF=220, NR=63, NPx=50,

No other PLLs active 100 110

Jitter, Period (peak-peak) * tj(∆P) From rising edge to the next rising edge at 2.5V, CL=15pF,

fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs

active (B=60MHz, C=40MHz, D=14.318MHz) 50 390 ps

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

Table 7: AC Timing Specifications, continued

Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization

data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION CLOCK

(MHz) MIN. TYP. MAX. UNITS

Clock Outputs (PLL B clock via CLK_B pin)

Duty Cycle * Ratio of pulse width (as measured from rising edge to

next falling edge at 2.5V) to one clock period 100 45 55 %

On rising edges 500µs apart at 2.5V relative to an ideal

clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,

NPx=50, No other PLLs active 100 45

Jitter, Long Term (σy(τ)) * tj(LT) On rising edges 500µs apart at 2.5V relative to an ideal

clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,

NPx=50, all other PLLs active (A=50MHz, C=40MHz,

D=14.318MHz) 60 75 ps

From rising edge to the next rising edge at 2.5V,

CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,

No other PLLs active 100 120

Jitter, Period (peak-peak) * tj(∆P) From rising edge to the next rising edge at 2.5V,

CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all

other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) 60 400 ps

Clock Outputs (PLL_C clock via CLK_C pin)

Duty Cycle * Ratio of pulse width (as measured from rising edge to

next falling edge at 2.5V) to one clock period 100 45 55 %

On rising edges 500µs apart at 2.5V relative to an ideal

clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,

NPx=50, No other PLLs active 100 45

Jitter, Long Term (σy(τ)) * tj(LT) On rising edges 500µs apart at 2.5V relative to an ideal

clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,

NPx=50, all other PLLs active (A=50MHz, B=60MHz,

D=14.318MHz) 40 105 ps

From rising edge to the next rising edge at 2.5V,

CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,

No other PLLs active 100 120

Jitter, Period (peak-peak) * tj(∆P) From rising edge to the next rising edge at 2.5V,

CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all

other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) 40 440 ps

Clock Outputs (Crystal Oscillator via CLK_D pin)

Duty Cycle * Ratio of pulse width (as measured from rising edge to

next falling edge at 2.5V) to one clock period 14.318 45 55 %

On rising edges 500µs apart at 2.5V relative to an ideal

clock, CL=15pF, fXIN=14.318MHz, No other PLLs active 14.318 20

Jitter, Long Term (σy(τ)) * tj(LT) From rising edge to the next rising edge at 2.5V,

CL=15pF, fXIN=14.318MHz, all other PLLs active

(A=50MHz, B=60MHz, C=40MHz) 14.318 40 ps

From rising edge to the next rising edge at 2.5V,

CL=15pF, fXIN=14.318MHz, No other PLLs active 14.318 90

Jitter, Period (peak-peak) * tj(∆P) From rising edge to the next rising edge at 2.5V,

CL=15pF, fXIN=14.318MHz, all other PLLs active

(A=50MHz, B=60MHz, C=40MHz) 14.318 450 ps

AMERICAN MICROSYSTEMS, INC.

March 2002

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

4.0 Package Information

Table 8: 16-pin SOIC (0.150") Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

MIN. MAX. MIN. MAX.

A 0.061 0.068 1.55 1.73

A1 0.004 0.0098 0.102 0.249

A2 0.055 0.061 1.40 1.55

B 0.013 0.019 0.33 0.49

C 0.0075 0.0098 0.191 0.249

D 0.386 0.393 9.80 9.98

E 0.150 0.157 3.81 3.99

e 0.050 BSC 1.27 BSC

H 0.230 0.244 5.84 6.20

h 0.010 0.016 0.25 0.41

L 0.016 0.035 0.41 0.89

Θ0°8°0°8°

SEATING PLANE

1ALL RADII:

0.005" TO 0.01"

BASE PLANE

7° typ.h x 45°

AMERICAN MICROSYSTEMS, INC.

Table 9: 16-pin SOIC (0.150") Package Characteristics

PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS

Thermal Impedance, Junction to Free-Air

16-pin 0.150” SOIC ΘJA Air flow = 0 m/s 110 °C/W

Corner lead 4.0

Lead Inductanc e, Self L11 Center lead 3.0 nH

Lead Inductanc e, Mutual L12 Any lead to any adjacent l ead 0.4 nH

Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF

3.1.02

FS6372

FS6372FS6372

FS6372

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or ICROM-Bas ed 3-PLL Cloc k Gen erat or IC

ROM-Bas ed 3-PLL Cloc k Gen erat or IC

ISO9001

ISO9001ISO9001

ISO9001

5.0 Ordering Information

5.1 Device Ordering Codes

DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING

TEMPERATURE RANGE SHIPPING

CONFIGURATION

11486-802 16-pin (0.150”) SOIC

(Small Outl i ne Package) 0°C to 70°C (Commercial) Tape-and-Reel

11486-812 16-pin (0.150”) SOIC

(Small Outl i ne Package) 0°C to 70°C (Commercial) Tubes

11486-902 16-pin (0.150”) SOIC

(Small Outl i ne Package) -40°C to 85°C (Industrial) Tape-and-Reel

FS6372

11486-912 16-pin (0.150”) SOIC

(Small Outl i ne Package) -40°C to 85°C (Industrial) Tubes

Devices sold by AMI are covered b y the warranty and pat ent indem nific ation pro visions ap pearing in its T erms of Sale

only. AMI m akes no warrant y, express, s tatutory im plied or b y descript ion, r egarding th e infor m ation set f orth here in or

regarding t he f r eed om of the des cr ibed de vic es from patent inf r ingement. AMI mak es no warranty of merchantabi l it y or

fitness for any pur poses. AMI reser ves the right to discont inue pro duction and c hange s pecific ations and prices a t any

time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring ex-

tended tem perature range, u nusual environm enta l requirem ents, or h igh reliab ilit y applications , such as m ilitary, m edi-

cal life-s uppor t or life-s ustaining e qu ipment, are s p ec if ic ally not recomm ended without add itional pr oc ess ing by AMI f or

such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,

WWW Add ress: http://www.amis.com E-mail: t

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