Preliminary Datasheet
Specifications in this document are tentative and subject to change.
R01DS0190EJ 00 6 0 Rev.0.60 Page 1 of 56
Apr 15, 2013
RX111 Group
Renesas MCUs
Features
32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 49 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32-bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Low power consumption function
Operation from a single 1.8 to 3.6 V supply
Three low power consumption modes
On-chip flash memory for code, no wait states
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
16 to 128 Kbyte capacities
Programmable at 1.8 V
For instructions and operands
On-chip data flash memory
8 Kbytes
1,000,000 Erase/Write cycles
BGO (Background Operation)
On-chip SRAM, no wait states
8 to 16 Kbyte capacities
Data transfer controller (DTC)
Four transfer modes
Transfer can be set for each int errupt source.
Event link controller (ELC)
Module operation can be initiated by event signals
without going through interrupts.
Link operation between modules is possible while the
CPU is sleeping.
Reset and power supply voltage management
Six types including Power-On Reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External clock input frequency: Up to 20 MHz
Main oscillator frequency: 1 to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a dedicated 32.768-kHz clock for the RTC
On-chip clock frequency accuracy measurement circuit
(CAC)
Realtime clock (RTC)
30-second, leap year, and error adjustment functions
Calendar count mode or binary count mode selectable
Capable of initiating exit from software standby mode
Independent watchdog timer (IWDT)
15-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
On-chip functions for IEC 60730 compliance
Clock frequency accuracy measurement circuit, IWDT,
functions to assist in RAM testing, etc.
USB
USB2.0 host (32-Kbyte or more ROM)/function/
OTG (On-The-Go) (one channel)
Full-speed = 12 Mbps, low-speed = 1.5 Mbps
Isochronous transfer
BC (Battery Charging)
Up to five channels for communication
SCI: Asynchronous mode, clock synchronous mode,
smart card interface (up to seven channels)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI (one channel)
Up to 8 extended-function timers
16-bit MTU: Input capture/output compare,
complementary PWM output, phase counting mode
(six channels)
16-bit CMT (two channels)
12-bit A/D converter
Up to 14 channels
1 μs minimum conversion speed
Double trigger (data duplication) function for motor
control
8-bit D/A converter
Two channels (for 64 pins only)
Temperature sensor
General I/O ports
5-V tolerant, open drain, input pull-up
Multi-function pin controller (MPC)
Multiple I/O pins can be selected for peripheral functions.
Operating temperature range
40C to 85C
40°C to 105°C
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8 mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5 mm pitch
PWQN0048KB-A 7 × 7mm, 0.50mm pitch
PWQN0040KC-A 6 × 6mm, 0.50mm pitch
PWLG0064 KA-A 5 × 5mm, 0.5mm pitch
PWLG0036 KA-A 4 × 4 mm, 0.5 mm pitch
32 MHz 32-bit RX MCUs, 50 DMIPS,
up to 128 Kbytes of flash memory, USB 2.0 full-speed host/function/
OTG up to 5 comms channels, 12-bit A/D, 8-bit D/A, RTC
R01DS0190EJ0060
Rev.0.60
Apr 15, 2013
R01DS0190EJ 00 6 0 Rev.0.60 Page 2 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the spec ifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modul es and channels wil l
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1 Outline of Specifications (1/3)
Classification Module/Function Description
CPU CPU Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per one clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multipli er: 32-bit × 32-bit 64-bit
On-chip divider: 32-bit ÷ 32-bit 32 bits
Barrel shifter: 32 bits
Memory ROM Capacity: 16 K /32 K /6 4 K /96 K /128 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asynchronous serial communication/USB communication), self-progra mming
RAM Capacity: 8 K /10 K /16 Kbytes
32 MHz, no-wait memory access
E2 DataFlash Capacity: 8 Kbytes
Number of erase/write cycles: 1,0 00,000 (typ)
MCU operating mode Single-chip mode
Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed on- chip o scillato r, high -speed on- chip o scillato r,
IWDT-dedicated on-chip oscillator, and PLL frequency synthesizer
Oscillation stop detection: Available
Measurement circuit for accuracy of clock frequency (clock accuracy check: CAC)
Independent settings for the system clo ck (ICLK), periphe ral module clock (PCLK), and FlashI F clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization wit h the peripheral module clock (PCLK): 32 MHz (at
max.)
The flash peripheral circuit runs in synchronization with the FlashIF clock (FCLK): 32 MHz (at max.)
The ICLK frequency can onl y be set to FCLK, PCLKB , or PCLKD multiplied by n (n: 1, 2, 4, 8, 16 , 32,
64).
Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit
(LVDAa) When the voltage on VCC falls below t he voltage detecti on level, a n internal rese t or interna l interrupt
is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power
consumption Low power consumption
functions Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating
power consumption Operating power co ntrol modes
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt Interrupt controller (ICUb) Interrupt vectors: 82
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
R01DS0190EJ 00 6 0 Rev.0.60 Page 3 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
DMA Data transfer controller
(DTCa) Transfer modes: Normal transf er, repeat transfer, and bl ock transfer
Activation sources: Interrupts
Chain transfer function
I/O ports General I/O ports 64-pin /48-pin /40- pin /36-pin
I/O: 46/30/24/20
Input: 3/3/1/1
Pull-up resistors: 38/24/19/16
Open-drain outputs: 34/24/19/16
5-V tolerance: 4/4/4/4
Event link controller (ELC) Event signals of 35 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation fo r port B
Multi-function pin controlle r (MPC) Capable of selecting the input/output function from multiple pins
Timers Multi-function timer pulse
unit 2 (MTU2a) (16 bits × 6 channels) × 1 unit
Time bases for the six 16-bit ti mer channels can be provided via up to 16 pulse-input/ output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024 , MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input captu re registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of trigger s for A/D converter conversion
Port output enable 2
(POE2a) Controls the high-impedance state of the MTU’s waveform output pins
Compare match timer
(CMT) (16 bits × 2 channels) × 1 unit
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Independent watchdog
timer (IWDTa) 14 bits × 1 channel
Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Realtime clock (RTCA) Clock source: Sub-clock
Calendar count mode or binary count mode selectable
Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
Communication
functions Serial communications
interfaces (SCIe, SCIf) 3 channels (channel 1, 5: SCIe, channel 12: SCIf)
Serial communications modes: Asynchronous, clock synchronous, and smart card interface
On-chip baud rate genera tor allows selection of the desired bit rate
Choice of LSB-first or MSB-fi rst transfer
Enables transfer rate clock input from the MTU
Simple I2C
Simple SPI
Master/slave mode supported (SCIf only)
Start frame and information frame are included (SCIf only)
Start-bit detection in asynchronous mode: Low level or falling edge is selectable
I2C bus inter f ace (RIIC) 1 channel
Communications formats:
I2C bus format/SMBus format
Master mode or slave mode selectable
Supports fa st m o de
Serial peripheral interface
(RSPI) 1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-fi rst transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or receiv ed in a single transfer operati on (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
Table 1.1 Outline of Specifications (2/3)
Classification Module/Function Description
R01DS0190EJ 00 6 0 Rev.0.60 Page 4 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Communication
function USB 2.0 host/function
module (USBc) USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated.
Host (32-Kbyte or more ROM)/function module: 1 port
Compliant with USB version 2.0
Transfer speed: Full-speed (12 Mbps), low-speed (1.5 Mbps)
OTG (ON-The-Go) is supported.
Isochronous transfer is supported.
BC (Battery Charger) is supported.
12-bit A/D converter (S12ADb) 1 unit (1 unit × 14 channels)
12-bit resolution
Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 32 MHz
Operating modes
Scan mode (single scan mode, co ntinuous scan mode, and group scan mode)
Double-trigger mode (duplication of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
Temperature sensor (TEMPSa) 1 channel
The voltage of the temperature is converted into a digital value by the 12-bit A/D converter.
D/A converter (DA) 2 channels
8-bit resolution
Output voltage: 0 V to VCC
CRC calculator (CRC) CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
Generation of CRC codes for use with LS B-first or MSB-first communications is selectable.
Data operation circuit (DOC) Comparison, addition, and subt raction of 16-bit data
Power supply voltages/ Operating frequencies VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 3.6 V: 32 MHz
Supply current 3.2 mA at 32 MHz (typ.)
Operating temperat ure range D version: 40 to +85°C, G version: 40 to +105°C
Packages 64-pin LFQFP (PLQP0064KB-A) 10 × 10 mm, 0.5 mm pitch
64-pin LQFP (PLQP0064GA-A) 14 × 14 mm, 0.8 mm pitch
48-pin LFQFP (PLQP0048KB-A) 7 × 7 mm, 0.5 mm pitch
40-pin HWQFN (PWQN0040KC-A) 6 × 6mm, 0.50mm pitc h
36-pin WFLGA (PWLG0036KA-A) 4 × 4 mm, 0.5 mm pitch
64-pin WFLGA (PWLG0064KA-A) 5 × 5 mm, 0.5 mm pitch
48-pin HWQFN (PWQN0048KB-A) 7 × 7 mm, 0.5 mm pitch
On-chip debugging system E1 emulator (FINE interface)
Table 1.1 Outline of Specifications (3/3)
Classification Module/Function Description
R01DS0190EJ 00 6 0 Rev.0.60 Page 5 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Table 1.2 Comparison of Functions for Different Packages
Module/Functions
RX111 Group
64 Pins 48 Pins 40 Pins 36 Pins
Interrupts External interrupts NMI, IRQ0 to IRQ7
DMA Data transfer controller Supported
Timers Multi-function timer pulse unit 2 6 channels (MTU0 to MTU5)
Port output enable 2 POE0# to POE3#, POE8# POE0#, POE2#, POE3#, POE8#
Compare match timer 2 channels × 1 unit
Realtime clock Supported Not supported
Independent watchdog timer Supported
Communication
functions Serial communications interfaces
[simple I2C, simple SPI] 2 channels (SCI1, SCI5)
Serial communications interface
[simple I2C, simple SPI] 1 channel (SCI12)
I2C bus interface 1 channel
Serial peripheral interface 1 channel 1 channel
(SSLA1 and
SSLA3 are not
supported)
1 channel
(SSLA1 to SSLA3 are not supported)
USB 2.0 host/function module
(USBc) 1 channel
(Host/Function/
OTG)
1 channel
(Host/Function)
12-bit A/D converter
(including high-precision channels) 14 channels
(6 channels) 10 channels
(4 channels) 8 channels
(3 channels) 7 channels
(2 channels)
D/A converter 2 channels Not supported
Temper ature sensor Supported
CRC calculator Supported
Event link controller Supported
Packages 64-pin LFQFP
64-pin LQFP
64-pin WFLGA
48-pin LFQFP
48-pin HWQFN 40-pin HWQFN 36-pin WFLGA
R01DS0190EJ 00 6 0 Rev.0.60 Page 6 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
1.2 List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package
type.
Table 1.3 List of Products (1/2)
Group Part No. Orderable Part No. Package ROM
Capacity RAM
Capacity E2
DataFlash
Maximum
Operating
Frequency Operating
Temperature
RX111 R5F51115AGFM R5F51115AGFM#30 PLQP0064KB-A
128 Kbytes
16 Kbytes
8 Kbytes 32 MHz 40 to +105°C
R5F51115AGFKt R5F51115AGFK#30 PLQP0064GA-A
R5F51115AGFL R5F51115AGFL#30 PLQP0048KB-A
R5F51115AGNE R5F51115AGNE#V0 PWQN0048KB-A
R5F51114AGFM R5F51114AGFM#30 PLQP0064KB-A
96 Kbytes
R5F51114AGFK R5F51114AGFK#30 PLQP0064GA-A
R5F51114AGFL R5F51114AGFL#30 PLQP0048KB-A
R5F51114AGNE R5F51114AGNE#V0 PWQN0048KB-A
R5F51113AGFM R5F51113AGFM#30 PLQP0064KB-A
64 Kbytes
10 Kbytes
R5F51113AGFK R5F51113AGFK#30 PLQP0064GA-A
R5F51113AGFL R5F51113AGFL#30 PLQP0048KB-A
R5F51113AGNE R5F51113AGNE#V0 PWQN0048KB-A
R5F51113AGNF R5F51113AGNF#V0 PWQN0040KC-A
R5F51111AGFM R5F51111AGFM#30 PLQP0064KB-A
32 Kbytes
R5F51111AGFK R5F51111AGFK#30 PLQP0064GA-A
R5F51111AGFL R5F51111AGFL#30 PLQP0048KB-A
R5F51111AGNE R5F51111AGNE#V0 PWQN0048KB-A
R5F51111AGNF R5F51111AGNF#V0 PWQN0040KC-A
R5F5111JAGFM R5F5111JAGFM#30 PLQP0064KB-A
16 Kbytes 8 Kbytes
R5F5111JAGFK R5F5111JAGFK#30 PLQP0064GA-A
R5F5111JAGFL R5F5111JAGFL#30 PLQP0048KB-A
R5F5111JAGNE R5F5111JAGNE#V0 PWQN0048KB-A
R5F5111JAGNF R5F5111JAGNF#V0 PWQN0040KC-A
R01DS0190EJ 00 6 0 Rev.0.60 Page 7 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Note: Orderable part numbers are current as of when this manual was published. Please make sure to refer the relevant product page
on the Renesas website for the latest part numbers.
RX111 R5F51115ADFM R5F51115ADFM#30 PLQP0064KB-A
128 Kbytes
16 Kbytes
8 Kbytes 32 MHz 40 to +85°C
R5F51115ADFK R5F51115ADFK#30 PLQP0064GA-A
R5F51115ADLF R5F51115ADLF#U0 PWLG0064KA-A
R5F51115ADFL R5F51115ADFL#30 PLQP0048KB-A
R5F51115ADNE R5F51115ADNE#V0 PVQN0048KA-A
R5F51114ADFM R5F51114ADFM#30 PLQP0064KB-A
96 Kbytes
R5F51114ADFK R5F51114ADFK#30 PLQP0064GA-A
R5F51114ADLF R5F51114ADLF#U0 PWLG0064KA-A
R5F51114ADFL R5F51114ADFL#30 PLQP0048KB-A
R5F51114ADNE R5F51114ADNE#V0 PWQN0048KB-A
R5F51113ADFM R5F51113ADFM#30 PLQP0064KB-A
64 Kbytes
10 Kbytes
R5F51113ADFK R5F51113ADFK#30 PLQP0064GA-A
R5F51113ADLF R5F51113ADLF#U0 PWLG0064KA-A
R5F51113ADFL R5F51113ADFL#30 PLQP0048KB-A
R5F51113ADNE R5F51113ADNE#V0 PWQN0048KB-A
R5F51113ADLM R5F51113ADLM#U0 PWLG0036KA-A
R5F51113ADNF R5F51113ADNF#V0 PWQN0040KC-A
R5F51111ADFM R5F51111ADFM#30 PLQP0064KB-A
32 Kbytes
R5F51111ADFK R5F51111ADFK#30 PLQP0064GA-A
R5F51111ADLF R5F51111ADLF#U0 PWLG0064KA-A
R5F51111ADFL R5F51111ADFL#30 PLQP0048KB-A
R5F51111ADNE R5F51111ADNE#V0 PWQN0048KB-A
R5F51111ADLM R5F51111ADLM#U0 PWLG0036KA-A
R5F51111ADNF R5F51111ADNF#V0 PWQN0040KC-A
R5F5111JADFM R5F5111JADFM#30 PLQP0064KB-A
16 Kbytes 8 Kbytes
R5F5111JADFK R5F5111JADFK#30 PLQP0064GA-A
R5F5111JADLF R5F5111JADLF#U0 PWLG0064KA-A
R5F5111JADFL R5F5111JADFL#30 PLQP0048KB-A
R5F5111JADNE R5F5111JADNE#V0 PWQN0048KB-A
R5F5111JADLM R5F5111JADLM#U0 PWLG0036KA-A
R5F5111JADNF R5F5111JADNF#V0 PWQN0040KC-A
Table 1.3 List of Products (2/2)
Group Part No. Orderable Part No. Package ROM
Capacity RAM
Capacity E2
DataFlash
Maximum
Operating
Frequency Operating
Temperature
R01DS0190EJ 00 6 0 Rev.0.60 Page 8 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type
Type of memory
F: Flash memory version
ROM, RAM, and E2 DataFlash capacity
FM: LFQFP/64/0.50
FK: LQFP/64/0.80
LF: WFLGA/64/0.50
FL: LFQFP/48/0.50
NE: HWQFN/48/0.50
NF: HWQFN/40/0.50
LM: WFLGA/36/0.50
ROM, RAM, and E2 DataFlash capacity
5: 128 Kbytes/16 Kbytes/8 Kbytes
4: 96 Kbytes/16 Kbytes/8 Kbytes
3: 64 Kbytes/10 Kbytes/8 Kbytes
1: 32 Kbytes/10 Kbytes/8 Kbytes
J: 16 Kbytes/8 Kbytes/8 Kbytes
Group name
10: RX110 Group
11: RX111 Group
Renesas MCU
Renesas semiconductor product
Series name
RX100 Series
D: Operating temperature (-40°C to +85°C)
G: Operating temperature (-40°C to +105°C)
R 5 F 5 1 D F MA511#30
Packing, Terminal material (Pb-free)
#3: Tray/Sn (Tin) only
#V: Tray/Sn (Tin) only
#U: Tray/SnCu and others
Production identification code
R01DS0190EJ 00 6 0 Rev.0.60 Page 9 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
1.3 Block Diagram
Figure 1.2 shows a block diagram of the RX111.
Figure 1.2 RX111 Block Diagram
Ext ernal bu s
BSC
ICUb: Interrupt controller
DTCa: Data transfer controller
IWDTa: Independen t w atchdo g timer
ELC: Event link controller
CRC: CRC (cyclic redundancy check) calculator
SCIe/SCIf: Serial commu nication s inte rface
RSPI: Serial peripheral interface
RIIC: I2C bus interface
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
USBc: USB 2.0 host/function module
CMT: Compare match timer
RTCA: Realtime clock
DOC: Data operation circuit
CAC: Clock frequency accuracy measurement circuit
Operand bus
Instruction bus
Internal main bus 1
Clock
generation
circuit
RX CPU
RAM
ROM Port 0
Port 1
Port 2
Port 3
Port 4
Internal perip he r al bus es 1 to 6
Internal main bus 2
DTCa
ICUb
Port 5
Port A
Port B
Port C
Port E
E2 DataFlash
IWDTa
ELC
CRC
SCIe × 2 channels
SCIf × 1 channel
RSPI × 1 channel
RIIC × 1 channel
MTU2a × 6 channels
POE2a
USBc × 1 port
CMT × 2 channels ( unit 0 )
RTCA
12-bit A/D converter × 14 channels
8-bit D/A converter × 2 channels
DOC
CAC
Temperature sensor
R01DS0190EJ0060 Rev.0.60 Page 10 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
1.4 Pin Functions
Table 1.4 lists the pin functions.
Table 1.4 Pin Functions (1/ 3)
Classifications Pin Name I/O Description
Power supply VCC Input Power supply pin. Connect it to the system power supply.
VCL Connect this pin to the VSS pin via the 4.7 μF smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the pin.
VSS Input Ground pin. Connect it to the system power supply (0 V).
Clock XTAL Output/
Input *1Pins for connecting a crystal resonator. An external clock can be input
through the XTAL pin.
EXTAL Input
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCIN and XCOUT.
XCOUT Output
CLKOUT Output Clock output pin
Operating mode
control MD Input Pin for setting the operating mode. The signal levels on this pin must not be
changed during operation.
System control RES# Input Reset pin. This LSI enters the reset state when this signal goes low.
CAC CACREF Input Input pin for the clock frequency accuracy measurement circuit.
On-chip
emulator FINED I/O FINE interface pin.
LVD CMPA2 Input Detection target voltage pin for voltage detection 2
Interrupts NMI Input Non-maskable interrupt request pin.
IRQ0 to IRQ7 Input Interrupt request pins.
Multi-function
timer pulse unit 2 MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D I/O The TGRA0 to TGRD0 input capture input/output compare output/PWM
output pins.
MTIOC1A, MTIOC1B I/O The TGRA1 and TGRB1 input capture input/output compare output/PWM
output pins.
MTIOC2A, MTIOC2B I/O The TGRA2 and TGRB2 input capture input/output compare output/PWM
output pins.
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D I/O The TGRA3 to TGRD3 input capture input/output compare output/PWM
output pins.
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D I/O The TGRA4 to TGRD4 input capture input/output compare output/PWM
output pins.
MTIC5U, MTIC5V, MTIC5W Input The TGRU5, TGRV5, and TGRW5 input capture input/external pulse input
pins.
MTCLKA, MTCLKB,
MTCLKC, MTCLKD Input Input pins for the external clock.
Port output
enable 2 POE0# to POE3#, POE8# Input Input pins for request signals to place the MTU pins in the high impedance
state.
Realtime clock RTCOUT Output Output pin for the 1-Hz/64-Hz clock.
Serial
communications
interface (SCIe)
Asynchronous mode/clock synchronous mode
SCK1, SCK5 I/O Input/output pins for the clock
RXD1, RXD5 Input Input pins for received data
TXD1, TXD5 Output Output pins for transmitted data
CTS1#, CTS5# Input Input pins for controlling the start of transmission and reception
RTS1#, RTS5# Output Output pins for controlling the start of transmission and reception
Simple I2C mode
SSCL1, SSCL5 I/O Input/output pins for the I2C clock
SSDA1, SSDA5 I/O Input/output pins for the I2C data
R01DS0190EJ0060 Rev.0.60 Page 11 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Serial
communications
interface (SCIe)
Simple SPI mode
SCK1, SCK5 I/O Input/output pins for the clock
SMISO1, SMISO5 I/O Input/output pins for slave transmit data
SMOSI1, SMOSI5 I/O Input/output pins for master transmit data
SS1#, SS5# Input Chip-select input pins
Serial
communications
interface (SCIf)
Asynchronous mode/clock synchronous mode
SCK12 I/O Input/output pin for the clock
RXD12 Input Input pin for received data
TXD12 Output Output pin for transmitted data
CTS12# Input Input pin for controlling the start of transmission and reception
RTS12# Output Output pin for controlling the start of transmission and reception
Simple I2C mode
SSCL12 I/O Input/output pin for the I2C clock
SSDA12 I/O Input/output pin for the I2C data
Simple SPI mode
SCK12 I/O Input/output pin for the clock
SMISO12 I/O Input/output pin for slave transmit data
SMOSI12 I/O Input/output pin for master transmit data
SS12# Input Chip-select input pin
Extended serial mode
RXDX12 Input Input pin for data reception by SCIf
TXDX12 Output Output pin for data transmission by SCIf
SIOX12 I/O Input/output pin for data reception or transmission by SCIf
I2C bus interface SCL0 I/O Input/output pin for I2C bus interface clocks. Bus can be directly driven by
the N-channel open drain output.
SDA0 I/O Input/output pin for I2C bus interface data. Bus can be directly driven by the
N-channel open drain output.
Serial peripheral
interface RSPCKA I/O Clock input/output pin for the RSPI.
MOSIA I/O Input or output data output from the master for the RSPI.
MISOA I/O Input or output data output from the slave for the RSPI.
SSLA0 I/O Input/output pin to select the slave for the RSPI.
SSLA1 to SSLA3 Output Output pins to select the slave for the RSPI.
USB 2.0 host/
function module VCC_USB Input Power supply pin for USB. Connect this pin to VCC.
VSS_USB Input Ground pin for USB. Connect this pin to VSS.
USB0_DP I/O D+ I/O pin of the USB on-chip transceiver.
USB0_DM I/O D- I/O pin of the USB on-chip transceiver.
USB0_VBUS Input USB cable connection monitor pin.
USB0_EXICEN Output Low-power control signal for the OTG chip.
USB0_VBUSEN Output VBUS (5 V) supply enable signal for the OTG chip.
USB0_OVRCURA,
USB0_OVRCURB Input External overcurrent detection pins.
USB0_ID Input Mini-AB connector ID input pin during operation in OTG mode.
12-bit A/D
converter AN000 to AN004, AN006,
AN008 to AN015 Input Input pins for the analog signals to be processed by the A/D converter.
ADTRG0# Input Input pin for the external trigger signals that start the A/D conversion.
D/A converter DA0, DA1 Output Output pins for the analog signals to be processed by the D/A converter.
Table 1.4 Pin Functions (2/ 3)
Classifications Pin Name I/O Description
R01DS0190EJ0060 Rev.0.60 Page 12 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Note 1. For external clock input.
Analog power
supply AVCC0 Input Analog voltage supply pin for the 12-bit A/D converter. Connect this pin to
VCC if the 12-bit A/D converter is not to be used.
AVSS0 Input Analog ground pin for the 12-bit A/D converter. Connect this pin to VSS if
the 12-bit A/D converter is not to be used.
VREFH0 Input Analog reference voltage supply pin for the 12-bit A/D converter. Connect
this pin to VCC if the 12-bit A/D converter is not to be used.
VREFL0 Input Analog reference ground pin for the 12-bit A/D converter. Connect this pin
to VSS if the 12-bit A/D converter is not to be used.
I/O ports P03, P05 I/O 2-bit input/output pins.
P14 to P17 I/O 4-bit input/output pins.
P26, P27 I/O 2-bit input/output pins.
P30 to P32, P35 I/O 4-bit input/output pins. (P35 input pin)
P40 to P44, P46 I/O 6-bit input/output pins.
P54, P55 I/O 2-bit input/output pins.
PA0, PA1, PA3, PA4, PA6 I/O 5-bit input/output pins.
PB0, PB1, PB3, PB5 to PB7 I/O 6-bit input/output pins.
PC0 to PC7 I/O 8-bit input/output pins.
PE0 to PE7 I/O 8-bit input/output pins.
PH6, PH7 Input 2-bit input pins.
PJ6, PJ7 I/O 2-bit input/output pins.
Table 1.4 Pin Functions (3/ 3)
Classifications Pin Name I/O Description
R01DS0190EJ0060 Rev.0.60 Page 13 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
1.5 Pin Assignments
Figure 1.3 to Figure 1.7 show the pin assignments. Table 1.5 to Table 1.6 show the lists of pins and pin functions.
Figure 1.3 Pin Assignments of the 64-Pi n LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
54
55
51
49
50
52
53
56
57
58
59
60
61
63
64
62
RX111 Group
PLQP0064KB-A
(64-pin LQFP)
(Top view)
PE2
PE1
PE0
PE7
PE6
P46
P44
P43
P42
P41
PJ7/VREFL0
P40
PJ6/VREFH0
AVSS0
AVCC0
P05
PE3
PE4
PE5
PA0
PA1
PA3
PA4
PA6
VSS
PB0
VCC
PB1
PB3
PB5
PB6/PC0
PB7/PC1
PC2
PC3
PC4
PC5
PC6
PC7
P54
P55
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P14
P15
P16
P17
P03
P27
P26
P30
P31
MD
RES#
PH7/XCOUT
PH6/XCIN
P35/NMI
XTAL
EXTAL
VCL
VSS
VCC
P32
Note: This figure indicates the power supply pins and I/O ports.
For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin LQFP)”.
R01DS0190EJ0060 Rev.0.60 Page 14 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Figure 1.4 Pin Assignments of the 64-Pi n WFLGA
AVSS0
RX111 Group
PWLG0064KA-A
(64-pin WFLG A)
(Upper perspective view)
PH7/
XCOUT PH6/
XCIN RES# XTAL EXTAL VCL VSS
AVCC0 P03 P05 P30 MD P32 P17 VCC
PJ6/
VREFH0 P40 P27 P26 P31 P35 P16 VCC_USB
PJ7/
VREFL0 P42 P41 PE0 P55 P14 P15 USB0_DM
P43 P44 PE7 PA6 PB3 P54 PC6 USB0_DP
P46 PE6 PE5 PA4 PB1 PC7 PC5 VSS_USB
PE2 PE1 PA1 PA3 PB0 PC4 PC3 PC2
PE3 PE4 PA0 VSS VCC PB5 PB6 PB7
ABCDEFGH
8
7
6
5
4
3
2
1
ABCDEFGH
8
7
6
5
4
3
2
1
Note: This figure indicates the power supply pins and I/O port pins. For the pin
configuration, see the table “List of Pins and Pin Functions (64-Pin WFLGA)”.
For the position of A1 pin in the package, see “Package Dimensions”.
R01DS0190EJ0060 Rev.0.60 Page 15 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure 1.5 Pin Assignments of the 48-Pi n LQFP/HWQFN
Note: This figure indicates The power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions
(48-Pin LQFP/HWQFN)”.
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
38
39
37
40
41
42
43
44
45
47
48
46
RX111 Group
PLQP0048KB-A
(48-pin LQFP)
(Top view)
PE2
PE1
PE0
PE7
P46
P42
P41
PJ7/VREFL0
P40
PJ6/VREFH0
AVSS0
AVCC0
PE3
PE4
PA1
PA3
PA4
PA6
VSS
PB0/PC0
VCC
PB1/PC1
PB3/PC2
PB5/PC3
PC4
PC5
PC6
PC7
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P14
P15
P16
P17
P27
P26
MD
RES#
PH7/XCOUT
PH6/XCIN
P35/NMI
XTAL
EXTAL
VCL
VSS
VCC
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
38
39
37
40
41
42
43
44
45
47
48
46
RX111 Group
PWQN0048KB-A
(48-pin HWQFN)
(Top view)
PE2
PE1
PE0
PE7
P46
P42
P41
PJ7/VREFL0
P40
PJ6/VREFH0
AVSS0
AVCC0
PE3
PE4
PA1
PA3
PA4
PA6
VSS
PB0/PC0
VCC
PB1/PC1
PB3/PC2
PB5/PC3
PC4
PC5
PC6
PC7
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P14
P15
P16
P17
P27
P26
MD
RES#
PH7/XCOUT
PH6/XCIN
P35/NMI
XTAL
EXTAL
VCL
VSS
VCC
18
17
16
15
14
13
R01DS0190EJ0060 Rev.0.60 Page 16 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure 1.6 Pin Assignments of the 40-Pin HWQFN
20
19
18
17
31
32
33
34
35
36
37
39
40
38
PE2
PE1
PE0
P46
P42
P41
PJ7/VREFL0
PJ6/VREFH0
AVSS0
AVCC0
PC4
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P14
P15
P16
P17
P32
P27
P26
MD
RES#
P35/NMI
XTAL
EXTAL
VCL
VSS
VCC
16
15
14
13
12
11
30
29
28
27
26
25
24
23
22
21
RX111 Group
PWQN0040KC-A
(40-pin HWQF N)
(Top view)
PE3
PE4
PA1
PA3
PA4
PA6
VSS
PB0
VCC
PB3
1
2
3
4
5
6
7
8
9
10
Note: This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (40-Pin HWQFN)”.
R01DS0190EJ0060 Rev.0.60 Page 17 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure 1.7 Pin Assignments of the 36-Pi n WFLGA
AVSS0
RX111 Group
PWLG0036KA-A
(36-pin WFLGA)
(Upper perspective view)
RES# XTAL EXTAL VCL VSS
AVCC0 P27 MD P35 P17 VCC
PJ6/
VREFH0 PJ7/
VREFL0 PE3 P14 P16 VCC_USB
P42 PE0 PE4 PA6 P15 USB0_DM
P41 PE1 PA4 PB3 PC4 USB0_DP
PE2 PA3 VSS PB0 VCC VSS_USB
ABCDEF
6
5
4
3
2
1
Note: This figure indicates the power supply pins and I/O port pins. For the pin
configuration, see the table “List of Pins and Pin Functions (36-Pin WFLGA)”.
For the position of A1 pin in the package, see “Package Dimensions”.
R01DS0190EJ0060 Rev.0.60 Page 18 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Table 1.5 List of Pins and Pin Functions (64-Pin LQFP) (1/2)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
1P03 DA0
2 P27 MTIOC2B SCK1/SCK12 IRQ3/CMPA2/
CACREF/ADTRG0#
3 P26 MTIOC2A TXD1/SMOSI1/SSDA1/USB0_VBUSEN
4 P30 MTIOC4B/POE8# RXD1/SMISO1/SSCL1 IRQ0
5 P31 MTIOC4D CTS1#/RTS1#/SS1# IRQ1
6MD FINED
7RES#
8 XCOUT PH7
9XCIN PH6
10 P35 NMI
11 XTAL
12 EXTAL
13 VCL
14 VSS
15 VCC
16 P32 MTIOC0C/RTCOUT IRQ2
17 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8# SCK1/MISOA/SDA0/RXD12/RXDX12/
SMISO12/SSCL12 IRQ7
18 P16 MTIOC3C/MTIOC3D/
RTCOUT TXD1/SMOSI1/SSDA1/MOSIA/SCL0/
USB0_VBUS/USB0_VBUSEN/
USB0_OVRCURB
IRQ6/ADTRG0#
19 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT
20 P14 MTIOC0A/MTIOC3A/
MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/
TXDX12/SIOX12/SMOSI12/SSDA12/
USB0_OVRCURA
IRQ4
21 VCC_USB
22 USB0_DM
23 USB0_DP
24 VSS_USB
25 P55 MTIOC4D
26 P54 MTIOC4B
27 PC7 MTIOC3A/MTCLKB TXD1/SMOSI1/SSDA1/MISOA/
USB0_OVRCURB CACREF
28 PC6 MTIOC3C/MTCLKA RXD1/SMISO1/SSCL1/MOSIA/
USB0_EXICEN
29 PC5 MTIOC3B/MTCLKD SCK1/RSPCKA/USB0_ID
30 PC4 MTIOC3D/MTCLKC/POE0# SCK5/SSLA0/USB0_VBUS/
USB0_VBUSEN IRQ2/CLKOUT
31 PC3 MTIOC4D TXD5/SMOSI5/SSDA5
32 PC2 MTIOC4B RXD5/SMISO5/SSCL5/SSLA3
33 PB7/PC1 MTIOC3B
34 PB6/PC0 MTIOC3D
35 PB5 MTIOC2A/MTIOC1B/POE1#
36 PB3 MTIOC0A/MTIOC3B/
MTIOC4A/POE3# USB0_OVRCURA
37 PB1 MTIOC0C/MTIOC4C IRQ4
38 VCC
39 PB0 MTIC5W/MTIOC0C/
RTCOUT SCL0/RSPCKA IRQ2/ADTRG0#
40 VSS
41 PA6 MTIC5V/MTCLKB/MTIOC2A/
POE2# CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3
R01DS0190EJ0060 Rev.0.60 Page 19 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
42 PA4 MTIC5U/MTCLKA/MTIOC2B TXD5/SMOSI5/SSDA5/SSLA0 IRQ5
43 PA3 MTIOC0D/MTCLKD/
MTIOC1B/POE0# RXD5/SMISO5/SSCL5/MISOA IRQ6
44 PA1 MTIOC0B/MTCLKC/
RTCOUT SCK5/SSLA2
45 PA0 MTIOC4A SSLA1 CACREF
46 PE5 MTIOC4C/MTIOC2B IRQ5/AN013
47 PE4 MTIOC4D/MTIOC1A/
MTIOC3A MOSIA IRQ4/AN012
48 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011
49 PE2 MTIOC4A RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010
50 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12 IRQ1/AN009
51 PE0 MTIOC2A/POE3# SCK12 IRQ0/AN008
52 PE7 IRQ7/AN015
53 PE6 IRQ6/AN014
54 P46 AN006
55 P44 AN004
56 P43 AN003
57 P42 AN002
58 P41 AN001
59 VREFL0 PJ7
60 P40 AN000
61 VREFH0 PJ6
62 AVSS0
63 AVCC0
64 P05 DA1
Table 1.5 List of Pins and Pin Functions (64-Pin LQFP) (2/2)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
R01DS0190EJ0060 Rev.0.60 Page 20 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Table 1.6 List of Pins and Pin Functions (64-Pi n WFLGA) (1/2)
Pin
No.
Power Supply,
Clock, System
Control I/O Port Timers
(MTU, POE, RTC) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
A1 AVSS0
A2 AVCC0
A3 VREFH0 PJ6
A4 VREFL0 PJ7
A5 P43 AN003
A6 P46 AN006
A7 PE2 MTIOC4A RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010
A8 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011
B1 XCOUT PH7
B2 P03 DA0
B3 P40 AN000
B4 P42 AN002
B5 P44 AN004
B6 PE6 IRQ6/AN014
B7 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12 IRQ1/AN009
B8 PE4 MTIOC1A/MTIOC3A/
MTIOC4D MOSIA IRQ4/AN012
C1 XCIN PH6
C2 P05 DA1
C3 P27 MTIOC2B SCK1/SCK12 IRQ3/CMPA2/CACREF/
ADTRG0#
C4 P41 AN001
C5 PE7 IRQ7/AN015
C6 PE5 MTIOC2B/MTIOC4C IRQ5/AN013
C7 PA1 MTIOC0B/MTCLKC/
RTCOUT SCK5/SSLA2
C8 PA0 MTIOC4A SSLA1 CACREF
D1 RES#
D2 P30 MTIOC4B/POE8# RXD1/SMISO1/SSCL1 IRQ0
D3 P26 MTIOC2A TXD1/SMOSI1/SSDA1/
USB0_VBUSEN
D4 PE0 MTIOC2A/POE3# SCK12 IRQ0/AN008
D5 PA6 MTIC5V/MTIOC2A/MTCLKB/
POE2# CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3
D6 PA4 MTIC5U/MTIOC2B/MTCLKA TXD5/SMOSI5/SSDA5/SSLA0 IRQ5
D7 PA3 MTIOC0D/MTCLKD/
MTIOC1B/POE0# RXD5/SMISO5/SSCL5/MISOA IRQ6
D8 VSS
E1 XTAL
E2 MD FINED
E3 P31 MTIOC4D CTS1#/RTS1#/SS1# IRQ1
E4 P55 MTIOC4D
E5 PB3 MTIOC0A/MTIOC3B/
MTIOC4A/POE3# USB0_OVRCURA
E6 PB1 MTIOC0C/MTIOC4C IRQ4
E7 PB0 MTIC5W/MTIOC0C/
RTCOUT SCL0/RSPCKA IRQ2/ADTRG0#
E8 VCC
F1 EXTAL
R01DS0190EJ0060 Rev.0.60 Page 21 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
F2 P32 MTIOC0C/RTCOUT IRQ2
F3 P35 NMI
F4 P14 MTIOC0A/MTIOC3A/
MTCLKA CTS1#/RTS1#/SS1#/TXD12/
TXDX12/SIOX12/SMOSI12/
SSDA12/SSLA0/USB0_OVRCURA
IRQ4
F5 P54 MTIOC4B
F6 PC7 MTIOC3A/MTCLKB TXD1/SMOSI1/SSDA1/MISOA/
USB0_OVRCURB CACREF
F7 PC4 MTCLKC/MTIOC3D/POE0# SCK5/SSLA0/USB0_VBUSEN/
USB0_VBUS IRQ2/CLKOUT
F8 PB5 MTIOC1B/MTIOC2A/POE1#
G1 VCL
G2 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8# SCK1/MISOA/SDA0/RXD12/
RXDX12/SMISO12/SSCL12 IRQ7
G3 P16 MTIOC3C/MTIOC3D/
RTCOUT TXD1/SMOSI1/SSDA1/SCL0/
MOSIA/USB0_VBUSEN/
USB0_OVRCURB/USB0_VBUS
IRQ6/ADTRG0#
G4 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT
G5 PC6 MTIOC3C/MTCLKA RXD1/SMISO1/SSCL1/MOSIA/
USB0_EXICEN
G6 PC5 MTIOC3B/MTCLKD SCK1/RSPCKA/USB0_ID
G7 PC3 MTIOC4D TXD5/SMOSI5/SSDA5
G8 PB6 MTIOC3D
H1 VSS
H2 VCC
H3 VCC_USB
H4 USB0_DM
H5 USB0_DP
H6 VSS_USB
H7 PC2 MTIOC4B RXD5/SMISO5/SSCL5/SSLA3
H8 PB7 MTIOC3B
Table 1.6 List of Pins and Pin Functions (64-Pi n WFLGA) (2/2)
Pin
No.
Power Supply,
Clock, System
Control I/O Port Timers
(MTU, POE, RTC) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
R01DS0190EJ0060 Rev.0.60 Page 22 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Table 1.7 List of Pins and Pin Functions (48-Pin LQFP/HWQFN) (1/2)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
1 P27 MTIOC2B SCK1/SCK12 IRQ3/CMPA2/
CACREF/ADTRG0#
2 P26 MTIOC2A TXD1/SMOSI1/SSDA1/USB0_VBUSEN
3MD FINED
4RES#
5 XCOUT PH7
6XCIN PH6
7P35 NMI
8XTAL
9EXTAL
10 VCL
11 VSS
12 VCC
13 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8# SCK1/MISOA/SDA0/RXD12/RXDX12/
SMISO12/SSCL12 IRQ7
14 P16 MTIOC3C/MTIOC3D/
RTCOUT TXD1/SMOSI1/SSDA1/MOSIA/SCL0/
USB0_VBUS/USB0_VBUSEN/
USB0_OVRCURB
IRQ6/ADTRG0#
15 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT
16 P14 MTIOC0A/MTIOC3A/
MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/
TXDX12/SIOX12/SMOSI12/SSDA12/
USB0_OVRCURA
IRQ4
17 VCC_USB
18 USB0_DM
19 USB0_DP
20 VSS_USB
21 PC7 MTIOC3A/MTCLKB TXD1/SMOSI1/SSDA1/MISOA/
USB0_OVRCURB CACREF
22 PC6 MTIOC3C/MTCLKA RXD1/SMISO1/SSCL1/MOSIA/
USB0_EXICEN
23 PC5 MTIOC3B/MTCLKD SCK1/RSPCKA/USB0_ID
24 PC4 MTIOC3D/MTCLKC/POE0# SCK5/SSLA0/USB0_VBUS/
USB0_VBUSEN IRQ2/CLKOUT
25 PB5/PC3 MTIOC2A/MTIOC1B/POE1#
26 PB3/PC2 MTIOC0A/MTIOC3B/
MTIOC4A/POE3# USB0_OVRCURA
27 PB1/PC1 MTIOC0C/MTIOC4C IRQ4
28 VCC
29 PB0/PC0 MTIC5W/MTIOC0C/
RTCOUT SCL0/RSPCKA IRQ2/ADTRG0#
30 VSS
31 PA6 MTIC5V/MTCLKB/MTIOC2A/
POE2# CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3
32 PA4 MTIC5U/MTCLKA/MTIOC2B TXD5/SMOSI5/SSDA5/SSLA0 IRQ5
33 PA3 MTIOC0D/MTCLKD/
MTIOC1B/POE0# RXD5/SMISO5/SSCL5/MISOA IRQ6
34 PA1 MTIOC0B/MTCLKC/
RTCOUT SCK5/SSLA2
35 PE4 MTIOC4D/MTIOC1A/
MTIOC3A MOSIA IRQ4/AN012
36 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011
37 PE2 MTIOC4A RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010
38 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12 IRQ1/AN009
R01DS0190EJ0060 Rev.0.60 Page 23 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
39 PE0 MTIOC2A/POE3# SCK12 IRQ0/AN008
40 PE7 IRQ7/AN015
41 P46 AN006
42 P42 AN002
43 P41 AN001
44 VREFL0 PJ7
45 P40 AN000
46 VREFH0 PJ6
47 AVSS0
48 AVCC0
Table 1.7 List of Pins and Pin Functions (48-Pin LQFP/HWQFN) (2/2)
Pin
No. Power Supply, Clock,
System Control I/O Port Timers
(MTU, POE, RTC) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
R01DS0190EJ0060 Rev.0.60 Page 24 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Table 1.8 List of Pins and Pin Functions (40-Pin HWQFN) (1/2)
Pin
No.
Power Supply,
Clock, System
Control I/O Port Timers (MTU, POE) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
1 P27 MTIOC2B SCK1/SCK12 IRQ3/CMPA2/CACREF/
ADTRG0#
2 P26 MTIOC2A TXD1/SMOSI1/SSDA1/
USB0_VBUSEN
3MD FINED
4RES#
5P35 NMI
6XTAL
7EXTAL
8VCL
9VSS
10 VCC
11 P32 MTIOC0C IRQ2
12 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8# SCK1/MISOA/SDA0/RXD12/
RXDX12/SMISO12/SSCL12 IRQ7
13 P16 MTIOC3C/MTIOC3D TXD1/SMOSI1/SSDA1/SCL0/
MOSIA/USB0_VBUSEN/
USB0_OVRCURB/USB0_VBUS
IRQ6/ADTRG0#
14 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT
15 P14 MTIOC0A/MTIOC3A/
MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/
TXDX12/SIOX12/SMOSI12/
SSDA12/USB0_OVRCURA
IRQ4
16 VCC_USB
17 USB0_DM
18 USB0_DP
19 VSS_USB
20 PC4 MTIOC3D/MTCLKC/POE0# SCK5/SSLA0/USB0_VBUS/
USB0_VBUSEN IRQ2/CLKOUT
21 PB3 MTIOC0A/MTIOC3B/
MTIOC4A/POE3# USB0_OVRCURA
22 VCC
23 PB0 MTIOC0C/MTIC5W SCL0/RSPCKA IRQ2/ADTRG0#
24 VSS
25 PA6 MTIOC2A/MTIC5V/MTCLKB/
POE2# CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3
26 PA4 MTIOC2B/MTIC5U/MTCLKA TXD5/SMOSI5/SSDA5/SSLA0 IRQ5
27 PA3 MTIOC0D/MTIOC1B/
MTCLKD/POE0# RXD5/SMISO5/SSCL5/MISOA IRQ6
28 PA1 MTIOC0B/MTCLKC SCK5/SSLA2
29 PE4 MTIOC1A/MTIOC3A/
MTIOC4D MOSIA IRQ4/AN012
30 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011
31 PE2 MTIOC4A RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010
32 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12 IRQ1/AN009
33 PE0 MTIOC2A/POE3# SCK12 IRQ0/AN008
34 P46 AN006
35 P42 AN002
36 P41 AN001
37 VREFL0 PJ7
38 VREFH0 PJ6
39 AVSS0
R01DS0190EJ0060 Rev.0.60 Page 25 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
40 AVCC0
Table 1.8 List of Pins and Pin Functions (40-Pin HWQFN) (2/2)
Pin
No.
Power Supply,
Clock, System
Control I/O Port Timers (MTU, POE) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
R01DS0190EJ0060 Rev.0.60 Page 26 of 56
Apr 15, 2013
RX111 Group 1. Overview
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Table 1.9 List of Pins and Pin Functions (36-Pin WFLGA)
Pin
No.
Power Supply,
Clock, System
Control I/O Port Timers (MTU, POE) Communication
(SCIe, SCIf, RSPI, RIIC, USB) Others
A1 AVSS0
A2 AVCC0
A3 VREFH0 PJ6
A4 P42 AN002
A5 P41 AN001
A6 PE2 MTIOC4A RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010
B1 RES#
B2 P27 MTIOC2B SCK1/SCK12 IRQ3/CMPA2/CACREF/
ADTRG0#
B3 VREFL0 PJ7
B4 PE0 MTIOC2A/POE3# SCK12 IRQ0/AN008
B5 PE1 MTIOC4C TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12 IRQ1/AN009
B6 PA3 MTIOC0D/MTCLKD/
MTIOC1B/POE0# RXD5/SMISO5/SSCL5/MISOA IRQ6
C1 XTAL
C2 MD FINED
C3 PE3 MTIOC0A/MTIOC1B/
MTIOC4B/POE8# CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011
C4 PE4 MTIOC1A/MTIOC3A/
MTIOC4D MOSIA IRQ4/AN012
C5 PA4 MTIOC2B/MTIC5U/MTCLKA TXD5/SMOSI5/SSDA5/SSLA0 IRQ5
C6 VSS
D1 EXTAL
D2 P35 NMI
D3 P14 MTIOC0A/MTIOC3A/
MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/
TXDX12/SIOX12/SMOSI12/
SSDA12/USB0_OVRCURA
IRQ4
D4 PA6 MTIC5V/MTCLKB/MTIOC2A/
POE2# CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3
D5 PB3 MTIOC0A/MTIOC3B/
MTIOC4A/POE3# USB0_OVRCURA
D6 PB0 MTIOC0C/MTIC5W SCL0/RSPCKA IRQ2/ADTRG0#
E1 VCL
E2 P17 MTIOC0C/MTIOC3A/
MTIOC3B/POE8# SCK1/MISOA/SDA0/RXD12/
RXDX12/SMISO12/SSCL12 IRQ7
E3 P16 MTIOC3C/MTIOC3D TXD1/SMOSI1/SSDA1/SCL0/
MOSIA/USB0_VBUSEN/
USB0_OVRCURB/USB0_VBUS
IRQ6/ADTRG0#
E4 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT
E5 PC4 MTIOC3D/MTCLKC/POE0# SCK5/SSLA0/USB0_VBUSEN/
USB0_VBUS IRQ2/CLKOUT
E6 VCC
F1 VSS
F2 VCC
F3 VCC_USB
F4 USB0_DM
F5 USB0_DP
F6 VSS_USB
R01DS0190EJ0060 Rev.0.60 Page 27 of 56
Apr 15, 2013
RX111 Group 2. CPU
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
2. CPU
Figure 2.1 shows the register set of the CPU.
Figure 2.1 Register Set of the CPU
R01DS0190EJ0060 Rev.0.60 Page 28 of 56
Apr 15, 2013
RX111 Group 2. CPU
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
2.1 Genera l-Purpose R egisters (R0 to R15)
This CPU has 16 general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers.
R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the
interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor
status word (PSW).
2.2 Control Registers
(1) Interrupt Stack Pointer (ISP)/User Stack Pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of 4, as this reduces the numbers of cycles required to execute interrupt sequences and
instructions entailing stack manipulation.
(2) Interrupt Table Register (INTB)
The interrupt table register (INTB) specifies the address where the relocatable vector table starts.
(3) Program Counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(4) Processor Status Word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(5) Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(6) Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to in terrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(7) Fast Interrupt Vector Register (FINTV)
The fast in ter rupt vector register (F INTV) is provided to speed up response to interrupts.
The FINTV register specifies a branc h des tination address when a fast interrupt has been generated.
2.3 Register Associated with DSP Instructions
(1) Accumulator (ACC)
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
R01DS0190EJ0060 Rev.0.60 Page 29 of 56
Apr 15, 2013
RX111 Group 3. Address Space
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
3. Address Space
3.1 Address Space
This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 3.1 shows the memory map.
R01DS0190EJ0060 Rev.0.60 Page 30 of 56
Apr 15, 2013
RX111 Group 3. Address Space
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure 3.1 Memory Map
Reserved area*3
Reserved area*3
Reserved area*3
On-chip ROM (E2 DataFlash)
(8 KB)
Reserved area*3
0000 0000h
0008 0000h
FFFF FFFFh
Single-chip mode*1
RAM*2
On-chip ROM (program ROM)*2
0010 0000h
Peripheral I/O registers
0010 2000h
0080 0000h
FFFE 0000h
Peripheral I/O registers
Peripheral I/O registers
007F C000h
007F C500h
007F FC00h
0000 4000h
Note 1. The address space in boot mode is the same as the address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
Note: See Table 1.3, List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
ROM (bytes) RAM (bytes)
Capacity Address Capacity Address
128 K FFFE 0000h to FFFF FFFFh 16 K 0000 0000h to 0000 3FFFh
96 K FFFE 8000h to FFFF FFFFh
64 K FFFF 0000h to FFFF FFFFh 10 K 0000 0000h to 0000 27FFh
32 K FFFF 8000h to FFFF FFFFh
16 K FFFF C000h to FFFF FFFFh 8 K 0000 0000h to 0000 1FFFh
R01DS0190EJ0060 Rev.0.60 Page 31 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
4. I/O Registers
This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as
shown below. Notes on writing to I/O registers are also given belo w.
(1) I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
Numbers of cycles for access indicate numbers of cycles of the given base clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2) Notes on writing to I/O registers
While writing to an I/O register, the CPU starts executing subsequent instructions before the I/O register write access is
completed. This may cause the subsequent instructions to be executed before the write value is reflected in the operation.
The examples below show how subsequent instructions must be executed after a write access to an I/O register is
completed.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) cleared to 0.
A WAIT instruction is executed immediat ely after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is comp leted using the following
procedure and then execute the subsequent instruction.
(a) Write to an I/O register.
(b) Read the value in the I/O register and write it to a general register.
(c) Execute the operation using the value read.
(d) Execute the subsequent instruction.
Example of instructions
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
R01DS0190EJ0060 Rev.0.60 Page 32 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
When executing an instruction after writing to multiple registers, only read the last I/O register written to and execute the
instruction using that value; it is not necessary to execute the instru ction using the values written to all the registers.
(3) Number of cycles necessary for accessing I/O registers
See Table 4.1 for details on the number of clock cycles necessary for accessing I/O registers.
The number of access cycles to I/O registers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronizati on cycl es +
Number of bus cycles for internal peripheral buses 1 to 6
The number of bus cycles of internal peripheral buses 1 to 6 differs according to the register to be accessed.
When peripheral functions co nnect ed to internal peripheral buses 2 to 6 or registers for the external bus cont rol unit
(except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access cycles shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the su bsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction
fetching to the external memory or bus access from the different bus master (DTC).
(4) Notes on sleep mode and mode transitions
During sleep mode or mode transitions, do not write to the system control related registers (indicated by ‘SYSTEM’ in
the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).
R01DS0190EJ0060 Rev.0.60 Page 33 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
4.1 I/O Register Addresses (Address Order)
Table 4.1 List of I/O Registers (Address Order) (1/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
0008 0000h SYSTEM Mode Monito r Re gi ste r MDMONR 16 16 3 ICLK
0008 0008h SYSTEM System Control Register 1 SYSCR1 16 16 3 ICLK
0008 000Ch SYSTEM Standby Control Register SBYCR 16 16 3 ICLK
0008 0010h SYSTEM Module Stop Control Register A MSTPCRA 32 32 3 ICLK
0008 0014h SYSTEM Module Stop Control Register B MSTPCRB 32 32 3 ICLK
0008 0018h SYSTEM Module Stop Control Register C MSTPCRC 32 32 3 ICLK
0008 0020h SYSTEM System Clock Contro l R egi ste r SCKCR 32 32 3 ICLK
0008 0026h SYSTEM System Clock Control Register 3 SCKCR3 16 16 3 ICLK
0008 0028h SYSTEM PLL Control Register PLLCR 16 16 3 ICLK
0008 002Ah SYSTEM PLL Control Register 2 PLLCR2 8 8 3 ICLK
0008 0032h SYSTEM Main Clock Oscillator Control Register MOSCCR 8 8 3 ICLK
0008 0033h SYSTEM Sub-Clock Oscillator Control Register SOSCCR 8 8 3 ICLK
0008 0034h SYSTEM Low-Speed On-Chip Oscillator Control Register LOCOCR 8 8 3 ICLK
0008 0035h SYSTEM IWDT-Dedicated On-Chip Oscillator Control Register ILOCOCR 8 8 3 ICLK
0008 0036h SYSTEM High-Speed On-Chip Oscillator Control Register HOCOCR 8 8 3 ICLK
0008 003Ch SYSTEM Oscillator Wait Counter Overflow Register OSCOVFSR 8 8 3 ICLK
0008 003Eh SYSTEM Clock Output Control Register CKOCR 16 16 3 ICLK
0008 0040h SYSTEM Oscillation Stop Detection Control Register OSTDCR 8 8 3 ICLK
0008 0041h SYSTEM Oscillation Stop Detection Status Register OSTDSR 8 8 3 ICLK
0008 00A0h SYSTEM Operating Power Contro l R egi ste r OPCCR 8 8 3 ICLK
0008 00A1h SYSTEM Sleep Mode Return Clock Source Switching Register RSTCKCR 8 8 3 ICLK
0008 00A2h S YSTEM Main Clock Oscillator Wait Control Register MOSCWTCR 8 8 3 ICLK
0008 00A5h SYSTEM High-Spe ed On- C hip Osci l la tor Wait Control Register HOC OW TC R 8 8 3 ICLK
0008 00AAh SYSTEM Sub Operating Power Control Register SOPCCR 8 8 3 ICLK
0008 00C0h SYSTEM Reset Status Register 2 RSTSR2 8 8 3 ICLK
0008 00C2h SYSTEM Sof tw ar e Re set R egister SWRR 16 16 3 ICLK
0008 00E0h SYSTEM Voltage Monitor i ng 1 Circuit Control Register 1 LV D1CR1 8 8 3 ICLK
0008 00E1h SYSTEM Voltage Monitoring 1 Circuit Status Register LVD1SR 8 8 3 ICLK
0008 00E2h SYSTEM Voltage Monitor i ng 2 Circuit Control Register 1 LV D2CR1 8 8 3 ICLK
0008 00E3h SYSTEM Voltage Monitoring 2 Circuit Status Register LVD2SR 8 8 3 ICLK
0008 03FEh SYSTEM Protect Register PRCR 16 16 3 ICLK
0008 1300h BSC Bus Error Status Clear Register BERCLR 8 8 2 ICLK
0008 1304h BSC Bus Error Monitoring Enable Register BEREN 8 8 2 ICLK
0008 1308h BSC Bus Error Status Register 1 BERSR1 8 8 2 ICLK
0008 130Ah BSC Bus Error Status Register 2 BERSR2 16 16 2 ICLK
0008 1310h BSC Bus Priority Control Regi ste r BUSPRI 16 16 2 ICLK
0008 2400h DTC DTC Control Register DTCCR 8 8 2 ICLK
0008 2404h DTC DTC Vector Base Register DTCVBR 32 32 2 ICLK
0008 2408h DTC DTC Address Mode Register DTCADMOD 8 8 2 ICLK
0008 240Ch DTC DTC Module Start Register DTCST 8 8 2 ICLK
0008 240Eh DTC DTC Status Register DTCSTS 16 16 2 ICLK
0008 7010h ICU Interrupt Request Register 016 IR016 8 8 2 ICLK
0008 701Bh ICU Interrupt Request Register 027 IR027 8 8 2 ICLK
0008 701Ch ICU Interrupt Request Register 028 IR028 8 8 2 ICLK
0008 701Dh ICU Interrupt Request Register 029 IR029 8 8 2 ICLK
0008 7020h ICU Interrupt Request Register 032 IR032 8 8 2 ICLK
0008 7021h ICU Interrupt Request Register 033 IR033 8 8 2 ICLK
0008 7022h ICU Interrupt Request Register 034 IR034 8 8 2 ICLK
0008 7024h ICU Interrupt Request Register 036 IR036 8 8 2 ICLK
R01DS0190EJ0060 Rev.0.60 Page 34 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 7025h ICU Interrupt Request Register 037 IR037 8 8 2 ICLK
0008 7026h ICU Interrupt Request Register 038 IR038 8 8 2 ICLK
0008 702Ch ICU Interrupt Request Register 044 IR044 8 8 2 ICLK
0008 702Dh ICU Interrupt Request Register 045 IR045 8 8 2 ICLK
0008 702Eh ICU Interrupt Request Register 046 IR046 8 8 2 ICLK
0008 702Fh ICU Interrupt Request Register 047 IR047 8 8 2 ICLK
0008 7039h ICU Interrupt Request Register 057 IR057 8 8 2 ICLK
0008 703Fh ICU Interrupt Request Register 063 IR063 8 8 2 ICLK
0008 7040h ICU Interrupt Request Register 064 IR064 8 8 2 ICLK
0008 7041h ICU Interrupt Request Register 065 IR065 8 8 2 ICLK
0008 7042h ICU Interrupt Request Register 066 IR066 8 8 2 ICLK
0008 7043h ICU Interrupt Request Register 067 IR067 8 8 2 ICLK
0008 7044h ICU Interrupt Request Register 068 IR068 8 8 2 ICLK
0008 7045h ICU Interrupt Request Register 069 IR069 8 8 2 ICLK
0008 7046h ICU Interrupt Request Register 070 IR070 8 8 2 ICLK
0008 7047h ICU Interrupt Request Register 071 IR071 8 8 2 ICLK
0008 7058h ICU Interrupt Request Register 088 IR088 8 8 2 ICLK
0008 7059h ICU Interrupt Request Register 089 IR089 8 8 2 ICLK
0008 705Ah ICU Interrupt Request Register 090 IR090 8 8 2 ICLK
0008 705Ch ICU Interrupt Request Register 092 IR092 8 8 2 ICLK
0008 705Dh ICU Interrupt Request Register 093 IR093 8 8 2 ICLK
0008 7066h ICU Interrupt Request Register 102 IR102 8 8 2 ICLK
0008 7067h ICU Interrupt Request Register 103 IR103 8 8 2 ICLK
0008 706Ah ICU Interrupt Request Register 106 IR106 8 8 2 ICLK
0008 7072h ICU Interrupt Request Register 114 IR114 8 8 2 ICLK
0008 7073h ICU Interrupt Request Register 115 IR115 8 8 2 ICLK
0008 7074h ICU Interrupt Request Register 116 IR116 8 8 2 ICLK
0008 7075h ICU Interrupt Request Register 117 IR117 8 8 2 ICLK
0008 7076h ICU Interrupt Request Register 118 IR118 8 8 2 ICLK
0008 7077h ICU Interrupt Request Register 119 IR119 8 8 2 ICLK
0008 7078h ICU Interrupt Request Register 120 IR120 8 8 2 ICLK
0008 7079h ICU Interrupt Request Register 121 IR121 8 8 2 ICLK
0008 707Ah ICU Interrupt Request Register 122 IR122 8 8 2 ICLK
0008 707Bh ICU Interrupt Request Register 123 IR123 8 8 2 ICLK
0008 707Ch ICU Interrupt Request Register 124 IR124 8 8 2 ICLK
0008 707Dh ICU Interrupt Request Register 125 IR125 8 8 2 ICLK
0008 707Eh ICU Interrupt Request Register 126 IR126 8 8 2 ICLK
0008 707Fh ICU Interrupt Request Register 127 IR127 8 8 2 ICLK
0008 7080h ICU Interrupt Request Register 128 IR128 8 8 2 ICLK
0008 7081h ICU Interrupt Request Register 129 IR129 8 8 2 ICLK
0008 7082h ICU Interrupt Request Register 130 IR130 8 8 2 ICLK
0008 7083h ICU Interrupt Request Register 131 IR131 8 8 2 ICLK
0008 7084h ICU Interrupt Request Register 132 IR132 8 8 2 ICLK
0008 7085h ICU Interrupt Request Register 133 IR133 8 8 2 ICLK
0008 7086h ICU Interrupt Request Register 134 IR134 8 8 2 ICLK
0008 7087h ICU Interrupt Request Register 135 IR135 8 8 2 ICLK
0008 7088h ICU Interrupt Request Register 136 IR136 8 8 2 ICLK
0008 7089h ICU Interrupt Request Register 137 IR137 8 8 2 ICLK
0008 708Ah ICU Interrupt Request Register 138 IR138 8 8 2 ICLK
0008 708Bh ICU Interrupt Request Register 139 IR139 8 8 2 ICLK
0008 708Ch ICU Interrupt Request Register 140 IR140 8 8 2 ICLK
0008 708Dh ICU Interrupt Request Register 141 IR141 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (2/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 35 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 70AAh ICU Interrupt Request Register 170 IR170 8 8 2 ICLK
0008 70ABh ICU Interrupt Request Register 171 IR171 8 8 2 ICLK
0008 70DAh ICU Interrupt Request Register 218 IR218 8 8 2 ICLK
0008 70DBh ICU Interrupt Request Register 219 IR219 8 8 2 ICLK
0008 70DCh ICU Interrupt Request Register 220 IR220 8 8 2 ICLK
0008 70DDh ICU Interrupt Request Register 221 IR221 8 8 2 ICLK
0008 70DEh ICU Interrupt Request Register 222 IR222 8 8 2 ICLK
0008 70DFh ICU Interrupt Request Register 223 IR223 8 8 2 ICLK
0008 70E0h ICU Interrupt Request Register 224 IR224 8 8 2 ICLK
0008 70E1h ICU Interrupt Request Register 225 IR225 8 8 2 ICLK
0008 70EEh ICU Interrupt Request Register 238 IR238 8 8 2 ICLK
0008 70EFh ICU Interrupt Request Register 239 IR239 8 8 2 ICLK
0008 70F0h ICU Interrupt Request Register 240 IR240 8 8 2 ICLK
0008 70F1h ICU Interrupt Request Register 241 IR241 8 8 2 ICLK
0008 70F2h ICU Interrupt Request Register 242 IR242 8 8 2 ICLK
0008 70F3h ICU Interrupt Request Register 243 IR243 8 8 2 ICLK
0008 70F4h ICU Interrupt Request Register 244 IR244 8 8 2 ICLK
0008 70F5h ICU Interrupt Request Register 245 IR245 8 8 2 ICLK
0008 70F6h ICU Interrupt Request Register 246 IR246 8 8 2 ICLK
0008 70F7h ICU Interrupt Request Register 247 IR247 8 8 2 ICLK
0008 70F8h ICU Interrupt Request Register 248 IR248 8 8 2 ICLK
0008 70F9h ICU Interrupt Request Register 249 IR249 8 8 2 ICLK
0008 711Bh ICU DTC Activation Enable Register 027 DTCER027 8 8 2 ICLK
0008 711Ch ICU DTC Activation Enable Register 028 DTCER028 8 8 2 ICLK
0008 711Dh ICU DTC Activation Enable Register 029 DTCER029 8 8 2 ICLK
0008 7124h ICU DTC Activation Enable Register 036 DTCER036 8 8 2 ICLK
0008 7125h ICU DTC Activation Enable Register 037 DTCER037 8 8 2 ICLK
0008 712Dh ICU DTC Activation Enable Register 045 DTCER045 8 8 2 ICLK
0008 712Eh ICU DTC Activation Enable Register 046 DTCER046 8 8 2 ICLK
0008 7140h ICU DTC Activation Enable Register 064 DTCER064 8 8 2 ICLK
0008 7141h ICU DTC Activation Enable Register 065 DTCER065 8 8 2 ICLK
0008 7142h ICU DTC Activation Enable Register 066 DTCER066 8 8 2 ICLK
0008 7143h ICU DTC Activation Enable Register 067 DTCER067 8 8 2 ICLK
0008 7144h ICU DTC Activation Enable Register 068 DTCER068 8 8 2 ICLK
0008 7145h ICU DTC Activation Enable Register 069 DTCER069 8 8 2 ICLK
0008 7146h ICU DTC Activation Enable Register 070 DTCER070 8 8 2 ICLK
0008 7147h ICU DTC Activation Enable Register 071 DTCER071 8 8 2 ICLK
0008 7166h ICU DTC Activation Enable Register 102 DTCER102 8 8 2 ICLK
0008 7167h ICU DTC Activation Enable Register 103 DTCER103 8 8 2 ICLK
0008 716Ah ICU DTC Activation Enable Register 106 DTCER106 8 8 2 ICLK
0008 7172h ICU DTC Activation Enable Register 114 DTCER114 8 8 2 ICLK
0008 7173h ICU DTC Activation Enable Register 115 DTCER115 8 8 2 ICLK
0008 7174h ICU DTC Activation Enable Register 116 DTCER116 8 8 2 ICLK
0008 7175h ICU DTC Activation Enable Register 117 DTCER117 8 8 2 ICLK
0008 7179h ICU DTC Activation Enable Register 121 DTCER121 8 8 2 ICLK
0008 717Ah ICU DTC Activation Enable Register 122 DTCER122 8 8 2 ICLK
0008 717Dh ICU DTC Activation Enable Register 125 DTCER125 8 8 2 ICLK
0008 717Eh ICU DTC Activation Enable Register 126 DTCER126 8 8 2 ICLK
0008 7181h ICU DTC Activation Enable Register 129 DTCER129 8 8 2 ICLK
0008 7182h ICU DTC Activation Enable Register 130 DTCER130 8 8 2 ICLK
0008 7183h ICU DTC Activation Enable Register 131 DTCER131 8 8 2 ICLK
0008 7184h ICU DTC Activation Enable Register 132 DTCER132 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (3/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 36 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 7186h ICU DTC Activation Enable Register 134 DTCER134 8 8 2 ICLK
0008 7187h ICU DTC Activation Enable Register 135 DTCER135 8 8 2 ICLK
0008 7188h ICU DTC Activation Enable Register 136 DTCER136 8 8 2 ICLK
0008 7189h ICU DTC Activation Enable Register 137 DTCER137 8 8 2 ICLK
0008 718Ah ICU DTC Activation Enable Register 138 DTCER138 8 8 2 ICLK
0008 718Bh ICU DTC Activation Enable Register 139 DTCER139 8 8 2 ICLK
0008 718Ch ICU DTC Activation Enable Register 140 DTCER140 8 8 2 ICLK
0008 718Dh ICU DTC Activation Enable Register 141 DTCER141 8 8 2 ICLK
0008 71DBh ICU DTC Activation Enable Register 219 DTCER219 8 8 2 ICLK
0008 71DCh ICU DTC Activation Enable Register 220 DTCER220 8 8 2 ICLK
0008 71DFh ICU DTC Activation Enable Register 223 DTCER223 8 8 2 ICLK
0008 71E0h ICU DTC Activation Enable Register 224 DTCER224 8 8 2 ICLK
0008 71EFh ICU DTC Activation Enable Register 239 DTCER239 8 8 2 ICLK
0008 71F0h ICU DTC Activation Enable Register 240 DTCER240 8 8 2 ICLK
0008 71F7h ICU DTC Activation Enable Register 247 DTCER247 8 8 2 ICLK
0008 71F8h ICU DTC Activation Enable Register 248 DTCER248 8 8 2 ICLK
0008 7202h ICU Interrupt Request Enable Register 02 IER02 8 8 2 ICLK
0008 7203h ICU Interrupt Request Enable Register 03 IER03 8 8 2 ICLK
0008 7204h ICU Interrupt Request Enable Register 04 IER04 8 8 2 ICLK
0008 7205h ICU Interrupt Request Enable Register 05 IER05 8 8 2 ICLK
0008 7207h ICU Interrupt Request Enable Register 07 IER07 8 8 2 ICLK
0008 7208h ICU Interrupt Request Enable Register 08 IER08 8 8 2 ICLK
0008 720Bh ICU Interrupt Request Enable Register 0B IER0B 8 8 2 ICLK
0008 720Ch ICU Interrupt Request Enable Register 0C IER0C 8 8 2 ICLK
0008 720Dh ICU Interrupt Request Enable Register 0D IER0D 8 8 2 ICLK
0008 720Eh ICU Interrupt Request Enable Register 0E IER0E 8 8 2 ICLK
0008 720Fh ICU Interrupt Request Enable Register 0F IER0F 8 8 2 ICLK
0008 7210h ICU Interrupt Request Enable Register 10 IER10 8 8 2 ICLK
0008 7211h ICU Interrupt Request Enable Register 11 IER11 8 8 2 ICLK
0008 7215h ICU Interrupt Request Enable Register 15 IER15 8 8 2 ICLK
0008 721Bh ICU Interrupt Request Enable Register 1B IER1B 8 8 2 ICLK
0008 721Ch ICU Interrupt Request Enable Register 1C IER1C 8 8 2 ICLK
0008 721Dh ICU Interrupt Request Enable Register 1D IER1D 8 8 2 ICLK
0008 721Eh ICU Interrupt Request Enable Register 1E IER1E 8 8 2 ICLK
0008 721Fh ICU Interrupt Request Enable Register 1F IER1F 8 8 2 ICLK
0008 72E0h ICU Software Interrupt Activation Register SWINTR 8 8 2 ICLK
0008 72F0h ICU Fast Interrupt Set Register FIR 16 16 2 ICLK
0008 7300h ICU Interrupt Source Priority Register 000 IPR000 8 8 2 ICLK
0008 7303h ICU Interrupt Source Priority Register 003 IPR003 8 8 2 ICLK
0008 7304h ICU Interrupt Source Priority Register 004 IPR004 8 8 2 ICLK
0008 7305h ICU Interrupt Source Priority Register 005 IPR005 8 8 2 ICLK
0008 7320h ICU Interrupt Source Priority Register 032 IPR032 8 8 2 ICLK
0008 7321h ICU Interrupt Source Priority Register 033 IPR033 8 8 2 ICLK
0008 7322h ICU Interrupt Source Priority Register 034 IPR034 8 8 2 ICLK
0008 7324h ICU Interrupt Source Priority Register 036 IPR036 8 8 2 ICLK
0008 7325h ICU Interrupt Source Priority Register 037 IPR037 8 8 2 ICLK
0008 7326h ICU Interrupt Source Priority Register 038 IPR038 8 8 2 ICLK
0008 732Ch ICU Interrupt Source Priority Register 044 IPR044 8 8 2 ICLK
0008 7339h ICU Interrupt Source Priority Register 057 IPR057 8 8 2 ICLK
0008 733Fh ICU Interrupt Source Priority Register 063 IPR063 8 8 2 ICLK
0008 7340h ICU Interrupt Source Priority Register 064 IPR064 8 8 2 ICLK
0008 7341h ICU Interrupt Source Priority Register 065 IPR065 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (4/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 37 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 7342h ICU Interrupt Source Priority Register 066 IPR066 8 8 2 ICLK
0008 7343h ICU Interrupt Source Priority Register 067 IPR067 8 8 2 ICLK
0008 7344h ICU Interrupt Source Priority Register 068 IPR068 8 8 2 ICLK
0008 7345h ICU Interrupt Source Priority Register 069 IPR069 8 8 2 ICLK
0008 7346h ICU Interrupt Source Priority Register 070 IPR070 8 8 2 ICLK
0008 7347h ICU Interrupt Source Priority Register 071 IPR071 8 8 2 ICLK
0008 7358h ICU Interrupt Source Priority Register 088 IPR088 8 8 2 ICLK
0008 7359h ICU Interrupt Source Priority Register 089 IPR089 8 8 2 ICLK
0008 735Ah ICU Interrupt Source Priority Register 090 IPR090 8 8 2 ICLK
0008 735Ch ICU Interrupt Source Priority Register 092 IPR092 8 8 2 ICLK
0008 735Dh ICU Interrupt Source Priority Register 093 IPR093 8 8 2 ICLK
0008 7366h ICU Interrupt Source Priority Register 102 IPR102 8 8 2 ICLK
0008 7367h ICU Interrupt Source Priority Register 103 IPR103 8 8 2 ICLK
0008 736Ah ICU Interrupt Source Priority Register 106 IPR106 8 8 2 ICLK
0008 7372h ICU Interrupt Source Priority Register 114 IPR114 8 8 2 ICLK
0008 7376h ICU Interrupt Source Priority Register 118 IPR118 8 8 2 ICLK
0008 7379h ICU Interrupt Source Priority Register 121 IPR121 8 8 2 ICLK
0008 737Bh ICU Interrupt Source Priority Register 123 IPR123 8 8 2 ICLK
0008 737Dh ICU Interrupt Source Priority Register 125 IPR125 8 8 2 ICLK
0008 737Fh ICU Interrupt Source Priority Register 127 IPR127 8 8 2 ICLK
0008 7381h ICU Interrupt Source Priority Register 129 IPR129 8 8 2 ICLK
0008 7385h ICU Interrupt Source Priority Register 133 IPR133 8 8 2 ICLK
0008 7386h ICU Interrupt Source Priority Register 134 IPR134 8 8 2 ICLK
0008 738Ah ICU Interrupt Source Priority Register 138 IPR138 8 8 2 ICLK
0008 738Bh ICU Interrupt Source Priority Register 139 IPR139 8 8 2 ICLK
0008 73AAh ICU Interrupt Source Priority Register 170 IPR170 8 8 2 ICLK
0008 73ABh ICU Interrupt Source Priority Register 171 IPR171 8 8 2 ICLK
0008 73DAh ICU Interrupt Source Priority Register 218 IPR218 8 8 2 ICLK
0008 73DEh ICU Interrupt Source Priority Register 222 IPR222 8 8 2 ICLK
0008 73EEh ICU Interrupt Source Priority Register 238 IPR238 8 8 2 ICLK
0008 73F2h ICU Interrupt Source Priority Register 242 IPR242 8 8 2 ICLK
0008 73F3h ICU Interrupt Source Priority Register 243 IPR243 8 8 2 ICLK
0008 73F4h ICU Interrupt Source Priority Register 244 IPR244 8 8 2 ICLK
0008 73F5h ICU Interrupt Source Priority Register 245 IPR245 8 8 2 ICLK
0008 73F6h ICU Interrupt Source Priority Register 246 IPR246 8 8 2 ICLK
0008 73F7h ICU Interrupt Source Priority Register 247 IPR247 8 8 2 ICLK
0008 73F8h ICU Interrupt Source Priority Register 248 IPR248 8 8 2 ICLK
0008 73F9h ICU Interrupt Source Priority Register 249 IPR249 8 8 2 ICLK
0008 7500h ICU IRQ Control Register 0 IRQCR0 8 8 2 ICLK
0008 7501h ICU IRQ Control Register 1 IRQCR1 8 8 2 ICLK
0008 7502h ICU IRQ Control Register 2 IRQCR2 8 8 2 ICLK
0008 7503h ICU IRQ Control Register 3 IRQCR3 8 8 2 ICLK
0008 7504h ICU IRQ Control Register 4 IRQCR4 8 8 2 ICLK
0008 7505h ICU IRQ Control Register 5 IRQCR5 8 8 2 ICLK
0008 7506h ICU IRQ Control Register 6 IRQCR6 8 8 2 ICLK
0008 7507h ICU IRQ Control Register 7 IRQCR7 8 8 2 ICLK
0008 7510h ICU IRQ Pin Digital Filter Enable Register 0 IRQFLTE0 8 8 2 ICLK
0008 7514h ICU IRQ Pin Digital Filter Setting Register 0 IRQFLTC0 16 16 2 ICLK
0008 7580h ICU Non-Maskable Interrupt Status Register NMISR 8 8 2 ICLK
0008 7581h ICU Non-Maskable Interrupt Enable Register NMIER 8 8 2 ICLK
0008 7582h ICU Non-Maskable Interrupt Status Clear Register NMICLR 8 8 2 ICLK
0008 7583h ICU NMI Pin Interrupt Control Regis ter NMICR 8 8 2 ICLK
Table 4.1 List of I/O Registers (Address Order) (5/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 38 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 7590h ICU NMI Pin Digital Filter Enable Register NMIFLTE 8 8 2 ICLK
0008 7594h ICU NMI Pin Digital Filter Setting Register NMIFLTC 8 8 2 ICLK
0008 8000h CMT Com pare Match Timer Start Registe r 0 CMSTR0 16 16 2 or 3 PCLKB
0008 8002h CMT0 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB
0008 8004h CMT0 Compare Match Timer Counter CMCNT 16 16 2 or 3 PCLKB
0008 8006h CMT0 Compare Match Timer Constant Register CMCOR 16 16 2 or 3 PCLKB
0008 8008h CMT1 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB
0008 800Ah CMT1 Compare Match Timer Counter CMCNT 16 16 2 or 3 PCLKB
0008 800Ch CMT1 Compare Match Timer Constant Register CMCOR 16 16 2 or 3 PCLKB
0008 8030h IWDT IWDT Refresh Register IWDTRR 8 8 2 or 3 PCLKB
0008 8032h IWDT IWDT Control Register IWDTCR 16 16 2 or 3 PCLKB
0008 8034h IWDT IWDT Status Register IWDTSR 16 16 2 or 3 PCLKB
0008 8036h IWDT IWDT Reset Control Register IWDTRCR 8 8 2 or 3 PCLKB
0008 8038h IWDT IWDT Count Stop Control Register IWDTCSTPR 8 8 2 or 3 PCLKB
0008 80C0h DA D/A Data Register 0 DADR0 16 16 2 or 3 PCLKB
0008 80C2h DA D/A Data Register 1 DADR1 16 16 2 or 3 PCLKB
0008 80C4h DA D/A Control Register DACR 8 8 2 or 3 PCLKB
0008 80C5h DA DADRm Format Select Register DADPR 8 8 2 or 3 PCLKB
0008 8280h CRC CRC Control Register CRCCR 8 8 2 or 3 PCLKB
0008 8281h CRC CRC Data Input Register CRCDIR 8 8 2 or 3 PCLKB
0008 8282h CRC CRC Data Output Register CRCDOR 16 16 2 or 3 PCLKB
0008 8300h RIIC0 I2C Bus Control Register 1 ICCR1 8 8 2 or 3 PCLKB
0008 8301h RIIC0 I2C Bus Control Register 2 ICCR2 8 8 2 or 3 PCLKB
0008 8302h RIIC0 I2C Bus Mode Register 1 ICMR1 8 8 2 or 3 PCLKB
0008 8303h RIIC0 I2C Bus Mode Register 2 ICMR2 8 8 2 or 3 PCLKB
0008 8304h RIIC0 I2C Bus Mode Register 3 ICMR3 8 8 2 or 3 PCLKB
0008 8305h RIIC0 I2C Bus Function Enable Register ICFER 8 8 2 or 3 PCLKB
0008 8306h RIIC0 I2C Bus Status Enable Register ICSER 8 8 2 or 3 PCLKB
0008 8307h RIIC0 I2C Bus Interrupt Enable Register ICIER 8 8 2 or 3 PCLKB
0008 8308h RIIC0 I2C Bus Status Register 1 ICSR1 8 8 2 or 3 PCLKB
0008 8309h RIIC0 I2C Bus Status Register 2 ICSR2 8 8 2 or 3 PCLKB
0008 830A h RIIC0 Slave Address Register L0 SARL0 8 8 2 or 3 PCLKB
0008 830Ah RIIC0 Timeout Internal Counter L TMOCNTL 8 8 2 or 3 PCLKB
0008 830B h RIIC0 Slave Address Registe r U0 SARU0 8 8 2 or 3 PCLKB
0008 830Bh RIIC0 Timeout Internal Counter U TMOCNTU 8 8 *12 or 3 PCLKB
0008 830Ch RIIC0 Slave Address Register L1 SARL1 8 8 2 or 3 PCLKB
0008 830Dh RIIC0 Slave Address Register U1 SARU1 8 8 2 or 3 PCLKB
0008 830E h RIIC0 Slave Address Register L2 SARL2 8 8 2 or 3 PCLKB
0008 830Fh RIIC0 Slave Address Register U2 SARU2 8 8 2 or 3 PCLKB
0008 8310h RIIC0 I2C Bus Bit Rate Low-Level Regi ster ICBRL 8 8 2 or 3 PCLKB
0008 8311h RIIC0 I2C Bus Bit Rate High-Level Register ICBRH 8 8 2 or 3 PCLKB
0008 8312h RIIC0 I2C Bus Transmit Data Register ICDRT 8 8 2 or 3 PCLKB
0008 8313h RIIC0 I2C Bus Re ceive Data Register ICDRR 8 8 2 or 3 PCLKB
0008 8380h RSPI0 RSPI Control Register SPCR 8 8 2 or 3 PCLKB
0008 8381h RSPI0 RSPI Slave Select Polarity Register SSLP 8 8 2 or 3 PCLKB
0008 8382h RSPI0 RSPI Pin Control Register SPPCR 8 8 2 or 3 PCLKB
0008 8383h RSPI0 RSPI Status Register SPSR 8 8 2 or 3 PCLKB
0008 8384h RSPI0 RSPI Data Register SPDR 32 16, 32 2 or 3 PCLKB
0008 8388h RSPI0 RSPI Sequence Control Register SPSCR 8 8 2 or 3 PCLKB
0008 8389h RSPI0 RSPI Sequence Status Register SPSSR 8 8 2 or 3 PCLKB
0008 838Ah RSPI0 RSPI Bit Rate Register SPBR 8 8 2 or 3 PCLKB
0008 838Bh RSPI0 RSPI Data Control Register SPDCR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (6/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 39 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 838Ch RSPI0 RSPI Clock Delay Register SPCKD 8 8 2 or 3 PCLKB
0008 838Dh RSPI0 RSPI Slave Select Negation Delay Register SSLND 8 8 2 or 3 PCLKB
0008 838Eh RSPI0 RSPI Next-Access Delay Register SPND 8 8 2 or 3 PCLKB
0008 838Fh RSPI0 RSPI Control Register 2 SPCR2 8 8 2 or 3 PCLKB
0008 8390h RSPI0 RSPI Command Register 0 SPCMD0 16 16 2 or 3 PCLKB
0008 8392h RSPI0 RSPI Command Register 1 SPCMD1 16 16 2 or 3 PCLKB
0008 8394h RSPI0 RSPI Command Register 2 SPCMD2 16 16 2 or 3 PCLKB
0008 8396h RSPI0 RSPI Command Register 3 SPCMD3 16 16 2 or 3 PCLKB
0008 8398h RSPI0 RSPI Command Register 4 SPCMD4 16 16 2 or 3 PCLKB
0008 839Ah RSPI0 RSPI Command Register 5 SPCMD5 16 16 2 or 3 PCLKB
0008 839Ch RSPI0 RSPI Command Register 6 SPCMD6 16 16 2 or 3 PCLKB
0008 839Eh RSPI0 RSPI Command Register 7 SPCMD7 16 16 2 or 3 PCLKB
0008 8600h MTU3 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8601h MTU4 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8602h MTU3 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8603h MTU4 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8604h MTU3 Timer I/O Control Register H TIORH 8 8 2 or 3 PCLKB
0008 8605h MTU3 Timer I/O Control Register L TIORL 8 8 2 or 3 PCLKB
0008 8606h MTU4 Timer I/O Control Register H TIORH 8 8 2 or 3 PCLKB
0008 8607h MTU4 Timer I/O Control Register L TIORL 8 8 2 or 3 PCLKB
0008 8608h MTU3 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8609h MTU4 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 860Ah MTU Timer Output Master Enable Register TOER 8 8 2 or 3 PCLKB
0008 860Dh MTU Timer Gate Control Register TGCR 8 8 2 or 3 PCLKB
0008 860Eh MTU Timer Output Control Register 1 TOCR1 8 8 2 or 3 PCLKB
0008 860Fh MTU Timer Output Control Register 2 TOCR2 8 8 2 or 3 PCLKB
0008 8610h MTU3 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8612h MTU4 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8614h MTU Timer Cycle Data Register TCDR 16 16 2 or 3 PCLKB
0008 8616h MTU Timer Dead Time Data Register TDDR 16 16 2 or 3 PCLKB
0008 8618h MTU3 Timer General Register A TGRA 16 16 2 or 3 PCLKB
0008 861Ah MTU3 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 861Ch MTU4 Timer General Register A TGRA 16 16 2 or 3 PCLKB
0008 861Eh MTU4 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 8620h MTU Timer Subcounter TCNTS 16 16 2 or 3 PCLKB
0008 8622h MTU Timer Cycle Buffer Register TCBR 16 16 2 or 3 PCLKB
0008 8624h MTU3 Timer General Register C TGRC 16 16 2 or 3 PCLKB
0008 8626h MTU3 Timer General Register D TGRD 16 16 2 or 3 PCLKB
0008 8628h MTU4 Timer General Register C TGRC 16 16 2 or 3 PCLKB
0008 862Ah MTU4 Timer General Register D TGRD 16 16 2 or 3 PCLKB
0008 862Ch MTU3 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 862Dh MTU4 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8630h MTU Timer Interrupt Skipping Set Register TITCR 8 8 2 or 3 PCLKB
0008 8631h MTU Timer Interrupt Skipping Counter TITCNT 8 8 2 or 3 PCLKB
0008 8632h MTU Timer Buffer Transfer Set Register TBTER 8 8 2 or 3 PCLKB
0008 8634h MTU Timer Dead Time Enable Register TDER 8 8 2 or 3 PCLKB
0008 8636h MTU Timer Output Level Buffer Regi ster TOLBR 8 8 2 or 3 PCL KB
0008 8638h MTU3 Timer Buffer Operation Transfer Mode Register TBTM 8 8 2 or 3 PCLKB
0008 8639h MTU4 Timer Buffer Operation Transfer Mode Register TBTM 8 8 2 or 3 PCLKB
0008 8640h MTU4 Timer A/D Converter Start Request Control Register TADCR 16 16 2 or 3 PCLKB
0008 8644h MTU4 Timer A/D Converter Start Request Cycle Set Register A TADCORA 16 16 2 or 3 PCLKB
0008 8646h MTU4 Timer A/D Converter Start Request Cycle Set Register B TADCORB 16 16 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (7/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 40 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 8648h MTU4 Timer A/D Converter Start Request Cycle Set Buffer Register A TADCOBRA 16 16 2 or 3 PCLKB
0008 864Ah MTU4 Timer A/D Converter Start Request Cycle Set Buffer Register B TADCOBRB 16 16 2 or 3 PCLKB
0008 8660h MTU Timer Waveform Control Register TWCR 8 8, 16 2 or 3 PCLKB
0008 8680h MTU Timer Start Register TSTR 8 8, 16 2 or 3 PCLKB
0008 8681h MTU Timer Synchronous Register TSYR 8 8, 16 2 or 3 PCLKB
0008 8684h MTU Timer Read/Write Enable Register TRWER 8 8, 16 2 or 3 PCLKB
0008 8690h MTU0 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8691h MTU1 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8692h MTU2 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8693h MTU3 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8694h MTU4 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8695h MTU5 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB
0008 8700h MTU0 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8701h MTU0 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8702h MTU0 Timer I/O Control Register H TIORH 8 8 2 or 3 PCLKB
0008 8703h MTU0 Timer I/O Control Register L TIORL 8 8 2 or 3 PCLKB
0008 8704h MTU0 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8705h MTU0 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8706h MTU0 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8708h MTU0 Timer General Register A TGRA 16 16 2 or 3 PCLKB
0008 870Ah MTU0 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 870Ch MTU0 Timer General Register C TGRC 16 16 2 or 3 PCLKB
0008 870Eh MTU0 Timer General Register D TGRD 16 16 2 or 3 PCLKB
0008 8720h MTU0 Timer General Register E TGRE 16 16 2 or 3 PCLKB
0008 8722h MTU0 Timer General Register F TGRF 16 16 2 or 3 PCLKB
0008 8724h MTU0 Timer Interrupt Enable Register 2 TIER2 8 8 2 or 3 PCLKB
0008 8726h MTU0 Timer Buffer Operation Transfer Mode Register TBTM 8 8 2 or 3 PCLKB
0008 8780h MTU1 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8781h MTU1 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8782h MTU1 Timer I/O Control Register TIOR 8 8 2 or 3 PCLKB
0008 8784h MTU1 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8785h MTU1 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8786h MTU1 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8788h MTU1 Timer General Register A TGRA 16 16 2 or 3 PCLKB
0008 878Ah MTU1 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 8790h MTU1 Timer Input Capture Control Register TICCR 8 8 2 or 3 PCLKB
0008 8800h MTU2 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 8801h MTU2 Timer Mode Register TMDR 8 8 2 or 3 PCLKB
0008 8802h MTU2 Timer I/O Control Register TIOR 8 8 2 or 3 PCLKB
0008 8804h MTU2 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 8805h MTU2 Timer Status Register TSR 8 8 2 or 3 PCLKB
0008 8806h MTU2 Timer Counter TCNT 16 16 2 or 3 PCLKB
0008 8808h MTU2 Timer General Register A TGRA 16 16 2 or 3 PCLKB
0008 880Ah MTU2 Timer General Register B TGRB 16 16 2 or 3 PCLKB
0008 8880h MTU5 Timer Counter U TCNTU 16 16 2 or 3 PCLKB
0008 8882h MTU5 Timer General Register U TGRU 16 16 2 or 3 PCLKB
0008 8884h MTU5 Timer Control Register U TCRU 8 8 2 or 3 PCLKB
0008 8886h MTU5 Timer I/O Control Register U TIORU 8 8 2 or 3 PCLKB
0008 8890h MTU5 Timer Counter V TCNTV 16 16 2 or 3 PCLKB
0008 8892h MTU5 Timer General Register V TGRV 16 16 2 or 3 PCLKB
0008 8894h MTU5 Timer Control Register V TCRV 8 8 2 or 3 PCLKB
0008 8896h MTU5 Timer I/O Control Register V TIORV 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (8/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 41 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 88A0h MTU5 Timer Counter W TCNTW 16 16 2 or 3 PCLKB
0008 88A2h MTU5 Timer General Register W TGRW 16 16 2 or 3 PCLKB
0008 88A4h MTU5 Timer Control Register W TCRW 8 8 2 or 3 PCLKB
0008 88A6h MTU5 Timer I/O Control Register W TIORW 8 8 2 or 3 PCLKB
0008 88B2h MTU5 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB
0008 88B4h MTU5 Timer Start Register TSTR 8 8 2 or 3 PCLKB
0008 88B6h MTU5 Timer Compare Match Clear Register TCNTCMPCLR 8 8 2 or 3 PCLKB
0008 8900h POE Input Level Control/Status Register 1 ICSR1 16 8, 16 2 or 3 PCLKB
0008 8902h POE Output Level Control/Status Register 1 O CSR1 16 8, 16 2 or 3 PCLKB
0008 8908h POE Input Level Control/Status Register 2 ICSR2 16 8, 16 2 or 3 PCLKB
0008 890Ah POE Software Port Outp ut Ena ble R egister SPOER 8 8 2 or 3 PCLKB
0008 890Bh POE Port Output Enable Control Register 1 POECR1 8 8 2 or 3 PCLKB
0008 890Ch POE Port Output Enable Control Register 2 POECR2 8 8 2 or 3 PCLKB
0008 890Eh POE Input Level Control/Status Register 3 ICSR3 16 8, 16 2 or 3 PCLKB
0008 9000h S12AD A/D Control Register ADCSR 16 16 2 or 3 PCLKB
0008 9004h S12AD A/D Channel Select Register A ADANSA 16 16 2 or 3 PCLKB
0008 9008h S12AD A/D-Converted Value Addition Mode Select Registe r ADADS 16 16 2 or 3 PCLKB
0008 900Ch S12AD A/D-Converted Value Addition Count Select R egiste r ADADC 8 8 2 or 3 PCLKB
0008 900Eh S12AD A/D Control Extended Register ADCER 16 16 2 or 3 PCLKB
0008 9010h S12AD A/D Start Trigger Select Register ADSTRGR 16 16 2 or 3 PCLKB
0008 9012h S12AD A/D Converted Extended Input Control Register ADEXICR 16 16 2 or 3 PCLKB
0008 9014h S12AD A/D Channel Select Register B ADANSB 16 16 2 or 3 PCLKB
0008 9018h S12AD A/D Data Duplication Register ADDBLDR 16 16 2 or 3 PCLKB
0008 901Ah S12AD A/D Temperature Sensor Data Register ADTSDR 16 16 2 or 3 PCLKB
0008 901Ch S12AD A/D Internal Reference Voltage Data Register ADOCDR 16 16 2 or 3 PCLKB
0008 9020h S12AD A/D Data Register 0 ADDR0 16 16 2 or 3 PCLKB
0008 9022h S12AD A/D Data Register 1 ADDR1 16 16 2 or 3 PCLKB
0008 9024h S12AD A/D Data Register 2 ADDR2 16 16 2 or 3 PCLKB
0008 9026h S12AD A/D Data Register 3 ADDR3 16 16 2 or 3 PCLKB
0008 9028h S12AD A/D Data Register 4 ADDR4 16 16 2 or 3 PCLKB
0008 902Ch S12AD A/D Data Register 6 A DDR6 16 16 2 or 3 PCLKB
0008 9030h S12AD A/D Data Register 8 ADDR8 16 16 2 or 3 PCLKB
0008 9032h S12AD A/D Data Register 9 ADDR9 16 16 2 or 3 PCLKB
0008 9034h S12AD A/D Data Register 10 ADDR10 16 16 2 or 3 PCLKB
0008 9036h S12AD A/D Data Register 11 ADDR11 16 16 2 or 3 PCLKB
0008 9038h S12AD A/D Data Register 12 ADDR12 16 16 2 or 3 PCLKB
0008 903Ah S12AD A/D Data Register 13 ADDR13 16 16 2 or 3 PCLKB
0008 903Ch S12AD A/D Data Register 14 ADDR14 16 16 2 or 3 PCLKB
0008 903Eh S12AD A/D Data Register 15 ADDR15 16 16 2 or 3 PCLKB
0008 9060h S12AD A/D Sampling State Register 0 ADSSTR0 8 8 2 or 3 PCLKB
0008 9061h S12AD A/D Sampling State Register L ADSSTRL 8 8 2 or 3 PCLKB
0008 9070h S12AD A/D Sampling State Register T ADSSTRT 8 8 2 or 3 PCLKB
0008 9071h S12AD A/D Sampling State Register O ADSSTRO 8 8 2 or 3 PCLKB
0008 9073h S12AD A/D Sampling State Register 1 ADSSTR1 8 8 2 or 3 PCLKB
0008 9074h S12AD A/D Sampling State Register 2 ADSSTR2 8 8 2 or 3 PCLKB
0008 9075h S12AD A/D Sampling State Register 3 ADSSTR3 8 8 2 or 3 PCLKB
0008 9076h S12AD A/D Sampling State Register 4 ADSSTR4 8 8 2 or 3 PCLKB
0008 9078h S12AD A/D Sampling State Register 6 ADSSTR6 8 8 2 or 3 PCLKB
0008 A020h SCI1 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A021h SCI1 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A022h SCI1 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 A023h SCI1 Transmit Data Register TDR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (9/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 42 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 A024h SCI1 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A025h SCI1 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A026h SCI1 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A027h SCI1 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A028h SCI1 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A029h SCI1 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A02Ah SCI1 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB
0008 A02Bh SCI1 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB
0008 A02Ch SCI1 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A02Dh SCI1 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 A0A0h SCI5 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 A0A1h SCI5 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 A0A2h SCI5 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 A0A3h SCI5 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 A0A4h SCI5 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 A0A5h SCI5 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 A0A6h SCI5 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 A0A7h SCI5 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 A0A8h SCI5 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 A0A9h SCI5 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 A0AAh SCI5 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB
0008 A0ABh SCI5 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB
0008 A0ACh SCI5 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 A0ADh SCI5 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 B000h CAC CAC Contro l Register 0 CACR0 8 8 2 or 3 PCLKB
0008 B001h CAC CAC Contro l Register 1 CACR1 8 8 2 or 3 PCLKB
0008 B002h CAC CAC Contro l Register 2 CACR2 8 8 2 or 3 PCLKB
0008 B003h CAC CAC Interrupt Co ntr o l Re gi ste r CAICR 8 8 2 or 3 PCLKB
0008 B004h CAC CAC Status Register CASTR 8 8 2 or 3 PCLKB
0008 B006h CAC CAC Upper-Limit Value Setting Register CAULVR 16 16 2 or 3 PCLKB
0008 B008h CAC CAC Lower-Limit Value Setting Register CALLVR 16 16 2 or 3 PCLKB
0008 B00Ah CAC CAC Counter Buffer Register CACNTBR 16 16 2 or 3 PCLKB
0008 B080h DOC DOC Control Register DOCR 8 8 2 or 3 PCLKB
0008 B082h DOC DOC Data Input Register DODIR 16 16 2 or 3 PCLKB
0008 B084h DOC DOC Data Setting Register DODSR 16 16 2 or 3 PCLKB
0008 B100h ELC Event Link Control Register ELCR 8 8 2 or 3 PCLKB
0008 B102h ELC Event Link Setting Register 1 ELSR1 8 8 2 or 3 PCLKB
0008 B103h ELC Event Link Setting Register 2 ELSR2 8 8 2 or 3 PCLKB
0008 B104h ELC Event Link Setting Register 3 ELSR3 8 8 2 or 3 PCLKB
0008 B105h ELC Event Link Setting Register 4 ELSR4 8 8 2 or 3 PCLKB
0008 B108h ELC Event Link Setting Register 7 ELSR7 8 8 2 or 3 PCLKB
0008 B110h ELC Event Link Setting Register 15 ELSR15 8 8 2 or 3 PCLKB
0008 B111h ELC Event Link Setting Register 16 ELSR16 8 8 2 or 3 PCLKB
0008 B113h ELC Event Link Setting Register 18 ELSR18 8 8 2 or 3 PCLKB
0008 B115h ELC Event Link Setting Register 20 ELSR20 8 8 2 or 3 PCLKB
0008 B117h ELC Event Link Setting Register 22 ELSR22 8 8 2 or 3 PCLKB
0008 B119h ELC Event Link Setting Register 24 ELSR24 8 8 2 or 3 PCLKB
0008 B11Ah ELC Event Link Setting Register 25 ELSR25 8 8 2 or 3 PCLKB
0008 B11Fh ELC Event Link Option Setting Register A ELOPA 8 8 2 or 3 PCLKB
0008 B120h ELC Event Link Option Setting Register B ELOPB 8 8 2 or 3 PCLKB
0008 B121h ELC Event Link Option Setting Register C ELOPC 8 8 2 or 3 PCLKB
0008 B123h ELC Port Group Setting Register 1 PGR1 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (10/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 43 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 B125h ELC Port Group Control Register 1 PGC1 8 8 2 or 3 PCLKB
0008 B127h ELC Port Buffer Register 1 PDBF1 8 8 2 or 3 PCLKB
0008 B129h ELC Event Link Port Setting Register 0 PEL0 8 8 2 or 3 PCLKB
0008 B12Ah ELC Event Link Port Setting Register 1 PEL1 8 8 2 or 3 PCLKB
0008 B12Dh ELC Event Link Software Event Generation Register ELSEGR 8 8 2 or 3 PCLKB
0008 B300h SCI12 Serial Mode Register SMR 8 8 2 or 3 PCLKB
0008 B301h SCI12 Bit Rate Register BRR 8 8 2 or 3 PCLKB
0008 B302h SCI12 Serial Control Register SCR 8 8 2 or 3 PCLKB
0008 B303h SCI12 Transmit Data Register TDR 8 8 2 or 3 PCLKB
0008 B304h SCI12 Serial Status Register SSR 8 8 2 or 3 PCLKB
0008 B305h SCI12 Receive Data Register RDR 8 8 2 or 3 PCLKB
0008 B306h SCI12 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB
0008 B307h SCI12 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB
0008 B308h SCI12 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB
0008 B309h SCI12 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB
0008 B30Ah SCI12 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB
0008 B30Bh SCI12 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB
0008 B30Ch SCI12 I2C Status Register SISR 8 8 2 or 3 PCLKB
0008 B30Dh SCI12 SPI Mode Register SPMR 8 8 2 or 3 PCLKB
0008 B320h SCI12 Extended Serial Mode Enable Register ESMER 8 8 2 or 3 PCLKB
0008 B321h SCI12 Control Register 0 CR0 8 8 2 or 3 PCLKB
0008 B322h SCI12 Control Register 1 CR1 8 8 2 or 3 PCLKB
0008 B323h SCI12 Control Register 2 CR2 8 8 2 or 3 PCLKB
0008 B324h SCI12 Control Register 3 CR3 8 8 2 or 3 PCLKB
0008 B325h SCI12 Port Control Register PCR 8 8 2 or 3 PCLKB
0008 B326h SCI12 Interrupt Control Register ICR 8 8 2 or 3 PCLKB
0008 B327h SCI12 Status Register STR 8 8 2 or 3 PCLKB
0008 B328h SCI12 Status Clear Register STCR 8 8 2 or 3 PCLKB
0008 B329h SCI12 Control Field 0 Data Register CF0DR 8 8 2 or 3 PCLKB
0008 B32Ah SCI12 Control Field 0 Compare Enable Register CF0CR 8 8 2 or 3 PCLKB
0008 B32Bh SCI12 Control Field 0 Receive Data Register CF0RR 8 8 2 or 3 PCLKB
0008 B32Ch SCI12 Primary Control Field 1 Data Register PCF1DR 8 8 2 or 3 PCLKB
0008 B32Dh SCI12 Secondary Control Field 1 Data Register SCF1DR 8 8 2 or 3 PCLKB
0008 B32Eh SCI12 Control Field 1 Compare Enable Register CF1CR 8 8 2 or 3 PCLKB
0008 B32Fh SCI12 Control Field 1 Receive Data Register CF1RR 8 8 2 or 3 PCLKB
0008 B330h SCI12 Timer Control Register TCR 8 8 2 or 3 PCLKB
0008 B331h SCI12 Timer Mode Register TMR 8 8 2 or 3 PCLKB
0008 B332h SCI12 Timer Prescaler Register TPRE 8 8 2 or 3 PCLKB
0008 B333h SCI12 Timer Count Register TCNT 8 8 2 or 3 PCLKB
0008 C000h PORT0 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C001h PORT1 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C002h PORT2 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C003h PORT3 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C004h PORT4 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C005h PORT5 Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Ah PORTA Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Bh PORTB Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Ch PORTC Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C00Eh PORTE Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C012h PORTJ Port Direction Register PDR 8 8 2 or 3 PCLKB
0008 C020h PORT0 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C021h PORT1 Port Output Data Register PODR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (11/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 44 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 C022h PORT2 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C023h PORT3 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C024h PORT4 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C025h PORT5 Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Ah PORTA Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Bh PORTB Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Ch PORTC Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C02Eh PORTE Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C032h PORTJ Port Output Data Register PODR 8 8 2 or 3 PCLKB
0008 C040h PORT0 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C041h PORT1 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C042h PORT2 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C043h PORT3 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C044h PORT4 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C045h PORT5 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C04Ah PORTA P ort Input Dat a Registe r PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C04Bh PORTB Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C04Ch PORTC Port Input Data Registe r PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C04Eh PORTE Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C051h PORTH Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C052h PORTJ Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles
when read ing,
2 or 3 PCLKB cycles
when writing
0008 C060h PORT0 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C061h PORT1 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C062h PORT2 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C063h PORT3 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C064h PORT4 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C065h PORT5 Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Ah PORTA Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Bh PORTB Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Ch PORTC Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C06Eh PORTE Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C071h PORTH Port Mode Register PMR 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (12/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 45 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 C072h PORTJ Port Mode Register PMR 8 8 2 or 3 PCLKB
0008 C083h PORT1 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C085h PORT2 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C086h PORT3 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C094h PORTA Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C095h PORTA Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C096h PORTB Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C097h PORTB Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C098h PORTC Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C099h PORTC Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C09Ch PORTE Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C09Dh PORTE Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB
0008 C0A2h PORTE Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB
0008 C0C0h PORT0 Pull-Up Control Register P CR 8 8 2 or 3 PCLKB
0008 C0C1h PORT1 Pull-Up Control Register P CR 8 8 2 or 3 PCLKB
0008 C0C2h PORT2 Pull-Up Control Register P CR 8 8 2 or 3 PCLKB
0008 C0C3h PORT3 Pull-Up Control Register P CR 8 8 2 or 3 PCLKB
0008 C0C5h PORT5 Pull-Up Control Register P CR 8 8 2 or 3 PCLKB
0008 C0CAh PORTA Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0CBh PORTB Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0CCh PORTC Pu ll-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C0CEh PORTE Pull-Up Control Register PCR 8 8 2 or 3 PCLKB
0008 C11Fh MPC Write-Protect Register PWPR 8 8 2 or 3 PCLKB
0008 C120h PORT Port Switching Register B PSRB 8 8 2 or 3 PCLKB
0008 C121h PORT Port Switching Register A PSRA 8 8 2 or 3 PCLKB
0008 C143h MPC P03 Pin Function Control Register P03PFS 8 8 2 or 3 PCLKB
0008 C145h MPC P05 Pin Function Control Register P05PFS 8 8 2 or 3 PCLKB
0008 C14Ch MPC P14 Pin Function Control Register P14PFS 8 8 2 or 3 PCLKB
0008 C14Dh MPC P15 Pin Function Control Register P15PFS 8 8 2 or 3 PCLKB
0008 C14Eh MPC P16 Pin Function Control Register P16PFS 8 8 2 or 3 PCLKB
0008 C14Fh M PC P17 Pin Function Control Register P17PFS 8 8 2 or 3 PCLKB
0008 C156h MPC P26 Pin Function Control Register P26PFS 8 8 2 or 3 PCLKB
0008 C157h MPC P27 Pin Function Control Register P27PFS 8 8 2 or 3 PCLKB
0008 C158h MPC P30 Pin Function Control Register P30PFS 8 8 2 or 3 PCLKB
0008 C159h MPC P31 Pin Function Control Register P31PFS 8 8 2 or 3 PCLKB
0008 C15Ah MPC P32 Pin Function Control Register P32PFS 8 8 2 or 3 PCLKB
0008 C15Dh MPC P35 Pin Function Control Register P35PFS 8 8 2 or 3 PCLKB
0008 C160h MPC P40 Pin Function Control Register P40PFS 8 8 2 or 3 PCLKB
0008 C161h MPC P41 Pin Function Control Register P41PFS 8 8 2 or 3 PCLKB
0008 C162h MPC P42 Pin Function Control Register P42PFS 8 8 2 or 3 PCLKB
0008 C163h MPC P43 Pin Function Control Register P43PFS 8 8 2 or 3 PCLKB
0008 C164h MPC P44 Pin Function Control Register P44PFS 8 8 2 or 3 PCLKB
0008 C166h MPC P46 Pin Function Control Register P46PFS 8 8 2 or 3 PCLKB
0008 C16Ch MPC P54 Pin Function Control Register P54PFS 8 8 2 or 3 PCLKB
0008 C16Dh MPC P55 Pin Function Control Register P55PFS 8 8 2 or 3 PCLKB
0008 C190h MPC PA0 Pin Function Control Register PA0PFS 8 8 2 or 3 PCLKB
0008 C191h MPC PA1 Pin Function Control Register PA1PFS 8 8 2 or 3 PCLKB
0008 C193h MPC PA3 Pin Function Control Register PA3PFS 8 8 2 or 3 PCLKB
0008 C194h MPC PA4 Pin Function Control Register PA4PFS 8 8 2 or 3 PCLKB
0008 C196h MPC PA6 Pin Function Control Register PA6PFS 8 8 2 or 3 PCLKB
0008 C198h MPC PB0 Pin Function Control Register PB0PFS 8 8 2 or 3 PCLKB
0008 C199h MPC PB1 Pin Function Control Register PB1PFS 8 8 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (13/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 46 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 C19Bh MPC PB3 Pin Function Control Register PB3PFS 8 8 2 or 3 PCLKB
0008 C19Dh MPC PB5 Pin Function Control Register PB5PFS 8 8 2 or 3 PCLKB
0008 C19Eh MPC PB6 Pin Function Control Register PB6PFS 8 8 2 or 3 PCLKB
0008 C19Fh M PC PB7 Pin Function Control Register PB7PFS 8 8 2 or 3 PCLKB
0008 C1A2h MPC PC2 Pin Function Control Register PC2PFS 8 8 2 or 3 PCLKB
0008 C1A3h MPC PC3 Pin Function Control Register PC3PFS 8 8 2 or 3 PCLKB
0008 C1A4h MPC PC4 Pin Function Control Register PC4PFS 8 8 2 or 3 PCLKB
0008 C1A5h MPC PC5 Pin Function Control Register PC5PFS 8 8 2 or 3 PCLKB
0008 C1A6h MPC PC6 Pin Function Control Register PC6PFS 8 8 2 or 3 PCLKB
0008 C1A7h MPC PC7 Pin Function Control Register PC7PFS 8 8 2 or 3 PCLKB
0008 C1B0h MPC PE0 Pin Function Control Register PE0PFS 8 8 2 or 3 PCLKB
0008 C1B1h MPC PE1 Pin Function Control Register PE1PFS 8 8 2 or 3 PCLKB
0008 C1B2h MPC PE2 Pin Function Control Register PE2PFS 8 8 2 or 3 PCLKB
0008 C1B3h MPC PE3 Pin Function Control Register PE3PFS 8 8 2 or 3 PCLKB
0008 C1B4h MPC PE4 Pin Function Control Register PE4PFS 8 8 2 or 3 PCLKB
0008 C1B5h MPC PE5 Pin Function Control Register PE5PFS 8 8 2 or 3 PCLKB
0008 C1B6h MPC PE6 Pin Function Control Register PE6PFS 8 8 2 or 3 PCLKB
0008 C1B7h MPC PE7 Pin Function Control Register PE7PFS 8 8 2 or 3 PCLKB
0008 C1D6h MPC PJ6 Pin Function Control Register PJ6PFS 8 8 2 or 3 PCLKB
0008 C1D7h MPC PJ7 Pin Function Control Register PJ7PFS 8 8 2 or 3 PCLKB
0008 C290h SYSTEM Reset Status Register 0 RSTSR0 8 8 4 or 5 PCLKB
0008 C291h SYSTEM Reset Status Register 1 RSTSR1 8 8 4 or 5 PCLKB
0008 C293h SYSTEM Main Clock Oscillator Forced Oscillation Control Register MOFCR 8 8 4 or 5 PCLKB
0008 C297h SYSTEM Voltage Monitoring Circuit Control Register LVCMPCR 8 8 4 or 5 PCLKB
0008 C298h SYSTEM Voltage Detection Level Select Register LVDLVLR 8 8 4 or 5 PCLKB
0008 C29Ah SYSTEM Voltage Monitoring 1 Circuit Control Register 0 LVD1CR0 8 8 4 or 5 PCLKB
0008 C29Bh SYSTEM Voltage Monitoring 2 Circuit Control Register 0 LVD2CR0 8 8 4 or 5 PCLKB
0008 C400h RTC 64-Hz Counter R64CNT 8 8 2 or 3 PCLKB
0008 C402h RTC Second Counter RSECCNT 8 8 2 or 3 PCLKB
0008 C402h RTC Binary Counter 0 BCNT0 8 8 2 or 3 PCLKB
0008 C404h RTC Minute Counter RMINCNT 8 8 2 or 3 PCLKB
0008 C404h RTC Binary Counter 1 BCNT1 8 8 2 or 3 PCLKB
0008 C406h RTC Hour Counter RHRCNT 8 8 2 or 3 PCLKB
0008 C406h RTC Binary Counter 2 BCNT2 8 8 2 or 3 PCLKB
0008 C408h RTC Day-Of-Week Counter RWKCNT 8 8 2 or 3 PCLKB
0008 C408h RTC Binary Counter 3 BCNT3 8 8 2 or 3 PCLKB
0008 C40Ah RTC Date Counter RDAYCNT 8 8 2 or 3 PCLKB
0008 C40Ch RTC Month Counter RMONCNT 8 8 2 or 3 PCLKB
0008 C40Eh RTC Year Counter RYRCNT 16 16 2 or 3 PCLKB
0008 C410h RTC Second Alarm Register RSECAR 8 8 2 or 3 PCLKB
0008 C410h RTC Binary Counter 0 Alarm Register BCNT0AR 8 8 2 or 3 PCLKB
0008 C412h RTC Minute Alarm Register RMINAR 8 8 2 or 3 PCLKB
0008 C412h RTC Binary Counter 1 Alarm Register BCNT1AR 8 8 2 or 3 PCLKB
0008 C414h RTC Hour Alarm Register RHRAR 8 8 2 or 3 PCLKB
0008 C414h RTC Binary Counter 2 Alarm Register BCNT2AR 8 8 2 or 3 PCLKB
0008 C416h RTC Day-of-Week Alarm Register RWKAR 8 8 2 or 3 PCLKB
0008 C416h RTC Binary Counter 3 Alarm Register BCNT3AR 8 8 2 or 3 PCLKB
0008 C418h RTC Date Alarm Register RDAYAR 8 8 2 or 3 PCLKB
0008 C418h RTC Binary Counter 0 Alarm Enable Register BCNT0AER 8 8 2 or 3 PCLKB
0008 C41Ah RTC Month Alarm Register RMONAR 8 8 2 or 3 PCLKB
0008 C41Ah RTC Binary Counter 1 Alarm Enable Register BCNT1AER 8 8 2 or 3 PCLKB
0008 C41Ch RTC Year Alarm Register RYRAR 16 16 2 or 3 PCLKB
Table 4.1 List of I/O Registers (Address Order) (14/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 47 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
0008 C41Ch RTC Binary Counter 2 Alarm Enable Register BCNT2AER 16 16 2 or 3 PCLKB
0008 C41Eh RTC Year Alarm Enable Register RYRAREN 8 8 2 or 3 PCLKB
0008 C41Eh RTC Binary Counter 3 Alarm Enable Register BCNT3AER 8 8 2 or 3 PCLKB
0008 C422h RTC RTC Control Register 1 RCR1 8 8 2 or 3 PCLKB
0008 C424h RTC RTC Control Register 2 RCR2 8 8 2 or 3 PCLKB
0008 C426h RTC RTC Control Register 3 RCR3 8 8 2 or 3 PCLKB
0008 C42Eh RTC Time Error Adjustment Register RADJ 8 8 2 or 3 PCLKB
000A 0000h USB0 System Configuration Control Register SYSCFG 16 16 3 or 4 PCLKB
000A 0004 h USB0 Sys tem Configuration Status Register 0 SYSSTS0 16 16 9 PCLK or more
000A 0008 h USB0 Dev ice State Control Register 0 DVSTCTR0 16 16 9 PCLK or more
000A 0014h USB0 CFIFO Port Register CFIFO 16 16 3 or 4 PCLKB
000A 0018h USB0 D0FIFO Port Register D0FIFO 16 16 3 or 4 PCLKB
000A 001Ch USB0 D1FIFO Port Register D1FIFO 16 16 3 or 4 PCLKB
000A 0020h USB0 CFIFO Port Select Register CFIFOSEL 16 16 3 or 4 PCLKB
000A 0028h USB0 D0FIFO Port Select Register D0FIFOSEL 16 16 3 or 4 PCLKB
000A 002Ch USB0 D1FIFO Port Select Register D1FIFOSEL 16 16 3 or 4 PCLKB
000A 0022h USB0 CFIFO Port Control Re gi ste r CFIFOCTR 16 16 3 or 4 PCLKB
000A 002Ah USB0 D0FIFO Port Control Register D0FIFOCTR 16 16 3 or 4 PCL KB
000A 002Eh USB0 D1FIFO Port Control Register D1FIFOCTR 16 16 3 or 4 PCL KB
000A 0030h USB0 Interrupt Enable Register 0 INTENB0 16 16 9 PCLKB or more
000A 0032h USB0 Interrupt Enable Register 1 INTENB1 16 16 9 PCLKB or more
000A 0036h USB0 BRDY Interrupt Enable Register BRDYENB 16 16 9 PCLKB or more
000A 0038h USB0 NRDY Interrup t Enable Register NRDYENB 16 16 9 PCLKB or more
000A 003Ah USB0 BEMP Interrupt Enable Register BEMPENB 16 16 9 PCLKB or more
000A 003Ch USB0 SOF Out put Configuration Register SOFCFG 16 16 9 PCLKB or more
000A 0040h USB0 Interrupt Status Register 0 INTSTS0 16 16 9 PCLKB or more
000A 0042h USB0 Interrupt Status Register 1 INTSTS1 16 16 9 PCLKB or more
000A 0046h USB0 BRDY Interrupt Status Register BRDYSTS 16 16 9 PCLKB or more
000A 0048h USB0 NRDY Interrup t Status Register NRDYSTS 16 16 9 PCLKB or more
000A 004Ah USB0 BEMP Interrupt Status Register BEMPSTS 16 16 9 PCLKB or more
000A 004Ch USB0 Frame Number Register FRMNUM 16 16 9 PCLKB or more
000A 0054h USB0 USB Request Type Register USBREQ 16 16 9 PCLKB or more
000A 0056 h USB0 USB Request Value Regist er USBVAL 16 16 9 PCLKB or more
000A 0058h USB0 USB Request Index Register USBINDX 16 16 9 PCLKB or more
000A 005Ah USB0 USB Request Length Register USBLENG 16 16 9 PCLKB or more
000A 005Ch USB0 DCP Configuration Register DCPCFG 16 16 9 PCLKB or more
000A 005Eh USB0 DCP Maximum Packet Size Register DCPMAXP 16 16 9 PCLKB or more
000A 0060h USB0 DCP Control Register DCPCTR 16 16 9 PCLKB or more
000A 0064h USB0 Pipe Window Select Register PIPESEL 16 16 9 PCLKB or more
000A 0068h USB0 Pipe Configuration Register PIPECFG 16 16 9 PCLKB or more
000A 006Ch USB0 Pipe Maximum Packet Size Register PIPEMAXP 16 16 9 PCLKB or more
000A 006Eh USB0 Pipe Cycle Control Register PIPEPERI 16 16 9 PCLKB or more
000A 0070h USB0 PIPE1 Control Register PIPE1CTR 16 16 9 PCLKB or more
000A 0072h USB0 PIPE2 Control Register PIPE2CTR 16 16 9 PCLKB or more
000A 0074h USB0 PIPE3 Control Register PIPE3CTR 16 16 9 PCLKB or more
000A 0076h USB0 PIPE4 Control Register PIPE4CTR 16 16 9 PCLKB or more
000A 0078h USB0 PIPE5 Control Register PIPE5CTR 16 16 9 PCLKB or more
000A 007Ah USB0 PIPE6 Control Register PIPE6CTR 16 16 9 PCLKB or more
000A 007Ch USB0 PIPE7 Control Register PIPE7CTR 16 16 9 PCLKB or more
000A 007Eh USB0 PIPE8 Control Register PIPE8CTR 16 16 9 PCLKB or more
000A 0080h USB0 PIPE9 Control Register PIPE9CTR 16 16 9 PCLKB or more
000A 0090h USB0 PIPE1 Transaction Counter Enable Register PIPE1TRE 16 16 9 PCLKB or more
Table 4.1 List of I/O Registers (Address Order) (15/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 48 of 56
Apr 15, 2013
RX111 Group 4. I/O Register s
Under development Preliminary document
Specifications in this document are tentative and subject to change.
Note 1. Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the
TMR0 or TMR2 register.
000A 0092h USB0 PIPE1 Transaction Counter Register PIPE1TRN 16 16 9 PCLKB or more
000A 0094h USB0 PIPE2 Transaction Counter Enable Register PIPE2TRE 16 16 9 PCLKB or more
000A 0096h USB0 PIPE2 Transaction Counter Register PIPE2TRN 16 16 9 PCLKB or more
000A 0098h USB0 PIPE3 Transaction Counter Enable Register PIPE3TRE 16 16 9 PCLKB or more
000A 009Ah USB0 PIPE3 Transaction Counter Register PIPE3TRN 16 16 9 PCLKB or more
000A 009Ch USB0 PIPE4 Transaction Counter Enable Register PIPE4TRE 16 16 9 PCLKB or more
000A 009Eh USB0 PIPE4 Transaction Counter Register PIPE4TRN 16 16 9 PCLKB or more
000A 00A0h USB0 PIPE5 Transaction Counter Enable Register PIPE5TRE 16 16 9 PCLKB or more
000A 00A2h USB0 PIPE5 Transaction Counter Register PIPE5TRN 16 16 9 PCLKB or more
000A 00B0h USB0 BC Control Register 0 USBBCCTRL0 16 16 9 PCLKB or more
000A 00CCh USB0 USB Module Control Reg i ster USBMC 16 16 9 PCLKB or more
000A 00D0h USB0 Device Address 0 Configuration Register DEVADD0 16 16 9 PCLKB or more
000A 00D2h USB0 Device Address 1 Configuration Register DEVADD1 16 16 9 PCLKB or more
000A 00D4h USB0 Device Address 2 Configuration Register DEVADD2 16 16 9 PCLKB or more
000A 00D6h USB0 Device Address 3 Configuration Register DEVADD3 16 16 9 PCLKB or more
000A 00D8h USB0 Device Address 4 Configuration Register DEVADD4 16 16 9 PCLKB or more
000A 00DAh USB0 Device Address 5 Configuration Register DEVADD5 16 16 9 PCLKB or more
007F C090h FLASH E2 DataFlash Control Register DFLCTL 8 8 2 or 3 FCLK
Table 4.1 List of I/O Registers (Address Order) (16/16)
Address Module
Symbol Register Name Register
Symbol Number
of Bits Access
Size Number of
Access States
R01DS0190EJ0060 Rev.0.60 Page 49 of 56
Apr 15, 2013
RX111 Group Appendix 1. Package Dimensions
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Appendix 1. Package Dimensions
Information on the latest version of the package dimensions or mountings has been displ ayed in “Packages” on Renesas
Electronics Corporation webs ite.
Figure A 64-Pin LQFP (PLQP0064KB-A)
Terminal cross section
b1
c1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Index mark
*3
17
32
64
49
116
3348
F
*1
*2
x
bp
HE
E
HD
D
ZD
ZE
Detail F
A
c
A2
A1
L1
L
P-LFQFP64-10x10-0.50 0.3g
MASS[Typ.]
64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A
RENESAS CodeJEITA Package Code Previous Code
1.0
0.125
0.18
1.25
1.25
0.08
0.20
0.145
0.09
0.250.200.15
MaxNomMin
Dimension in Millimeters
Symbol
Reference
10.110.0
9.9
D
10.110.0
9.9
E
1.4
A2
12.212.011.8
12.212.011.8
1.7
A
0.15
0.1
0.05
0.65
0.5
0.35
L
x
c
0.5
e
0.08
y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
e
yS
S
R01DS0190EJ0060 Rev.0.60 Page 50 of 56
Apr 15, 2013
RX111 Group Appendix 1. Package Dimensions
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure B 64-Pin LQFP (PLQP0064GA-A)
Terminal cross section
b1
c1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*3
116
17
32
33
48
49
64
F
*1
*2
x
Index mark
D
HD
E
HE
ebp
ZD
ZE
Detail F
c
A
A2
A1
L
L1
Previous CodeJEITA Package Code RENESAS Code
PLQP0064GA-A 64P6U-A/
MASS[Typ.]
0.7gP-LQFP64-14x14-0.80
1.0
0.125
0.35
1.0
1.0
0.20
0.20
0.145
0.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
14.114.013.9
D14.114.013.9
E1.4
A216.216.015.8 16.216.015.8 1.7
A0.20.1
0
0.70.50.3
L
x
c
0.8
e
0.10
y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
yS
S
R01DS0190EJ0060 Rev.0.60 Page 51 of 56
Apr 15, 2013
RX111 Group Appendix 1. Package Dimensions
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure C 64-Pin WFLGA (PWLG0064KA-A)
64-PIN PLASTIC FLGA (5x5)
E
w
5.00o0.10
0.20
y
0.20
0.08
y1
ZD 0.75
0.05x
D 5.00o0.10
A 0.69o0.07
b0.25o0.04
P64FC-50-AN5
ZE 0.75
S
BSw
S
y
y1
e0.50
INDEX MARK
wSA ZD
ZE
A
b
S
A
B
e
xS
8
7
6
5
4
3
2
1
BCDEFGH A
C
D
CDDETAIL DETAIL EDETAIL
M
60x A B
ITEM DIMENSIONS
(UNIT:mm)
3.90
3.90
b
0.34o0.03 0.55
0.70o0.03
0.55o0.04
0.70o0.03
0.55o0.04
0.75 0.75
0.55 0.55
R0.17o0.015 R0.17o0.015
R0.125o0.02 R0.125o0.02
R0.275o0.02
R0.35o0.015
0.75
0.55o0.04
0.70o0.03
0.55
0.75
0.55o0.04
0.70o0.03
(LAND PAD)
(APERTURE OF
SOLDER RESIST)
E
E
D
2011 Renesas Electronics Corporation. All rights reserved.
R01DS0190EJ0060 Rev.0.60 Page 52 of 56
Apr 15, 2013
RX111 Group Appendix 1. Package Dimensions
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure D 48-Pin LQFP (PLQP0048KB-A)
Terminal cross section
b1
c1
bp
c
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Detail F
L1
c
A
L
A1A2
*3
F
48
37
36 25
24
13
121
*1
*2
x
Index mark
ZE
ZD
bp
e
HE
HD
D
E
Previous CodeJEITA Package Code RENESAS Code
PLQP0048KB-A 48P6Q-A
MASS[Typ.]
0.2gP-LFQFP48-7x7-0.50
1.0
0.125
0.20
0.75
0.75
0.08
0.20
0.145
0.09
0.270.220.17
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.17.06.9
D
7.17.06.9
E
1.4
A2
9.29.08.8
9.29.08.8
1.7
A
0.20.1
0
0.65
0.5
0.35
L
x
c
0.5
e
0.10
y
HD
HE
A1
bp
b1
c1
ZD
ZE
L1
yS
S
R01DS0190EJ0060 Rev.0.60 Page 53 of 56
Apr 15, 2013
RX111 Group Appendix 1. Package Dimensions
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure E 48-Pin HWQFN (PWQN0048KB-A)
2012 Renesas Electronics Corporation. All rights reserved.
DETAIL OF A PART
S
y
e
Lp
SxbA B
M
A
D
E
36
37 24
25
12
13
1
48
A
S
B
A
S
D2
E2
EXPOSED DIE PAD
ITEM D2 E2
A
MIN NOM MAX
5.45 5.50
EXPOSED
DIE PAD
VARIATIONS
5.55
MIN NOM MAX
5.45 5.50 5.55
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A
P48K8-50-5B4-5 0.13
D
E
A
b
e
Lp 0.40
0.50
7.00
7.00
0.75
0.25
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.70
0.18
0.80
0.30
0.30 0.50
x0.05
6.95
6.95
7.05
7.05
y0.05
R01DS0190EJ0060 Rev.0.60 Page 54 of 56
Apr 15, 2013
RX111 Group Appendix 1. Package Dimensions
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure F 40-Pin HWQFN (PWQN0040KC-A)
2012 Renesas Electronics Corporation. All rights reserved.
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-4 0.09
DETAIL OF A PART
S
y
e
Lp
SxbA B
M
A
D
E
30
20
21
10
11
1
40
A
S
B
A
S
D2
E2
31
EXPOSED DIE PAD
ITEM D2 E2
A
MIN NOM MAX
4.45 4.50
EXPOSED
DIE PAD
VARIATIONS
4.55
MIN NOM MAX
4.45 4.50 4.55
D
E
A
b
e
Lp 0.40
0.50
6.00
6.00
0.75
0.25
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.70
0.18
0.80
0.30
0.30 0.50
x0.05
5.95
5.95
6.05
6.05
y0.05
R01DS0190EJ0060 Rev.0.60 Page 55 of 56
Apr 15, 2013
RX111 Group Appendix 1. Package Dimensions
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
Figure G 36-Pin WFLGA (PWLG0036KA-A)
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023
ITEM DIMENSIONS
D
E
w
e
A
b
x
y
y1
ZD
ZE
4.00±0.10
4.00±0.10
0.05
0.20
0.69±0.07
0.08
0.50
0.24±0.05
(UNIT:mm)
0.20
0.75
0.75
S
y1 S A
S
y
Sx32x b A B
M
e
SwB
ZD
ZE
INDEX MARK
B
C
A
SwA
D
E
E
1
2
E
FDCBA
3
4
5
6
CDDETAIL DETAIL EDETAIL
b
0.34±0.05 0.55
0.70 ±0.05
0.55 ±0.05
0.70 ±0.05
0.55 ±0.05
0.75
φ
φ
0.75
0.55 0.55
R0.17±0.05 R0.17 ±0.05
R0.12 ±0.05 R0.12 ±0.05
R0.275±0.05
R0.35±0.05
0.75
0.55±0.05
0.70±0.05
0.55
0.75
0.55±0.05
0.70±0.05
(LAND PAD)
(APERTURE OF
SOLDER RESIST)
D
2.90
2.90
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0190EJ0060 Rev.0.60 Page 56 of 56
Apr 15, 2013
RX111 Group REVISION HISTORY
Under development Preliminary document
Specifications in this document are tent ative and subject to change.
REVISION HISTORY RX111 Group Datasheet
Rev. Date Description
Page Summary
0.60 Apr 15, 2013 First edition, issued
All trademarks and registered trademarks are the property of their respective owners.
REVISION HISTORY
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, et c., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up o r pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequat e. When it is dr y, a humidifier should be used. It is recommende d
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive m aterial. All test and measuremen t
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare ha nds. Similar precautio ns need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and exter nal interface, as a rule, s witch on the external power supply after s witching on the in ternal
power supply. When s witching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. T he correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The curr ent injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device an d accord ing to related specifications governing the device.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in acc ord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedanc e state. In operation
with an unused pin in the ope n-circuit state, extra electromagnetic noise i s induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. U nused
pins should be handle d as described under Handlin g of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is suppli ed.
The states of internal circuits in the LSI are indeterminate a nd the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal i s applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which res etting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expa nsion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operati ng clock signal has become
stable. When switching the clock sign al during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabiliz ation of
the clock signal. Moreover, when switching to a clock sig na l produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having d ifferent part numbers may
differ because of the differences in internal memory capacity and layo ut pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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2880 Scott Boulevard Santa Clara
,
CA 95050-2554
,
U.S.A
.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Mala
y
sia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petalin
g
Jaya, Selan
g
or Darul Ehsan, Malaysi
a
Tel: +60-3-7955-9390
,
Fax: +60-3-7955-951
0
Renesas Electronics Korea Co.
,
Ltd
.
11F., Samik Lavied' or Bld
g
., 720-2 Yeoksam-Don
g
, Kan
g
nam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737
,
Fax: +82-2-558-514
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©
2013 Renesas Electronics Corporation. All ri
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hts reserved
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