Document Number: MMA51xxKW
Rev. 11, 08/2012
Freescale Semiconductor
Data Sheet: Technical Data
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
Xtrinsic MMA51xxKW
PSI5 Inertial Sensor
The MMA51xxKW family , a SafeAssure solution, includes the AKLV27 and PSI5
Version 1.3 compatible overdamped Z-axis satellite accelerometers.
Features
• ±60g to ±480g Full-Scale Rang e
• Selectable 400 Hz, 3-Pole, or 4-pole Low-Pass Filter
• Single Pole High Pass Filter with Fast Startup and Output Rate Limiting
• PSI5 Version 1.3 Compatib l e
– PSI5-P10P-500/3L Compatible
– Programmable Time Slots with 0.5 μs Resolution
– Selectable Baud Rate: 125 kBaud or 190.5 kBaud
– Selectable Data Length: 8 or 10 bits
– Selectable Error Detection: Even Parity, or 3-bit CRC
– Optional Daisy Chain with External Low-Side Switch
– Two-Wire Programmin g Mode
• 16 μs Internal Sample Rate, with Interpolation to 1 μs
• Pb-Free 16-Pin QFN, 6 by 6 Package
• Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C)
(http://www.aecouncil.com/)
Typical Applications
• Airbag Front and Side Crash Detection
For user register array programming, please consult your Freescale
representative.
ORDERING INFORMATION
Device Axis Range Package Shipping
MMA5106KW Z±60g 2086-01 Tubes
MMA5112KW Z±120g 2086-01 Tubes
MMA5124KW Z±240g 2086-01 Tubes
MMA5148KW Z±480g 2086-01 Tubes
MMA5106KWR2 Z±60g 2086-01 Tape & Reel
MMA5112KWR2 Z±120g 2086-01 Tape & Reel
MMA5124KWR2 Z±240g 2086-01 Tape & Reel
MMA5148KWR2 Z±480g 2086-01 Tape & Reel
MMA51xxKW
16-PIN QFN
CASE 2086-01
PIN CONNECTIONS
Bottom View
Top View
V
CC
V
SS
BUS_SW
V
SSA
TEST
V
BUF
D
OUT
D
IN
V
REGA
CS
V
REG
V
SS
I
DATA
SLCK
V
SSA
PCM
1
2
3
4
5678
12
11
10
9
16 15 14 13
17
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2Freescale Semiconductor, Inc.
MMA51xxKW
Application Diagram
Figure 1. Applicatio n Diag ram
Device Orientation
Figure 2. Device Orientation Diagram
External Component Recommendatio ns
Ref Des Type Description Purpose
C1 Ceramic 2.2 nF, 10%, 50V mini mum, X7R VCC Power Supply Decoupling and Signal Damping
C3 Ceramic 470 pF, 10%, 50V minimum, X7R IDATA Filtering and Signal Damping
C2 Ceramic 15 nF, 10%, 50V minimum, X7R VCC Power Supply Decoupling
C4, C5, C6 Ceramic 1 μF, 10%, 10V minimum, X7R Voltage Regulator Output Capacitor(s)
R1 General Purpose 82Ω, 5%, 200 PPM VCC Filtering and Signal Damping
R2 General Purpose 27Ω, 5%, 200 PPM IDATA Filtering and Signal Damping
R3 General Purpose 20 kΩ, 5%, 200 PPM Gate Resistor for External Low-Side Daisy Chain FET
M1 N-Channel MOSFET —Low-Side Daisy Chain Transistor
C1
C6
VVBUF VCE
VSS
C4 C5
VREG
VREGA
CS
SCLK
DO
DI
MMA51xx
VSSA
VSS
VCC
VBUF
PCM
R1
R2
IDATA
C3
C2
VSS_OUT
R3 M1
Optional for
BUS_SW
Note: Pin names and refe rences
may differ from PSI5 V1.3
pin names and references Daisy Chain
Z: 0g
EARTH GROUND
Z: 0g Z: 0g Z: 0g Z: +1g Z: -1g
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
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MMA51xxKW
Internal Block Diagram
Figure 3. Block Diagram
Self-Test
Interface
ΣΔ
Converter
VCC
Serial
Encoder
VBUF
Sync Pulse
Detection
Programming
Interface
PCM
VBUF
VSS
Buffer
Regulator
Voltage Digital
Regulator
Voltage
Analog
Regulator
Voltage
VREG
VREGA
VREGA
VREG
VCC
VREG
VREGA VREG
Reference
Voltage
VREF
VSSA
DIN
SPI
DOUT
CS
SCLK
IDATA
VBUF
Daisy Chain
Switch Driver
BUS_SW
Control
Logic
OTP
Array
g-cell
Control
In Status
Out
SINC Filter Compensation
LPF
IIR PCM
DSP
HPF
Low Voltage
Detection
Encoder
Offset
Monitor
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4Freescale Semiconductor, Inc.
MMA51xxKW
1 Pin Connections
Figure 4. Top View, 16-Pin QFN Package
Table 1. Pin Description
Pin Pin
Name Formal Name Definition
1 VCC Supply This pin is connected to th e PSI5 power and data line throug h a resistor and supp lies power to the device. A n external capa c-
itor must be connected between this pin and VSS. Reference Figure 1.
2 VSS Digital GND This pin is the power supply return node for the digital circuitry.
3 IDATA Response
Current This pin is connected to the PS I5 power and data line through a resistor and modulates the response current for PSI5 com-
munication. Reference Figure 1.
4 VSS Digital GND This pin is the power supply return node for the digital circuitry.
5PCM PCM
Output This pin provides a 4 MHz PCM signal proport iona l to the acce ler ati on da ta fo r te st pu rposes. The o utput ca n be enab led via
OTP. Reference Sect i on 3.5.3.7. If unused, this pin must be left unconnected.
6SCLK SPI Clock This input pin provi des the serial clock to the SPI port for test purposes. An internal pulldown device is connected to this pin.
This pin must be grounded or left unconnected in the application.
7 DOUT SPI Data Out This pin functions as the serial dat a output fr om the SPI port for test pur poses. This pin must be lef t uncon necte d in t he a ppli-
cation.
8 DIN SPI Data In This pin functions as the serial data input to the SPI port for test purposes. An internal pulldown device is connected to this
pin. This pin must be grounded or left uncon nected in the application.
9 VREG Digital
Supply This pin is connected to the power supply for the internal digital circuitry. An external capacito r must be connected between
this pin and VSS. Reference Figure 1.
10 CS Chip Select This input pin provid es the chip se lect to the SPI p ort for t est purposes. An int ernal pullup device is connected to t his pin.This
pin must be left unconnected in the application.
11 VREGA Analog
Supply This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected bet ween
this pin and VSSA. Reference Figure 1.
12 VSSA Analog GND This pin is the power supply return node for the analog circuitry.
13 VBUF Power
Supply
This pin is connected to a buffer reg ulator for t he int ernal circuitry. The buffer regulat or supplies both t he analo g (VREGA) and
digital (VREG) supplies to provide immunity from EMC and supply dropouts on VCC. An external capacitor must be connecte d
between this pin and VSS. Reference Figure 1.
14 TEST Test Pin This pin is must be grounded or left unconnected in the application.
15 BUS_SW Bus Swit ch
Gate Drive This pin is the drive for a low- side da isy cha in swit ch. When d aisy chain mode is enabled, this pin is connect ed to th e gate of
an n-channel FET which connects VSS to VSS_OUT. Reference Figure 1. If unused, this pin must be left unconnected.
16 VSSA Analog GND This pin is the power supply return node for the analog circuitry.
17 PAD Die Attach Pa d This pin is the die attach flag, and is internally connected to VSS. Re ference Section 7 for die attach pad connection details.
Corner
Pads Corner Pads The corner pads are internally connect ed to VSS.
V
CC
V
SS
BUS_SW
V
SSA
TEST
V
BUF
D
OUT
D
IN
V
REGA
CS
V
REG
V
SS
I
DATA
SLCK
V
SSA
PCM
1
2
3
4
5678
12
11
10
9
16 15 14 13
17
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MMA51xxKW
2 Electrical Characteristics
2.1 Maximum Rati ngs
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.
2.2 Operating Range
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#Rating Symbol Value Unit
1
2
3
Supply Voltage (VCC, IDATA)
Reverse Current ≤ 160 mA, t ≤ 80 ms
Continuous
Transient (< 10 μs)
VCC_REV
VCC_MAX
VCC_TRANS
-0.7
+20.0
+25.0
V
V
V
(3)
(3)
(9)
4VBUF, Tes t, BUS_SW -0.3 to +4.2 V(3)
5VREG, VREGA, SCLK, CS, DIN, DOUT, PCM -0.3 to +3.0 V(3)
6Powered Shock (six sides, 0.5 ms du ration) gpms ±2000 g(3)
7Unpowered Shock (six sides, 0.5 ms durati on) gshock ±2500 g(3)
8Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation) hDROP 1.2 m(5)
9
10
11
12
Electrostatic Discharge (per AEC-Q100)
External Pins (VCC, IDATA, VSS, VSSA), HBM (100 pF, 1.5 kΩ)
HBM (100 pF, 1.5 kΩ)
CDM (R = 0 Ω)
MM (200 pF, 0 Ω)
VESD
VESD
VESD
VESD
±4000
±2000
±1500
±200
V
V
V
V
(5)
(5)
(5)
(5)
13
14
Temperature Range
Storage
Junction Tstg
TJ-40 to +125
-40 to +150 °C
°C (3)
(9)
15 Thermal Resistance θJC 2.5 °C/W (9,14)
#Characteristic Symbol Min Typ Max Units
16
17 Supply Voltage VCC
VCC_UV
VL
4.2
VVCC_UV_F —
—
VH
17.0
VLV
V(1)
(9)
18 Programming Voltage (IDATA ≤ 85 mA)
Applied to IDATA, VCC VPP 14.0 — — V (3)
19
20
Operating Temperatur e Range TA
TA
TL
-40
-40 ⎯
⎯
TH
+105
+125 °C
°C (1)
(3)
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6Freescale Semiconductor, Inc.
MMA51xxKW
2.3 E lectrical Characteristics - Supply and I/O
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
# Characteristic Symbol Min Typ Max Units
21 Quiescent Supply Current * IIDLE 4.0 ⎯8.0 mA (1)
22 Modulation Supply Current * IMOD IIDLE+ 22.0 IIDLE+ 26.0 IIDLE+ 30.0 mA (1)
23 Inrush Current (Power On until VBUF, VREG, VREGA Stable) IINRUSH ⎯⎯ 30 mA (3)
24
25
26
Internally Regulated Voltages
VBUF
VREG
VREGA
*
*
*
VBUF
VREG
VREGA
3.60
2.425
2.425
3.80
2.50
2.50
4.00
2.575
2.575
V
V
V
(1)
(1)
(1)
27
28
29
30
31
32
33
34
Low Voltage Detection Threshold
VCC Falling
VBUF Falling
VREG Falling
VREGA Falling
Hysteresis
VCC
VBUF
VREG
VREGA
VVCC_UV_F
VBUF_UV_F
VREG_UV_F
VREGA_UV_F
VCC_HYST
VBUF_HYST
VREG_HYST
VREGA_HYST
3.40
2.95
2.15
2.15
0.10
0.05
0.05
0.05
3.70
3.15
2.25
2.25
0.25
0.10
0.10
0.10
4.0
3.35
2.35
2.35
0.40
0.15
0.15
0.15
V
V
V
V
V
V
V
V
(3, 6)
(3, 6)
(3, 6)
(3, 6)
(3)
(3)
(3)
(3)
35
36
External Capacitor (VBUF, VREG, VREGA)
Capacitance
ESR (including interconnect resistance) ESR 500
01000
⎯1500
200 nF
mΩ(9)
(9)
37
38
Synchronization Pulse (See Figure 5)
VIDLE Voltage Range
DC Sync Pulse Detection Threshold *
*VIDLE
ΔVSYNC
⎯
VIDLE+1.4 ⎯
VIDLE+2.0 15.4
VIDLE+2.6 V
V(3, 11)
(3, 6)
39 Sync Pu ls e Pulldow n C u rrent ISYNC_PD ⎯IMOD - IIDLE ⎯mA (3)
40 Output High Voltage (DO)
ILoad = 100 μAV
OH VREG - 0.1 ⎯⎯V(9)
41 Output Low Voltage (DO)
ILoad = 100 μAV
OL ⎯⎯0.1 V (9)
42 Input High Voltage
CS, SCLK, DI VIH 0.7 * VREG ⎯⎯V(9)
43 Input Low Voltage
CS, SCLK, DI VIL ⎯⎯0.3 * VREG V(9)
44
45
Input Current
High (at VIH) (DI )
Low (at VIL) (CS)IIH
IIL -100
10 ⎯
⎯-10
100 μA
μA(9)
(9)
46 Pulldown Resistance (SCLK) RPD 20 ⎯100 kΩ(9)
47 BUS_SW Output High Voltage (BUS_SW)
ILoad = 100 μAV
BUS_SW_OH 3.15 ⎯VBUF V(9)
48 Output Low Voltage (BUS_SW)
ILoad = 100 μAV
BUS_SW_OL 0.0 ⎯0.45 V (9)
49 Daisy Chain Addressing Mode Sync Pulse Period ⎯tS-S_PM_L ⎯s(7)
50 Bus Switch Output Activation Time (C = 50 pF)
From last bit of “SetAdr” Response to 80% of VBUS_SW_OH tBUS_SW ⎯⎯300 μs(7)
51 Sync Pulse Blanking Time after “SetAdr” Command Received
From last bit of “SetAdr” Response tDC_BLANKING 200000 / fOSC s(7)
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MMA51xxKW
2.4 E lectrical Characteristics - Sensor and Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
# Characteristic Symbol Min Typ Max Units
52
53
54
55
56
57
58
59
60
61
Sensitivity (10-bit output @ 100 Hz, referenced to 0 Hz)
±60g Range
±120g Range
±240g Range
±480g Range
Total Sensitivity Error (including non-linearity)
TA = 25°C, ≤ ±240g
TL ≤ TA ≤ TH, ≤ ±240g
TL ≤ TA ≤ TH, ≤ ±240g, VVCC_UV_F ≤ VCC ≤ VL
TA = 25°C, > ±240g
TL ≤ TA ≤ TH, > ±240g
TL ≤ TA ≤ TH, > ±240g, VVCC_UV_F ≤ VCC ≤ VL
*
*
*
*
*
*
*
*
SENS
SENS
SENS
SENS
ΔSENS_240
ΔSENS_240
ΔSENS_240
ΔSENS_480
ΔSENS_480
ΔSENS_480
—
—
—
—
-5
-7
-7
-5
-7
-7
8
4
2
1
—
—
—
—
—
—
—
—
—
—
+5
+7
+7
+5
+7
+7
LSB/g
LSB/g
LSB/g
LSB/g
%
%
%
%
%
%
(1)
(1)
(1)
(1)
(1)
(1)
(9)
(1)
(1)
(9)
62
63
Digital Offset Before Offset Cancellation
10-bit
10-bit, TL ≤ TA ≤ TH, VVCC_UV_F ≤ VCC ≤ VL *OFF10Bit
OFF10Bit -52
-52 0
0+52
+52 LSB
LSB (1)
(9)
64
65
Digital Offset After Offset Cancellation
10-bit, 0.3 Hz HPF or 0.1 Hz HPF
10-bit, 0.04 Hz HPF *
*OFF10Bit
OFF10Bit -1
-2 0
0+1
+2 LSB
LSB (1)
(9)
66 Continuous Offset Monitor Limit
10-bit output, before compensation OFFMON -66 ⎯+66 LSB (3)
67 Range of Output (1 0-Bit Mode)
Acceleration RANGE -480 ⎯+480 LSB (3)
68
69
Cross-Axis Sensitivity
X-axis to Z-Axis
Y-axis to Z-Axis *
*VXZ
VYZ -5
-5 ⎯
⎯+5
+5 %
%(3)
(3)
70 System Output Noise Peak (10-bit Mode, 1 Hz - 1 kHz, All Ranges) * nPeak -4 — +4 LSB (3)
71 System Output Noise RMS (10-bit mode, 1 Hz - 1 kHz, All Ranges) * nRMS ——+1.0LSB(3)
72
73
Non-linearity
10-bit output, ≤ ±240g
10-bit output, > ±240g NLOUT_240g
NLOUT_480g -2
-2 ⎯
⎯+2
+2 %
%(3)
(3)
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8Freescale Semiconductor, Inc.
MMA51xxKW
2.5 E lectrical Characteristics - Self-Test and Overload
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
# Characteristic Symbol Min Typ Max Units
74
75
76
77
10-Bit Output During Active Self-Test (TL ≤ TA ≤ TH)
±60g Range
±120g Range
±240g Range
±480g Range
*
*
*
*
gST10_60Z
gST10_120Z
gST10_240Z
gST10_480Z
120
40
35
12
⎯
⎯
⎯
⎯
280
160
153
94
LSB
LSB
LSB
LSB
(3)
(3)
(3)
(3)
78
79
Acceleration (without hitting internal g-cell stops)
±60g Range Positive
±60g Range Negative gg-cell_Clip60ZP
gg-cell_Clip60ZN 425
-1205 642
-720 980
-512 g
g(9)
(9)
80
81
Acceleration (without hitting internal g-cell stops)
±120g Range Positive
±120g Range Negative gg-cell_Clip120ZP
gg-cell_Clip120ZN 425
-1205 642
-720 980
-512 g
g(9)
(9)
82
83
Acceleration (without hitting internal g-cell stops)
±240g Range Positive
±240g Range Negative gg-cell_Clip240ZP
gg-cell_Clip240ZN 1450
-3100 2180
-2210 2800
-1800 g
g(9)
(9)
84
85
Acceleration (without hitting internal g-cell stops)
±480g Range Positive
±480g Range Negative gg-cell_Clip480ZP
gg-cell_Clip480ZN 2200
-3700 2800
-3220 3300
-2780 g
g(9)
(9)
86
87
ΣΔ and Sinc Filter Clipping Limit
±60g Range Positive
±60g Range Negative gADC_Clip60ZP
gADC_Clip60ZN 159
-334 238
-274 336
-216 g
g(9)
(9)
88
89
ΣΔ and Sinc Filter Clipping Limit
±120g Range Positive
±120g Range Negative gADC_Clip120ZP
gADC_Clip120ZN 305
-693 433
-544 577
-414 g
g(9)
(9)
90
91
ΣΔ and Sinc Filter Clipping Limit
±240g Range Positive
±240g Range Negative gADC_Clip240ZP
gADC_Clip240ZN 836
-1909 1178
-1566 1599
-1245 g
g(9)
(9)
92
93
ΣΔ and Sinc Filter Clipping Limit
±480g Range Positive
±480gZ Range Negative gADC_Clip480ZP
gADC_Clip480ZN 1591
-3217 2014
-2856 2478
-2524 g
g(9)
(9)
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Freescale Semiconductor, Inc. 9
MMA51xxKW
2.6 Dynamic Electrical Characteristics - PSI5
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
# Characteristic Symbol Min Typ Max Units
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
Initialization Timing
Phase 1
Phase 2 (10-Bit, Synchronous Mode, k = 4)
Phase 2 (8-Bit, Synchronous Mode, k = 8)
Phase 2 (10-Bit, Asynchronous Mode 0, k = 8)
Phase 2 (8-Bit, Asynchronous Mode 0, k = 16)
Phase 3 (10-Bit, Synchronous Mode, ST_RPT = 0)
Phase 3 (8-Bit, Synchronous Mode, ST_RPT = 0)
Phase 3 (10-Bit, Asyn chronous Mode 0, ST_RPT = 0)
Phase 3 (8-Bit, Asynchronous Mode 0, ST_RPT = 0)
Offset Cancellation Stage 1 Operating Time
Offset Cancellation Stage 2 Operating Time
Self-Test Stage 1 Ope r ating Time
Self-Test Stage 2 Ope r ating Time
Self-Test Stage 3 Ope r ating Time
Self-Test Repetitions
Programming Mode Entry Window
tPSI5_INIT1
tPSI5_INIT2_10s
tPSI5_INIT2_8s
tPSI5_INIT2_10a0
tPSI5_INIT2_8a0
tPSI5_INIT3_10s
tPSI5_INIT3_8s
tPSI5_INIT3_10a0
tPSI5_INIT3_8a0
tOC1
tOC2
tST1
tST2
tST3
ST_RPT
tPME
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
⎯
532000 / fOSC
256 * tS-S
288 * tS-S
512 * tASYNC
576 * tASYNC
2 * tS-S
2 * tS-S
19 * tASYNC
2 * tASYNC
320000 / fOSC
280000 / fOSC
128000 / fOSC
128000 / fOSC
128000 / fOSC
⎯
300000 / fOSC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
⎯
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
(7)
(7)
(7)
(7)
(7)
(7, 12)
(7, 12)
(7, 12)
(7, 12)
(7)
(7)
(7)
(7)
(7)
(7, 12)
(7)
110
111
112
113
114
115
116
117
118
119
120
121
Synchronization Pulse (Figure 5, Figure 28 and Figure 32)
Reset to first sync pulse (Prog ram Mode Entry)
Reset to first sync pulse (Normal Mode)
Sync Pulse Period
Sync Pulse Width
Sync Pulse Reference LPF time constant
Sync Pulse Reference Discharge Start Time
Sync Pulse Reference Discharge Activation Time
Sync Pulse Detection Disable Time (BLANKTIME = 0)
Analog Delay of Sync Pulse Detection
Sync Pulse Pulldown Function Delay Time
Sync Pulse Pulldown Function Activate Time
Sync Pulse Detection Jitter
tRS_PM
tRS
tS-S
tSYNC
tSYNC_LPF
tSYNC_LPF_RST_ST
tSYNC_LPF_RST
tSYNC_OFF_500
tA_SYNC_DLY
tPD_DLY
tPD_ON
tSYNC_JIT
58
tPSI5_INIT1
tSYNC_OFF
9
120
⎯
⎯
⎯
50
⎯
⎯
0
⎯
⎯
⎯
⎯
280
66 / fOSC
616 / fOSC
1810 / fOSC
⎯
74 / fOSC
64 / fOSC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
600
⎯
⎯
2 / fOSC
ms
s
μs
μs
μs
s
s
s
ns
s
s
s
(7)
(7)
(7)
(7)
(9)
(7)
(7)
(7)
(9)
(7)
(7)
(7)
122
123 Data Transmission Single Bit Time (PSI5 Low Bit Rate)
Data Transmission Single Bit Time (PSI5 High Bit Rate) *
*tBIT_LOW
tBIT_HI 7.6000
4.9875 8.0000
5.2500 8.4000
5.5125 μs
μs(7)
(7)
124
125
Modulation Current (20% to 80% of IMOD - IIDLE)
Rise Time
Fall Time tRISE
tFALL 324
324 463
463 602
602 ns
ns (3)
(3)
126
127 Position of bit tra nsition (PSI5 Low Baud Rate)
Position of bit transition (PSI5 High Baud Rate ) *
*tBittrans_LowBaud
tBittrans_HighBaud 49
47 50
⎯51
53 %
%(7)
(7)
128 Asynchronous Response Time * tASYNC ⎯912 / fOSC ⎯s(7)
129
130
131
132
133
134
135
136
Time Slots
Minimum Programmed Time Slot (TIMESLOTx = 0x001)
Maximum Programmed Time Slot (TIMESLOTx = 0x3FF)
Default Time Slot (TIMESLOTx = 0x000)
Time Plot Resolution
Sync Pulse to Daisy Chain Default Time Slot 1
Sync Pulse to Daisy Chain Default Time Slot 2
Sync Pulse to Daisy Chain Default Time Slot 3
Sync Pulse to Daisy Chain Programming Time Slot
*
tTIMESLOTx_MIN
tTIMESLOTx_MAX
tTIMESLOT_DFLT
tTIMESLOTx_RES
tTIMESLOT_DC1
tTIMESLOT_DC2
tTIMESLOT_DC3
tTIMESLOT_DCP
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2 / fOSC
2046 / fOSC
186 / fOSC
2 / fOSC
186 / fOSC
768 / fOSC
1400 / fOSC
186 / fOSC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
s
s
s
s/LSB
s
s
s
s
(7, 9)
(3, 7)
(3, 7)
(7)
(7)
(7)
(7)
(7)
137
138
Data Interpolation Latency (Figure 35, Figure 36)
Data Setup Time - Synchronous Mode (Figure 36)
Data Setup Time - Double Sample Rate Mode (Figure 37)
Data Setup Time - 16 Bit Resolution Mode (Figure 39)
tLAT_INTERP
tDATASETUP_synch
tDATASETUP_double
tDATASETUP_16
64 / fOSC
48 / fOSC
48 / fOSC
48 / fOSC
⎯
⎯
⎯
⎯
65 / fOSC
56 / fOSC
60 / fOSC
60 / fOSC
s
s
s
s
(7)
(7)
(7)
(7)
139
140
141
142
143
Programming Mode Timing
Programming Mode Sync Pulse Period
Programming Mode Command Timeout
OTP Write Command to VCC = VPP
OTP Write CMD Response to OTP programming start
Time to program the OTP User Array
tS-S_PM_L
tPM_TIMEOUT
tPROG_HOLD
tPROG_DELAY
tPROG_ARRAY
495
⎯
⎯
⎯
70
500
4 * tS-S_PM
⎯
⎯
⎯
505
⎯
20
40
⎯
μs
μs
μs
ms
ms
(7)
(7)
(7)
(7)
(7)
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10 Freescale Semiconductor, Inc.
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2.7 Dynamic Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
# Characteristic Symbol Min Typ Max Units
144 Internal Oscillator Frequency * fOSC 3.80 4 4.20 MHz (1)
145
146
147
148
DSP Low-Pass Filter (Note15)
Cutoff frequency LPF0 (referenced to 0 Hz)
Filter Order LPF0
Cutoff frequency LPF1 (referenced to 0 Hz)
Filter Order LPF1
*
*
*
*
fC_LPF0
OLPF0
fC_LPF1
OLPF1
⎯
⎯
⎯
⎯
400
3
400
4
⎯
⎯
⎯
⎯
Hz
1
Hz
1
(7)
(7)
(7)
(7)
149
150
151
152
153
154
155
156
157
158
159
160
161
162
DSP Offset Cancellation Low-Pass Filter (Note15)
Offset Cancellation Low-Pass Filter Input Sample Rate
Stage 1 Cutoff frequency, Startup Phase 1
Stage 1 Filter Order, Start up Phase 1
Stage 2 Cutoff frequency, Startup Phase 1
Stage 2 Filter Order, Start up Phase 1
Cutoff frequency, Option 0
Filter Order, Option 0
Offset Cancellation Output Update Rate (8-Bit Mode)
Offset Cancellation Out put Step Size (8-Bit Mode)
Offset Cancellation Output Update Rate (10-Bit Mode)
Offset Cancellation Out put Step Size (10-Bit Mode)
Offset Monitor Update Frequency
Offset Monitor Count Limit
Offset Monitor Counter Size
tOC_SampleRate
fC_OC10
OOC10
fC_OC03
OOC03
fC_OC0
OOC0
tOffRate_8
OFFStep_8
tOffRate_10
OFFStep_10
OFFMONOSC
OFFMONCNTLIMIT
OFFMONCNTSIZE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
256
10.0
1
0.300
1
0.100
1
fOSC / 2e6
0.125
fOSC / 2e6
0.5
fOSC / 2000
4096
8192
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
μs
Hz
1
Hz
1
Hz
1
s
LSB
s
LSB
Hz
1
1
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
163
164
165
166
Sensing Element Natural Frequency
±60g
±120g
±240g
±480g
fgcell_Z60
fgcell_Z120
fgcell_Z240
fgcell_Z480
7000
7000
13600
16289
⎯
⎯
⎯
⎯
8000
8000
15100
17996
Hz
Hz
Hz
Hz
(9)
(9)
(9)
(9)
167
168
169
170
Sensing Element Roll-off Freq uency (-3 db)
±60g
±120g
±240g
±480g
fgcell_Z60
fgcell_Z120
fgcell_Z240
fgcell_Z480
798
798
2000
2250
⎯
⎯
⎯
⎯
2211
2211
4700
6350
Hz
Hz
Hz
Hz
(9)
(9)
(9)
(9)
171
172
173
174
Sensing Element Damping Ratio
±60g
±120g
±240g
±480g
ζgcell_Z60
ζgcell_Z120
ζgcell_Z240
ζgcell_Z480
1.870
1.870
1.750
1.250
⎯
⎯
⎯
⎯
4.610
4.610
3.500
3.000
⎯
⎯
⎯
⎯
(9)
(9)
(9)
(9)
175
176
177
178
Sensing Element Delay (@100 Hz)
±60g
±120g
±240g
±480g
fgcell_delay_Z60
fgcell_delay_Z120
fgcell_delay_Z240
fgcell_delay_Z480
77
77
40
21
⎯
⎯
⎯
⎯
200
200
86
60
μs
μs
μs
μs
(9)
(9)
(9)
(9)
179 Package Resonance Frequency fPackage 100 ⎯⎯kHz (9)
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2.8 Dynamic Electrical Characteristics - Supply and SPI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
1. Parameters tested 100% at final test.
2. Parameters tested 100% at wafer probe.
3. Verified by characterization.
4. * Indicates critical characteristic.
5. Verified by qualification testing.
6. Parameters verified by pass/fail testing in production.
7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing
is determined by internal system clock frequency.
8. N/A.
9. Verified by simulation.
10. N/A.
11. Measured at VCC pin; VSYNC guaranteed across full VIDLE range.
12. Self-Test repeats on failure up to a ST_RPTMAX times before transmitting Sensor Error Message.
13. N/A.
14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
15. Filter cutoff frequencies are directly dependent upon the internal oscillator frequency.
# Characteristic Symbol Min Typ Max Units
180 Quiescent Current Settling Time (Power Applied to Iq = IIDLE ± 2 mA) tSET ⎯⎯ 5ms(3)
181 Reset Recovery Internal Delay (A ft e r inte rn al POR) tINT_INIT ⎯16000 / fOSC ⎯s(7)
182
183
184
VCC Micro-cut (CBUF=CREG=CREGA=1 μF)
Survival Time (VCC disconnect without Reset, CBUF=CREG=CREGA=700 nF)
Survival Time (VCC disconnect without Reset, CBUF=CREG=CREGA=1 μF)
Reset Time (VCC disconnect above which Reset is guaranteed)
tVCC_MICROCUTmin
tVCC_MICROCUT
tVCC_RESET
30
50
⎯
⎯
⎯
⎯
⎯
⎯
1000
μs
μs
μs
(3)
(3)
(3)
185
186
187
188
VBUF, Capacitor Monitor Disconnect Time (Figure 10)
POR to first Capacitor Test Disconnect
Disconnect Time (Figure 10)
Disconnect Delay, Asynchronous Mode (Figure 10)
Disconnect Delay, Synchronous Mode (Figure 11)
tPOR_CAPTEST
tCAPTEST_TIME
tCAPTEST_ADLY
tCAPTEST_SDLY
⎯
⎯
⎯
⎯
12000 / fOSC
1.5
688 / fOSC
72 / fOSC
⎯
5.0
⎯
⎯
s
μs
s
s
(7)
(7)
(7)
(7)
189
190
191
VREG, VREGA Capacitor Monitor
POR to first Capacitor Test Disconnect
Disconnect Time
Disconnect Rate
tPOR_CAPTEST
tCAPTEST_TIME
tCAPTEST_RATE
⎯
⎯
⎯
12000 / fOSC
6 / fOSC
256 / fOSC
⎯
⎯
⎯
s
s
s
(7)
(7)
(7)
192
193
194
195
196
197
198
199
200
201
202
203
204
205
Serial Interface Timing (See Figure 7, CDOUT ≤ 80 pF, RDOUT ≥ 10 kΩ)
Clock (SCLK) period (10% of VCC to 10% of VCC)
Clock (SCLK) high time (90% of VCC to 90% of VCC)
Clock (SCLK) low time (10% of VCC to 10% of VCC)
Clock (SCLK) rise time (10% of VCC to 90% of VCC)
Clock (SCLK) fall time (90% of VCC to 10% of VCC)
CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC)
CS asserted to DOUT valid (CS = 10% of VCC to DOUT = 10/90% of VCC)
Data setup time (DIN = 10/90% of VCC to SCLK = 10% of VCC)
DIN Data hold time (SCLK = 90% of VCC to DIN = 10/90% of VCC)
DOUT Data hold time (SCLK = 90% of VCC to DOUT = 10/90% of VCC)
SCLK low to data valid (SCLK = 10% of VCC to DOUT = 10/90% of VCC)
SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC)
CS high to DOUT disable (CS = 90% of VCC to DOUT = Hi Z)
CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)
tSCLK
tSCLKH
tSCLKL
tSCLKR
tSCLKF
tLEAD
tACCESS
tSETUP
tHOLD_IN
tHOLD_OUT
tVALID
tLAG
tDISABLE
tCSN
320
120
120
⎯
⎯
60
⎯
20
10
0
⎯
60
⎯
1000
⎯
⎯
⎯
15
15
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
40
28
⎯
60
⎯
⎯
⎯
50
⎯
60
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
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12 Freescale Semiconductor, Inc.
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Figure 5. Sync Pulse Charac teristics
Figure 6. Powerup T imin g
GND
VCC
tSYNC
ΔVSYNC
VSYNC
tRS tS-S
VIDLE
V
CC
POR
VCC_UV_f + VCC_HYST
Time
V
REG
V
BUF
VCC_UV_f
VBUF_UV_f + VBUF_HYST
VBUF_UV_f
VREG_UV_f + VREG_HYST
VREG_UV_f
V
REG
VREGA_UV_f+VREGA_HYST
VREGA_UV_f
Response Terminated if in process
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Figure 7. Serial Interface Timing
tSCLK
SCLK
D
IN
CS
D
OUT
tSCLKH
tSCLKL
tACCESS
tSCLKR tSCLKF
tLEAD tCSN
tSETUP
tHOLD_IN
tVALID tDISABLE
tHOLD_OUT
tLAG
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3 Functional Description
3.1 User Accessible Data Array
A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable
block, an OTP user programmable block, and read only registers for device status. The OTP blocks incorporate independen t
error detection circuitry for fault detection (reference Se ction 3.2). Portions of the factory programmable array are reserved for
factory-programmed trim values. The user accessible data is shown in Table 2.
Type codes
F: Freescale programmed OTP location
U: User programmable OTP location via PSI5
R: Readable register via PSI5
3.1.1 Device Serial Number Registers
A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial num-
ber is composed of the following information:
Serial numbers begin at 1 for all produced devices in each lot and are sequentially assigned. Lot numbers begin at 1 and are
sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number . Depending on
lot size and quantities, all possible lot numbers and seri al numbers may not be assigned.
The serial number registers are included in the factory programmed OTP CRC verification. Reference Section 3.2.1 for details
regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or
performance, and are only used for traceability purposes.
Table 2. User Accessible Data
Byte
Addr
(XLong
Msg)
Register
Nibble
Addr
(Long
Msg)
Bit Function Nibble
Addr
(Long
Msg)
Bit Function
Type
7654 3210
$00 SN0 $01 SN[7] SN[6] SN[5] SN[4] $00 SN[3] SN[2] SN[1] SN[0]
F, R
$01 SN1 $03 SN[15] SN[14] SN[13] SN[12] $02 SN[11] SN[10] SN[9] SN[8]
$02 SN2 $05 SN[23] SN[22] SN[21] SN[20] $04 SN[19] SN[18] SN[17] SN[16]
$03 SN3 $07 SN[31] SN[30] SN[29] SN[28] $06 SN[27] SN[26] SN[25] SN[24]
$04 DEVCFG1 $090010$08 1 RNG[2] RNG[1] RNG[0]
$05 DEVCFG2 $0B LOCK_U PCM SYNC_PD LATENCY $0A DATASIZE BLANKTIME P_CRC BAUD
U, R
$06 DEVCFG3 $0D TRANS_MD[1] TRANS_MD[0] LPF[1] LPF[0] $0C TIMESLOTB[9] TIMESLOTB[8] TIMESLOTA[9] TIMESLOTA[8]
$07 DEVCFG4 $0F TIMESLOTA[7] TIMESLOTA[6] TIMESLOTA[5] TIMESLOTA[4] $0E TIMESLOTA[3] TIMESLOTA[2] TIMESLOTA[1] TIMESLOTA[0]
$08 DEVCFG5 $11 TIMESLOTB[7] TIMESLOTB[6] TIMESLOTB[5] TIMESLOTB[4] $10 TIMESLOTB[3] TIMESLOTB[2] TIMESLOTB[1] TIMESLOTB[0]
$09 DEVCFG6 $13 INIT2_EXT ASYNC U_DIR[1] U_DIR[0] $12 U_REV[3] U_REV[2] U_REV[1] U_REV[0]
$0A DEVCFG7 $15 MONTH[3] MONTH[2] MONTH[1] MONTH[0] $14 YEAR[3] YEAR[2] YEAR[1] YEAR[0]
$0B DEVCFG8 $17 UD[2] UD[1] UD[0] DAY[4] $16 DAY[3] DAY[2] DAY[1] DAY[0]
$0C SC $19 0 TM_B RESERVED IDEN_B $18 OC_INIT_B IDEF_B OFF_B 0 R
$0D MFG_ID $1B MFG_ID[7] MFG_ID[6] MFG_ID[5] MFG_ID[4] $1A MFG_ID[3] MFG_ID[2] MFG_ID[1] MFG_ID[0] U, R
Bit Range Content
SN[12:0] Serial Number
SN[31:13] Lot Number
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3.1.2 Factory Configuration Register (DEVCFG1)
The factory configuration register is a factory programmed, read only register which contains user specific device configuration
information. The factory configuration register is included in the factory programmed OTP CRC verification.
3.1.2.1 Range Indication Bits (RNG[2:0])
The range indication bits are factory programmed and indicate the full-scale range of the device as shown below.
3.1.3 Device Configuration 2 Register (DEVCFG2)
Device configuration register 2 is a user programmable OTP register that contains device configuration information.
3.1.3.1 User Configuration Lock Bit (LOCK_U)
The LOCK_U bit allows the user to prevent writes to th e user configuration array once programming is complete d.
If the LOCK_U bit is written to ‘1’ when a PSI5 “Execute Programming of NVM” command is executed, the LOCK_U OTP bit
will be programmed. Upon completion of the OTP programming, an OTP readout will be executed, locking the array from future
OTP writes. The User Programmable OTP Array Error Detection is also activated (Reference Section 3.2.2).
3.1.3.2 PCM Enable Bit (PCM)
The PCM bit enables the PCM ou tput pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code
Modulated signal proportional to the acceleration response. Reference Section 3.5.3.7 for more information regarding the PCM
output. When the PCM bit is cleared, the PCM output pin is actively pulled low.
Location Bit
AddressRegister76543210
$04DEVCFG100101RNG[2]RNG[1]RNG[0]
Factory Default00100000
RNG[2] RNG[1] RNG[0] Full-Scale Acceleration
Range g-Cell Design PSI5 Init Data
Transmission (D9)
Reference Table 12
0 0 0 Reserved N/A 0001
0 0 1 ±60g Medium-g 0111
0 1 0 Reserved N/A 0010
0 1 1 ±120g Medium-g 1000
1 0 0 Reserved N/A 0011
1 0 1 ±240g High-g 1001
1 1 0 Reserved N/A 0100
1 1 1 ±480g High-g 1010
Location Bit
Address Register 76543210
$05 DEVCFG2 LOCK_U PCM SYNC_PD LATENCY DATASIZE BLANKTIME P_CRC BAUD
Factory Default00000000
PCM PCM Output
0Actively Pulled Low
1PCM Signal Enabled
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3.1.3.3 Sync Pulse Pulldown Enable Bit (SYNC_PD)
The sync pulse pulldown enable bit selects if the sync pulse pulldown is enabled once a sync pulse is detected. Reference
Section 4.2.1.2 for more information regarding th e sync pulse pulldown.
If Daisy Chain Mode is enabled, the Sync Pulse Pu lldown is enabled as listed below:
3.1.3.4 Latency Selection Bit (LATENCY)
The latency selection bit selects between one of two data latency methods to accommodate synchronized sampling or simul-
taneous sampling. Reference Section 4. 5 for more information regarding latency and data synchronization.
3.1.3.5 Data Size Selection Bit (DATASIZE)
The data size selection bit selects one of two data lengths for the PSI5 response message as shown below.
3.1.3.6 PSI5 Sync Pulse Blanking Time Selection Bit (BLANKTIME)
The PSI5 sync pulse blanking time selection bit selects the timing for ignoring sync pulses after successful reception of a sync
pulse. Reference Section 4.2.1.1 for details regarding sync pulse detection and blanking.
3.1.3.7 PSI5 Response Message Error Detection Selection Bit (P_CRC)
The PSI5 response message error detection selection bit selects either even parity, or a 3-Bit CRC for error detection of the
PSI5 response message. Reference Section 4.3.3 for details regarding response message error detection.
Note: The PSI5 specification recommends parity for data lengths of 10 bits or less.
SYNC_PD Sync Pulse Pulldown
0 Disabled
1 Enabled
SYNC_PD Daisy Chain Address
Programmed “Run Mode”
Command Received Daisy Chain Address = ‘001’ Sync Pulse Pulldown
0 x x x Disabled
1 No x x Enabled
1 Yes No x Disabled
1 Yes Yes No Disabled
1 Yes Yes Yes Enabled
Latency Data Latency
0 Simultaneous Sampling Mode (Latency relative to Sync Pulse)
1 Synchronous Sampling Mode (Latency relative to Time Slot)
DATASIZE Data Length
0 10 Bits
1 8 Bits
BLANKTIME Blanking Time Method
0 Maximum of tSYNC_OFF_500 or Response Transmission Complete
1 Blanking Time determined by end of response transmission for programmed time slot
P_CRC Parity or CRC
0Parity
1CRC
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3.1.3.8 Baud Rate Selection Bit (BAUD)
The baud rate selection bit selects one of two PSI5 baud rates as shown below. Reference Section 2.6 for baud rate timing
specifications.
3.1.4 Device Configuration Registers (DEVCFG3, DEVCFG4, DEVCFG5)
Device configuration registers 3, 4, and 5 are user programmable OTP re gisters which contain device configuration
information.
3.1.4.1 PSI5 Transmission Mode Selection Bits (TRANS_MD[1:0])
The PSI5 transmission mode selecti on bits select the PSI5 transmission mode as shown below.
3.1.4.2 Low-Pass Filter Selection Bit (LPF[1:0])
The low-pass filter selection bits select the low-pass filter for the acceleration signal as described below:
3.1.4.3 TimeSlot Selection Bits (TIMESLOTx[9:0])
The timeslot selection bits select the time slot(s) to be used for data transmission. Reference Section 4.5 for details regarding
PSI5 transmission modes and time slots. Accepted ti me slot values are 0.5 μs to 511.5 μs in 0.5 μs increments. Care must be
taken to prevent from programming time slots which violate the PSI5 V ersion 1.3 specification, or time slots which will cause data
contention.
Note: TIMESLOTB is only used for Synchronous Double Sample Rate Mode and 16-Bit Resolution Mode.
BAUD Baud Rate
0 Low Baud Rate (125 kBaud)
1 High Baud Rate (190.5 kBaud)
Location Bit
AddressRegister76543210
$06 DEVCFG3 TRANS_MD[1] TRANS_MD[0] LPF[1] LPF[0] TIMESLOTB[9] TIMESLOTB[8] TIMESLOTA[9] TIMESLOTA[8]
$07 DEVCFG4 TIMESLOTA[7] TIMESLOTA[6] TIMESLOTA[5] TIMESLOTA[4] TIMESLOTA[3] TIMESLOTA[2] TIMESLOTA[1] TIMESLOTA[0]
$08 DEVCFG5 TIMESLOTB[7] TIMESLOTB[6] TIMESLOTB[5] TIMESLOTB[4] TIMESLOTB[3] TIMESLOTB[2] TIMESLOTB[1] TIMESLOTB[0]
Factory Default00000000
TRANS_MD[1] TRANS_MD[0] Operating Mode Reference
0 0 Normal Mode (Asynchronous or Parallel, Synchronous) Section 4.5.1
0 1 Synchronous Double Sample Rate Mode Section 4.5.2
1 0 16-bit Resolution Mode (Two 10-bit Responses) Section 4.5.3
1 1 Daisy Chain Mode Section 4.5.4
LPF[1] LPF[0] Low-Pass Filter Selected
0 0 400 Hz, 3-Pole
0 1 400 Hz, 4-Pole
10 Reserved
11 Reserved
TIMESLOTx[9:0] ASYNC Bit Time Slot Reference
00 0000 0000 0 Default Time Slot (tTIMESLOT_DFLT) from start of Sync Pulse (tTRIG)Section 4.5
1 Asynchronous Mode Section 4.5.1.1
Non-Zero N/A TimeSlot Definition from start of Sync Pulse (tTRIG) in 0.5μs Increments Section 4.5
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18 Freescale Semiconductor, Inc.
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3.1.5 Device Configuration Registers 6, 7, and 8 (DEVCFG6, DEVCFG7, DEVCFG8)
Device configuration registers 6, 7 and 8 are user programmable OTP registers which contain device configuration and user
specific manufacturing information. The user specific manufacturing information bits have no impact on the performance, but are
transmitted during the PSI5 initialization phase 2 in 10-bit mode.
3.1.5.1 Initialization Phase 2 Data Extension Bit (INIT2_EXT)
The initialization phase 2 data extension bit enables or disables data transmission in data fields D27 through D32 of PSI5 Ini-
tialization Phase 2 as shown below.
3.1.5.2 Asynchronous Mode Bit (ASYNC)
The asynchronous mode bit enables asynchronous data transmission as described in Section 3.1.4.3.
3.1.5.3 User Sensing Direction (U_DIR[1:0])
The user sensing direction registers are user programmable OTP registers which contain the module level sensing direction.
This data is transmitted to the main ECU during PSI5 initialization phase 2 in 10-bit mode, as describ ed in Section 4.4.2.1.
3.1.5.4 User Product Revision (U_REV[3:0])
The user product revision registers are user programmable OTP registers which contain the module production revision. The
device supports up to 16 product revisions. This data is transmitted to the main ECU during PSI5 initialization phase 2 in 10-bit
mode, as described in Section 4.4.2.1.
Location Bit
AddressRegister76543210
$09 DEVCFG6 INIT2_EXT ASYNC U_DIR[1] U_DIR[0] U_REV[3] U_REV[2] U_REV[1] U_REV[0]
$0A DEVCFG7 MONTH[3] MONTH[2] MONTH[1] MONTH[0] YEAR[3] YEAR[2] YEAR[1] YEAR[0]
$0B DEVCFG8 UD[2] UD[1] UD[0] DAY[4] DAY[3] DAY[2] DAY[1] DAY[0]
Factory Default 00000000
INIT2_EXT Description
0 D27 through D32 are set to “0000”
1 D27 through D32 are transmitted as defined in Section 4.4.2.1
U_DIR[1] U_DIR[0] Module Sensing Direction
As Defined in AKLV27 PSI5 Init Data Transmission (D8)
Reference Table 12
0 0 Connector Direction (β) 0000
0 1 Bushing Direction (α) 0100
1 0 Perpendicular to α and β (γ) 1000
1 1 Not used 1100
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3.1.5.5 User Production Date Information (YEAR[3:0], MONTH[3:0], DAY[4:0)
The user production date informa tion registers are user programmable OTP registers which contain the module production
date. The table below shows the relationship between the stored values and the production date.
The Julian date value is transmitted to the main ECU during PSI5 initialization phase 2 in 10-bit mode, as described in
Section 4.4.2.1.
3.1.5.6 User Specific Data (UD[2:0])
The user specific data bits are user programmable OTP bits. These bits have no impact on device operation or performance.
Programmed Value Decoded Value Julian Date Value
YEAR[3:0] Year JY[6:0]
0000 2009 0001001
•
•
•
•
•
•
•
•
•
1111 2024 0011000
MONTH[3:0] Month JM[3:0]
0000 N/A 0000
0001 January 0001
•
•
•
•
•
•
•
•
•
1100 December 1100
•
•
•
•
•
•
•
•
•
1111 N/A N/A
DAY[4:0] Day JD[4:0]
00000 N/A 00000
00001 Day 1 00001
•
•
•
•
•
•
•
•
•
11111 Day 31 11111
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3.1.6 Status Check Register (SC)
The status check register is a read-only register containing device status information.
3.1.6.1 Test Mode Flag (TM_B)
The test mode bit is cleared if the device is in test mode.
3.1.6.2 Internal Data Error Flag (IDEN_B)
The internal da ta error bit is cleared if a register data error detection is detected in the user accessible OTP array. A device
reset is required to clear the error.
3.1.6.3 Offset Cancella tion Init Status Flag (OC_INIT_B)
The offset cancellation initialization status bit is set once the offset cancellation initialization process is complete, and the filter
has switched to normal mode.
3.1.6.4 Internal Factory Data Error Flag (IDEF_B)
The internal factory data error bit is cleared if a register data CRC fault is detected in the factory programmable OTP array. A
device reset is required to clear the error.
3.1.6.5 Offset Error Flag (OFF_B)
The offset error flag is cleared if the acceleration signal reaches the offset limit.
Location Bit
AddressRegister76543210
$0C SC 0 TM_B RESERVED IDEN_B OC_INIT_B IDEF_B OFF_B 0
TM_B Operating Mode
0 Test Mode is active
1 Test Mode is not active
IDEN_B Error Condition
0 Error detection mismatch in user programmable OTP array
1 No error detected
OC_INIT_B Error Condition
0 Offset Cancellation in initialization
1 Offset Cancellation initialization complete (tOC1 and tOC2 expired)
IDEF_B Error Condition
0 CRC error in factory programmable OTP array
1 No error detected
OFF_B Error Condition
0 Offset error detected
1 No error detected
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3.1.7 Manufacturer ID (MFG_ID)
The manufacturer ID register is a user programmable OTP register that contains the PSI5 manufacturer ID. The manufacturer
ID register has no impact on the performance, but is transmitted during the PSI5 initialization phase 2 in 10 -bit mode.
3.2 O TP Array CRC Verification
3.2.1 Factory Programmed OTP Array CRC Verification
The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC veri fication is enabled only when the
factory programmed array is locked. The CRC verification uses a generato r polynomial of g(x) = X3 + X + 1, with a seed
value = ‘111’.
Once the CRC verification is enabled, the CRC is continuously calculated on all bits in registers $00, $01, $02, $03, and $04
and on the factory programmable device configuration bits with the exception of the factory lock bit. Bits are fed in from right to
left (LSB first), and top to bottom (lower addresses first) in the register map. The calculated CRC is then compared against the
stored 3 bit CRC. If a CRC error is detected in the OTP array, the IDEF_B bit is cleared in the SC register.
The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array val-
ues.
3.2.2 User Programmable OTP Array Error Detection
The user programmable OTP array is independently verified for errors. The Error Detection is enabled only when the LOCK_U
bit in the user da ta register array is set.
When a PSI5 Programming Mode “Execute Programming of NVM” command is received and the LOCK_U bit is set, the device
calculates the error detection code and writes the code to NVM, enabling the Error Detection.
Once the error detection is enabled, the error detection code is continuously calculated on all bits in registers $05, $06, $07,
$08, $09, $0A, $0B and $0D with the exception of the LOCK_U bit. The calculated code is then compared against the stored
error code. If a mismatch is detect ed, the IDEN_B bit is cleared in the SC register.
The error detection is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
Location Bit
AddressRegister76543210
$0D MFG_ID MFG_ID[7] MFG_ID[6] MFG_ID[5] MFG_ID[5] MFG_ID[3] MFG_ID[2] MFG_ID[1] MFG_ID[0]
Factory Default 00000000
MFG_ID PSI5 Init Data Transmission (D$, D5)
Reference Table 10
0000 0000 D4 = 0100
D5 = 0110
Other D4 = MFG_ID[7:4]
D5 = MFG_ID[3:0]
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3.3 Voltage Regulators
The device derives its internal supply voltage from the VCC and VSS pins. Separate internal voltage regulators are used for the
analog (VREGA) and digital circuitry (VREG). The analog and digital regulators are supplied by a buffer regulator (VBUF) to provide
immunity from EMC and supply dropouts on VCC. External filter capacitors are required, as shown in Figure 1.
The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the
internal voltages have increased above the under-voltage detection thresholds. The voltage monitor asserts internal reset when
the external supply or internally regulated voltages fall below the under-voltage detection thresholds. A reference generator pro-
vides a reference voltage for the ΣΔ converter.
Figure 8. Voltage Regulation and Monitoring
VREGA
VREG
VCC
VOLTAGE
REGULATOR
REFERENCE
GENERATOR
VREGA = 2.50 V
DIGITAL
LOGIC
DSP
OTP
ARRAY
OSCILLATOR
ΣΔ
CONVERTER
BIAS
GENERATOR
TRIM TRIM
V
REF
VREF_MOD = 1.250 V
VREG = 2.50 V
VOLTAGE
REGULATOR VBUF
BANDGAP
REFERENCE
VBUF
VBUF
V
REF
V
REGA
VREF
POR
V
CC
COMPARATOR
V
REF
COMPARATOR
COMPARATOR
V
BUF
COMPARATOR
V
REGA
V
REG
VOLTAGE
REGULATOR
Micro-cut
TRIM
TRIM
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3.3.1 VBUF, VREG, and VREGA Regulator Capacitor
The internal regu lators require an external capacitor between each of the regulator pins (VBUF, VREG, or VREGA) and the as-
sociated the VSS / VSSA pin for stability. Figure 1 shows the recommended types and values for each of these capacitors.
3.3.2 VCC, VBUF, VREG, and VREGA Under-Voltage Monitor
A circuit is incorporated to monitor the supply voltage (VCC) and all internally regulated voltages (VBUF, VREG, and VREGA). If
any of internal regu lator voltages fall below the speci fied under-voltage thresholds in Section 2, the device will be reset. If VCC
falls below the specified threshold, PSI5 transmissions are terminated for the present response. Once the supply returns above
the threshold, the device will respond to the next detected sync pulse. Referen c e Figure 9.
Figure 9. VCC Micro-Cut Response
VCC
POR
VREG
Time
VBUF
VREGA
VCC under-voltage detected
Response Terminated
IDATA
VCC micro-cut occurs
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3.3.3 VBUF, VREG, and VREGA Capacitance Monitor
A monitor circuit is incorporated to ensure predictable operation if the conne ction to the external VBUF, VREG, or VREGA, ca-
pacitor becomes open.
In asynchronous mode, the VBUF regulator is disabled tCAPTEST_ADLY seconds after each data transmission for a duration of
tCAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold,
forcing a device reset.
In synchronous mode, the VBUF regulator is disabled tCAPTEST_SDLY seconds after each sync pulse for a duration of
tCAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold,
forcing a device reset.
The VREG and VREGA regulators are disabled at a continuous rate (tCAPTEST_RATE), for a duration of tCAPTEST_TIME seconds.
If either external capacitor is not present, the associated regulator voltage will fall below the internal reset threshold , forcing a
device reset.
Figure 10. VBUF Capacitor Monitor - Asynchronous Mode
Figure 11. VBUF Capacitor Monitor - Synchronous Mode
CAP_Test
V
BUF
Time
Capacitor Present
V
BUF_UV_f
POR
Capacitor Open
tCAPTEST_TIME
IDATA
tCAPTEST_ADLY
CAP_Test
V
BUF
Time
Capacitor Present
V
BUF_UV_f
POR
Capacitor Open
tCAPTEST_TIME
VCC
tCAPTEST_SDLY
tTRIG
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Figure 12. VREG Capacitor Monitor
Figure 13. VREGA Capacitor Monitor
3.4 I nternal Oscillator
A factory trimmed oscillator is included as specified in Section 2.
CAP_Test
V
REG
Time
Capacitor Present
POR
Capacitor Open
tCAPTEST_TIME
tCAPTEST_RATE
V
PORVREG_f
CAP_Test
V
REGA
Time
Capacitor Present
V
PORREGA_f
POR
Capacitor Open
tCAPTEST_TIME
tCAPTEST_RATE
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3.5 Acceleration Signal Path
3.5.1 Transducer
The transducer is an overdamped mass-spring-damper system define d by the following transfer function:
where:
ζ = Damping Ratio
ωn = Natural Frequen cy = 2 ∗ Π ∗ fn
Reference Section 2.7 for transducer parameters.
3.5.2 ΣΔ Converter
A sigma delta modulator converts the differential capacitance of the transducer to a 1 MHz data stream that is input to the DSP
block.
Figure 14. ΣΔ Converter Block Diagram
3.5.3 Digital Signal Processing Block
A Digital Signal Processing (DSP) block is used to perform signal filtering and compensation. A diagram illustrating the signal
processing flow within the DSP block is shown in Figure 15.
Figure 15. Signal Chain Di agram
Hs()
ωn
2
s22ξω
ns⋅⋅ ⋅ ω
n
2
++
---------------------------------------------------------=
1-BIT
QUANTIZER
z
-1
1 - z
-1
z
-1
1 - z
-1
FIRST
INTEGRATOR SECOND
INTEGRATOR
α
1
=
β
1
α
2
β
2
V
X
C
INT1
g-CELL
C
BOT
C
TOP
Δ
C = C
TOP
- C
BOT
ΣΔ
_OUT
V =
±
2
×
V
REF
ADC
DAC
V =
Δ
C x V
X
/ C
INT1
ΣΔ
_OUT
SINC FILTER LOW-PASS FILTER
OUTPUT
OUTPUT
COMPENSATION
ABCD
INTERPOLATION
SCALING
F
OFFSET
RATE LIMITING
OFFSET CANCELLATION
DOWNSAMPLING LOW-PASS FILTER
E
CANCELLATION
OUTPUT
GH
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3.5.3.1 Decimation Sinc Filter
The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc
filter with a decimation factor of 16.
Figure 16. Sinc Filter Response, tS = 16 μs
Table 3. Signal Chain Characteristic s
Description Sample
Time
(μs)
Data
Width
(Bits)
Over
Range
(Bits
Signal
Width
(Bits)
Signal
Noise
(Bits)
Signal
Margin
(Bits) Typical Block Latency Reference
ASD 1 1 1 203/fosc Section 3.5.2
BSINC Filter 16 20 13 Section 3.5.3.2
CLow-Pass Filter 16 26 410 3 9 Reference Section 3.5.3.2 Section 3.5.3.2
DCompensation 16 26 410 3 9 68/fosc
EDown Sampling 16 26 410 3 9
FHigh Pass Filter 16 26 410 3 9 Reference Section 3.5.3.3 Section 3.5.3.3
GDSP Sampling 16 10 4/fosc Section 3.5.3.5
10-Bit Output Scaling
HInterpolation 110 64/fosc Section 3.5.3.5
Hz() 1z
16
–
–
16 1 z 1–
–()×
-------------------------------------3
=
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3.5.3.2 Low-Pass Filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter.
The device provides the option for one of two low-pass filters. The filter is selected with the LPF[1:0] bits in the DEVCFG3
register . The filter selection options are listed in Section 3.1.4.2. Response parameters for the low-pass filter are specified in Sec-
tion 2.7. Filter characteristics are illustrated in Figure 17 and Figure 18.
Note: Low-Pass Filter values do not include g-cell frequency response.
Table 4. Low-Pass Filter Coefficients
Description Filter Coefficients Group Delay
400 Hz, 3-Pole LPF
a05.189235225042199e-02
2816/fosc
n11 1.629077582099646e-03 d11 1.0
n12 1.630351547919014e-03 d12 -9.481076477495780e-01
n13 0d
13 0
n21 2.500977520825902e-01 d21 1.0
n22 4.999999235890745e-01 d22 -1.915847097557409e+00
n23 2.499023243303036e-01 d23 9.191065266874253e-01
400 Hz, 4-Pole LPF
a03.143225986084408e-03
3392/fosc
n11 9.951105668343345e-04 d11 1.0
n12 2.003487780064749e-03 d12 -1.892328151433503e+00
n13 1.008466113720278e-03 d13 8.954713774195870e-01
n21 2.516720624825626e-01 d21 1.0
n22 4.999888752940916e-01 d22 -1.918978239761011e+00
n23 2.483390622233452e-01 d23 9.229853042218408e-01
Hz() a0n11 z0
⋅()n12 z1–
⋅()n13 z2–
⋅()++
d11 z0
⋅()d12 z1–
⋅()d13 z2–
⋅()++
------------------------------------------------------------------------------------------------- n21 z0
⋅()n22 z1–
⋅()n23 z2–
⋅()++
d11 z0
⋅()d22 z1–
⋅()d23 z2–
⋅()++
-------------------------------------------------------------------------------------------------
⋅⋅=
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Figure 17. Low-Pass Filter Characteristics: fC = 400 Hz, 4-Pole, tS = 16 μs
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Figure 18. Low-Pass Filter Characteristics: fC = 400 Hz, 3-Pole, tS = 16 μs
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3.5.3.3 Offset Cancellation
The device provides an optional offset cancellation circuit to remove internal offset error. A block diagram of the offset cancel-
lation is shown in Figure 19.
Figure 19. Offset Cancellation Bloc k Diagram
The transfer function for the offset LPF is:
Response parameters are specified in Section 2 and the offset LPF coefficients are specified in Table 6.
During startup, two phases of the offset LPF are used to allow for fast convergence of the internal offset error during initializa-
tion. The timing and characteristics of each phase are shown in Table 5 and Table 6 and specified in Section 2. For more infor-
mation regarding the startup timing, reference the PSI5 initialization information in Section 4.4. The offset low-p ass filter used in
normal operation is selected by the OC_FILT bit as shown in Table 5.
During the Initialization Self-Test phase, the offset cancellation circuit output value is frozen.
During normal operation, output rate limiting is applied to the output of the high pass filter. Rate limiting updates the offset
cancellation output by OFFStep_xx LSB every tOffRate_xx seconds.
Table 5. Offset Cancellation Startup Characteristics and Timing
Offset Cancellation
Startup Phase Offset LPF Output Rate Limiting Total Time for Phase
110 Hz Bypassed 80 ms
20.3 Hz Bypassed 70 ms
Self-Test 0.3 Hz Bypassed (Frozen during ST2) 96 ms per Self-Test Sequence (up to 6 repeats)
Complete 0.1 Hz Enabled N/A
TO_OUTPUT SCALING
OFFSET CANCELLATION
a0
n1n2z1–
⋅()+
d1d2z1–
⋅()+
-------------------------------------
⋅
LOW-PASS FILTER
INPUT DAT A
INC/DEC
COUNTER
CLK
OUT
0.5 Hz (Der ived from f
OSC
)
OFFMONNEG
OFFMONPOS
OFF_ERR
INC/DEC
COUNTER
CLK
OUT
UP/DOWN
2 kHz (Derived from f
OSC
)
OFFMONCNTLIMIT
Input Data downsampled to 256
μ
s
Hz() ao0no1no2z1–
⋅()+
do1do2z1–
⋅()+
----------------------------------------------
⋅=
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Figure 20. 10 Hz Offset Cancellation Low-Pass Filter Characteristics
Figure 21. 0.1 Hz Offset Can cellation Low-Pass Filter Characteristics
Table 6. High Pass Filter Coefficients
Description Coefficients Group Delay
10 Hz HPF
ao00.015956938266754
16.384 msno10.499998132328277 do11.0
no20.499998132328277 do2-0.984043061733246
0.3 Hz HPF
ao00.000482380390167
537.6 msno10.499938218213271 do11.0
no20.499938218213271 do2-0.999517619609833
0.1 Hz HPF
ao00.0001608133316040
1591msno10.4999999403953552 do11.0
no20.4999999403953552 do2-0.9998391270637512
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3.5.3.4 Offset Monitor
The device includes an offset monitor circuit. The output of the single pole low-pass filter in the offset cancellation block is
continuously monitored against the offset limits specified in Section 2.4. An up/down counter is employed to count up If the output
exceeds the limits, and to count down if the output is within the limits. The output of the counter is compared against the count
limit OFFMONCNTLIMIT. If the counter exceeds the limit, the OFF_B flag in the SC register is cleared. The counter rails once the
max counter value is reached (OFFMON CNTSIZE). The offset monitor is disabled during Initialization Phase 1, Phase 2, and
Phase 3.
3.5.3.5 Data Interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital
signal processing chain is dela y ed one sample time. On detection of a syn c pulse the transmitted data is interpolated from the
2 previous samples, resulting in a latency of one sample time, and a maximum signal jitter of ±1/16 of a sample time. Reference
Section 4.5 for more information regarding interpolation and data latency.
3.5.3.6 Output Scaling
The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-bit word which spans the acceleration range of the
device. Figure 22 shows the method used to establish the output accele ration data word from the 26-b i t DSP output.
Figure 22. 10-Bit Output Scaling Diagram
3.5.3.7 PCM Output Function
The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2
register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the 10-bit
acceleration response is output onto the PCM pin. The PC M output is intended for test use only.
Figure 23. PCM Output Function Block Diagra m
Over Range Signal Noise Margin
D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 ... D2 D1 D0
8-bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 Using Rounding
10-bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 Using Rounding
Output Scaling
D[21:13]
A
9 Bit ADDER
PCM
B
CARRY
SUM
fCLK = 4 MHz
Sample updated every 16μS9
9
9
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
Section 3.5.3.6
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3.6 O verload Response
3.6.1 Overload Performance
The device is designed to operate within a specified range. Acceleration beyond that range (overload) impacts the output of
the sensor. Accelera tion beyond the range of the device can generate a DC shift at the output of the device that is dependent
upon the overload frequency and amplitude. The g-cell is overdamped, providing the optimal design for overload performance.
However, the perfo r mance of the device during an overload cond ition is affected by many other parameters, including:
• g-cell damp ing
• Non-linearity
• Clipping limits
• Symmetry
Figure 24 shows the g-cell, ADC and output cli pping of The device over frequency. The relevant parameters are specified in
Section 2.
Figure 24. Output Clipping vs. Frequency
3.6.2 Sigma Delta Modulator Over Range Response
Over Range conditions exist when the signa l level is beyond the full-scale range of the device but within the computational
limits of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates
predictably under all cases of over range, although the signal may include residual high frequency components for some time
after returning to the normal range of operation due to non-linear effects of the sensor.
5kHz fg-Cell fLPF
gADC_Clip
gg-cell_Clip
Determined by g-cell
10kHz
g-cellRolloff
Acceleration (g)
Frequency (kHz)
LPFRolloff
Region Clipped by g-cell
Region Clipped by ADC
Region of Signal Distortion due to
Asymmetry and Non-Linearity
Region of No Signal Distortion Beyond
Specification
Region of Interest
roll-off and ADC clipping
gRange_Norm
Determined by g-cell
roll-off and full-scale range
Region Clipped
by Output
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4 PSI5 Layer and Protocol
4.1 Communication Interface Overview
The communication interface betwe en a master device and the MMA51xx is established via a PSI5 compatible 2-wire inter-
face, with parallel or serial (daisy-chain) connections to the satellite modules. Figure 25 shows one possible system configuration
for multiple satellite modules in parallel.
Figure 25. PSI5 Satellite Interface Diagram
4.2 D ata Transmission Physical Layer
The device us es a two wire i nterfa ce for bo th it s po wer supp ly (VCC), and data transmission. The PSI5 master supplies a pre-
regulated voltage. Data transmissions and synchronization control from the PSI5 master to the device are accomplished via mod-
ulation of the supply voltage. Data transmissions from the device to the PSI5 master are accomplished via modulation of the cur-
rent on the power supply line.
4.2.1 Synchronization Pulse
The PSI5 master modulates the supply voltage in the positive direction to provide synchronization of the satellite sensor data.
Upon reception of a synchronization pulse, the device delays a specified period of time, called a time slot, before transmitting
acceleration data. For more details regarding time slots, refer to Section 3.1.4, and Section 4.5.
Figure 26. Synchronous Communication Overview
MMA51xx
VCC
IData
SATELLITE MODULE #1
VCC
VSS
VCC_OUT
VSS_OUT
MASTER DEVICE
SATELLITE MODULE #2
VCC
VSS
VCC_OUT
VSS_OUT
Discrete
Components
Discrete
Components
VSS
VCC
IData
VSS
MMA51xx
GND
VIDLE
SYNC PULSES
VIDLE+ ΔVSYNC
IIDLE
IIDLE + IMOD
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4.2.1.1 Synchronization Pulse Detection
The Synchronization (Sync) pulse detection block generates a valid synchronization pulse signal following the detection of an
externally generated Sync pulse. This signal resets the Sync pulse time reference (tTRIG), and initiates the timers associated with
response messages.
The supply voltage can vary throughout the specified range, so the external Sync pulses may have different absolute voltage
levels. Thus, the Sync pulse detection threshold (VCC_SYNC) is dependent not only on the Sync pulse absolute voltage, but also
on the supply voltage. Figure 27 shows a block diagram of the Sync pulse detection circuit.
Figure 27. Synchronizati on Pulse Detection Circuit
The start of a Sync pulse is detected when the comparator output is set (VSYNC exceeds VSYNC_REF). The comparator output
is input into a counter, and the counter is updated at a fixed frequency of fOSC/2. At a fixed time after the initial sync pulse detection
(tSYNC_LPF_RST_ST), the counter is compared against a limit (the minimum value of tSYNC). If the counter is above the limit, a valid
sync pulse is detected.
If the Sync pulse is valid, the following occur:
1. The valid Sync pulse detection signal is set.
2. The detection counter is reset and disabled for tSYNC_OFF (referenced from tTRIG). tSYNC_OFF is a user
programmable option. Reference Section 3.1.3.6 for details on the selectable option, and Sectio n 2.6 for timing
specifications for each option.
a. If BLANKTIME = ‘0’, tSYNC_OFF = tSYNC_OFF_500
b. If BLANKTIME = ‘1’, tSYNC_OFF=tSYNC_OFF_VAR= tTIMESLOT_DLYx + (2+DATASIZE+(P_CRC?3:1)) *tBIT_x
3. The Sync pulse detection low-pass filter is reset for a specified time (tSYNC_LPF_RESET).
If the Sync pulse is invalid, all timers are reset, and the detector becomes sensitive for the very next f SYNC_DET sample.
The output of the comparator is monitored at the fOSC/2 freque ncy. Once the comparator output goes high, all of the internal
timers are started, so that the tTRIG jitter is minimized.
fOSC/2
SYNC_OFF
VCC
SYNC_LPF_RESET
VSS
SYNC_DET
SYNC_OFFSET
SYNC_LPF
D
R
COUNTER
CONTROL
LOGIC
SYNC_LPF_RESET
VSYNC_REF
V
SYNC_COMP
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Figure 28. Synchroniza ti on Pulse Detection Timing
4.2.1.2 Synchronization Pulse Pulldown Function
The device includes an optional Sync pulse pulldown function for systems in which the master device does not include an
active pulldown function. The modulation current pulldown circuit is used, which sinks IMOD-IIDLE additional current from the IDATA
pin. The pulldown current is activated after tPD_DLY (referenced to tTRIG), and is activated for tPD_ON.
4.3 D ata Transmission Data Link Layer
4.3.1 Bit Encoding
The device outputs data by modulation of the VCC current using Manchester 2 Encoding. Data is stored in a transition occurring
in the middle of the bit time. The signal idles at the normal quiescent supply current. A logic low is defin ed as an increase in
current at the middle of a bit time. A logic high is defined as a decrease in current at the middle of a bit time. There is always a
transition in the middle of the bit time. If consecutive “1” or “0” data are transmitted, There will also be a transition at the start of
a bit time.
Figure 29. Manchester 2 Data Bit Encoding
SYNC PULSE
SYNC_LPF_RESET
SYNC OFF
RESPONSE
tTRIG
tSYNC_LPF_RST_ST
tTIMESLOTx
tSYNC_LPF_RST
tSYNC_OFF_xxx
VSYNC_COMP
tA_SYNC_DLY
SYNC_PULSE_PD
tPD_DLY
tPD_ON
IMOD CURRENT ‘0’ BIT
CONSECUTIVE
‘0’ DATA BITS
IDLE CURRENT
‘1’ BIT SENSED HIGH
tBIT SENSED LOW
CONSECUTIVE
‘1’ DATA BITS
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4.3.2 Data Transmission
Transmission frames are composed of two start bits, an 8-Bit or 10-bit data word, and error detection bit(s). Data words are
transmitted least-significant bit (LSB) first. A typical Manchester-encoded transmission frame is illustrated in Figure 30.
Figure 30. Example Manchester Encoded Data Transfer - PSI5-x10P
4.3.3 Error Detection
Error detection of the transmitted data is accomplished via either a parity bit, or a 3-Bit CRC. The type of error detection used
is selected by the P_CRC bit in the DEVCFG register.
4.3.3.1 Parity Error Detection
When parity error detection is selected, even parity is employed. The number of logic ‘1’ bits in the transmitted message must
be an even number.
4.3.3.2 3-Bit CRC Error Detection
When CRC error detection is selected, a 3-bit CRC is appended to each response message. The 3-bit CRC uses a generator
polynomial of g(x) = X3+X+1, with a seed value = ‘111’. Data from the transmitted message is read into the CRC calculator LSB
first, and the data is augmented with three ‘0’s. St art bits are not used in the CRC calculation.Table 7 shows some example CRC
calculation values for 10-bit data transmissions.
Table 7. PSI5 3-Bit CRC Calculation Examples
Data Transmitted CRC
HEX D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C2 C1 C0
0x000 0000000000110
0x0CC 0011001100011
0x151 0101010001000
0x1E0 0111100000011
0x1F4 0111110100010
0x220 1000100000100
0x275 1001110101111
0x333 1100110011001
0x3FF 1111111111100
SB1 SB0 D0 D1 D2 D3 D4 D5 D8 D9 PAR
‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’
Data Bit
Bit Value
D6 D7
‘1’ ‘1’
tFRAME
tBIT tTRAN = tBIT * (2+DATASIZE+(P_CRC?3:1))
IMOD
SB1
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4.3.4 Data Range Values
Table 9 shows the details for each data range.
Table 8. PSI5 Data Values
8-Bit Data Value 10-Bit Data Value Description
Decimal Hex Decimal Hex
+127 $7F
+511 $1FF
Reserved
•
•
•
•
•
•
+502 $1F6
+126 $7E +501 $1F5
+125 $7D +500 $1F4 Sensor Defect Error Message
N/A N/A
+499 $1F3
Reserved
•
•
•
•
•
•
+489 $1E9
+124 $7C +488 $1E8 Sensor Busy
+123 $7B +487 $1E7 Sensor Ready
+122 $7A +486 $1E6 Sensor Ready, but Unlocked
N/A N/A
+485 $1E5
Reserved
•
•
•
•
•
•
+121 $79 +481 $1E1
+120 $78 +480 $1E0 Maximum positive acceleration value
•
•
•
•
•
•
•
•
•
•
•
•Positive acceleration values
+3 $03 +3 $03
+2 $02 +2 $02
+1 $01 +1 $01
00000g level
-1 $FF -1 $3FF Negative acceleration values-2 $FE -2 $3FE
-3 $FD -3 $3FD
•
•
•
•
•
•
•
•
•
•
•
•
-120 $88 -480 $220 Maximum negative acceleration value
-121 $87 -481 $21F Initialization Data Codes
10-Bit Status Data Nibble 1 - 16 (0000 - 1111) (Dx)
8-Bit Status Data Nibble 1 - 4 (00 - 11) (Dx)
•
•
•
•
•
•
•
•
•
•
•
•
-124 $84 -496 $210
-125 $83 -497 $20F Initialization Data IDs
Block ID 1 - 16 (10-bit Mode) (IDx)
Block ID 1 - 4 (8-Bit Mode) (IDx)
•
•
•
•
•
•
•
•
•
•
•
•
-128 $80 -512 $200
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4.4 Initialization
Following powerup, the device proceeds through an initialization process which is divided into 3 phases:
• Initialization Phase 1: No Data transmissions occur
• Initialization Phase 2: Sensor self-test and transmission of configuration information
• Initialization Phase 3: Transmission of “Sensor Busy”, and “Sensor Ready” / “Sensor Defect” message
Once initializati on is completed the device begins normal mode operation, which continues as long as the supply voltage re-
mains within the specified limits.
Figure 31. PSI5 Sensor 10-Bit Initial izatio n
During PSI5 initialization, the device completes an internal initialization process consisting of th e following:
• Power-on Reset
• Device Initialization
• Program Mode Entry Verification
• Offset Cancellation Initialization (2 Stages)
•Self-Test
Figure 32 shows the timing for internal and external initialization.
Figure 32. Initiali zation Timing
INIT 1 INIT 3 NORMAL MODE
INIT 2
Normal Mode
...
POR
GND
VIDLE
VIDLE+ ΔVSYNC
IIDLE
IIDLE + IMOD
Sync Pulses Ignored or
Program Mode Entry Sync Pulses
tINT_INIT
tPSI5_INIT1
Self-Test
Raw Offset
Calculation
PSI5 Initialization
Phase 1
tPSI5_INIT2 tPSI5_INIT3
PSI5 Initialization
Phase 2
PSI5 Initialization
Phase 3
PSI5
Normal Mode
POR
Internal
Delay tOC1
Offset Cancellation
Stage 1
tST1
Self-Test
Deflection
Verification
tST2
Self-Test
Normal Data
Calculation
tST3 ST_RPT * tST
Self-Test
Repeat
(If Necessary)
tOC2
Offset Cancellation
Stage 2
Programming Mode Entry
1) Min. 31 sync pulses
2) PME command
Sync
Pulses
Ignored
tRS_PM tPME
No
PM
Entry
PM
Entry
tPROG_MODE_START_DELAY
No Transmissions
In Response to
Sync Pulses Programming
Mode
Otherwise
Sync Pulses Ignored
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4.4.1 PSI5 Initialization Phase 1
During PSI5 initialization phase 1, the device begins internal initialization and self checks, but transmits no dat a. Initialization
begins with the sequence below and shown in Figure 32:
• Internal Delay to ensure analog circuitry has stabilized (tINT_INIT)
• Offset Cancellation pha se 1 Initialization (tOC1)
• Monitor for the Programming Mode Entry Sequence (tPME)
– A sequence of sync pulses received during the program mode entry window in PSI5 initialization phase 1
will allow the device to enter into a PSI5 programming mode if the LOCK_U bit is not set. Reference
Section 5.2 for details.
• Offset Cancellation pha se 2 Initialization (tOC2)
• If the Programming Mode Entry Sequence is not detected, the device enters Initialization Phase 2 (tPSI5_INIT2)
4.4.2 PSI5 Initialization Phase 2
During PSI5 initialization phase 2, the device continues it’s internal self checks and transmits the PSI5 initialization phase 2
data. The PSI5 initialization data transmission format varies depending on whether the device is programmed for 8-bit or 10-bit
data. Initialization is transmitted using the initialization data codes and IDs specified in Table 12, and in the order shown in
Figure 33 and Figure 34.
Figure 33. PSI5 Initialization Phase 2 Data Tran smission Order (10-bit Mode)
Figure 34. PSI5 Initialization Phase 2 Data Transmission Order (8-bit Mod e)
The Initialization phase 2 time is calculated with the following equation:
where: • TRANSNIBBLE = # of Transmissions per Data Nibble
2 for 10-bit Data: 1 for ID, and 1 for Data
4 for 8-bit Data: 2 for ID, and 2 for Data
• k = the repetition rate for the data fields
• Data Fields = 32 data fields for 10-bit data, 9 data fields for 8-bit data
•t
S-S = Sync Pulse Period
D1 D2 ... D32
ID11D11ID12D12... ID1kD1kID21D21ID22D22... ID2kD2k... ID321D321ID322D322... ID32kD32k
Repeat k times Repeat k times ... Repeat k times
D1 D2 ... D9
ID1H
1D1H1ID1H
2D1H2... ID1H
kD1HkID1L
1D1L1ID1L
2D1L2... ID1L
kD1Lk... ID9L
1D9L1ID9L
2D9L2... ID9L
kD9Lk
Repeat k times Repeat k times ... Repeat k times
tPHASE2 TRANSNIBBLE k×DataFields()tSS–
××=
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4.4.2.1 PSI5 Initialization Phase 2 (10-Bit Mode)
In PSI5 initialization phase 2, 10-bit mode, the device transmits a sequence of sensor specific configuration and serial number
information. The transmission data is in conformance with the PSI5 specification, Revision 1.3 and AKLV27, Revision 1.10. The
data content and transmission format is shown in Table 9 and Table 10. Table 9 shows the 10-bit phase 2 timing for different op-
erating modes. Times are calculated using the equation in Section 4.4.2.
1. Offset and average se lf-test data will only be transmit ted with sync pulse periods that guarantee the self-test phase1 and phase 2 will be complete prior to
required transmission. If sync pulse periods faster than this are used, ‘0’ s will be transmitted inste ad of offset and/or average self-test data.
Table 9. Initialization Phase 2 Time (10-Bit Mode)
Operating Mode Repetition Rate (k) # of Transmissions Nominal Phase 2 Time
Asynchronous Mode (228 μs) 8 512 116.7 ms
Synchronous Mode (500 μs) 4 256 128.0 ms
Table 10. PSI5 Initialization Phase 2 Data (10-Bit Mode)
PSI5 V1.2
Field ID # PSI5 V1.2
Nibble ID # Page
Address PSI5 Nibble
Address Register Address Description Value
F1 D1
0
0000 Hard-coded Protocol Revision = V1.3 0100
F2 D2, D3 0001, 0010 Hard-coded Number of Data Blocks = 32 0010 0000
F3 D4, D5 0011, 0100 MFG_ID Manufacturer ID User
F4 D6, D7 0101, 0110 Hard-coded S ensor Type = Acceleration (high-g) 0000 0001
F5
D8 0111
U_DIR[1:0] = 00: 0000
U_DIR[1:0] = 01: 0100
U_DIR[1:0] = 10: 1000
U_DIR[1:0] = 11: 1100 (not used)
Axis User
D9 1000
±60g: 0111
±120g: 1000
±240g: 1001
±480g: 1010
Range Varies
F6 D10 1001 DEVCFG2[7:4] Sensor Specific Information User
D11 1010 DEVCFG2[3:0] Sensor Specific Information User
F7 D12 1011 Hard-coded Product Revision Factory
D13 1100 Hard-coded Product Revision Factory
D14 1101 DEVCFG6[3:0] Product Revision User
F8
D15 1110 DEVCFG7[7:0], DEVCFG8[4:0]
converted to
Binary coded Julian Date
Reference Section 3.1.5.5
JY[6:3] User
D16 1111 JY[2:0], JM[3] User
D17
1
0000 JM[2:0], JD[1] User
D18 0001 JD[3:0] User
F9
D19 0010 SN0 (High Nibble) MMA51xx Serial Number Factory
D20 0011 SN0 (Low Nibble) MMA51xx Serial Number Factory
D21 0100 SN1 (High Nibble) MMA51xx Serial Number Factory
D22 0101 SN1 (Low Nibble) MMA51xx Serial Number Factory
D23 0110 SN2 (High Nibble) MMA51xx Serial Number Factory
D24 0111 SN2 (Low Nibble) MMA51xx Serial Number Factory
D25 1000 SN3 (High Nibble) MMA51xx Serial Number Factory
D26 1001 SN3 (Low Nibble) MMA51xx Serial Number Factory
D27 1010 Initial Raw Offset (Offset[3:0]) Raw Offset1
(If INIT2_EXT=1, ‘0000’ otherwise) Varies
D28 1011 Initial Raw Offset (Offset7:4]) Raw Offset1
(If INIT2_EXT=1, ‘0000’ otherwise) Varies
D29 1100 ([AvgSelfTest[1:0],Offset[9:8]]) Raw Off/Avg ST1
(If INIT2_EXT=1, ‘0000’ otherwise) Varies
D30 1101 Average Self-Test
(AvgSelfTest[5:2]) Avg Self-Test1
(If INIT2_EXT=1, ‘0000’ otherwise) Varies
D31 1110 Average Self-Test
(AvgSelfTest[9:6]) Avg Self-Test1
(If INIT2_EXT=1, ‘0000’ otherwise) Varies
D32 1111 DEVCFG1 [7:4] Sensor Specific
(If INIT2_EXT=1, ‘0000’ otherwise) 0010
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4.4.2.2 Initialization Phase 2 (8-Bit Mode)
In PSI5 initialization phase 2, 8-bit mode, the device transmits a sequence of sensor specific configuration and serial number
information. The transmission data uses a format similar to the PSI5 specification, Revision 1.3 10-bit format modified for 8-bit
transmission. The data content and transmission format is shown in Table 11 and Table 12. Table 11 shows the 8-bit phase 2
timing for different operating modes. Times are calculated using the equation in Section 4.4.2.
Table 11. Initialization Phase 2 Time (8-Bit Mode)
Operating Mode Repetition Rate (k) # of Transmissions Nominal Phase 2 Time
Asynchronous Mode 0 (228 μs) 16 576 131.3 ms
Synchronous Mode (500 μs) 8 288 144.0 ms
Table 12. PSI5 Initialization Phase 2 Data (8-Bit Mode)
PSI5 V1.2
Field ID # PSI5 V1.2
Nibble ID # Page
Address PSI5 Half-Nibble
Address Register Address Description Value
F1 D1 H 0 00 Hard-coded Protocol Revision = V1.3 01
F1 D1 L 0 01 Hard-coded Protocol Revision = V1.3 00
F2 D2 H 0 10 Hard-coded Number of Data Blocks = 9 00
F2 D2 L 0 11 Hard-coded Number of Data Blocks = 9 10
F2 D3 H 1 00 Hard-coded Number of Data Blocks = 9 00
F2 D3 L 1 01 Hard-coded Number of Data Blocks = 9 00
F3 D4 H 1 10 Hard-coded, MFG_ID[7:6] Manufacturer ID
User
F3 D4 L 1 11 Hard-coded, MFG_ID[5:4] Manufacturer ID
F3 D5 H 2 00 Hard-coded, MFG_ID[3:2] Manufacturer ID
F3 D5 L 2 01 Hard-coded, MFG_ID[1:0] Manufacturer ID
F4 D6 H 2 10 Hard-coded Sensor Type = Acceleration (high-g) 00
F4 D6 L 2 11 Hard-coded Sensor Type = Acceleration (high-g) 00
F4 D7 H 3 00 Hard-coded Sensor Type = Acceleration (high-g) 00
F4 D7 L 3 01 Hard-coded Sensor Type = Acceleration (high-g) 01
F5 D8 H 3 10 U_DIR[1:0] = 00: 0000
U_DIR[1:0] = 01: 0100
U_DIR[1:0] = 10: 1000
U_DIR[1:0] = 11: 1100 (not used)
Axis
User
F5 D8 L 3 11 User
F5 D9 H 4 00 ±60g: 0111
±120g: 1000
±240g: 1001
±480g: 1010
Range
Varies
F5 D9 L 4 01 Varies
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4.4.3 Internal Self-Test
During PSI5 Initialization Phase 2 and Phase 3, the device completes it’s internal self-test as described below and shown in
Figure 32.• Self-Test Phase 1 - Raw Offset Calculation
– The average offset is calculated for tST1 (Self-Test Disabled).
– If the INIT2_EXT bit is set, this 10-bit value is transmitted in Initialization Phase 2 (reference Section 4.4.2).
• Self-Test Phase 2 - Self-Test Deflection Verificati on
– The offset cancellation value is frozen for tST2 + 2ms
– Self-Test is enabled
–After t
ST2/2, the acceleration output value is averaged for tST2/2 to determine the self-test value
– If the INIT2_EXT bit is set, this10-bit value is transmitted in Initialization Phase 2 (reference Section 4.4.2).
– The self-test value is compared against the limits specified in Section 2.5
– Self-Test is disabled
• Self-Test Phase 3 - Self-Test Normal Data Calculation
– The average offset is calculated for tST3
– If Self-Test passed, the device advances to normal mode
– If Self-Test failed, the device repeats Self-Test Phases 1 through 3 up to ST_RPT times.
4.4.4 Initialization Phase 3
During PSI5 initialization phase 3, the device completes it’s internal self checks, and transmits a combination of “Sensor Busy”,
“Sensor Ready”, or “Sensor Defect” messages as defined in Table 8. The number of messages transmitted in initialization phase
3 varies depending on the mode of operation, and the number of self-test repetitions. Self-Test is repeated on failure up to
ST_RPT times to provide immunity to misuse inputs during initialization. Self-Test terminates successfully after one successful
self-test sequence.
Table 13 shows the nominal Initialization Phase 3 times for different operating modes and self-test repeats. Times are ca lcu-
lated using the following equation.
tPSI5INIT3 ROUNDUP tINTINIT tOC1 tOC2 tST1 tST2 tST3
++()STRPT 1+()×+++()tPSI5INIT1 tPSI5INIT2xx
+()–
tSS–
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2+
⎝ ⎠
⎛ ⎞ tSS–
×=
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Table 13. Initialization Phase 3 Time
Operating Mode Self-Test
Repetitions # of Sensor Busy
Messages # of Sensor Ready or Sensor
Defect Messages Nominal Phase 3
Time (ms)
8-Bit Asynchronous Mode 0 (228 μs)
00
2
0.46
1 359 82.31
2 780 178.30
3 1201 274.28
4 1622 370.27
5 2043 466.26
10-Bit Asynchronous Mode 0 (228 μs)
02 0.91
1 423 96.90
2 844 192.89
3 1265 288.88
4 1686 384.86
5 2107 480.85
8-Bit Synchronous Mode (500 μs)
00 1.00
1 138 70.00
2 330 166.00
3 522 262.00
4 714 358.00
5 906 454.00
10-Bit Synchronous Mode (500 μs)
00 1.00
1 170 86.00
2 362 182.00
3 554 278.00
4 746 374.00
5 938 470.00
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4.5 PSI5 Transmission Modes
4.5.1 Normal Mode
4.5.1.1 Asynchronous Mode
The device can be programmed to respond in asynchronous mode with the followi ng settings:
• TRANS_MD[1:0] = ‘00’ (“Normal Mode”)
• ASYNC = ‘1’ in the DEVCFG6 Register
• TIMESLOTA[9:0] = 0x000 in the DEVCFG3 and DEVCFG4 registers
In asynchronous mode, the device transmits data at a fixed rate (tASYNC) and will not respond to normal sync pulses. However ,
during initialization phase 1, sync pulses are monitored to decode the Programming Mode Entry Command and allow entry into
Programming Mode if the LOCK_U bit is not set.
4.5.1.2 Simultaneous Sampling Mode
The device can be programmed to respond in Simultaneous Sampling Mode by setting the TRANS_MD[1:0] bits to “Normal
Mode”, and by programming the LATENCY bit to “Simultaneous Sampling Mode”.
In Simultaneous Sampling Mode, the most recent interpolated acceleration data sample is latched at tTRIG (rising edge of Sync
Pulse) and transmitted starting at the time programmed in TIMESLOTA[9:0], relative to tTRIG.
Figure 35. Simultaneous Sampling Mode
≤ tLAT_INTERP
tTIMESLOTA
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4.5.1.3 Synchronous Sampling Mode with Minimum Latency
The device can be programmed to respond in Synchronous Sampling Mode with minimum latency by setting the
TRANS_MD[1:0] bits to “Normal Mode”, and by programming the LATENCY bit to “Synchronous Sampling Mode”.
In Synchronous Sampling Mode, the most recent interpolated acceleration data sample is latched at the time programmed in
TIMESLOTA[9:0], rel ative to tTRIG (ris ing edge of Sync Pulse). The data is transmitted starting at the time programmed in
TIMESLOTA[9:0], rel ative to tTRIG.
Figure 36. Synchronous Sampling Mode with Minimum Latency
tTIMESLOTA
≤ tLAT_INTERP + tDATASETUP_synch
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4.5.2 Synchronous Double Sample Rate Mode
The device can be programmed to respond in Synchronous Double Sample Rate Mode with minimum latency by setting the
TRANS_MD[1:0] bits to “Synchronous Double Sample Rate Mode”. The LATENCY bit does not affect operation in this mode.
In Synchronous Double Sample Rate Mode, the most recent interpolated acceleration data sample is latched at the time pro-
grammed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync Pulse). This data is transmitted starting at the time pro-
grammed in TIMESLOTA[9:0], relative to tTRIG. In addition, the most recent interpolated acceleration data sample is latched at
the time programmed in TIMESLOTB[9:0], relative to tTRIG (rising edge of Sync Pulse) This data is transmitted starting at the time
programmed in TIMESLOTB[9:0], relative to tTRIG.
When Synchronous Double Sample Rate Mode is enabled, PSI5 Initialization data is transmitted in both TIMESLOT A[9:0] and
TIMESLOTB[9:0]. Identical data is transmitted in both Time slots, including th e 10-bit resolution Raw Offset and Self-Test Data
in Field 9, D27 though D31 if enabled.
Figure 37. Synchronous Double Sample Rate Mode
Note: In the event that the programmed values in TIMESLOTA[9:0] and TIMESLOTB[9:0] result in a conflict, no data will be
transmitted in TIMESLOTB[9:0].
tTIMESLOTA
≤tLAT_INTERP+tDATASETUP_double ≤tLAT_INTERP+tDATASETUP_double tTIMESLOTB
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4.5.3 16-Bit Resolution Mode
The device can be programmed to respond in 16-bit Resolution Mode by setting the TRANS_MD[1:0] bits to “16-bit Resolution
Mode”. In this mode, the 26 bit digital output from the DSP is clipped and scaled to a 16-bit word. Figure 38 shows the method
used to establish the 16-bit data word from the 26 bit DSP output.
Figure 38. 16-Bit Output Scaling Diagram
16-Bit Resolution Mode can be programmed to operate in either “Simultaneous Sampling Mode”, or “Synchronous Sampling
Mode”, by setting the LA TENCY bit to the desired operating mode. In Simultaneous Sampling Mode, the most recent interpolated
acceleration data sample is latched at tTRIG (rising edge of Sync Pulse). In Synchronous Sampling Mode, the most recent inter-
polated acceleration data sample is latched at the time programmed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync
Pulse).
The most significant 10 bits (D[21:12]) are truncated and transmitted starting at the time programmed in TIMESLOT A[9:0], rel-
ative to tTRIG. The 16-bit value is then clipped to ±480 counts, and the least significant 10 bits (D15:D6) are transmitted starting
at the time programmed in TIMESLOTB[9:0], relative to tTRIG.
When 16-Bit Resolution Mode is enabled, PSI5 Initialization data is transmitted in both TIMESLOTA[9:0] and
TIMESLOTB[9:0]. Identical data is transmitted in both Time slot s, including the 10-Bit Resolution Raw Offset and Self-Test Data
in Field 9, D27 though D31 if enabled.
Figure 39. 16-Bit Resolution Mode with Synchronous Samplin g
Note: In the event that the programmed values in TIMESLOTA[9:0] and TIMESLOTB[9:0] result in a conflict, no data will be
transmitted in TIMESLOTB[9:0].
Over Range Signal Noise Margin
D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 ... D2 D1 D0
16-bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Using Rounding
≤tLAT_INTERP + tDATASETUP_16
tTIMESLOTA tTIMESLOTB
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4.5.4 Daisy Chain Mode
The device can be programmed to operate in Daisy Chain Mode by setting the TRANS_MD[1:0] bits to “Daisy Chain Mode”.
Daisy Chain Mode can be programmed to operate in either “Simultaneous Sampling Mode”, or “Synchronous Sampling Mode”
by setting the LA TENCY bit to the desired operating mode. In Simultaneous Sampling Mode, the most recent interpolated accel-
eration data sample is latched at tTRIG (rising edge of Sync Pulse). In Synchronous Sampling Mode, the most recent interpolated
acceleration data sample is latched at the time programmed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync Pulse).
When programmed to operate in Daisy Chain Mode, the procedure below is followed:
• On powerup, the device proceeds through normal PSI5 initialization as specified in Section 4.4 using a predefined
time slot tTIMESLOT_DCP.
• Upon successful completion of Initialization Phase 3, including the 2 “Sensor Ready” or Sensor Defect”
messages, responses to sync. pulses are terminated and the device waits for a PSI5 “Set Address” command
defined in Table 14 and Table 15.
– The Daisy Chain Programming command and response formats are defined in Section 5.4 .
– Valid Daisy Chain Addresses are defined in Table 16.
– The response to the PSI5 Set Address command uses the predefined time sl ot tTIMESLOT_DCP.
• After receiving a valid address and completing the response, sync. pulses are blanked for tDC_BLANKING. Once
the blanking time expires, the device does not respond to any sync. pulses until a “Run Mode” command is
received, as defined in Table 14 and Table 15.
• When the “Run Mode” command is received, the device responds to this command using the programmed daisy
chain time slot. All commands are then ignored, and sync pulses are responded to with acceleration data using
the following response format, regardless of the state of the relevant bits in the Device Configuration Registers:
• During initialization and Run Mode, the Sync pulse pu lldown is enabled as specified in Section 3.1.3.3.
Parameter Reference Value
Time Slot Section 3.1.4.3 Default time slot specified in Table 16
Data Size Section 3.1.3.5 10-bit data
Error Checking Section 3.1.3.7 Even Parity
Baud Rate Section 3.1.3.8 Low Baud Rate: 125 kBaud
Table 14. Daisy Chain Programming Commands and Res p onses
#CMD
Type SAdr FC Command Response (OK) Response (Error)
A2 A1 A0 F2 F1 F0 RC RD1 RC RD1
D0 Short 0 0 0 A2 A1 A0 Set Sensor Address (Daisy Chain) OK SAdr Error ErrN
D1 Short 111000 Broadcast Message - “Run Mode” OK 0x000 Error ErrN
Table 15. Daisy Chain Programming Respo ns e Cod e Defi ni tions
Response Code Definition Value
RC = OK Command Message Received Properly 0x1E1
RC = Error Error during transmission of Command Message 0x1E2
SAdr Programmed Sensor Address, prepended with 0s Varies
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4.6 E rror Handling
4.6.1 Sensor Defect Message
The following failures will cause the device to transmit a “Senso r Defect” error message:
4.6.2 No Response Error
The following failures will cause the device to stop tran smitting:
Table 16. Valid Daisy Chain Addr esses
Sensor Address
(SAdr) Description Bus Switch Control Default Time Slot
A2 A1 A0
0 0 0 Address of unprogrammed sensor N/A N/A
0 0 1 Sensor Address 1 CLOSED tTIMESLOT_DC1
0 1 0 Sensor Address 2 CLOSED tTIMESLOT_DC2
0 1 1 Sensor Address 3 CLOSED tTIMESLOT_DC3
1 0 0 Sensor Address 4 OPEN tTIMESLOT_DC1
1 0 1 Sensor Address 5 OPEN tTIMESLOT_DC2
1 1 0 Sensor Address 6 OPEN tTIMESLOT_DC3
1 1 1 Global Address for Broadcast Message to all Sensors N/A N/A
Error Condition Error Type
Offset Error Temporary (Normal transmissions continue once offset returns within limits)
Self-Test Failure Latched until reset
IDEN_B, IDEF_B flag cleared Latched until reset
Error Condition Error Type
Under-Voltage Failure (VCC) Temporary: Normal transmissions continue once voltage returns above failure limit)
Under- / Over-Temperature Failure Temporary: Normal transmissions continue once temperature returns within the specified limits)
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5 Programming Mode Via PSI5
5.1 Introduction
Programming mode via PSI5 is a synchronous communication mode that allows fo r bidirectional communication with the de-
vice. Programming mode is intended for factory programming of the OTP array. It is not intended for use in normal operation .
5.2 P rogramming Mode Via PSI5 Entry
The device enters programming mode if and onl y if the following sequence occurs:
• The device is unlocked (the LOCK_U bit in the DEVCFG2 register is ‘0’).
• At least 31 sync pulses are detected, directly preceding the Programming Mode Entry Short Command during the
Programming Mode Entry Window shown in Figure 32.
– The window timing is defined in Sectio n 2.6 (tPME).
– The Sync pulses and Programming Mode Entry command must be received with a sync pulse period
of tS-S_PM_L
If the Programming Mode entry requirement is not met:
• Programming Mode Entry is blocked until the device is Reset.
• The device proceeds with PSI5 Initialization Phase 2, and PSI5 Initialization Phase 3.
• The device enters normal mode, and responds as programmed to normal sync pulses.
If the Programming Mode entry requirement is met:
• Normal transmissions to sync pulses are te rminated.
• After a predefined Start Delay, the device begins to decode PSI5 Short and Long Commands.
• The device responds only to valid PSI5 Short and Long Commands addressed to Sensor Address ‘001’, as
defined in Table 18.
Note: The sync pulse pulldown is disabled in the Programming Mode Entry Window regardless of the state of the SYNCPD bit.
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5.3 P rogramming Mode Via PSI5 - Data Link Layer
5.3.1 Programming Mode Via PSI5 - Command Bit Encoding
Commands messages are transmitted via the modulation of the supply voltage. The presence of a sync pulse is a logic '1' and
the absence of a sync pulse is a logic '0'. Sync pulses are expected at a rate of tS-S_PM_L.
5.3.2 Programming Mode Via PSI5 - Command Message Format
Command message data frames consist of a start condition, 3 Start Bits (S[2:0]), a 3 bit Sensor Address (SAdr[2:0]), a 3-bit
Function Code (FC[2:0]), an optional Register Address (RAdr[5:0]), an optional data field (D[3:0]), and a 3-bit CRC (C[2:0]. The
start condition consists of one of the following:
1. A minimum of 5 consecutive logic ‘0’s (with not sync bits)
2. A minimum of 31 consecutive logic ‘1’s
The command message format is shown in Figure 41.
Figure 40. Programming Mode Via PSI5 Command Data Format
Bit stuffing is necessary to maintain a synchronized time base between the command master and the device. A logic ‘1’ Sync
bit is added every 4th bit in the command message to ensure there will never be more than 3 logic '0' bits in a row.
Figure 41. Programming Mode Via PSI5 Command Data Format with Sync Bits
Once a command is received and verified, the device expects 2 to 3 consecutive sync pulses (depending upon the command
message lengths described below). For each of these sync pulses, the device will respond with the following settings:
Figure 42. Programming Mode Via PSI5 Response Message Settings
Start Bits Sensor Address Function Code Register Address Data CRC Response
S2 S1 S0 SA0 SA1 SA2 FC0 FC1 FC2 RA0 RA1 RA2 RA3 RA4 RA5 D0 D1 D2 D3 C2 C1 C0 RC RD1 RD0
0101000100000001111000 $3FF$3FF$3FF
CRC
Data to be written to register (optional)
Register Address (optional)
Function Codes for MMA51xx (Reference Section 5.3.6)
Sensor Address - Fixed at 001 for MMA51xx
Start Bit Sequence = 010
Start Bits Sensor
Address Function Code Register Address Data CRC Response
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy D0 D1 D2 Sy D3 C2 C1 Sy C0 RC RD1 RD0
01011 0 010 0 010 0 010 0 0111111001 0 $1E2 $3FF $3FF
Parameter Register Bits Reference Value
Time Slot N/A N/A tTIMESLOT_DC1
Data Size DATASIZE = 0 Section 3.1.3.5 10-bit data
Error Checking P_CRC = 0 Section 3.1.3.7 Even Parity
Baud Rate BAUD Section 3.1.3.8 125 kBaud
Sync Pulse Pulldown SYNCPD Section 3.1.3.3 Disabled
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5.3.2.1 Short Frame Command and Response Format
Short frames are the simplest type of command message. No data is transmitted in a short frame command. Only specific
instructions are performed in response to short frame commands. The Short Frame format is shown in Figure 43. Short Frame
commands and responses are defined in Section 5.3.6, Table 18.
Figure 43. Programming Mode Via PSI5 Short Command and Response Format
5.3.2.2 Long Frame Command and Response Format
Long frame s allow f or the tran smission of dat a nibb les for register writes. The device can provide register data in response to
a read or write request. The Long Frame format is shown in Figure 44. Long Frame commands and responses are defined in
Section 5.3.6.
Figure 44. Programming Mod e Via PSI5 Long Com mand and Response Format
5.3.3 Command Message CRC
Programming mode command error checking is accomplished by a 3-bit CRC. The 3-bit CRC is calculated using all message
bits except start bit s and sync bits. The CRC verification uses a generator polynomial of g(x) = X3+X+1, with a seed value = ‘1 11’.
The data is provided to the CRC calculator in the order received (LSB first, SAdr , FC, RAdr , Data), and then augmented with three
‘0’s. Table 8 shows some example CRC calculation values for 10-bit data transmissions.
The calculated CRC is then compared against the received 3-bit CRC (received MSB first). If a CRC mismatch is detected,
the device responds with a CRC Error response as defined in Section 5.3.7.
5.3.4 Command Sync Pulse Blanking Time
In Programming Mode and Programming Mode Entry, the device employs a fixed Sync Pulse blanking time of tSYNC_OFF_500
regardless of the state of the BLANKTIME bit.
5.3.5 Command Timeout
In the event that the device does not detect a sync pulse within a 4-bit window time (missing sync bit), the command reception
will be terminated and the device will respond to the next sync pulse with a Short Frame Framing Error response as defined in
Section 5.3.7.
Start Bits Sensor
Address Function Code CRC Response
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy C2 C1 C0 RC RD1
010110010011 0 0 0 $1E2 $3FF
Start Bits Sensor
Address Function Code Regi ster Address Data CRC Response
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy D0 D1 D2 Sy D3 C2 C1 Sy C0 RC RD1 RD0
010110010 1 0100010 0 0111111001 0 $1E2 $3FF $3FF
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5.3.6 Programming Mode Via PSI5 Command and Response Summary
Note: When reading the last address in the data array, RData+1 will always return 0x00.
5.3.7 Programming Mode Via PSI5 Error Response Summary
* ErrN is transmitted in the 4 LSBs of RD1. All other bits in the response data field are set to ‘0’.
Table 17. Programming Mode Via PSI5 Commands and Resp onses
#CMD
Type SAdr FC Command Register
Address Data
Field Response (OK) Response (Error)
RC RD1 RD0 RC RD1 RD0
S0 Short
001
100 Execute Programming of NVM N/A N/A OK 0x2AA N/A Error ErrN N/A
S1 Short 101 Invalid Command N/A N/A No Response No Response
S2 Short 110 Invalid Command N/A N/A No Response No Response
S3 Short 111 Enter Programming Mode N/A N/A OK 0x0CA N/A No Response
LR Long 010 Read nibble located at address
RA5:RA0 Varies Varies OK RData RData+1 Error ErrN 0x000
LW Long 011 Write nibble to register RA5:RA0 Varies Varies OK WData RA5:RA0 Error ErrN 0x000
XLR XLong 000 Invalid Command Any Any No Response No Response
XLW XLong 001 Invalid Command Any Any No Response No Response
Table 18. Programming Mode Via PSI5 Response Code Definitions
Response Code Definition Value
RC = OK Command Message Received Properly 0x1E1
RC = Error Error during transmission of Command Message 0x1E2
RData Byte Contents of Register located at Byte address in which nibble address RA5:RA0 falls in.
(Example: For RA5:RA0 = $04 - RData = Data at Byte Address $02) Varies
RData + 1 Byte Contents of Register located at Byte address in which nibble address RA5:RA0 +2 falls in.
(Example: For RA5:RA0 = $04 - RData + 1= Data at Byte Address $03) Varies
WData Byte Contents of Register located at Byte address in which nibble address RA5:RA0 falls
in after write operation. (Example: For RA5:RA0 = $04 - RData = Data at Byte Address $02) Varies
Table 19. Error Response Summary
ErrN* Mnemonic Description Supported By MMA51xx
0000 General General Error No
0001 Framing Framing Error Yes
0010 CRC CRC Error on Received Message Yes
0011 Address Sensor Address Not Supported No (Invalid Address is ignored)
0100 FC Function Code Not Supported No (N/A)
0101 Data Range Unsupported Register Address Yes
0110 Write Protect Destination Address is Write protected (Locked) Yes
0111 Reserved Reserved No
1000
Reserved Reserved No
1001
1010
1011
1100
1101
1110
1111
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5.4 OTP Programming Via PSI5 Procedure
1. Enter Programming Mode.
2. Load desired data into the OTP shadow registers using PSI5 Long Write commands.
3. Send “Execute Programming of NVM“Short command.
4. Set VCC = VPP prior to, or within tPROG_HOLD after the “Execute Programming of NVM” Command has been
transmitted. There is an internal delay of tPROG_DELAY after the “Execute Programming of NVM” Command is
received until the OTP programming begins.
5. Delay a minimum of tPROG_USER. During the OTP Write sequence, sync pulses will be ignored. However,
transmission of sync pulses during the OTP Write sequence should be prevented.
6. Read the SC register and verify IDEF_B flag is set (indicating the write is complete and successful, and the shadow
registers have been refreshed with the OTP contents).
7. Read the OTP register values and compare to the desired values.
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6 SPI Diagnostic and Programming Mode
SPI Diagnostic and Programming Mode allows for the following functions:
• Programming of the OTP array
• Reading of memory registers
SPI transfers fo llow CPOL = 0, CPHA = 0, MSB first convention. Figure 7 shows the SPI transfer timing, and Figure 45 shows
the SPI transfer protocol.
Figure 45. SPI Transfer Protocol
The following operations are supported in DPM:
• Register pointer write
• Register pointer read
• Register data write
• Register data read
• Acceleration data read
6.1 Communication Error Detection
6.1.1 Data Input Parity Detection
All commands except for the DPM Entry command employ odd parity to ensure data integrity. For Read commands, the parity
bit is located in bit D10, and the parity is calculated using bits D15 through D11. For Write commands, the parity bit is located in
bit D9, and the parity is calculated using bits D15 through D0. If a parity error is detected, both the current and subsequent com-
mands are ignored, and the parity fault response is transmitted during the subsequent SPI transfer.
6.1.2 Data Output Parity
All responses except for the DPM entry response employ odd parity to ensure data integrity . Parity is calculated using the entire
16-bit message.
6.2 DPM Entry
DPM can be activated at any time during the operation of the device, provided the SPI DPM Entry command is the first com-
mand transmitted. If an i n cor r ec t D P M En try command is r ecei ved, DPM is locked out, and cannot be activated until the device
is reset.
The device responds to the DPM Entry command with the logical complement of the received data as confirmation that it has
been received correctly. Upon completion of a successful transfer DPM is activated. Once activated, the device will remain in
DPM until a reset condition occurs.
Following successful transmission of the DPM Entry command, DPM operations may be completed in any order.
SCLK
BIT 15
D
IN
D
OUT
CS
14 13 12 11 10 9876543210
D6 D5 D4 D3 D2 D1 D0
D15 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D14 D13 D12
D15 D14 D13 D12 D7D8D9D10D11
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6.3 DPM Command/Response Summary
Table 20 provides a summary of SPI commands and responses.
6.4 R egister Pointer Operations
Access to internal registers is accomplished via a pointer register . The pointer contains the address of the register affected by
register data write and read operations. Two register pointer operations are provided: Register Pointer Write, and Register Pointer
Read. Command and response information is shown in Table 20.
6.5 R egister Data Operations
T wo register operations are provided: Register Write, and Register Read. In each case, the address of the affected register is
contained in the register pointer.
6.5.1 Register Write Command
The Register Write command format is shown in Table 20. The least significant 8 bits of the Register Write command message
contain the data to be written to the register pointed to by the register pointer. The least significant 8 bits of the Register Write
response message contain the address of the register that was modified.
The write to the register is executed during the clock cycle immediately after CS is deasserted.
Table 20. SPI Command/Response Summary
Command Pin Bit
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SPI DPM Entry DIN 1010001101011100
DOUT 0101110010100011
Register Pointer Write DIN 010011PXA7A6A5A4A3A2A1A0
DOUT 10110P0100000000
Register Pointer Read DIN 01000P=00XXXXXXXXX
DOUT 10110P01A7A6A5A4A3A2A1A0
Register Data Write DIN 010110PXD7D6D5D4D3D2D1D0
DOUT 10100P10A7A6A5A4A3A2A1A0
Register Data Read DIN 01010P=10XXXXXXXXX
DOUT 10100P10D7D6D5D4D3D2D1D0
Acceleration Data Read DIN 01100P=10000000000
DOUT 10011PD9D8D7D6D5D4D3D2D1D0
Invalid Command Response
(Waiting for SPI DPM Entry)
DIN 00
D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
DOUT 1 No Response (all 0s) - DPM Entry Locked Out
DIN 011
D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
DOUT 1 No Response (all 0s) - DPM Entry Locked Out
DIN 11
D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
DOUT 0 0 No Response (all 0s) - DPM Entry Locked Out
DIN 10
D[13] D[12] D[11] ... D[x] Not SPI DPM Entry Command
DOUT 01
D[13] D[12] D[11] ... D[x] No Response (all 0s) - DPM Entry Locked Out
Invalid Command Response DIN XXXXXXXXXXXXXXXX
DOUT d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0]
Parity Fault Response
(Subsequent Message Response) DIN XXXXXXXXXXXXXXXX
DOUT 1000001111111111
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6.5.2 Register Read Command
The Register Read command format is shown in Table 20. The least significant 8 bits of the Register Read command message
are ignored. The least significant 8 bits of the Register Read response message contain the contents of the register pointed to
by the register pointer.
16 bit register reads are possible using consecutive Register Read commands. The high byte of a 16 bit register will automat-
ically be frozen on a read of the low byte of the register.
6.5.3 Acceleration Data Read Operations
The Acceleration Data Read command format is shown in Table 20. The response to this command provides either 8-bit, or
10-bit acceleration data depending on the state of the DATASIZE bit in the DEVCFG2 register.
6.5.4 Error Responses
6.5.4.1 Response to Invalid Commands
Reference Table 20 for responses to Invalid Commands.
6.5.4.2 Parity Fault Response
If the device detects a Command Parity fault, the current, and subsequent SPI commands are ignored and the device responds
to the subsequent message with the Pa rity Fault response, as shown in Table 20.
6.6 SPI OTP Programming Procedure
1. Set VCC = VPP.
2. Enter SPI DPM.
3. Load desired data into the OTP shadow registers using SPI Write commands.
a. Write the desired contents of DEVCFG2 ($05) to address $05
b. Write the desired contents of DEVCFG2 ($05) to address $1E
c. Write the desired contents of DEVCFG3 ($06) to address $06
d. Write the desired contents of DEVCFG3 ($06) to address $1F
e. Write the desired contents of DEVCFG4 ($07) to address $07
f. Write the desired contents of DEVCFG4 ($07) to address $20
g. Write the desired contents of DEVCFG5 ($08) to address $08
h. Write the desired contents of DEVCFG5 ($08) to address $21
i. Write the desired contents of DEVCFG6 ($09) to address $09
j. Write the desired contents of DEVCFG6 ($09) to address $22
k. Write the desired contents of DEVCFG7 ($0A) to address $0A
l. Write the desired contents of DEVCFG7 ($0A) to address $23
m.Write the desired contents of DEVCFG8 ($0B) to address $0B
n. Write the desired contents of DEVCFG8 ($0B) to address $24
o. Write the desired contents of MFG_ID ($0D) to address $0D
p. Write the desired contents of MFG_ID ($0D) to address $2E
4. Write 0x05 to register $44 to initiate the NVM programming.
5. Delay a minimum of tPROG_ARRAY
6. Read the SC register and verify the IDEF_B flag is set (ind icating the write is complete and successful).
DATASIZE Bit
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATASIZE = 1 (8-Bit Data)10011P00D7D6D5D4D3D2D1D0
DATASIZE = 0 (10-Bit Data)10011PD9D8D7D6D5D4D3D2D1D0
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7 Package
7.1 Case Outline Drawing
Reference Freescale Case Outli ne Drawing # 98ASA00090D
http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf
7.2 Recommended Footprint
Reference Freescale Application Note AN3111, latest revision:
http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf
Table 21. Revision History
Revision
number Revision
date Description of changes
9 03/2012 • Added SafeAssure logo, changed first paragraph and disclaimer to include trademark
information.
• Table 2: $04 DEVCFG1: Changed Bit Function 3 to 1.
• Section 3.1.2: Changed Bit 3 to 1 in register table.
• Section 3.1.2.1: Removed Axis column in table , changed last row g-cell design column to High-g.
10 07/2012 • Added Section 6: SPI Diagnostic and Programming Mode
11 08/2012 • Section 2.3: Lines 47 and 48 deleted.
• Section 2.6: Line 145, Time to program the OTP User Array Min value was 512 μs changed to
70 ms, changed symbol to tPROG_ARRAY.
• Section 2.8: Line 190, change Typ column from 6 / fOSC to 1.5, added Max column 5.0, changed
unit from “s” to “μs”.
• Section 2.7: Cutoff frequency, Option 1, Filter order, Option 1, Cutoff frequency, Option 2 and
Filter order, Opti on 2, table renumbering.
• Section 3.1: Changed “CRC circuitry” to “error detection circuitry”.
• Table 2: Changed bit names for addre ss $0 B from “CRC_U” to “UD”. Added $0D byte addr.
• Section 3.1.3.1: Changed “CRC Verification” to “Error Detection”.
• Section 3.1.5: Changed bit names for address $0B from “CRC_U” to “UD”.
• Section 3.1.5.4: Changed title from “User Confi guration CRC (CRC_U[2:0])” to “User Specific
Data (UD[2:0])” and change contents of paragraph.
• Section 3.1.6.6 - Deleted.
• Section 3.1.6.2: Changed “CRC fault” to “error detection mismatch” in paragraph and Error
Condition column.
• Added Section 3.1.7 Manufacturer ID (MFG_ID).
• Section 3.2.2: Changed title from “User Programmable OTP Array CRC Verification” to User
Programmable OTP Array Error Detection” and updated paragraph contents.
• Table 6: Deleted 0.04 Hz HPF rows.
• Table 10: Updated F3 register address from “Hard-coded” to “MFG_ID[7:0]”; Description from
“Manufacturer = F reescale” to “Manufacturer ID”; Value from “0100 0110” to “User”.
• Section 5.4: Change step 4; deleted “a” and “b”, added step 5.
• Table 10: F7, D12 and D13 Value column from “0001” to “Factory”.
• Table 12: Added register name (MFG_ID) and bit function f or Nibble IDs D4 H, D4 L, D5 H and
D5 L in Register Address column; changed Description column for all from “Satellite Manufacturer
= Freescale” to “Manufacturer ID”; changed Value column to “User”.
• Section 6.5.3: Changed first row from “DATASIZE = 0” to “DATASIZE = 1”, second row from
“DATASIZE = 1” to “DATASIZE = 0”.
• Section 6.6: Updated Steps 3-6. Deleted steps 7 and 8.
Document Number: MMA51xxKW
Rev. 11
08/2012
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Freescale reserves the right to make changes without further notice to any products
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QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale
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