M672061E 16 K 9 CMOS With Programmable Half Full Flag Parallel FIFO Rad Tolerant Description The M672061E implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information are required for the TEMIC FIFOs. Address pointers are automatically incremented with the write pin and read pin. The 9 bits wide data are used in data communications applications where a parity bit for error checking is necessary. The Retransmit pin reset the Read pointer to zero without affecting the write pointer. This is very useful for retransmitting data when an error is detected in the system. Using an array of eight transistors (8 T) memory cell, the M672061E combine an extremely low standby supply current (typ = 0.1 A) with a fast access time at 15 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 2 W. For military/space applications that demand superior levels of performance and reliability the M672061E is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) ,ESA SCC 9000 or QML. Features First-in first-out dual port memory 16384 x 9 organisation Fast Flag and access times: 15, 30 ns Wide temperature range : - 55 C to + 125 C Programmable Half Full Flag Rev. C - June 30, 1999 Fully expandable by word width or depth Asynchronous read/write operations Empty, full and half flags in single device mode Retransmit capability Bi-directional applications Battery back-up operation : 2 V data retention TTL compatible Single 5 V 10 % power supply High Performance SCMOS Technology 1 M672061E Interface Block Diagram 16384 x 9 16384 Pin Configuration FP 28 pin 400 mils (top view) W I8 I3 I2 I1 I0 XI FF Q0 Q1 Q2 Q3 Q8 GND 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC I4 I5 I6 I7 FL/RT RS EF XO/PHF Q7 Q6 Q5 Q4 R Rev. C - June 30, 1999 M672061E Pin Names NAMES DESCRIPTION I0-8 Inputs Q0-8 Outputs W Write Enable R Read Enable RS Reset EF Empty Flag NAMES FF XO/PHF XI DESCRIPTION Full Flag Expansion Out/Programmable HalfFull Flag Expansion IN FL/RT First Load/Retransmit VCC Power Supply GND Ground Signal Description Data In (I0 - I8) Data inputs for 9 - bit data Reset (RS) Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both internal read and write pointers to the first location. A reset is required after power-up before a write operation can be enabled. Both Rev. C - June 30, 1999 the Read Enable (R) and Write Enable (W) inputs must be in the high state during the period shown in figure 1 (i.e. tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. Otherwise, pulse write (or read) low during the reset operation has to effect to load the Programmable Half Full Flag register grow the data Inputs I0-I8 (or data outputs Q0-Q8) (shown in figure 2). In these two cases the Full Flag and the Programmable Half Full Flag are reseted to high and the Empty Flag to low. 3 M672061E Figure 1. Reset (no write to Programmable Half Full Flag register) tWR (tRR) Notes : 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS. Figure 2. Reset (write (read) to Programmable Half Full Flag register) RS tWR (tRR) tWPW (tRPW) W (R) tWC (tRC) tDS I0-I8 (Q0-Q8) tRSR tDH DATA VALID Write Enable (W) Read Enable (R) A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be maintained in the rise time of the leading edge of the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any current read operation. A read cycle is initiated on the falling edge of the Read Enable (R) provided that the Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not with standing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 - Q8) will return to a high impedance state until the next Read operation. When all the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the "final" read cycle, but inhibiting further read operations whilst the data outputs remain in a high impedance state. Once a valid write operation has been completed, the Empty Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO stack is empty, the internal read pointer is blocked from R, so that external changes to R will have no effect on the empty FIFO stack. Once half the memory is filled, and during the falling edge of the next write operation, the Programmable Half-Full Flag (PHF) will be set to low and remain in this state until the difference between the write and read pointers is less than or equal to half of the total available memory in the device. The Programmable Half-Full Flag (PHF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF, allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is blocked from W, so that external changes to W will have no effect on the full FIFO stack. 4 First Load/Retransmit (FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to ground to indicate that it Rev. C - June 30, 1999 M672061E is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by connecting the Expansion In (XI) to ground. The M672061E can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed low. A retransmit operation will set the internal read point to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the high state during retransmit. The retransmit feature is intended for use when a number of writes equals to or less than the depth of the FIFO has occured since the last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Programmable Half-Full Flag (PHF), in accordance with the relative locations of the read and write pointers. Expansion In (XI) This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain modes. Full Flag (FF) The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes. Empty Flag (EF) operations when the read pointer is equal to the write pointer, indicating that the device is empty. Expansion Out/Half-Full Flag (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is connected to ground, this output acts as an indication of a half-full memory. The M672061E offers a variable offset for the Half Full condition. The offset is loaded into a register during a reset cycle . When RS is low, the Programmable Half Full Flag (PHF) can be loaded from the DATA inputs I0-I8 by pulsing W low or from the DATA outputs Q0-Q8 by pulsing R low. The offset options are listed in table 1. If PHF is not loaded during the reset cycle, the default offset will be the half of the total memory of the device. The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the difference between the write and read pointers is less than or equal to the Programmable offset (if the Half Full Flag register has been loaded during the reset cycle) or the half of the total memory (if the Half Full register has not been loaded during the reset cycle). In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last memory location. Data Output (Q0 - Q8) DATA output for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state. The Empty Flag (EF) will go low, inhibiting further read Rev. C - June 30, 1999 5 M672061E Functional Description Operating Modes is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 3). In this mode the Programmable Half-Full Flag (PHF), which is an active low output, is shared with Expansion Out (XO). Single Device Mode A single M672061E may be used when the application requirements are for 16384 words or less. The M672061E Figure 3. Block Diagram of Single 16384 x 9. PHF (HALF-FULL FLAG) (W) WRITE (R) 9 DATAIN READ 9 M (I) DATAOUT (Q) 672061 FULL FLAG (FF) (EF) EMPTY FLAG (RS) (RT) RETRANSMIT RESET EXPANSION IN (XI) Width Expansion Mode Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Figure 4. Status flags (EF, FF and PHF) can be detected from any device. Figure 4 demonstrates an 18-bit word width by using two M672061E. Any word width can be attained by adding additional M672061E. Block Diagram of 16384 x 18 FIFO Memory Used in Width Expansion Mode. PHF PHF 18 9 9 DATAIN (I) (R) READ WRITE FULL FLAG (W) (FF) M M 672061 672061 (EF) EMPTY FLAG (RT) RETRANSMIT RESET (RS) 9 9 XI XI 18 (Q) DATAOUT Note : 3. Flag detection is accomplished by monitoring the FF, EF and the PHF signals on either (any) device used in the width expansion configuration. Do not connect any output control signals together. 6 Rev. C - June 30, 1999 M672061E Table 1 : Programmable Half Full Flag Offset I8 I7 I6 I5 I4 I3 I2 I1 I0 OFFSET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 32 0 0 0 0 0 0 0 1 0 64 0 0 0 0 0 0 0 0 8192 (Half Full) Default Offset 1 1 1 1 1 1 1 1 0 16384-64 1 1 1 1 1 1 1 1 1 16384-32 ... 1 ... Table 2 : Reset and retransmit Single Device Configuration/Width Expansion Mode INPUTS MODE INTERNAL STATUS RS RT XI Read Pointer Reset 0 X 0 Location Zero Retransmit 1 0 0 Read/Write 1 1 0 OUTPUTS Write Pointer EF FF PHF Location Zero 0 1 1 Location Zero Unchanged X X X Increment(4) Increment(4) X X X Note : 4. Pointer will increment if flag is high. Table 3 : Reset and First Load Truth Table Depth Expansion/Compound Expansion Mode INPUTS MODE INTERNAL STATUS OUTPUTS RS FL XI Read Pointer Write Pointer EF FF Reset First Device 0 0 (5) Location Zero Location Zero 0 1 Reset All Other Devices 0 1 (5) Location Zero Location Zero 0 1 Read/Write 1 X (5) X X X X Note : 5. XI is connected to XO of previous device. See fig. 5. Depth Expansion (Daisy Chain) Mode 2. All other devices must have FL in the high state. The M672061E can be easily adapted for applications which require more than 16384 words. Figure 5 demonstrates Depth Expansion using three M672061E. Any depth can be achieved by adding additional 672061. 3. The Expansion Out (XO) pin of each device must be connected to the Expansion In (XI) pin of the next device. See figure 5. The M672061E operates in the Depth Expansion configuration if the following conditions are met : 1. The first device must be designated by connecting the First Load (FL) control input to ground. Rev. C - June 30, 1999 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires that all EF's and all FFs be ORed (i.e. all must be set to generate the correct composite FF or EF). See figure 5. 7 M672061E 5. The Retransmit (RT) function and Programmable Half-Full Flag (PHF) are not available in the Depth Expansion Mode. Compound Expansion Module It is quite simple to apply the two expansion techniques described above together to create large FIFO arrays (see figure 6). In the write flow-through mode (figure 19), the FIFO stack allows a single word of data to be written immediately after a single word of data has been read from a full FIFO stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading edge of W. The W line must be toggled when FF is not set in order to write new data into the FIFO stack and to increment the write pointer. Bidirectional Mode Applications which require data buffering between two systems (each system being capable of Read and Write operations) can be created by coupling M672061E as shown in figure 7. Care must be taken to ensure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device on which W is in use ; EF is monitored on the device on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode. Data Flow - Through Modes Two types of flow-through modes are permitted : a read flow-through and a write flow-through mode. In the read flow-through mode (figure 18) the FIFO stack allows a single word to be read after one word has been written to an empty FIFO stack. The data is enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the first write edge and remains on the bus until the R line is raised from low to high, after which the bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating temporary reset and then will be set. In the interval in which R is low, more words may be written to the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; however, the same word (written on the first write edge) presented to the output bus as the read pointer will not be incremented if R is low. On toggling R, the remaining words written to the FIFO will appear on the output bus in accordance with the read cycle timings. 8 Rev. C - June 30, 1999 M672061E Figure 5. Block Diagram of 49152 x 9 FIFO Memory (Depth expansion). XO W R 6 FF 9 9 EF M 672061 9 Q FL FULL FF 9 VCC EMPTY EF M 672061 FL FF 9 EF M 672061 RS FL XI Figure 6. Compound FIFO Expansion. Q0 - Q8 Q0 - Q8 R . W . RS M 672061 DEPTH EXPANSION BLOCK Q9 - Q17 Q(N-8) - QN Q9 - Q17 Q(N-8) - QN M 672061 DEPTH EXPANSION BLOCK I0 - I8 M 672061 DEPTH EXPANSION BLOCK I9 - I17 I0 - I8 I(N-8) - IN I9 - I17 I(N-8) - IN Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4. 7. For Flag detection see section on Width Expansion and Figure 3. Figure 7. Bidirectional FIFO Mode. WA RB EFB PHFB M FFA 672061 IA 0-8 QB 0-8 SYSTEM A SYSTEM B QA 0-8 RA PHFA EFA Rev. C - June 30, 1999 M 672061 IB 0-8 WB FFB 9 M672061E Electrical Characteristics Absolute Maximum Ratings Supply voltage (VCC - GND) . . . . . . . . . . . . . . . . . . - 0.3 V to 7.0 V Input or Output voltage applied : . . . . (GND - 0.3 V) to (Vcc + 0.3 V) Storage temperature : . . . . . . . . . . . . . . . . . . . . . . - 65 C to + 150 C OPERATING RANGE OPERATING SUPPLY VOLTAGE OPERATING TEMPERATURE Military Vcc = 5 V 10 % - 55 C to + 125 C Automotive Vcc = 5 V 10 % - 40 C to + 125 C DC Parameters Parameter Description M 672061-30 M 672061-15 UNIT VALUE ICCOP (8) Operating supply current 150 165 mA Max ICCSB (9) Standby supply current 1.5 1.5 mA Max ICCPD (10) Power down current 400 400 A Max Notes : 8. Icc measurements are made with outputs open. 9. R = W = RS = FL/RT = VIH. 10. All input = Vcc. PARAMETER DESCRIPTION M672061E UNIT VALUE ILI (11) Input leakage current 1 A Max ILO (12) Output leakage current 10 A Max VIL (13) Input low voltage 0.8 V Max VIH (13) Input high voltage 2.2 V Min VIH (13) Input high voltage 2.2 V Min VOL (14) Output low voltage 0.4 V Max VOH (14) Output high voltage 2.4 V Min C IN (15) Input capacitance 8 pF Max C OUT (15) Output capacitance 8 pF Max Notes : 11. 12. 13. 14. 15. 0.4 Vin Vcc. R = VIH, 0.4 VOUT VCC. VIH max = Vcc + 0.3 V. VIL min = -0.3 V or -1 V pulse width 50 ns. For XI input VIH= 2.6V (Com), VIH= 2.8V (Mil, Auto, Ind) Vcc min, IOL = 8 mA, IOH = -2 mA. This parameter is sampled and not tested 100 % - TA = 25 C - F = 1 MHz. AC Test Conditions Input pulse levels Input rise/Fall times 10 : Gnd to 3.0 V : 5 ns Input timing reference levels Output reference levels Output load : 1.5 V : 1.5 V : See figure 8 Rev. C - June 30, 1999 M672061E Figure 8. Output Load. 5V 500 TO OUTPUT PIN 333 30 pF* * includes jig and scope capacitance SYMBOL (16) SYMBOL (17) PARAMETER (3) (7) M672061E - 30 MIN. READ CYCLE MAX. M672061E - 15 MIN. UNIT MAX. READ CYCLE TRLRL tRC Read cycle time 40 - 25 - ns TRLQV tA Access time - 30 - 15 ns TRHRL tRR Read recovery time 10 - 10 - ns TRLRH tRPW Read pulse width (19) 30 - 15 - ns TRLQX tRLZ Read low to data low Z (20) 3 - 0 - ns TWHQX tWLZ Write low to data low Z (20, 21) 3 - 3 - ns TRHQX tDV Data valid from read high 5 - 5 - ns TRHQZ tRHZ Read high to data high Z (20) - 20 - 15 ns TWLWL tWC Write cycle time 40 - 25 - ns TWLWH tWPW Write pulse width (19) 30 - 15 - ns TWHWL tWR Write recovery time 10 - 10 - ns TDVWH tDS Data set-up time 18 - 9 - ns TWHDX tDH Data hold time 0 - 0 - ns TRSLWL tRSC Reset cycle time 40 - 25 - ns TRSLRSH tRS Reset pulse width (19) 30 - 15 - ns TWHRSH tRSS Reset set-up time 40 - 25 - ns TRSHWL tRSR Reset recovery time 10 - 10 - ns WRITE CYCLE WRITE CYCLE RESET CYCLE RESET CYCLE RETRANSMIT CYCLE RETRANSMIT CYCLE TRTLWL tRTC Retransmit cycle time 40 - 25 - ns TRTLRTH tRT Retransmit pulse width (19) 30 - 15 - ns TWHRTH tRTS Retransmit set-up time (20) 30 - 15 - ns TRTHWL tRTR Retransmit recovery time 10 - 10 - ns TRSLEFL tEFL Reset to EF low - 30 - 25 ns TRSLFFH tHFH, tFFH Reset to HF/FF high - 30 - 25 ns TRLEFL tREF Read low to EF low - 30 - 15 ns TRHFFH tRFF Read high to FF high - 30 - 17 ns TEFHRH tRPE Read width after EF high 30 - 15 - ns TWHEFH tWEF Write high to EF high - 30 - 15 ns TWLFFL tWFF Write low to FF low - 30 - 17 ns TWLHFL tWHF Write low to HF low - 30 - 25 ns TRHHFH tRHF Read high to HF high - 30 - 25 ns TFFHWH tWPF Write width after FF high 30 - 15 - ns FLAGS FLAGS Rev. C - June 30, 1999 11 M672061E SYMBOL (16) SYMBOL (17) PARAMETER (3) (7) M672061E - 30 M672061E - 15 MIN. MAX. MIN. MAX. UNIT EXPANSION TWLXOL tXOL Read/Write to XO low - 30 - 15 ns TWHXOH tXOH Read/Write to XO high - 30 - 15 ns TXILXIH tXI XI pulse width 30 - 15 - ns TXIHXIL tXIR XI recovery time 10 - 10 - ns TXILRL tXIS XI set-up time 10 - 10 - ns Notes : 16. 17. 18. 19. 20. 21. 22. Figure 9. 12 STD symbol. ALT symbol. Timings referenced as in ac test conditions. Pulse widths less than minimum value are not allowed. Values guaranteed by design, not currently tested. Only applies to read data flow-through mode. All parameters tested only. Asynchronous Write and Read Operation. Rev. C - June 30, 1999 M672061E Figure 10. Full Flag from Last Write to First Read. Figure 11. Empty Flag from Last Read to First Write. Figure 12. Retransmit. Note : 23. EF, FF and PHF may change status during Retransmit, but flags will be valid at tRTC. Rev. C - June 30, 1999 13 M672061E Figure 13. Empty Flag Timing Figure 14. Full Flag Timing Figure 15. Programmable Half-Full Flag Timing. PROGRAMMABLE HALF FULL OFFSET OR LESS PROGRAMMABLE HALF FULL OFFSET OR LESS MORE THAN HALF FULL 14 Rev. C - June 30, 1999 M672061E Figure 16. Expansion Out. Figure 17. Expansion In. Figure 18. Read Data Flow - Through Mode. Rev. C - June 30, 1999 15 M672061E Figure 19. Write Data Flow - Through Mode. 16 Rev. C - June 30, 1999 M672061E Ordering Information 15 ns 30 ns Preview* CP = 32 pins 300 mils side brazed DP = Flat pack 28 pins 400 mils 0= Die form blank /883 MQ SV = = = = MHS standards MIL-STD 883 CLASS B or S QML-Q QML-V 672061 = 16384 x 9 FIFO EV = Very low power and rad tolerant M = Military S = Space -55 to +125C -55 to +125C The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use. Rev. C - June 30, 1999 17