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SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

SGx524 Regulating Pulse-Width Modulators

1 Features 3 Description

The SG2524 and SG3524 devices incorporate all the

1• Complete Pulse-Width Modulation (PWM) Power- functions required in the construction of a regulating

Control Circuitry power supply, inverter, or switching regulator on a

• Uncommitted Outputs for Single-Ended or Push- single chip. They also can be used as the control

Pull Applications element for high-power-output applications. The

SG2524 and SG3524 were designed for switching

• 8 mA (TYP) Standby Current regulators of either polarity, transformer-coupled dc-

to-dc converters, transformerless voltage doublers,

2 Applications and polarity-converter applications employing fixed-

• Transformer-coupled DC/DC convertors frequency, pulse-width modulation (PWM)

• Switching-regulators of any polarity techniques. The complementary output allows either

single-ended or push-pull application. Each device

includes an on-chip regulator, error amplifier,

programmable oscillator, pulse-steering flip-flop, two

uncommitted pass transistors, a high-gain

comparator, and current-limiting and shutdown

circuitry.

Device Information(1)

PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)

SOIC (16) 9.90 mm × 3.91 mm

SGx524 PDIP (16) 9.90 mm × 6.35 mm

NS (16) 10.30 mm × 5.30 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

4 Pinout Drawing

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

www.ti.com

Table of Contents

9.2 Functional Block Diagram......................................... 9

1 Features.................................................................. 19.3 Feature Description................................................. 10

2 Applications ........................................................... 19.4 Device Functional Modes........................................ 11

3 Description............................................................. 110 Application and Implementation........................ 12

4 Pinout Drawing....................................................... 110.1 Application Information.......................................... 12

5 Revision History..................................................... 210.2 Typical Application................................................ 14

6 Pin Configurations and Functions....................... 310.3 Examples of Other Output Stages........................ 16

7 Specifications......................................................... 411 Power Supply Recommendations ..................... 18

7.1 Absolute Maximum Ratings ..................................... 412 Layout................................................................... 18

7.2 ESD Ratings.............................................................. 412.1 Layout Guidelines ................................................. 18

7.3 Recommended Operating Conditions....................... 412.2 Layout Example .................................................... 19

7.4 Thermal Information.................................................. 413 Device and Documentation Support................. 20

7.5 Electrical Characteristics........................................... 513.1 Related Links ........................................................ 20

7.6 Electrical Characteristics — Continued, Both Parts.. 613.2 Trademarks........................................................... 20

7.7 Typical Characteristics.............................................. 713.3 Electrostatic Discharge Caution............................ 20

8 Parameter Measurement Information .................. 813.4 Glossary................................................................ 20

9 Detailed Description.............................................. 914 Mechanical, Packaging, and Orderable

9.1 Overview................................................................... 9Information........................................................... 20

5 Revision History

Changes from Revision I (February 2003) to Revision J Page

• Added Applications,Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,

Typical Characteristics,Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Deleted Ordering Information table. ....................................................................................................................................... 1

Product Folder Links: SG2524 SG3524

SG2524

SG3524

www.ti.com

SLVS077E –APRIL 1977–REVISED JANUARY 2015

6 Pin Configurations and Functions

Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

COL 1 12 O Collector terminal of BJT output 1

COL 2 13 O Collector terminal of BJT output 2

COMP 9 I/O Error amplifier compensation pin

CT 7 — Capacitor terminal used to set oscillator frequency

CURR LIM+ 4 I Positive current limiting amplifier input

CURR LIM- 5 I Negative current limiting amplifier input

EMIT 1 11 O Emitter terminal of BJT output 1

EMIT 2 14 O Emitter terminal of BJT output 2

GND 8 — Ground

IN+ 2 I Positive error amplifier input

IN- 1 I Positive error amplifier input

OSC OUT 3 O Oscillator Output

REF OUT 16 O Reference regulator output

RT 6 — Resistor terminal used to set oscillator frequency

SHUTDOWN 10 I Device shutdown

VCC 15 — Positive supply

Product Folder Links: SG2524 SG3524

SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC Supply voltage(2)(3) 40 V

ICC Collector output current 100 mA

IO(ref) Reference output current 50 mA

Current through CT terminal –5 mA

TJMaximum junction temperature 150 °C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings table may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions table are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values are with respect to network ground terminal.

(3) The reference regulator may be bypassed for operation from a fixed 5-V supply by connecting the VCC and reference output (REF

OUT) pin both to the supply voltage. In this configuration, the maximum supply voltage is 6 V.

7.2 ESD Ratings VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 1000

pins(1)

V(ESD) Electrostatic discharge V

Charged device model (CDM), per JEDEC specification JESD22- 1000

C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VCC Supply Voltage 8 40 V

Reference output current 0 50 mA

Current through CT terminal –0.03 –2 mA

RTTiming resistor 1.8 100 kΩ

CTTiming capacitor 0.001 0.1 µF

SG2524 –25 85

TAOperating free-air temperature °C

SG3524 0 70

7.4 Thermal Information SGx524

THERMAL METRIC(1) D N NS UNIT

16 PINS

RθJA Junction-to-ambient thermal resistance(2)(3) 73 67 64 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient

temperature is PD = (TJ(max) – TA)/θJA. Operation at the absolute maximum TJ of 150°C can impact reliability.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

Product Folder Links: SG2524 SG3524

( )

n 1

x x

N 1

s = -

SG2524

SG3524

www.ti.com

SLVS077E –APRIL 1977–REVISED JANUARY 2015

7.5 Electrical Characteristics

over operating free-air temperature range, VCC = 20 V, f = 20 kHz (unless otherwise noted)

SG2524 SG3524

PARAMETER TEST CONDITIONS(1) UNIT

MIN TYP(1) MAX MIN TYP(2) MAX

Reference section

Output voltage 4.8 5 5.2 4.6 5 5.4 V

Input Regulation VCC = 8 V to 40 V 10 20 10 30 mV

Ripple rejection f = 120 Hz 66 66 dB

Output regulation IO= 0 mA to 20 mA 20 50 20 50 mV

Output voltage change with temperature TA= MIN to MAX 0.3% 1% 0.3% 1%

Short-circuit output current(3) Vref = 0 100 100 mA

Error Amplifier section

VIO Input offset voltage VIC = 2.5 V 0.5 5 2 10 mV

IIB Input bias current VIC = 2.5 V 2 10 2 10 µA

Open-loop voltage amplification 72 80 60 80 dB

1.8 to 1.8 to

VICR Common-monde input voltage range TA= 25°C V

3.4 3.4

CMMR Common-mode rejection ratio 70 70 dB

B1Unity-gain bandwidth 3 3 MHz

Output swing TA= 25°C 0.5 3.8 0.5 3.8 V

(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

(2) All typical values, except for temperature coefficients, are at TA= 25°C.

(3) Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula:

Product Folder Links: SG2524 SG3524

( )

n 1

x x

N 1

s = -

SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

www.ti.com

7.6 Electrical Characteristics — Continued, Both Parts

over operating free-air temperature range, VCC = 20 V, f = 20 kHz (unless otherwise noted)

PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT

Oscillator section

fOSC Oscillator frequency CT= 0.001 μF, RT= 2 kΩ450 kHz

All values of voltage, temperature,

Standard deviation of frequency(3) 5 —

resistance, and capacitance constant

Frequency chance with voltage VCC = 8 V to 40 V, TA= 25°C 1%

ΔfOSC —

Frequency change with temperature TA= MIN to MAX 2%

Output amplitude at OSC OUT TA= 25°C 3.5 V

tWOutput pulse duration (width) at OSC OUT CT= 0.01 μF, TA = 25°C 0.5 µs

Output section

V(BR)CE Collector-emitter breakdown voltage 40 V

Collector off-state current VCE = 40 V 0.01 50 µA

Vsat Collector-emitter saturation voltage IC= 50 mA 1 2 V

VOEmitter output voltage VC= 20 V, IE= –250 μA 17 18 V

trTurn-off voltage rise time RC= 2 kΩ0.2 µs

tfTurn-on voltage fall time RC= 2 kΩ0.1 µs

Comparator section

Maximum duty cycle, each output 45%

Zero duty cycle 1

VIT Input threshold voltage at COMP V

Maximum duty cycle 3.5

IIB Input bias current –1 µA

Current limiting section

VIInput voltage range –1 1 V

V(SENSE) Sense voltage at TA= 25°C 175 200 225 mV

V(IN+)–V(IN–) ≥50 mV V(COMP) 2 V

Temperature coefficient of sense voltage 0.2 mV/°C

Total Device

VCC = 40 V, IN–, CURR LIM+, CT,

GND, COMP, EMIT 1, EMIT 2

Ist Standby current 8 10 mA

grounded, IN+ at 2 V, All other inputs

and outputs open

(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

(2) All typical values, except for temperature coefficients, are at TA= 25°C.

(3) Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula:

Product Folder Links: SG2524 SG3524

SG2524

SG3524

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SLVS077E –APRIL 1977–REVISED JANUARY 2015

7.7 Typical Characteristics

Figure 1. Open-Loop Voltage Amplification of Error Figure 2. Oscillator Frequency vs Timing Resistance

Amplifier vs Frequency

Product Folder Links: SG2524 SG3524

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SG3524

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8 Parameter Measurement Information

Figure 3. General Test Circuit

Figure 4. Switching Times

Product Folder Links: SG2524 SG3524

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SG3524

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SLVS077E –APRIL 1977–REVISED JANUARY 2015

9 Detailed Description

9.1 Overview

SGx524 is a fixed-frequency pulse-width-modulation (PWM) voltage-regulator control circuit. The regulator

operates at a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RT

establishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the

comparator, providing linear control of the output pulse duration (width) by the error amplifier.

The SGx524 contains an onboard 5-V regulator that serves as a reference, as well as supplying the SGx524

internal regulator control circuitry. The internal reference voltage is divided externally by a resistor ladder network

to provide a reference within the common-mode range of the error amplifier as shown in Figure 11, or an external

reference can be used.

The output is sensed by a second resistor divider network and the error signal is amplified. This voltage is then

compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator then is

steered to the appropriate output pass transistor (Q1 or Q2) by the pulse-steering flip-flop, which is

synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to

ensure both outputs are never on simultaneously during the transition times. The duration of the blanking pulse is

controlled by the value of CT.

The outputs may be applied in a push-pull configuration in which their frequency is one-half that of the base

oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The

output of the error amplifier shares a common input to the comparator with the current-limiting and shut-down

circuitry and can be overridden by signals from either of these inputs. This common point is pinned out externally

via the COMP pin, which can be employed to either control the gain of the error amplifier or to compensate it. In

addition, the COMP pin can be used to provide additional control to the regulator.

9.2 Functional Block Diagram

A. Resistor values shown are nominal.

Product Folder Links: SG2524 SG3524

O(max)

V R2

I 200 mV

R R1 R2

200 mV

æ ö

= +

ç ÷

è ø

SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

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9.3 Feature Description

9.3.1 Blanking

The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled by

the value of CTas shown in Figure 2. If small values of CTare required, the oscillator output pulse duration can

be maintained by applying a shunt capacitance from OSC OUT to ground.

9.3.2 Error Amplifier

The error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or

AC phase compensation. The compensation node (COMP) is a high-impedance node (RL=5MΩ). The gain of

the amplifier is AV = (0.002 Ω–1)RLand easily can be reduced from a nominal 10,000 by an external shunt

resistance from COMP to ground. Refer to Figure 1 for data.

9.3.3 Compensation

COMP, as previously discussed, is made available for compensation. Since most output filters introduce one or

more additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier,

introduction of a zero to cancel one of the output filter poles is desirable. This can be accomplished best with a

series RC circuit from COMP to ground in the range of 50 kΩand 0.001 μF. Other frequencies can be canceled

by use of the formula f ≈1/RC.

9.3.4 Output Circuitry

SGx524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Each

transistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA for

fast response.

9.3.5 Current Limiting

A current-limiting sense amplifier is provided in the SGx524 device. The current-limiting sense amplifier exhibits a

threshold of 200 mV ±25 mV and must be applied in the ground line since the voltage range of the inputs is

limited to 1 V to –1 V. Caution should be taken to ensure the –1-V limit is not exceeded by either input,

otherwise, damage to the device may result.

Foldback current limiting can be provided with the network shown in Figure 5. The current-limit schematic is

shown in Figure 6.

Figure 5. Foldback Current Limiting for Shorted Output Conditions

Product Folder Links: SG2524 SG3524

SG2524

SG3524

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SLVS077E –APRIL 1977–REVISED JANUARY 2015

Feature Description (continued)

Figure 6. Current-Limit Schematic

9.4 Device Functional Modes

9.4.1 Synchronous Operation

When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator

output terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration, RTCTmust be

selected for a clock period slightly greater than that of the external clock.

If two or more SGx524 regulators are operated synchronously, all oscillator output terminals must be tied

together. The oscillator programmed for the minimum clock period is the master from which all the other

SGx524s operate. In this application, the CTRTvalues of the slaved regulators must be set for a period

approximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT(slave) to ensure that

the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slave

regulators.

9.4.2 Shutdown Circuitry

COMP also can be employed to introduce external control of the SGx524. Any circuit that can sink 200 μA can

pull the compensation terminal to ground and, thus, disable the SGx524.

In addition to constant-current limiting, CURR LIM+ and CURR LIM– also can be used in transformer-coupled

circuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LIM–

also can be grounded to convert CURR LIM+ into an additional shutdown terminal.

Product Folder Links: SG2524 SG3524

SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

www.ti.com

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

There are a wide variety of output configurations possible when considering the application of the SG2524 as a

voltage-regulator control circuit. They can be segregated into three basic categories:

• Capacitor-diode-coupled voltage multipliers

• Inductor-capacitor-implemented single-ended circuits

• Transformer-coupled circuits

Examples of these categories are shown in Figure 7,Figure 8, and Figure 9, respectively. Typical Application

demonstrates how to set up the SG2524 for a capacitor-diode output design. The same techniques for setting up

the internal circuitry of the IC may also be used for the other two output stage examples shown Examples of

Other Output Stages.

Figure 7. Capacitor-Diode-Coupled Voltage-Multiplier Output Stages

Product Folder Links: SG2524 SG3524

SG2524

SG3524

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SLVS077E –APRIL 1977–REVISED JANUARY 2015

Application Information (continued)

Figure 8. Single-Ended Inductor Circuit

Figure 9. Transformer-Coupled Outputs

Product Folder Links: SG2524 SG3524

T C

1.30

R R

SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

www.ti.com

10.2 Typical Application

10.2.1 Capacitor-Diode Output

Figure 10. Capacitor-Diode Output Circuit Schematic

10.2.1.1 Design Requirements

• 15-V supply voltage

• –5-V output voltage

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Oscillator

The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 12.

where

• RTis in kΩ

• CTis in μF

• f is in kHz (1)

Practical values of CT fall between 0.001 μF and 0.1 μF. Practical values of RT fall between 1.8 kΩand 100 kΩ.

This results in a frequency range typically from 130 Hz to 722 kHz.

10.2.1.2.2 Voltage Reference

The 5-V internal reference can be employed by use of an external resistor divider network to establish a

reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 11), or an external

reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal

reference can be bypassed by applying the input voltage to both the VCC and VREF terminals. In this

configuration, however, the input voltage is limited to a maximum of 6 V.

Product Folder Links: SG2524 SG3524

R1 R2

V 2.5 V

V 2.5 V 1

æ ö

= -

ç ÷

è ø

SG2524

SG3524

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SLVS077E –APRIL 1977–REVISED JANUARY 2015

Typical Application (continued)

Figure 11. Error-Amplifier Bias Circuits

10.2.1.3 Application Curves

Figure 12. Output Dead Time vs Timing Capacitance

Product Folder Links: SG2524 SG3524

SG2524

SG3524

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10.3 Examples of Other Output Stages

10.3.1 Flyback Converter

Figure 13. Flyback Converter Circuit Schematic

10.3.2 Single-Ended LC

Figure 14. Single-Ended LC Circuit Schematic

Product Folder Links: SG2524 SG3524

SG2524

SG3524

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SLVS077E –APRIL 1977–REVISED JANUARY 2015

Examples of Other Output Stages (continued)

10.3.3 Push-Pull Transformer-Coupled

Figure 15. Push-Pull Transformer-Coupled Circuit Schematic

Product Folder Links: SG2524 SG3524

SG2524

SG3524

SLVS077E –APRIL 1977–REVISED JANUARY 2015

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11 Power Supply Recommendations

SGx524 is designed to operate from an input voltage supply range between 8 V and 40 V. This input supply

should be well regulated. If the input supply is located more than a few inches from the device, additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. A tantalum capacitor with a value of

47 μF is a typical choice, however this may vary depending upon the output power being delivered.

12 Layout

12.1 Layout Guidelines

Always try to use a low EMI inductor with a ferrite type closed core. Some examples would be toroid and

encased E core inductors. Open core can be used if they have low EMI characteristics and are located a bit

more away from the low power traces and components. Make the poles perpendicular to the PCB as well if using

an open core. Stick cores usually emit the most unwanted noise.

12.1.1 Feedback Traces

Try to run the feedback trace as far from the inductor and noisy power traces as possible. You would also like

the feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but

keeping it away from inductor EMI and other noise sources is the more critical of the two. Run the feedback trace

on the side of the PCB opposite of the inductor with a ground plane separating the two.

12.1.2 Input/Output Capacitors

When using a low value ceramic input filter capacitor, it should be located as close to the VIN pin of the IC as

possible. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner

voltage supply. Some designs require the use of a feed-forward capacitor connected from the output to the

feedback pin as well, usually for stability reasons. In this case it should also be positioned as close to the IC as

possible. Using surface mount capacitors also reduces lead length and lessens the chance of noise coupling into

the effective antenna created by through-hole components.

12.1.3 Compensation Components

External compensation components for stability should also be placed close to the IC. Surface mount

components are recommended here as well for the same reasons discussed for the filter capacitors. These

should not be located very close to the inductor either.

12.1.4 Traces and Ground Planes

Make all of the power (high-current) traces as short, direct, and thick as possible. It is good practice on a

standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. The inductor,

output capacitors, and output diode should be as close to each other possible. This helps reduce the EMI

radiated by the power traces due to the high switching currents through them. This will also reduce lead

inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce

voltage errors.

The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should be connected

close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of

the PCB. This will reduce noise as well by reducing ground loop errors as well as by absorbing more of the EMI

radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used to

separate the power plane (where the power traces and components are) and the signal plane (where the

feedback and compensation and components are) for improved performance. On multi-layer boards the use of

vias will be required to connect traces and different planes. It is good practice to use one standard via per 200

mA of current if the trace will need to conduct a significant amount of current from one plane to the other.

Arrange the components so that the switching current loops curl in the same direction. Due to the way switching

regulators operate, there are two power states. One state when the switch is on and one when the switch is off.

During each state there will be a current loop made by the power components that are currently conducting.

Place the power components so that during each of the two states the current loop is conducting in the same

direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces

radiated EMI.

Product Folder Links: SG2524 SG3524

GND

SG2524

IN+

CURR LIM+

CURR LIM±

9COMP

10SHUTDOWN

EMIT 1

COL 1

EMIT 2

VCC

REF OUT

OSC OUT

IN±

GND

COL 2

VIA to Power Plane

Power or GND Plane

VIA to GND Plane

LEGEND

VCC

OUTPUT

SG2524

SG3524

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SLVS077E –APRIL 1977–REVISED JANUARY 2015

12.2 Layout Example

Figure 16. Layout Example for SG2524

Product Folder Links: SG2524 SG3524

SG2524

SG3524

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13 Device and Documentation Support

13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

SG2524 Click here Click here Click here Click here Click here

SG3524 Click here Click here Click here Click here Click here

13.2 Trademarks

All trademarks are the property of their respective owners.

13.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: SG2524 SG3524

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SG2524D ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524

SG2524DR ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524

SG2524DRE4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524

SG2524DRG4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524

SG2524N ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -25 to 85 SG2524N

SG3524D ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524

SG3524DR ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524

SG3524DRE4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524

SG3524N ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SG3524N

SG3524NE4 ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SG3524N

SG3524NSR ACTIVE SO NS 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SG2524DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

SG2524DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

SG3524DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

SG3524NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Nov-2014

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SG2524DR SOIC D 16 2500 333.2 345.9 28.6

SG2524DRG4 SOIC D 16 2500 333.2 345.9 28.6

SG3524DR SOIC D 16 2500 333.2 345.9 28.6

SG3524NSR SO NS 16 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Nov-2014

Pack Materials-Page 2

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