ISL8013AIRZ-T - Intersil Corporation

ISL8013A

3A Low Quiescent Current 1MHz High Efficiency

Synchronous Buck Regulator

ISL8013A

The ISL8013A is a high efficiency, monolithic,

synchronous step-down DC/DC converter that can

deliver up to 3A continuous output current from a 2.8V to

5.5V input supply. It uses a current control architecture

to deliver very low duty cycle oper ation at high frequency

with fast transient response and ex cellent loop stability.

The ISL8013A integrates a pair of low ON-resistance

P-Channel and N-Channel internal MOSFETs to maxim ize

efficiency and minimize external component count. The

100% duty-cy cle operation allows less than 300mV

dropout voltage at 3A output curren t. High 1MHz

pulse-width modulation (PWM) switching frequency

allows the use of small external components and SYNC

input enables multiple ICs to synchronize out of phase to

reduce ripple and eliminate beat frequencies.

The ISL8013A can be configured for discontinuous or

forced continuous operation at light load. F orced

continuous operation reduces no ise and RF interf erence

while discontinuous mode provides high efficiency by

reducing switching losses at light loads.

Fault protection is pro vided by internal hiccup mode

current limiting during short circuit and overcurrent

conditions, an output over v oltage comparator and

over-temper ature monitor circuit. A power good output

voltage monitor indicates when the output is in

regulation.

The ISL8013A is offered in a space saving 4x4 QFN lead

free package with exposed pad lead fr ames f or low

thermal resistance.

The ISL8013A includes a pair of low ON-resistance

P-Channel and N-Channel internal MOSFETs to maxim ize

efficiency and minimize external component count. The

100% duty-cycle oper ation allows less than 300mV

dropout voltage at 3A.

The ISL8013A offers a 1ms Power Good (PG) timer at

power-up. When shutdown, ISL8013A discharges the

output capacitor. Other features include internal

soft-start, internal compensation, overcurrent protection,

and thermal shutdown.

The ISL8013A is offered in a 4mmx4mm 16 Ld QFN

package with 1mm maximum height. The complete

converter occupies less than 0.4in2 area.

Features

• High Efficiency Synchronous Buck Regulator with up

to 97% Efficiency

• Power-Good (PG) Output with a 1ms Delay

• 2.8V to 5.5V Supply Voltage

• 3% Output Accuracy Over-Temperature/Load/Line

• 3A Output Current

• Start-Up with Pre-Biased Output

• Internal Soft-Start - 1ms

• Soft-Stop Output Discharge During Disabled

• 35µA Quiescent Supply Current in PFM Mode

• Selectable Forced PWM Mode and PFM Mode

• External Synchronization up to 4MHz

• Less than 1µA Logic Controlled Shutdown Current

• 100% Maximum Duty Cycle

• Internal Current Mode Compensation

• Peak Current Limiting and Hiccup Mode Short Circuit

Protection

• Over-Temperature Protection

• Small 16 Ld 4mmx4mm QFN

• Pb-Free (RoHS Compliant)

Applications*(see page 16)

• DC/DC POL Modules

•µC/µP, FPGA and DSP Power

• Plug-in DC/DC Modules for Routers and Switchers

•Portable Instruments

• Test and Measurement Systems

• Li-ion Battery Powered Devices

• Small Form Factor (SFP) Modules

• Bar Code Readers

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a regi s tered trademark of Inters il Americas Inc.

All other trademarks mentioned are the property of their respective owners.

November 25, 2009

FN7526.0

2FN7526.0

November 25, 2009

Pin Configuration

ISL8013A

(16 LD QFN)

TOP VIEW

Ordering Information

PART NUMBER

(Notes 1, 2, 3) PART

MARKING

TEMP.

RANGE

(°C) PACKAGE

(Pb-Free) PKG.

DWG. #

ISL8013AIRZ 80 13AIRZ -40 to +85 16 Ld 4x4 QFN L16.4x4

NOTES:

1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb -free plast ic packaged produ cts emplo y special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temper atures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8013A. For more information on MSL please

see techbrief TB363.

VIN

VDD

SYNCH

16 14 13

6578

PGND

SGND

VFB

Refer to Application Note AN1365 for more layout suggestions.

Pin Descriptions

PIN NUMBER PIN NAME DESCRIPTION

1, 2 VIN Input supply voltage. Connect a 10µF ceramic capacitor to power ground.

3 VDD Input supply voltage for the analog circuitry. Connect to VIN pin.

5 EN Regulator enable pin. Enable the output when driven to high. Shut down the chip and

discharge output capacitor when driven to low. Do not leave this pin floating.

7PG 1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal

for the output voltage.

4 SYNCH Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect

to logic low or ground for PFM mode. Connect to an external function generator for

synchronization with the negative edge trigger. Do not leave this pin floating.

13, 14, 15 LX Switching node connection. Connect to one terminal of the inductor.

11, 12 PGND Power ground

9, 10 SGND Signal ground.

8 VFB Buck regulator output feedback. Connect to the output through a resistor divider for

adjustable output voltage. For 0.8V output voltage, connect this pin to the output.

6, 16 NC No connect.

- Exposed Pad The exposed pad must be connected to the SGND pin for proper electrical performance.

Place as much vias as possible under the pad connecting to SGND plane for optimal

thermal performance.

ISL8013A

3FN7526.0

November 25, 2009

Typical Application

FIGURE 1. TYPICAL APPLICATION DIAGRAM

1.5µH

PGND

VFB

VIN

SYNCH

INPUT 2.8V TO 5.5V OUTPUT

1.8V

2 x 22µF

ISL8013A

124k

100k

2 x 22µF

VDD

SGND

47pF

100k

ISL8013A

4FN7526.0

November 25, 2009

Block Diagram

FIGURE 2. FUNCTIONAL BLOCK DIAGRAM

CSA

OCP 1.4V

0.5V

SKIP

Slope

COMP

SLOPE

Soft

START

SOFT

0.8V EAMP COMP PWM/PFM

LOGIC

CONTROLLER

PROTECTION

DRIVER

VFB

0.736V

SYNCH

SHUTDOWN

VIN

PGND

OSCILLATOR

ZERO-CROSS

SENSING

BANDGAP

SCP

0.2V

SHUTDOWN

1ms

DELAY

27pF

390k

SGND

3pF

ISL8013A

5FN7526.0

November 25, 2009

Absolute Maximum Ratings (Reference to GND)Thermal Information

VIN, VDD . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)

EN, SYNCH, PG . . . . . . . . . . . . . . . . . .-0.3V to VIN + 0.3V

LX . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)

VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.8V

Recommended Operating Conditions

VIN Supply Voltage Range. . . . . . . . . . . . . . . . 2.8V to 5.5V

Load Current Range . . . . . . . . . . . . . . . . . . . . . . .0A to 3A

Ambient Temperature Range . . . . . . . . . . . .-40°C to +85°C

Thermal Resistance (Typical, Notes 4, 5))θJA (°C/W)θJC (°C/W)

16 Ld 4x4 QFN Package . . . . . . . 39 3

Junction Temperature Range . . . . . . . . . . -55°C to +125°C

Storage Temperature Range. . . . . . . . . . . -65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

features. See Tech Brief TB379.

5. θJC, “case temper atu re” locat ion is at the cent er of the expose d metal pad on th e package u nderside.

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended

operating conditions and the typical specification are measured at the following conditions

unless otherwise no ted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are at

TA= +25°C. Boldface limits apply over the operating temperature range, -40°C to

+85°C.

PARAMETER SYMBOL TEST CONDITIONS MIN

(Note 7) TYP MAX

(Note 7) UNITS

INPUT SUPPLY

VIN Undervoltage Lockout Threshold VUVLO Rising, no load -2.6 2.8 V

Falling, no load 2.15 2.35 -V

Quiescent Supply Current IVIN SYNCH = GND , no load at the output -35 -µA

SYNCH = GND, no load at the output

and no switches switching -30 45 µA

SYNCH = VDD, FS = 1MHz, no load

at the output -6.5 10 mA

Shut Down Supply Current ISD VIN = 5.5V, EN = low -0.1 2µA

OUTPUT REGULATION

Reference Voltage VREF 0.790 0.8 0.810 V

VFB Bias Current IVFB VFB = 0.75V -0.1 -µA

Line Regulation VIN = VO + 0.5V to 5.5V (minimal

2.8V) -0.2 -%/V

Soft-Start Ramp Time Cycle -1-ms

OVERCURRENT PROTECTION

Current Limit Blanking Time tOCON -17 -Clock pulses

Overcurrent and Auto Restart

Period tOCOFF -4-SS cycle

Switch Current Limit ILIMIT (Note 6) 4.0 4.8 5.9 A

Pea k S kip Limit ISKIP (Note 6) -1.2 -A

COMPENSATION

Error Amplif ier Trans-Conductance -20 -µA/V

Trans-Resistance RT 0.213 0.25 0.287 Ω

ISL8013A

6FN7526.0

November 25, 2009

P-Channel M OSFET ON-Resistance VIN = 5V, IO = 200mA -50 75 mΩ

VIN = 2.8V, IO = 200mA -70 100 mΩ

N-Channel MOSFET ON-Resistanc e VIN = 5V, IO = 200mA -50 75 mΩ

VIN = 2.8V, IO = 200mA -70 100 mΩ

LX Maximum Duty Cycle -100 -%

PWM Switching Frequency fS0.80 1.00 1.20 MHz

LX Minimum On-Time SYNCH = High --140 ns

Output Low Voltage Sinking 1mA --0.3 V

Delay Time (Rising Edge) 0.65 11.35 ms

PG Pin Leakage Current PG = VIN = 3.6V -0.01 0.1 µA

PGOOD Rising Threshold Percentage of regulation voltage 89 92 95 %

PGOOD Falling Threshold Percentage of regulation voltage 85 88 91.5 %

PGOOD Delay Time (Falling Edge) -15 -µs

EN, SYNCH

Logic Input Low --0.4 V

Logic Input High 1.4 --V

Synch Logic Input Leakage Current ISYNCH Pulled up to 5.5V -0.1 1µA

Enable Logic Input Leakage Current IEN -0.1 1µA

Thermal Shutdown -140 -°C

Thermal Shutdown Hyst eresis -25 -°C

NOTES:

6. Limits established by characterization and are not production tested.

7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established

by characterization and are not production tested.

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended

operating conditions and the typical specification are measured at the following conditions

unless otherwise no ted: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD. Typical values are at

TA= +25°C. Boldface limits apply over the operating temperature range, -40°C to

+85°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN

(Note 7) TYP MAX

(Note 7) UNITS

ISL8013A

7FN7526.0

November 25, 2009

ISL8013A

Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C,

VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,

C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A.

FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)

FIGURE 5. EFFICIENCY vs LOAD (

1MHz 5V

PWM)

FIGURE 6. EFFICIENCY vs LOAD (

1MHz 5V

PFM

)

FIGURE 7. POWER DISSIPATION vs LOAD (1MHz,

VOUT = 1.8V) FIGURE 8. POWER DISSIPATION WITH NO LOAD vs

VIN (PWM VOUT = 1.8V)

100

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PWM1.8VOUT-PWM

1.5VOUT-PWM

1.2VOUT-PWM

0.0 0.5 1.0 1.5 2.0 2.5 3.0 40

100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PFM1.8VOUT-PFM 1.5VOUT-PFM

1.2VOUT-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

100

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PWM

1.8VOUT-PWM 1.5VOUT-PWM

1.2VOUT-PWM

3.3VOUT-PWM

100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

EFFICIENCY (%)

2.5VOUT-PFM1.8VOUT-PFM

1.5VOUT-PFM

1.2VOUT-PFM

3.3VOUT-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

OUTPUT LOAD (A)

POWER DISSIPATION (mW)

5VIN-PWM

3.3V

IN-PFM

3.3VIN-PWM

5VIN-PFM

100

125

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN (V)

POWER DISSIPATION (mW)

8FN7526.0

November 25, 2009

FIGURE 9. POWER DISSIPATION WITH NO LOAD vs

VIN (PFM VOUT = 1.8V) FIGURE 10. VOUT REGULATION vs LOAD (1MHz,

VOUT = 1.2V)

FIGURE 11. VOUT REGULATION vs LOAD (1MHz,

VOUT = 1.5V) FIGURE 12. VOUT REGULATION vs LOAD (1MHz,

VOUT = 1.8V)

FIGURE 13. VOUT REGULATION vs LOAD (1MHz,

VOUT = 2.5V) FIGURE 14. VOUT REGULATION vs LOAD (1MHz,

VOUT = 3.3V)

Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C,

VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,

C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued)

0.05

0.10

0.15

0.20

0.25

POWER DISSIPATION (mW)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VIN (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.

1.16

1.17

1.18

1.19

1.20

1.21

1.22

1.23

1.24

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

3.3VIN-PFM

3.3VIN-PWM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

3.3VIN-PFM

3.3VIN-PWM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

1.75

1.76

1.77

1.78

1.79

1.80

1.81

1.82

1.83

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM 3.3VIN-PWM

3.3VIN-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.0

2.44

2.45

2.46

2.47

2.48

2.49

2.50

2.51

2.52

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

3.3VIN-PWM

3.3VIN-PFM

0.0 0.5 1.0 1.5 2.0 2.5 3.

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

3.36

OUTPUT LOAD (A)

OUTPUT VOLTAGE (V)

5VIN-PWM

5VIN-PFM

4.5VIN-PFM

4.5VIN-PWM

ISL8013A

9FN7526.0

November 25, 2009

FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN

(PWM VOUT = 1.8 ) FIGURE 16. OUTPUT VOLTAGE REGULATION vs VIN

(PFM VOUT = 1.8V)

FIGURE 17. STEADY STATE OPERATION AT NO LOAD

(PWM) FIGURE 18. STEADY STATE OPERATION AT NO LOAD

(PFM)

FIGURE 19. STEADY STATE OPERA TION WITH FULL

LOAD

FIGURE 20. MODE TRANSITION CCM TO DCM

Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C,

VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,

C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued)

1.750

1.760

1.770

1.780

1.790

1.800

1.810

1.820

1.830

OUTPUT VOLTAGE (V)

2.02.53.03.54.04.55.05.

INPUT VOLTAGE (V)

3A LOAD PWM 0A LOAD PWM

1.750

1.760

1.770

1.780

1.790

1.800

1.810

1.820

1.830

OUTPUT VOLTAGE (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.

INPUT VOLTAGE (V)

3A LOAD 0A LOAD

LX 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 0.5A/DIV

LX 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 0.5A/DIV

LX 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

ISL8013A

10 FN7526.0

November 25, 2009

FIGURE 21. MODE TRANSITION DCM TO CCM FIGURE 22. LOAD TRANSIENT (PWM)

FIGURE 23. LOAD TRANSIENT (PFM) FIGURE 24. SOFT-START WITH NO LOAD (PWM)

FIGURE 25. SOFT-START AT NO LOAD (PFM) FIGURE 26. SOFT-START WITH PRE-BIASED 1V

Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C,

VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,

C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued)

LX 2V/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DIV

LX 2V/DIV

VOUT RIPPLE 50mV/DIV

IL 1A/DI V

EN 5V/DIV

VOUT 0.5V/DIV

IL 1A/DIV

PG 5V/DIV

EN 5V/DIV

VOUT 0.5V/DIV

IL 1A/DIV

PG 5V/DIV

EN 5V/DIV

VOUT 0.5V/DIV

IL 5A/DI V

PG 5V/DIV

ISL8013A

11 FN7526.0

November 25, 2009

FIGURE 27. SOFT-START AT FULL LOAD FIGURE 28. SOFT-DISCHARGE SHUTDOWN

FIGURE 29. STEADY STATE OPERATION AT NO LOAD

WITH FREQUENCY = 2MHz FIGURE 30. STEADY STATE OPERATION AT FULL

LOAD WITH FREQUENCY = 2MHz

FIGURE 31. STEADY STATE OPERATION AT NO LOAD

WITH FREQUENCY = 4MHz FIGURE 32. STEADY STATE OPERATION AT FULL

LOAD (PWM) WITH FREQUENCY = 4MHz

Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C,

VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,

C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued)

VOUT 0.5V/DIV

IL 1A/DI V

EN 5V/DIV

PG 5V/DIV

VOUT 0.5V/DIV

IL 1A/DIV

EN 5V/DIV

PG 5V/DIV

LX 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

SYNCH 2V/DI V

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DIV

LX 2V/DIV

SYNCH 2V/DIV

VOUT RIPPLE 20mV/DIV

IL 1A/DI V

ISL8013A

12 FN7526.0

November 25, 2009

Theory of Operation

The ISL8013A is a step-down switching regulator

optimized for battery -powered handheld applications.

The regulator operates at 1MHz fixed switching

frequency under heavy load conditions to allow smaller

external inductors and capacitors to be used for minimal

printed-circuit board (PCB) area. At light load, the

regulator reduces the switching frequency, unless forced

to the fixed frequency , to minimize the switching loss and

to maximize the battery life. The quiescent current when

the output is not loaded is typically only 35µA. The

supply current is typically only 0.1µA when the regulator

is shut down.

PWM Control Scheme

Pulling the SYNCH pin HI (>2.5V) forces the converter

into PWM mode, regardless of output current. The

ISL8013A employs the current-mode pulse-width

modulation (PWM) control scheme for fast tr ansient

response and pulse-by-pulse current limiting. Figure 2

shows the block diagram. The current loop consists of the

oscillator, the PWM comparator, current sensing circuit

and the slope compensation for the current loop stability.

The gain for the current sensing circuit is typically

250mV/A. The control reference for the current loops

comes from the error amplifier's (EAMP) output.

The PWM oper at ion is in itiali ze d by the cloc k from the

oscillator. The P-Channel MOSFET is turned on at the

beginning of a PWM cycle and the current in the

MOSFET starts to ramp up. When the sum of the current

amplifier CSA and the slope compensation (237mV/µs)

reaches the control reference of the current loop, the

PWM compar ator COMP se nds a signal to the P WM logic

to turn off the P-MOSFET and turn on the N-Channel

MOSFET. The N-MOSFET stays on until the end of the

PWM cycle. Figure 36 shows the typical operating

waveforms during the PWM operation. The dotted lines

illustr ate the sum of the slope compen sati on r amp a nd

the current-sense amplifier’s CSA output.

The output voltage is regulated by controlling the VEAMP

voltage to the current loop. The bandgap circuit o utputs

a 0.8V reference voltage to the voltage loop. The

feedback signal comes from the VFB pin. The soft-start

FIGURE 33. OUTPUT SHORT CIRCUIT FIGURE 34. OUTPUT SHORT CIRCUIT RECOVERY

FIGURE 35. OUTPUT CURRENT LIMIT vs TEMPERATURE

Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C,

VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH,

C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A. (Continued)

PHASE 2V/DIV

VOUT 0.5V/DIV

IL 2A/DIV

PG 5V/DIV

LX 2V/DIV

VOUT 1V/DIV

IL 2A/DI V

PG 5V/DIV

4.000

4.125

4.250

4.375

4.500

4.625

4.750

4.875

5.000

-50-250 255075100

TEMPERATURE (°C)

OUTPUT CURRENT (A)

OCP_3.3VIN

OCP_5VIN

ISL8013A

13 FN7526.0

November 25, 2009

block, only affects the operation during the start -up and

will be discussed separately. The error amplifier is a

transconductance amplifier that con verts the v oltage

error signal to a current output. The voltage loop is

internally compensated with the 27pF and 390kΩ RC

network. The maximu m EAMP voltage output is precisely

clamped to 1.6V.

SKIP Mode

Pulling the SYNCH pin LO (<0.4V) forces the converter

into PFM mode. The ISL8013A enters a pulse-skipping

mode at light load to minimize the switching loss by

reducing the switching frequency. Figure 37 illustr ates

the skip-mode operation. A zero-cross sensing circuit

shown in Figure 2 monitors the N-MOSFET current for

zero crossing. When 8 consecutive cycles of the inductor

current crossing zero are detected, the regulator enters

the skip mode. During the eight detecting cycles, the

current in the inductor is allowed to become negativ e.

The counter is reset to zero when the current in any cycle

does not cross zero.

Once the skip mode is entered, the pulse modulation

starts being controlled by the SKIP comparator shown in

Figure 2. Each pulse cycle is still synchronized by the

PWM clock. The P-MOSFET is turned on at the clock's

rising edge and turned off when the output is higher than

1.5% of the nominal regulation or when its current

reaches the peak Skip current limit value. Then the

inductor current is discharging to 0A and sta ys at z ero.

The internal clock is disabled.The output voltage reduces

gradually due to the load current discharging the output

capacitor. When the output voltage drops to the nominal

voltage, the P-MOSFET will be turned on again at the

rising edge of the internal clock as it repeats the previous

operations.

The regulator resumes normal PWM mode operation

when the output voltage drops 1.5% below the nominal

voltage.

Synchronization Control

The frequency of operation can be synchronized u p to

4MHz by an external signal applied to the SYNCH pin.

The falling edge on the SYNCH triggers the rising edge of

the LX pulse. Make sure that the minimum on time of the

LX node is greater than 140ns.

Overcurrent Protection

The overcurrent protec tion is realized by monitoring the

CSA output with th e OCP compa r at or, as shown in

Figure 2. The current sensing circuit has a gain of

250mV/A, from the P-MOSFET current to the CSA

output. When the CSA output reaches 1.4V, which is

equiv ale nt to 4.8A fo r the swit ch cu rrent, th e OC P

compar ator is tripped t o tur n off t he P-MOSFET

immediately. The ov ercurren t function protects the

switching con v erter from a shor ted outpu t by

monitori ng the curr ent flow in g thro ugh t he upper

MOSFET.

Upon detection of overcurrent condition, the upper

MOSFET will be immediately turned off and will not be

turned on again until the next switching cy cle. Upon

detection of the initial overcurrent condition, the

overcurrent fault counter is set to 1. If, on the

subsequent cycle, another ov ercurren t condition is

detected, the OC fault counter will be incremented. If

there are 17 sequential OC fault detections, the regulator

will be shut down under an ov ercurrent fault condition.

An overcurrent fault condition will result in the regulator

attempting to restart in a hiccup mode within the delay of

four soft-start periods. A t the end of the fourth soft -start

wait period, the fault counters are reset and soft -start is

attempted again. If the overcurrent condition goes aw ay

during the delay of four soft-start periods, the output will

resume back into regulation point after hiccup mode

expires.

Short-Circuit Protection

The short-circuit protection SCP comparator monitors the

VFB pin voltage for output short -circuit protection. When

the VFB is lower than 0.2V, the SCP comparator forces

the PWM oscillator frequency to drop to 1/3 of the normal

operation v alue. This comparator is effective during start -

up or an output short-circu it ev ent.

FIGURE 36. PWM OPERATION WAVEFORMS

VEAMP

VCSA

DUTY

CYCLE

VOUT

ISL8013A

14 FN7526.0

November 25, 2009

During power-up, the open-drain power good output

holds low for about 1ms after VOUT reaches the

regulation voltage. The PG output also serves as a 1ms

delayed the P ower Good signal when the pull-up resistor

R1 is installed.

UVLO

When the input voltage is b elow th e underv oltag e

lock- out (UVLO) threshold, the regulator is disabled.

Soft Start-Up

The soft-start -up reduces the inrush current during the

start-up. The soft-start block outputs a ramp reference to

the input of the error amplifier. This voltage ramp limits

the inductor current as well as the output voltage speed

so that the output voltage rises in a controlled fashion.

When VFB is less than 0.2V at the beginning of the

soft-start, the switching frequency is reduced to 1/3 of

the nominal v alue so that the output can start -up

smoothly at light load condition. During soft-start, the IC

operates in the SKIP mode to support pre-biased output

condition.

Enable

The enable (EN) input allows the user to control the

turning on or off the regulator for purposes such as

power-up sequencing. When the regulator is enabled,

there is typically a 600µs delay for waking up the

bandgap reference and then the soft-start -up begins.

Discharge Mode (Soft-Stop)

When a transition to shu tdown mode occurs or the V IN

UVLO is set, the outputs discharge to GND through an

internal 100Ω switch.

Power MOSFETs

The power MOSFETs are optimized for best efficiency.

The ON-resistance for the P-MOSFET is typically 50mΩ

and the ON-resistance for the N-MOSFET is typically

50mΩ.

100% Duty Cycle

The ISL8013A features 100% duty cycle operation to

maximize the battery life. When the battery vo ltage

drops to a level that the ISL8013A can no longer

maintain the regulation at the output, the regulator

completely turns on the P-MOSFET. The maximum

dropout voltage under the 100% duty -cycle operation is

the product of the load current and the ON-resistance of

the P-MOSFET.

Thermal Shut-Down

The ISL8013A has built-in thermal protection. When the

internal temperature reaches +140°C, the regulator is

completely shut down. As the temper ature drops to

+115°C, the ISL8013A resumes operation by stepping

through the soft-start.

Applications Information

Output Inductor and Capacitor Selection

To consider steady state and tr ansient operations,

ISL8013A typically uses a 1.5µH output inductor. The

higher or lower inductor value can be used to optimize

the total converter system performance. For example, for

higher output voltage 3.3V application, in order to

decrease the inductor current ripple and output voltage

ripple, the output inductor value can be increased. It is

recommended to set the ripple inductor current

approximately 30% of the maximum output current for

optimized performance. The inductor ripple current can

be expressed as shown in Equation 1:

The inductor’s satur ation current r ating needs to be at

least larger than the peak current. The ISL8013A

protects the typical peak current 4.8A. The saturation

current needs be over 5.5A for maximum output current

application.

ISL8013A uses internal compensation network and the

output capacitor value is dependent on the output

FIGURE 37. SKIP MODE OPERATION WAVEFOR M S

CLOCK

VOUT

NOMINAL +1.5%

NOMINAL

PFM CURRENT LIMIT

LOAD CURRENTT

PWM PFM

8 CYCLES

ΔI

VO1VO

VIN

---------

–

⎝⎠

⎜⎟

⎛⎞

⋅

-------------------------------------

(EQ. 1)

ISL8013A

15 FN7526.0

November 25, 2009

voltage. The ceramic capacitor is recommended to be

X5R or X7R. The recommended X5R or X7R minimum

output capacitor values are shown in Table 1. In Table 1,

the minimum output capacitor v alue is given for th e

different output voltage to mak e sure that the whole

converter system is stable. Additional output capacitance

should be added for better performances in applications

where high load transient or low output ripple is required.

It is recommended to check the system level

performance along with the simulation model.

Output Voltage Selection

The output voltage of the regulator can be progr ammed

via an external resistor divider that is used to scale the

output voltage relativ e to the internal reference v oltage

and feed it back to the inverting input of the error

amplifier. Refer to Figure 1.

The output voltage programming resistor, R3, will depend

on the value chosen for the feedback resistor and the

desired output voltage of the regulator. The value for the

feedback resistor is typically between 10kΩ and 100kΩ,

as shown in Equation 2.

If the output voltage desired is 0.8V, then R3 is left

unpopulated and R2 is shorted. There is a leakage

current from VIN to LX. It is recommended to preload the

output with 10µA minimum. F or better performance, add

47pF in parallel with R2 (100kΩ).

Input Capacitor Selection

The main functions for the input capacitor are to provide

decoupling of the parasitic inductance and to pro vide

filtering function to prevent the switching current flowing

back to the battery r ail. Tw o 22µF X5R or X7R cer amic

capacitors are a good starting point for the input

capacitor selection.

TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT

VOUT (V) COUT (µF) L (µH)

0.8 2 x 22 1.0~2.2

1.2 2 x 22 1.0~2.2

1.5 2 x 22 1.5~3.3

1.8 2 x 22 1.5~3.3

2.5 2 x 22 1.5~3.3

3.3 2 x 22 2.2~4.7

3.6 2 x 22 2.2~4.7

R3R20.8V⋅

VOUT 0.8V–

----------------------------------=(EQ. 2)

ISL8013A

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil produc ts are sol d by desc rip tio n o nly . Intersil Corpor ation reserves the rig ht to make ch ange s in c irc uit design, soft ware and/or specifications

at any time without n oti ce. Acco rdin gly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of t hird parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Inters il o r i ts s ub si di arie s .

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7526.0

November 25, 2009

For additional products, see www.intersil.com/product_tree

Products

Intersil Corporation is a leader in the design and manuf acture of high-performance analog semiconductors. The

Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,

handheld products, and notebooks. Intersil's product families address power management and analog signal

processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related P arts, please see the respective device

information page on intersil.com: ISL8013A

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is beli eved to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev.

DATE REVISION CHANGE

11/25/09 FN7526.0 Initial Release.

ISL8013A

17 FN7526.0

November 25, 2009

ISL8013A

Package Outline Drawing

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 6, 02/08

located within the zo ne indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if presen t) is a no n- functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the m etallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tole rancing conform to AMSE Y14.5m-19 94 .

either a mol d or mark featur e.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

INDEX AREA

(4X) 0.15

PIN 1

4.00

+0.15

-0.10

16X 0 . 60

2 . 10 ± 0 . 15

0.28 +0.07 / -0.05

PIN #1 INDEX AREA

0.10 CM

0.65

12X

4X 1.95

A B

( 3 . 6 TYP )

( 2 . 10 ) ( 12X 0 . 65 )

( 16X 0 . 28 )

( 16 X 0 . 8 )

SEE DETAIL "X"

BASE PLANE

1.00 MAX

0 . 2 REF

0 . 00 MIN.

0 . 05 MAX.

0.08 C

SEATING PLANE

0.10 C