AT24CS128N-10SU-2.7 - Atmel Corporation

Features

•One-time Programmable (OTP) Feature

•Low-voltag e and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 3.6V)

•Internally Or ganized 16,384 x 8

•2-w ire Serial Interface

•Schm itt Trigger, Filtered Inpu ts f or Noise Suppression

•Bidirectio nal Dat a Transfer Proto col

•1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V ) Compati bility

•Write Protect Pin f or Hardware and Software Data Protecti on

•64-byte Page Wr it e M ode (Partial Page Writes Allowed)

•Self-timed Write Cycle (5 ms typical)

•High Reliabilit y

– Endurance: 100,000 Write Cycles

– Data Retention: 40 Years

•Automotive Grade and Extended Temperature Devices Avai lable

•8-lead JEDEC PDIP, 8-lead JEDEC SOIC and 8-lead EIAJ SOIC Packages

Description

The AT24CS12 8 provides 131,072 bits of s eria l el ectr ically-erasable and programma-

ble read only memor y (EEPROM) organized as 16,384 words of 8 bits each. The

devi ce’s cascadable feature allows up t o 4 devices to share a common 2-wire bus . The

device also features a one-time programmable 2048-bit array, which once enabled,

becomes read-only and cannot be overwritten. If not enabled, the OTP section will

function as par t of the nor mal memor y array. The device is optimized for u se in many

industrial and commercial applications where low-power and low-voltage operation

are essential. The device is available in space-saving 8-lead JEDEC PDIP, 8-lead

JEDE C SOI C and 8 -lead E IAJ SO IC pa ckages. In a dditio n, the e ntir e famil y is avail-

able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6 V) versions.

Rev. 1152F–SEE PR–7/0 3

2-wire Se rial

EEPROMs

with Permanent

Software Write

Protect

128K (16,384 x 8)

AT24CS128

Pin Configurations

Pin Name Functi on

A0 - A2 Address Inputs

SDA Se r ia l D ata

SCL Serial Clock Input

WP Write Protect

PDIP

GND

VCC

SCL

SDA

Pin SOIC

GND

VCC

SCL

SDA

2AT24CS128 1152F–SEEPR–7/03

Block Diagram

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPRO M device and negat ive edge clock data out of each device.

SERIAL DATA (SDA ): The SDA pin i s bidirec tional fo r serial d ata tran sfer. Th is pin i s open-

drain driven and may be wire-ORed with any number of other open-drain or open collector

devices.

DEVICE/PA GE ADDR ESSES (A 2, A1, A0): The A1 and A0 pins are device address inputs

tha t a re hard wired or left not con ne cted fo r hardw are c omp atibili ty with AT24C 32 . W hen th e

pins ar e hardwi red, as m any as four 128K devices ma y be addres sed on a single b us s ystem

(device addressing is discussed in detail under the Device Addressing section). When the pins

are not hardwired, the default A1 and A0 are zero. The A2 device address input is a “don’t

care” input.

WRITE PROTECT (WP): The write protect input, when tied to GND, allo ws normal write oper-

ations. When WP is tied high to VCC, all write operations to the memory are inhibited. I f left

Absolute Ma ximum Ratings*

Operating Temperature.................................. -55°C to +125 °C*NOTICE: Stresses beyond those listed under “Ab solute

Maxim um Rati ngs” may cause permanent dam-

age to the de vice . This is a stre ss rating onl y and

functi onal operation of the device at these o r any

other conditi ons beyond those indicat ed in the

operational sections of this specification is not

impli ed. Exposure to absolute maxi m um rating

condit ions f or e xtended p eriods ma y aff ect device

reliability.

Storage Temperat ure....................... .. ............ -65°C to +15 0 °C

Voltage on Any Pin

wit h R e spe ct to Gr o und ........... ......... .......... .......-1 .0 V to +7.0 V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT24CS128

1152F–SEEPR–7/03

unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write

operation crea tes a software write protect function.

Memory Organization AT24CS128, 128K SERIAL EEPRO M: The 128K i s interna lly organi zed as 25 6 pages

of 64-bytes each. Random word addressing requires a 14-bit data word address.

Note: This param eter is characterized and is not 100% tested.

Note: VIL min and VIH max are reference only and are not tested.

Pin C apacitance(1)

Applicable over recomme nded operat ing range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol Test Condition Max Units Conditi ons

CI/O Input/Output Capacit ance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A0, A1, SCL) 6 pF VIN = 0 V

DC Characteristics

Applicable over recomme nded operat ing range from: TAI = -40 °C to +85°C, VCC = +1.8V to +5.5 V, TAC = 0°C to +70°C,

VCC = +1.8V to +5.5V (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.8 3.6 V

VCC2 Supply Voltage 2.7 5.5 V

VCC3 Supply Voltage 4.5 5.5 V

ICC1 Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA

ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

ISB1 Standby Curr ent

(1.8V option) VCC = 1.8V VIN = VCC or VSS 1.0 µA

VCC = 3.6V 3.0

ISB2 Standby Curr ent

(2.7V option) VCC = 2.7V VIN = VCC or VSS 2.0 µA

VCC = 5.5V 5.0

ISB3 Standby Curr ent

(5.0V option) VCC = 4.5 - 5.5V VIN = VCC or VSS 5.0 µA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA

ILO Output Leakage

Current VOUT = VCC or VSS 0.05 3.0 µA

VIL Input Low Level(Note:) -0.6 VCC x 0.3 V

VIH Input High Level(Note:) VCC x 0.7 VCC + 0.5 V

VOL2 Output Low Level VCC3 = 3.0V IOL = 2.1 mA 0.4 V

VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

4AT24CS128 1152F–SEEPR–7/03

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:

RL (connects to VCC) : 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)

Input pul se voltages: 0.3VCC to 0. 7V CC

Input rise and fall times: ≤50 ns

Input and out put timing reference voltages: 0.5VCC

AC Characteristics

Applicable over rec om me nded operating range from TA = -40°C to +85°C, VCC = +1.8V t o +5.5V, CL = 1 00 pF (unless ot h-

erwise noted). Test con ditions are listed in Note 2.

Symbol Parameter

1.8-volt 2.7-volt 5.0-volt

UnitsMin Max Min Max Min Max

fSCL Clock Frequency, SCL 100 400 1000 kHz

tLOW Clock Pulse Width Low 4.7 1.3 0.4 µs

tHIGH Clock Pulse Width High 4.0 0.6 0.4 µs

tAA Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs

tBUF Time the bus must be free before a new

transmi ssion can start(1) 4.7 1.3 0.5 µs

tHD.STA St a rt Hold Ti me 4. 0 0. 6 0.25 µs

tSU.STA Star t Set-up Time 4.7 0.6 0.25 µs

tHD.DAT Data In Hold Time 0 0 0 µs

tSU.DAT Data In Set -up Time 200 100 100 ns

tRInputs Rise Time(1) 1.0 0.3 0.3 µs

tFInputs F all Time(1) 300 300 100 ns

tSU.STO Stop Set -up Time 4.7 0.6 0.2 5 µs

tDH Data O ut Hol d Time 100 50 50 ns

tWR Write Cycle Time 20 10 10 ms

Endurance(1) 5.0V, 25°C, Page Mode 100K 100K 100K Write

Cycles

AT24CS128

1152F–SEEPR–7/03

Device

Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external

device. Data on the SDA pin may change only during SCL low time periods (refer to Data

Validity timing diagram). Data changes during SCL high periods will indicate a start or stop

condition as defined below .

START CONDITION: A h igh-to-low transition of SDA with SCL high is a start condition whi ch

must precede any other command (refer to Start and Stop Definition timing diagram).

STOP CO NDITION: A low-to-high transition of SDA with SCL high is a stop c ondition. After a

read sequ ence, the stop com m and wi ll plac e the E E PROM in a standby p ower m ode (ref er to

Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and da ta words are serially transmitted to and from the

EEPRO M in 8-bit words. The EEPR OM sends a zero du ring the ninth clock cycle to acknowl-

edge that it has received each word.

STANDBY MODE: The A T24C S12 8 fe atures a low-power st andby m ode wh ich is enabl ed: a)

upon power-up and b) aft er the receipt of the STOP bit and the completion of any internal

operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire

part can be reset by followin g these steps: (a) Clock up to 9 cycles, (b) look for SD A high in

each cycle while SCL is high and then (c) create a start condition as SDA is high.

6AT24CS128 1152F–SEEPR–7/03

Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Note: The write cycle time tWR is the time from a valid st op condition of a write sequence to the end of the int ernal clear/write cycle.

Data Validity

twr(1)

STOP

CONDITION START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

AT24CS128

1152F–SEEPR–7/03

Start and Stop Definition

Output Acknowledge

8AT24CS128 1152F–SEEPR–7/03

Device

Addressing The 128K EEPROM requires an 8-bit device address word foll owing a st art c ondition to enable

the chip for a read or write operation (refer to Figure 1). The device address word consists of a

mandatory one, zero sequence for the first five most significant bits as shown. This is common

to all 2 -w ire EEPR O M dev ices.

The 128K uses the two device address bits A1, A0 to allow as many as four devices on the

same bus. Th ese bits mus t com pare to their correspondi ng hardwired input pins. The A1 and

A0 pi ns use an intern al proprie tary circui t that biases them to a l ogic low con dition if t he pins

are allowed to float.

The eigh th bit of the devic e address is the rea d/write operatio n select bit. A rea d operation is

initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will ou tput a zer o. If a compare is not

made, the device w ill retu rn to a standby state.

DATA SECU RITY: Th e AT 24C S12 8 has a h ardwa re da ta p rote ction sche me th at a llo ws th e

user to write protect the whole memo ry when the WP pin is at VCC.

Write

Operations BY TE WRITE: A write operatio n requires t wo 8-bit dat a word addre sses follo wing the devi ce

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a zero and then c lock in the first 8-bit data word. Following receipt of the 8-bit

data word, the EEPROM will output a zero. The addressing dev ice, such as a m icrocont roller,

then must terminate the write sequence with a stop condition. At this time the EEPROM enters

an internally-timed wri te cycle, tWR, to th e nonvo lat ile mem ory. All input s ar e disab led du ring

this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).

PA GE WRITE: The 128K EEPRO M is capable of 64-byte page writes.

A page write is initiated the same way as a byte write, bu t the microco ntroller does not se nd a

stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the m icrocont roller can transm it up to 63 more data words. Th e

EEPROM will respond with a zero after each data word received. The microcontroller must ter-

minate the page write sequence with a stop condition (refer to Figure 3).

The data word address lower 6 bits are internally incremented following the receipt of each

data word. The higher data word address bits are not incremented, retaining the memory page

row locati on. When the w ord ad dre ss, in ternal ly gen er ated, reache s the pa ge bou ndary , th e

following byte is placed at the beginning of the same page. If more than 64 data words are

transmitted to the EEPROM, the data word address will “roll over” and previous data will be

overwritten. The address “roll over” during write is from the last byte of the curre nt page to the

first b yte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the

EEPROM inputs are disabled, ackn owledge polling can be initiated. This involves sending a

start condition followed by t he device address word . The read/write bit is repres entative of the

operation desired. Only if the internal write cycle has completed will the EEPROM respond

with a zero, allowing the read or write sequence to continue.

AT24CS128

1152F–SEEPR–7/03

OTP D esc r ipt io n/

Operation The OTP feature provides the user with a 2048-bit (256 x 8) securit y section, which once

programm ed and enabl ed, becomes read-only and data cannot be changed or overwrit-

ten. The OTP section is located in the upper 2K section of the memory array in the

AT 24CS128. If not enabl ed, the OTP sec tion wil l function as part of the no rmal m em ory

array.

To enable the OTP section:

1. Inputs must be connected:

A2 = Don’t Care, A1 and A0 = VCC or GND

2. Initiate the p rogramming sequenc e:

START 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx STOP

Onc e enab led, prev iousl y written d ata can not be changed . The sta tus of th e OTP sec-

tion can only be confirmed by initiating a programming sequence to the OTP section and

verifyi ng by a read co mmand. The u se of the write prote ct (WP) feature can be utilized

with or without enabling the OTP function.

Rea d Oper ati on s Read op eratio ns are initiated the same way as write operat ions with the ex ception t hat

the read/write sele ct bit in the d evice address word i s set to on e. There a re thre e read

operations : current address read, random add ress read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the

last a ddress acc essed during the last read or write operat ion , inc remen ted by one. This

address stays valid between operations as long as the chip power is maintained. The

addres s “roll over” during read is from the last byte of the last memory page, to the first

byte of the first page.

Once the device address with the rea d/write select bit set to one is cl ocked in and

acknowl edged by the EEPROM, the cur rent add ress data word is serially clocked out.

The microcon troller do es not res pond with an in put zero b ut does gen erate a followin g

stop condition (refer to Figure 4).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the

dat a word address . Onc e th e device add ress word an d data wo rd addres s are clocke d

in and ack nowledged by the E EPROM , the microcontroller must gen erate another start

con dition. The m icrocontroller now initiates a current address read by sending a device

address with the read/write select bit h igh. The EEPROM acknowledges the device

address and serially clock s out the data word. The microcontroller does not respond

with a zero but does generate a following stop condition (refer to Figure 5).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or

a random address re ad. After the m icroc ontroller receives a data word, it responds with

an ac know ledge. As long as the EEP ROM receives an ac know ledge, it will cont inue to

increment the data word address and serially clock out sequential data words. When the

mem ory addres s limi t is reac hed, t he dat a word addres s wil l “roll over” and t he sequen-

tial read will continue. The sequential read operation is terminated when the

micro controlle r does not respon d with a zero but do es generat e a fo llowing stop con di-

tion (refer to Figure 6).

10 AT24CS128 1152F–SEEPR–7/03

Figu re 1. Device Add r ess

Figu re 2. Byte Write

Figu re 3. P age Wr ite

(* = DON’T CARE bit)

(† = DON’T CARE bit f o r the 128K)

AT24CS128

1152F–SEEPR–7/03

Figu re 4. Current Address Read

Figu re 5. Random Read

(* = DON’T CARE bit)

(† = DON’T CARE bit f o r the 128K)

Figu re 6. Sequent ial Read

12 AT24CS128 1152F–SEEPR–7/03

Note: For 2.7V de vices used in t he 4.5V t o 5.5V range, please refer to performance values in t he AC and DC Charac teri stics tables.

AT24CS128 Ordering Information

Order ing Code Package Operation Range

AT24CS128-10PI-2.7

AT24CS128N-10SI-2.7

AT24CS128W-10SI-2.7

8P3

8S1

8S2

Industrial

(-40°C to 85°C)

AT24CS128-10PI-1.8

AT24CS128N-10SI-1.8

AT24CS128W-10SI-1.8

8P3

8S1

8S2

Industrial

(-40°C to 85°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Pack age (PDIP)

8S1 8-lead , 0.1 50" Wide, Pla sti c Gull Wing Small Outline (JEDEC SOIC)

8S2 8-lead, 0.200" Wide, Pl astic Gull Wing Small Outline (EIAJ SOIC)

Options

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 3.6V)

AT24CS128

1152F–SEEPR–7/03

Packaging Information

8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

01/09/02

8P3 B

A2 A

4 PLCS

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

A 0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005 3

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

14 AT24CS128 1152F–SEEPR–7/03

8S1 – JEDEC SOIC

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

Note:

10/10/01

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) 8S1 A

Top View

End View

Side View COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

A – – 1.75

B – – 0.51

C – – 0.25

D – – 5.00

E – – 4.00

e 1.27 BSC

H – – 6.20

L – – 1.27

AT24CS128

1152F–SEEPR–7/03

8S2 – EIAJ

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8S2, 8-lead, 0.209" Body, Plastic Small

Outline Package (EIAJ)

5/2/02

8S2 B

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.

A 1.78 2.03

A1 0.05 0.33

b 0.35 0.51 5

C 0.18 0.25 5

D 5.13 5.38

E 5.13 5.41 2, 3

H 7.62 8.38

L 0.51 0.89

e 1.27 BSC 4

Pr inted o n rec ycled pa per.

1152F–SEEPR–7/03 xM

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