RT8011/A
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DS8011/A-02 March 2011 www.richtek.com
Features
zz
zz
zHigh Efficiency : Up to 95%
zz
zz
zLow RDS(ON) Internal Switches : 110mΩΩ
ΩΩ
Ω
zz
zz
zProgrammable Frequency : 300kHz to 4MHz
zz
zz
zNo Schottky Diode Required
zz
zz
z0.8V Reference Allows Low Output Voltage
zz
zz
zForced Continuous Mode Operation
zz
zz
zLow Dropout Operation : 100% Duty Cycle
zz
zz
zSynchronizable Switching Frequency (For RT8011
Only)
zz
zz
zPower Good Output Voltage Monitor (For RT8011
Only)
zz
zz
zRoHS Compliant and 100% Lead (Pb)-Free
Applications
zPortable Instruments
zBattery-Powered Equipment
zNotebook Computers
zDistributed Power Systems
zIP Phones
zDigital Ca meras
General Description
The RT801 1/A is a high efficiency synchronous, step-down
DC/DC converter . Its in put voltage ra nge is from 2.6V to
5.5V and provides an adjustable regulated output voltage
from 0.8V to 5V while delivering up to 2A of output current.
The internal synchronous low on-resistance power
switches increase efficiency and eliminate the need for
an external Schottky diode. Switching frequency is set
by an external resistor or can be synchronized to an
external clock. 100% duty cycle provides low dropout
operation extending battery life in portable systems.
Current mode operation with external compensation
allows the transient response to be optimized over a wide
ra nge of loads and output ca pa citors.
RT8011/A operation in forced continuous PWM Mode which
minimizes ripple voltage and reduces the noise and RF
interference.
100% duty cycle in Low Dropout Operation further
maximize battery life.
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Ordering Information Pin Configurations
(TOP VIEW)
MSOP-10
2A, 4MHz, Synchronous Step-Down Regulator
Marking Information
For marking information, conta ct our sales representative
directly or through a Richtek distributor located in your
area.
WDFN-10L 3x3
SHDN/RT
PGND
GND COMP
FB
VDD
PVDD
LX 7
6
5
1
2
3
4
8
WDFN-8EL 3x3
COMP
VDD
SHDN/RT
LX
GND FB
PGOOD
PGND PVDD
SYNC
56
7
8
4
3
210
9
SHDN/RT
SYNC
PGND
LX
COMP
FB
PGOOD
PVDD
VDD
GND 9
8
7
9
1
2
3
4
5
10
RT8011/A Package Type
F : MSOP-10 (RT8011)
QW : WDFN-10L 3x3 (RT8011)
QW : WDFN-8EL 3x3 (RT8011A)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Without SYNC and PGOOD Function
With SYNC and PGOOD Function
RT8011/A
2DS8011/A-02 March 2011www.richtek.com
Typical Application Circuit
Figure 1. T ypical Application Circuit f or RT801 1
Figure 2. T ypical Application Circuit for RT801 1A
Note : Using all Ceramic Capacitors
COMP
FB
PGOOD
SHDN/RT
SYNC
LX
RT8011
1
2
47
8
9
VDD
PVDD
GND
6
5PGND
3
10
VIN
2.6V to 5.5V
VOUT
2.5V/2A
ROSC
332k
L1
2.2uH
RCOMP
13k
RPGOOD
100k
CIN
22uF
R2 240k
CCOMP
1000pF
C1
22pF
R1
510k
COUT
22uF
COMP
FB
SHDN/RT
LX
RT8011A
1
36
7
VDD
PVDD
GND
5
4PGND
2
8
VIN
2.6V to 5.5V
VOUT
2.5V/2A
ROSC
332k
L1
2.2uH
RCOMP
13k
CIN
22uF
R2 240k
CCOMP
1000pF
R1
510k
COUT
22uF
Component Supplier Series Inductance (μH) DCR (mΩ) Current Rati ng (mA) Dime n sions (mm )
TAIYO YUDEN NR 4018 2.2 60 2700 4x4x1.8
Sumida CDRH4D28 2.2 31.3 2040 4.5x4.5x3
GOTREND GTSD53 2.2 29 2410 5x5x2.8
ABC SR0403 2.2 47 2600 4.5x4x3.2
Table 1
Component Supplier Part No. Capacitance (μF) Case Size
TDK C3225X5R0J226M 22 1210
TDK C3225X5R0J226M 22 1210
TDK C2012X5R0J106M 10 0805
Panasonic ECJ4YB0J226M 22 1210
Panasonic ECJ4YB1A226M 22 1210
Panasonic ECJ4YB1A106M 10 1210
TAIY O Y UDEN LMK325BJ226ML 22 1210
TAIY O Y UDEN JMK316BJ226ML 22 1206
TAIY O Y UDEN JMK212BJ106ML 10 0805
Table 2
RT8011/A
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Functional Pin Description
Pin Number Pin Function
RT8011 RT8011A Pin Name
1 1 SHDN/RT
Oscillator Resistor Input. Connecting a resistor to ground from this pin sets
the switc hing f requency. Fo r cing t his pi n t o VDD causes the device to be shut
down.
2 -- SYNC
External Clock Synchronization Input. The oscillation frequency can be
synchronized to an external oscillation applied to this pin. When tied to VDD,
internal oscillator is selected.
3 2 GND
Signal Ground. All small-signal components and compensation components
should connect to this ground, which in turn connects to PGND at one point.
4 3 LX Internal Power MOSFET Switches Output. Connect this pin to the inductor.
5 4 PGND Power Ground. Connect this pin close to the (−) terminal of CIN and COUT.
6 5 PVDD Power Inpu t Sup ply. Decouple this pin to PGND with a capacitor.
7 6 VDD
Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VDD
is equal to PVD D.
8 -- PGOOD
Power Good Indicator. Open-drain logic output that is pulled t o ground when
the outp ut voltage is not within ±12.5% of regulation point.
9 7 FB Feedback Pin. Receives the feedback voltage from a resistive divider
connected across the output.
10 8 COMP
Error Amplifier Compensation Point. The current comparator threshold
increases with this control voltage. Connect external com pensation elements
to this pin to stabilize the control loop.
Figure 4. RT801 1A Layout Guide
Figure 3. RT801 1 Layout Guide
Layout Guide
VIN
GND
L1
VOUT
GND
CIN COUT VOUT
VIN
RCOMP
CCOMP
R2
R1
CFROSC
CIN must be placed between
VDD and GND as closer as
possible LX should be
connected to
Inductor by wide
and short trace,
keep sensitive
compontents away
from this trace
Output capacitor must
be near RT8011
Connect the FB pin directly to feedback resistors. The
resistor divider must be connected between VOUT and
GND.
COMP
VDD
SHDN/RT
LX
GND
FB
PGOOD
PGND
PVDD
SYNC
5
6
7
8
4
3
2
10
9
1
RT8011
VIN
GND
L1
VOUT
GND
CIN COUT VOUT
RCOMP
CCOMP
R2
R1
CFROSC
CIN must be placed between
VDD and GND as closer as
possible LX should be
connected to
Inductor by wide
and short trace,
keep sensitive
compontents away
from this trace
Output capacitor must
be near RT8011A
Connect the FB pin directly to feedback resistors. The
resistor divider must be connected between VOUT and
GND.
COMP
VDD
SHDN/RT
LX
GNDFB
PGND
PVDD 4
5
63
2
8
7
1
RT8011A
RT8011/A
4DS8011/A-02 March 2011www.richtek.com
Function Block Diagram
RT8011
RT8011A
Driver
NISEN
Control
Logic
NMOS I Limit
0.9V
0.7V
0.4V
OC
Limit
ISEN
Slope
Com
OSC
Output
Clamp
EA
0.8V
Int-SS
POR
OTP
VREF
COMP
SHDN/RT
GND
FB
PVDD
SYNC
VDD
PGOOD
PGND
SD
LX
Driver
NISEN
Control
Logic
NMOS I Limit
0.9V
0.7V
0.4V
OC
Limit
ISEN
Slope
Com
OSC
Output
Clamp
EA
0.8V
Int-SS
POR
OTP
VREF
COMP
SHDN/RT
GND
FB
PVDD
VDD
PGND
SD
LX
RT8011/A
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DS8011/A-02 March 2011 www.richtek.com
Operation
Main Control Loop
The RT801 1/A is a monolithic, constant-frequency, current
mode step-down DC/DC converter. During normal
operation, the internal top power switch (P-Channel
MOSFET) is turned on at the beginning of each clock
cycle. Current in the inductor increases until the peak
inductor current reach the value defined by the voltage on
the COMP pin. The error a mplifier a djusts the voltage on
the COMP pin by comparing the feedback signal from a
resistor divider on the FB pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the COMP voltage until the
average inductor current matches the new load current.
When the top power MOSFET shuts off, the synchronous
power switch (N-Cha nnel MOSFET) turns on until either
the bottom current limit is rea ched or the beginning of the
next clock cycle.
The operating frequency is set by an external resistor
connected between the RT pin and ground. The pra ctical
switching frequency can range from 300kHz to 4MHz.
Power Good comparators will pull the PGOOD output low
if the output voltage comes out of regulation by 12.5%. In
an over-voltage condition, the top power MOSFET is turned
off and the bottom power MOSFET is switched on until
either the over-voltage condition clears or the bottom
MOSFET's current limit is re a ched.
Frequency Synchronization
The internal oscillator of the RT801 1 can be synchronized
to an external clock connected to the SYNC pin. The
frequency of the external clock can be in the range of
300kHz to 4MHz. For this a pplication, the oscillator timing
resistor should be chosen to correspond to a frequency
that is about 20% lower than the synchronization
frequency.
Dropout Operation
When the input supply voltage decrea ses toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces
the main switch to remain on for more than one cycle
eventually rea ching 100% duty cycle.
The output voltage will then be determined by the input
voltage minus the voltage drop across the internal
P-Channel MOSFET and the inductor .
Low Supply Operation
The RT8011/A is designed to operate down to an input
supply voltage of 2.6V. One important consideration at
low input supply voltages is that the RDS(ON) of the
P-Channel and N-Channel power switches increa ses. The
user should calculate the power dissipation when the
RT8011/A is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at duty cycles greater than 50%. It is
a ccomplished internally by adding a compensating ra mp
to the inductor current signal. Normally, the maximum
inductor peak current is reduced when slope compensation
is added. In the R T8011/A, however, separated inductor
current signals are used to monitor over current condition.
This keeps the maximum output current relatively constant
regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. A
current runaway detector is used to monitor inductor
current. As current increa sing beyond the control of current
loop, switching cycles will be skipped to prevent current
runaway from occurring.
RT8011/A
6DS8011/A-02 March 2011www.richtek.com
Absolute Maximum Ratings (Note 1)
zSupply Input Voltage, V DD, PV DD ----------------------------------------------------------------------------−0.3V to 6V
zLX Pin Switch Voltage--------------------------------------------------------------------------------------------−0.3V to (PV DD + 0.3V)
zOther I/O Pin Voltages -------------------------------------------------------------------------------------------−0.3V to (VDD + 0.3V)
zLX Pin Switch Current --------------------------------------------------------------------------------------------4A
zPower Dissipation, PD @ TA = 25°C
MSOP-10------------------------------------------------------------------------------------------------------------467mW
WDFN-10L 3x3 -----------------------------------------------------------------------------------------------------909mW
WDFN-8EL 3x3 ----------------------------------------------------------------------------------------------------909mW
zPa ckage Thermal Re sistance (Note 2)
MSOP-10, θJA ------------------------------------------------------------------------------------------------------214°C/W
WDFN-10L 3x3, θJA -----------------------------------------------------------------------------------------------110°C/W
WDFN-8EL 3x3, θJA -----------------------------------------------------------------------------------------------110°C/W
zJunction T emperature---------------------------------------------------------------------------------------------150°C
zLead Temperature (Soldering, 10 sec.)-----------------------------------------------------------------------260°C
zStorage T emperature Range ------------------------------------------------------------------------------------−65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) --------------------------------------------------------------------------------------2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------200V
Electrical Characteristics
(VDD = 3.3V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Voltage Range VDD 2.6 -- 5.5 V
Feedback Voltage VFB 0.784 0.8 0.816 V
Active , VFB = 0.78V, Not Switching -- 460 -- μA
DC Bias Current Shutdown -- -- 1 μA
Output Voltage Line Regulation VIN = 2.7V to 5.5V -- 0.04 -- % /V
Output Voltage Load Regulation 0A < ILOAD < 2A -- 0.25 - - %
Er ror Amp lifie r
Transconductance gm -- 800 -- μs
Current S ense Transresistance RT -- 0.4 -- Ω
Power Good Range -- ±12.5 ±15 %
Power Good Pull-Down
Resistance -- -- 120 Ω
To be continued
Recommended Operating Conditions (Note 4)
zSupply Input Voltage----------------------------------------------------------------------------------------------2.6V to 5.5V
zJunction T emperature Range------------------------------------------------------------------------------------ −40°C to 125°C
zAmbient T emperature Range------------------------------------------------------------------------------------ −40°C to 85°C
RT8011/A
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Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a effective single layer thermal conductivity test board of
JEDEC thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Parameter Symbol Test Conditions Min Typ Max Unit
R
OSC = 332k 0.8 1 1.2 MHz
Swi tching Frequ ency Switching Frequency 0.3 -- 4 MHz
Syn c Freq uency Range 0 .3 -- 4 M Hz
Switch On Resistance , High RPMOS I
SW = 0.5A -- 110 160 mΩ
Switch On Resistance , L ow RNMOS I
SW = 0.5A -- 110 170 mΩ
Pea k Cu rren t Limit ILIM 2.2 3.2 -- A
V
DD Rising -- 2.4 -- V
Under Voltage Lockout
Thr eshold V
DD Falling -- 2.3 -- V
S hutdown Threshold -- VIN − 0.7 VIN − 0.4 V
RT8011/A
8DS8011/A-02 March 2011www.richtek.com
Frequency vs. Temperature
1000
1020
1040
1060
1080
1100
-50 -25 0 25 50 75 100 125
Temperature
Fr equency (kHz)
(°C)
VIN = 3.3V, VOUT = 1.8V
IOUT = 0A
Quiescent Current vs. Input Voltage
450
470
490
510
530
550
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Input Volt age (V )
Qui escent Cur rent (uA)
Quiescent Current vs. Temperature
400
420
440
460
480
500
-50 -25 0 25 50 75 100 125
Temperature
Quiescent C urr ent ( uA)
(°C)
VIN = 3.3V
Peak Current Limited vs. Input Voltage
2.0
2.5
3.0
3.5
4.0
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
In put Voltage ( V)
Peak Current Li m it ed (A)
VOUT = 2.5V
Typical Operating Characteristics
Efficiency vs. Output Current
0
10
20
30
40
50
60
70
80
90
100
0 250 500 750 1000 1250 1500 1750 2000 2250
Output Current (mA)
Efficiency (%)
VIN = 3.3V, VOUT = 1.8V
VIN = 5V, VOUT = 1.8V
Output Voltage vs. Output Current
1.790
1.792
1.794
1.796
1.798
1.800
1.802
1.804
1.806
1.808
1.810
0 250 500 750 1000 1250 1500 1750 2000
Output Current (mA)
Output Voltage (V)
VIN = 3.3V
RT8011/A
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VREF vs. Input Voltage
0.800
0.801
0.802
0.803
0.804
0.805
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
In put Voltage (V )
VREF (V)
Output Voltage vs. Temperature
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
-50-250 255075100125
Temperature
Output Vo ltage (V)
(°C)
VIN = 3.3V
Output Ripple
Time (250ns/Div)
ILX
(2A/Div)
VOUT
(10mV/Div)
VIN = 5V, VOUT = 2.5V
IOUT = 2A
VLX
(5V/Div)
Output Ripple
Time (250ns/Div)
ILX
(2A/Div)
VOUT
(10mV/Div)
VIN = 3.3V, VOUT = 2.5V
IOUT = 2A
VLX
(5V/Div)
Load Transient Response
Time (50μs/Div)
ILX
(1A/Div)
VOUT
(50mV/Div)
VIN = 3.3V, VOUT = 2.5V
IOUT = 1A to 2A
Load Transient Response
Time (50μs/Div)
ILX
(1A/Div)
VOUT
(50mV/Div)
VIN = 3.3V, VOUT = 2.5V
IOUT = 0A to 2A
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10 DS8011/A-02 March 2011www.richtek.com
Soft Start and Inrush Current
Time (2.5ms/Div)
IIN
(2A/Div)
VLX
(5V/Div)
VIN = 5V, VOUT = 2.5V
IOUT = 2A
VOUT
(2V/Div)
VIN
(2V/Div)
Soft Start and Inrush Current
Time (2.5ms/Div)
IIN
(2A/Div)
VLX
(5V/Div)
VIN = 3.3V, VOUT = 2.5V
IOUT = 2A
VOUT
(2V/Div)
VIN
(2V/Div)
Power On & Inductor Current
Time (1ms/Div)
ILX
(2A/Div)
VLX
(5V/Div)
VIN = 5V, VOUT = 2.5V
IOUT = 2A
VOUT
(2V/Div)
VIN
(2V/Div)
Power On & Inductor Current
Time (1ms/Div)
ILX
(2A/Div)
VLX
(5V/Div)
VIN = 3.3V, VOUT = 2.5V
IOUT = 2A
VOUT
(2V/Div)
VIN
(2V/Div)
Power Good
Time (1ms/Div)
ILX
(2A/Div)
VOUT
(2V/Div)
VIN = 3.3V, VOUT = 2.5V
IOUT = 2A
PGOOD
(2V/Div)
VIN
(2V/Div)
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DS8011/A-02 March 2011 www.richtek.com
Application Information
The ba sic RT801 1/A application circuit is shown in Typical
Application Circuit. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by CIN and COUT.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequency improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance and/or ca pacitance to maintain
low output ripple voltage.
The operating frequency of the RT8011/A is determined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing ca pacitor within the oscillator. The RT resistor value
can be determined by examining the frequency vs. RT
curve. Although frequencies as high as 4MHz are possible,
the minimum on-time of the RT801 1/A imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 110ns. Therefore, the minimum duty cycle is
equal to 100 x 110ns x f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increa ses with higher VIN and decreases
with higher inductance.
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. Highest
efficiency operation is achieved at low frequency with small
ripple current. This, however, requires a large inductor . A
reasonable starting point for selecting the ripple current
is ΔI = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen a ccording to the following equation :
⎥
⎦
⎤
⎢
⎣
⎡−
⎥
⎦
⎤
⎢
⎣
⎡
×
=Δ IN
OUTOUT
LV
V
1
Lf
V
I
⎥
⎦
⎤
⎢
⎣
⎡−
⎥
⎦
⎤
⎢
⎣
⎡
Δ×
=IN(MAX)
OUT
L(MAX)
OUT VV
1
If V
L
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High eff iciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or mollypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which mea ns that
inductance collapses abruptly when the peak design
current is exceeded.
This result in an abrupt increa se in inductor ripple current
and consequent output voltage ripple.
Do not allow the core to saturate!
The transition from low current operation begins when the
peak inductor current falls below the minimum peak
current. Lower inductor values result in higher ripple current
which causes this to occur at lower load currents. This
causes a dip in efficiency in the upper range of low current
operation.
Figure 5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 100 200 300 400 500 600 700 800 900 100
0
RRT (k)
Fr equency (MHz)
RRT (kΩ)
1000
RT = 154k for 2MHz
RT = 332k for 1MHz
RT8011/A
12 DS8011/A-02 March 2011www.richtek.com
Figure 6. Setting the Output Voltage
⎟
⎠
⎞
⎜
⎝
⎛+×= R2
R1
1VV REFOUT
RT8011/A
VFB
GND
VOUT
R1
R2
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller ca se sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However , care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
a nd the power is supplied by a wall ada pter through long
wires, a load ste p at the output ca n induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to da mage the
part.
Output Voltage Programming
The output voltage is set by a n extern al resistive divider
a ccording to the following equation :
where VREF equals to 0.8V typical.
The resistive divider allows the FB pin to sense a fra ction
of the output voltage a s shown in Figure 6.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the top MOSFET. To
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used. RMS
current is given by :
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple current
ratings from ca p a citor ma nufa cturers are often ba sed on
only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required.
Several ca pacitors may also be paralleled to meet size or
height requirements in the design.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response a s described in a later section.
The output ripple, ΔVOUT, is determined by :
The output ripple is highest at maximum input voltage
since ΔIL increa ses with input voltage. Multiple ca pacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surfa ce mount packages. Special polymer
ca pacitors offer very low ESR but have lower ca pacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
1
VV
V
V
II OUT
IN
IN
OUT
OUT(MAX)RMS −=
⎥
⎦
⎤
⎢
⎣
⎡+Δ≤Δ OUT
LOUT 8fC1
ESRIV
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
a pplications provided that consideration is given to ripple
current ratings and long term reliability . Cera mic capacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
ca n also lea d to significa nt ringing.
Different core materi als and sha pes will cha nge the size/
current and price/current relationship of an inductor. T oroid
or shielded pot cores in ferrite or permalloy materials are
small and don't radiate energy but generally cost more
than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs. size requirements and
any radiated field/EMI requirements.
RT8011/A
13
DS8011/A-02 March 2011 www.richtek.com
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Ef ficiency ca n be expressed as :
Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc.
are the individual losses a s a percentage of in put power .
Although all dissipative elements in the circuit produce
losses, two main sources usually a ccount for most of the
losses: VDD quiescent current and I2R losses.
The VDD quiescent current loss dominates the eff iciency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve
at very low load currents can be misleading since the
a ctual power lost is of no consequence.
1. The VDD quiescent current is due to two components :
the DC bia s current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge ΔQ moves
from VDD to ground. The resulting ΔQ/Δt is the current out
of VDD that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f(QT+QB) where QT and QB
are the gate charges of the internal top and bottom
switches.
Both the DC bia s and gate charge losses are proportional
to VDD and thus the ir ef fects will be more pronounced at
higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main switch
a nd the synchronous switch. Thus, the series resista nce
looking into the LX pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (D) as follows :
RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1"D) The RDS(ON)
for both the top and bottom MOSFETs can be obtained
from the Typical Performance Characteristics curves. Thus,
to obtain I2R losses, simply a dd RSW to RL a nd multi ply
the result by the square of the average output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the RT8011/A does not dissipate
much heat due to its high efficiency. But, in applications
where the RT8011/A is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off a nd the SW node will become
high impeda nce. To avoid the RT8011/A from exceeding
the maximum junction temperature, the user will need to
do some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds
the maximum junction temperature of the part. The
temperature rise is given by : TR = PD x θJA Where PD is
the power dissipated by the regulator and θJA is the thermal
resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by :
TJ = TA + TR Where TA is the ambient temperature.
As an example, consider the RT8011/A in dropout at an
input voltage of 3.3V, a load current of 2A and an a mbient
temperature of 70°C. From the typical performance graph
of switch resistance, the RDS(ON) of the P-Channel switch
at 70°C is approximately 121mΩ. Therefore, power
dissipated by the part is :
PD = (ILOAD)2 (RDS(ON)) = (2A)2 (121mΩ) = 0.484W
For the DFN3x3 package, the θJA is 110°C/W. Thus the
junction temperature of the regulator is : TJ = 70°C +
(0.484W) (110°C/W) = 123.24°C Which is below the
maximum junction temperature of 125°C. Note that at
higher supply voltages, the junction temperature is lower
due to reduced switch resista nce (RDS(ON)).
Checking Tra n sient Re spon se
The regulator loop response can be checked by looking
at the load tra nsient response. Switching regulators ta ke
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by a n amount
equal to ΔILOAD(ESR), where ESR is the effective series
RT8011/A
14 DS8011/A-02 March 2011www.richtek.com
Figure 7. RT801 1 Demo Board
Figure 8. RT801 1A Demo Board (Only W DF N-8EL 3x3)
resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error sign al used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
The COMP pin external components and output capacitor
shown in T ypical Application Circuit will provide adequate
compensation f or most applications.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT801 1/A.
`A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
`Connect the terminal of the input capacitor(s), CIN, as
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.
`LX node is with high frequency voltage swing and should
be kept small area. Keep all sensitive small-signal nodes
away from LX node to prevent stray capacitive noise
pick-up.
`Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of powercomponents.
Y ou can connect the copper area s to any DC net (PVDD,
VDD, VOUT, PGND, GND, or a ny other DC rail in your
system).
`Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and GND.
RT8011/A
15
DS8011/A-02 March 2011 www.richtek.com
Outline Dimension
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.200 2.700 0.087 0.106
E 2.950 3.050 0.116 0.120
E2 1.450 1.750 0.057 0.069
e 0.500 0.020
L 0.350 0.450
0.014 0.018
W-Type 8EL DFN 3x3 Package (0.5mm Lead Pitch)
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID a nd T ie Bar M ark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A
RT8011/A
16 DS8011/A-02 March 2011www.richtek.com
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450
0.014 0.018
W-Type 10L DFN 3x3 Package
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID a nd T ie Bar M ark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A
RT8011/A
17
DS8011/A-02 March 2011 www.richtek.com
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
L
A2
A
b
A1
D
E1
E
e
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.810 1.100 0.032 0.043
A1 0.000 0.150 0.000 0.006
A2 0.750 0.950 0.030 0.037
b 0.170 0.270 0.007 0.011
D 2.900 3.100 0.114 0.122
e 0.500 0.020
E 4.800 5.000 0.189 0.197
E1 2.900 3.100 0.114 0.122
L 0.400 0.800
0.016 0.031
10-Lead MSOP Plastic Package
