This is information on a product in full production.
November 2015 DocID025718 Rev 4 1/39
ALED1642GW
16 channel LED driver with error detection, current gain control and
12/16-bit PWM brightness control for automotive applications
Datasheet
-
production data
Features
•AECQ100 qualification
•16 constant current output channels
•Output current: from 3 mA to 40 mA
•Current programmable through external
resistor
•7-bit global current gain adjustment in two
ranges
•12/16-bit PWM grayscale brightness control
•Programmable output turn-on/of f time
•Error detection mode (both open and shorted-
LED)
•Programmable shorted-LED detection
thresholds
•Auto power saving/auto-wakeup
•Selectable SDO synchronization on the CLK
falling edge
•Gradual output delay (selectable)
•Supply voltage: 3 V to 5.5 V
•Thermal shutdown and overtemperature alert
•Up to 30 MHz 4-wires interface
•20 V current generator rated voltage
Applications
•Full color/monochrome displays
•Dashboard (backlighting led indicators)
•Automotive Interior lighting
Description
The ALED1642GW is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The ALED1642GW
guarantees 20 V output driving capability allowing
the user to connect several LEDs in series. In the
output stage, sixteen regulated current sources
provide from 3 mA to 40 mA constant current to
drive the LEDs. The current is programmed
through an external resistor and can be adjusted
by a 7-bit current gain register in two subranges.
The brightness can be adjusted separately for
each channel through 12/16-bit grayscale control.
Programmable turn-on and turn-off time (four
different values available) improves the low noise
generation performance of the system.
Open/short error detection mode is available in
the ALED1642GW. The auto power-shutdown
and auto power-on features (selectable) allow the
device to save power without external
intervention.
Thermal management includes an
overtemperature data alert and output thermal
shutdown (170 °C). The high clock frequency is
up t o 30 M Hz a n d it m ak es t h e devi ce su i t ab l e f or
high data rate transmission. A selectable gradual
output delay reduces the inrush current, whereas
the selectable SDO synchronization feature works
when the device is used in daisy-chain
configuration. The supply voltage range is
between 3 V and 5.5 V.
TSSOP24
(exposed pad)
www.st.com
Contents ALED1642GW
2/39 DocID025718 Rev 4
Contents
1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2
6 Simplified internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6.1 Equivalent circuits of inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8.1 Gain control (from CFG 0 to 5) and current ranges (CFG- 6) . . . . . . . . . . 20
8.2 Error detection mode (CFG-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.3 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.4 Auto-wakeup/auto power shutdown (CFG-10) . . . . . . . . . . . . . . . . . . . . . 25
8.5 Programmable turn-on/turn-off time (CFG-11/12) . . . . . . . . . . . . . . . . . . . 25
8.6 SDO delay (CFG-13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.7 Gradual output delay (CFG-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.8 PWM counter setting and brightness register (CFG-15) . . . . . . . . . . . . . . 28
9 Thermal flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
10 Dropout voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
DocID025718 Rev 4 3/39
ALED1642GW Contents
39
11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.1 TSSOP24 exposed pad package information . . . . . . . . . . . . . . . . . . . . . 33
11.2 TSSOP24 exposed pad packing information . . . . . . . . . . . . . . . . . . . . . . 35
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
List of tables ALED1642GW
4/39 DocID025718 Rev 4
List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Programmable TON/TOFF (output rise and fall time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Digital key summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Example of current ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Gain steps for the current range selected by REXT = 11 kW. . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Diagnostic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Minimum dropout voltage for some current values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. TSSOP24 exposed pad mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. TSSOP24 exposed pad tape and reel mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DocID025718 Rev 4 5/39
ALED1642GW List of figures
39
List of figures
Figure 1. TSSOP24EP pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Typical chip-to-chip accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Typical application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Timing for clock, serial in, serial out, latch enable and outputs. . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. ALED1642GW simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Input and output equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Digital keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Channel data and write switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Channel current vs. gain register value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Error detection action sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Error detection power-on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Configuration register reading sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Configuration register reading sequence (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Configuration register reading sequence - SDO delay actives. . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Configuration register reading sequence - SDO delay actives (zoom). . . . . . . . . . . . . . . . 24
Figure 16. Output TON (current rise time) CFG - 12 = CFG - 11 = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17. Output TOFF (current fall time) CFG -12 = CFG - 11 = 0. . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. Output TON (current rise time) CFG -12 = CFG - 11 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 19. Output TOFF (current fall time) CFG -12 = CFG - 11 = 1. . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20. SDO delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. Gradual output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. PWCLK counter and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23. Brightness register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 24. Thermal flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 25. Typical channel dropout voltage vs. output current (VDD = 3.3 V). . . . . . . . . . . . . . . . . . . 31
Figure 26. TSSOP24 exposed pad outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 27. TSSOP24 exposed pad tape and reel outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin de s crip t io n ALED1642GW
6/39 DocID025718 Rev 4
1 Pin description
Figure 1. TSSOP2 4EP pinout
Table 1. Pin description
TSSOP24EP Symbol Name and function
1 GND Ground terminal
2 SDI Serial data input terminal
3 CLK Clock input terminal
4 LE Latch input terminal
5-20 OUT0-OUT15 Output terminals
21 PWCLK Clock input for PWM counter
22 SDO Serial data output terminal
23 R-EXT Terminal for external resistor for constant current
programming
24 VDD Supply voltage terminal
GND
SDI
CLK
LE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7 OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
PWCLK
SDO
R-EXT
VDD
AM13686v1
DocID025718 Rev 4 7/39
ALED1642GW Absolute maximum ratings
39
2 Absolute maximum ratings
S tressing the device above the ratings listed in the Table 2 may cause the device permanent
damage. Operating under conditions above those indicated in the operating section is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
the device reliability.
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
DD
Supply voltage 0 to 7 V
V
OUT
Output voltage -0.5 to 20 V
I
OUT
Output current 50 mA
V
i
Input voltage -0.4 to V
DD
+0.4 V
I
GND
GND terminal current 1400 mA
ESD Electrostatic discharge protection
HBM human body model ±2 kV
Thermal characteristics ALED1642GW
8/39 DocID025718 Rev 4
3 Thermal characteristics
4 Electrical characteristics
V
DD
= 3.3 V, T
j
= - 40 to 125 °C, unless otherwise specified.
Table 3. Thermal characteristics
Symbol Parameter Value Unit
T
a
Operative free-air temperature range
(1)
-40 to +150
°CT
OPR
Operative junction temperature range -40 to +150
T
STG
Storage ambient temperature range -55 to +150
R
thj-amb
Thermal resistance junction-ambient TSSOP24EP
(2)
37.5 °C/W
1. This data must be considered in adequate power dissipation conditions, the junction temperature mus t be maintained
below 150 °C.
2. The exposed pad should be soldered directly to the PCB to get the thermal benefits. The exposed pad can be attached to
a metal land electrically isolated or connected to ground.
Table 4. Electrical characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
V
DD
Supply vol tage 3 5.5
V
V
OUT
Output voltage Out 0 - out 15 - - 19
V
IH
Input voltage 0.7xV
DD
-V
DD
V
IL
GND - 0.3xV
DD
V
OL
Serial data output voltage
(SDO) V
DD
= 3 to 5.5 V
I = +/- 1 mA --0.4
V
OH
V
DD
-0.4 - -
I
Oleak
Output lea kage curre nt V
OUT
= 19 V, all outputs OFF - - 0.5 µA
V
uvlo
UVLO threshold ( risi ng) 2.7 2.9 V
UVLO threshold (falling) 2.2 2.3
Hy
uvlo
UVLO hysteresis 400 mV
DocID025718 Rev 4 9/39
ALED1642 G W Electri cal chara ct er ist ics
39
I
OL1
Output current precision
channel-to-channel
(all outputs ON)
(1)(2)
V
OUT
= 0.1 V; (I
OUT
= 3 mA)
R
EXT
= 11 k
CFG-0…CFG-5= “000000”
CFG-6 = “0”
--±4
%I
OL2
V
OUT
= 0.5 V; (I
OUT
= 20 mA)
R
EXT
= 11 k
CFG-0…CFG-5 = “011010”
CFG-6 = “1”
--±3
I
OL3
V
OUT
= 0.8 V; (I
OUT
= 36 mA)
R
EXT
= 11 k
CFG-0…CFG-5 = “111111”
CFG-6 = “1”
--±3
I
OL2a
Output current precision
device-to-device
(all outputs ON)
(1)
V
OUT
= 0.5 V; (I
OUT
= 20 mA)
R
EXT
=1 1 k
CFG-0…CFG-5 = “011010”
CFG-6 = “1”
--±6%
%/dV
OUT
Output current vs. output
voltage re gulation
(3)
V
OUT
from 1 V to 3 V; (I
OUT
=
36 mA) R
EXT
= 11 k
CFG-0…CFG-5 = “111111”
CFG-6 = “1”
-±0.1-
%/V
%/dV
DD
Output current vs. supply
volt a ge regu la tion
(4)
V
DD
from 3 V to 5.5 V
V
OUT
= 0.8 V; (I
OUT
= 36 mA)
R
EXT
= 11 k
CFG-0…CFG-5 = “111111”
CFG-6 = “1”
-±1-
Rup Pull-up resi stor for PWC LK pin 400 500 650 K
Rdw Pull-down resistor for LE pin 400 500 650
I
DD
(OFF1) Supply current (OFF) R
EXT
= 11 k
OUT 0 to 15 = OFF
CFG = default --6
mA
I
DD
(ON1)
Supply current (ON)
R
EXT
= 11 k; I
OUT
= 20 mA
OUT 0 to 15 = ON
CFG-0…CFG-5 = “011010”
CFG-6 = “1”
-8
I
DD
(ON2)
R
EXT
= 11 k; I
OUT
= 36 mA
OUT 0 to 15 = ON
CFG-0…CFG-5 = “111111”
CFG-6 = “1”
-10
I
DD
(auto
OFF) Supply current (auto OFF)
R
EXT
= 11 k;
OUT 0 to 15 = OFF
CFG-0…CFG-5 = “111111”
CFG-6 = “1”
-200500µA
Table 4. Electrical characteristics (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
Electrical characteristics ALED1642GW
10/39 DocID025718 Rev 4
Figure 2. Typical chip-to-chip accuracy
T
flg
Thermal flag 150
°C
T
sd
Thermal shutdown
(5)
170
T
sd-hy
Thermal shutdown
hysteresis
(5)
15 20
1. Tested with just one output loaded.
2. (Ioutn - Ioutavg1-15)/ Ioutavg1-15) x 100.
3.
4.
5. Not tested, guaranteed by design.
Table 4. Electrical characteristics (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
13
100
)V0.1Voutn@Ioutn()V0.1Voutn@Ioutn()V0.3Voutn@Ioutn(
)V/(% −
×
=
=−=
=Δ
35.5100
)V0.3Vdd@Ioutn()V0.3Vdd@Ioutn()V5.5Vdd@Ioutn(
)V/(% −
×
=
=−=
=Δ
AM13688V1
0
0.5
1
1.5
2
2.5
3
3.5
4
0 5 10 15 20 25 30 35 40
Chip-to-chip (%)
I
OUT
(mA)
V
DD
=3.3/5 V; T=25 ° C
DocID025718 Rev 4 11/39
ALED1642 G W Electri cal chara ct er ist ics
39
Figure 3. Typical application schematic
AM13689V1
ALED1642GW
Supply voltage
SDI
CLK
LE
PWCLK
VDD OUT0 OUT1 OUT15
R-EXT
Current setting
resistor
Data loaded
through serial
interface
LED common rail voltage
…..
SDO Data output
+
Cin
Cled
GND
Switching characteristics ALED1642GW
12/39 DocID025718 Rev 4
5 Switching characteristics
V
DD
= 3.3 V, T
j
= 25 °C, unless otherwise specified.
Table 5. Switching characteristics
(1)(2)
Symbol Parameter Conditions Min. Typ. Max. Unit
f
clk
Clock frequency Cascade operation - - 30 MHz
f
pwclk
PWclock frequency - - 30
tr
(SDO)
SDO rise time R
EXT
= 11 k; I
OUT
= 20 mA
V
OUT
= 0.8 V
VIH = V
DD
; VIL = GND
RL = 3.3 K; CL = 10 pF
CFG-0…CFG-5 = “011010”
CFG-6 = “1”
-5-
ns
tf
(SDO)
SDO fall time - 5 -
tPLHLE LE - OUTn
(3)
Propagation delay
time
(“L to “H”)
R
EXT
= 11 k; I
OUT
= 20 mA
V
OUT
= 0.8 V
VIH = V
DD
; VIL = GND
RL = 50 ; CL = 10 pF
CFG-0…CFG-5 = “011010”
CFG-6 = “1”
-200-
tPLH CLK - SDO
CFG-13 = ‘0’ 81525
tPHLLE LE - OUTn
(3)
Propagation delay
time
(“H” to “L”)
-100-
tPHL CLK - SDO
CFG-13 = ‘0’ 81525
tw(CLK) CLK
Pulse wi dth
20 - -
t
W
(PWCLK) PWCLK 20 - -
tw(L) LE 20 - -
t
gr-d
Gradual delay ch-to-ch 10
t
su(L)
Setup time for LE 5 - -
t
h(L)
Hold time for LE 5 - -
t
su(D)
Setup time for SDI 5 - -
t
h(D)
Hold time for SDI 10 - -
tclkr
(4)
Maximu m CLK rise t ime - - 5 µs
tclkf
(4)
Maximum CLK fall time - - 5
I
out-ov
Output current turn-on overshoot V
OUT
= 0.6 to 3 V
CL = 10 pF; I
OUT
= 3 to 36 mA --10%
t
n-err
Normal error detection
minimum output ON time --1µs
DocID025718 Rev 4 13/39
ALED1642 G W S witc hin g chara cter ist ics
39
t
shutdown
Auto power shutdown time (auto OFF) From LE falling edge to R
EXT
voltage reference at -10% -100- ns
t
wakeup
Auto-wakeup From LE falling edge to R
EXT
voltage reference at 90% -3 -µs
1. All table limits are guaranteed by design.
2. Not tested in production.
3. CFG -11= 0 and CFG -12 = 0 (output tr = 30 ns; output tf = 20 ns); CFG-14=1 (no output gradual delay).
4. If devices are connected in cascade and tclkr or tclkf is large, it may be critical to achieve the timing required for data
transfer between two cascaded devices.
Table 5. Switching characteristics
(1)(2)
Symbol Parameter Conditions Min. Typ. Max. Unit
Table 6. Programmable T
ON
/T
OFF
(output rise and fall time)
Configuration bits
(CFG-12 - CFG-11) Conditions Typ. (20% to 80%) Unit
Turn-on Turn-off
0 - 0R
EXT
= 11 k; I
OUT
= 20 mA
V
OUT
= 0.8 V
VIH= V
DD
; VIL= GND
RL = 50 ; CL=10pF
CFG-0...CFG-5=“011010”
CFG-6 = “1”
30 ns 20 ns
ns
0 - 1 100 ns 40 ns
1 - 0 140 ns 80 ns
1 - 1 180 ns 150 ns
Switching characteristics ALED1642GW
14/39 DocID025718 Rev 4
Figure 4. Timing for clock, serial in, serial out, latch enable and outputs
The correct sampling of the data depends on the stability of the data at SDI on the rising
edge of the clock signal and it is assured by a proper data setup and hold time (t
SU(D)
and
t
h(D)
), as shown in Figure 4. The same figure shows the propagation delay from CLK to SDO
(t
PLH
/t
PHL
). Figure 4 describes also the minimum duration of CLK, LE pulses (t
W(CLK)
) and
t
W(L)
respectively and the propagation delay from LE to OUT
n
(t
PLHLE
and t
PHLLE
) in the
hypothe si s that all chan nel s hav e alread y been enabl ed by PW M counter.
DocID025718 Rev 4 15/39
ALED1642GW Simplified internal block diagram
39
6 Simplified internal block diagram
Figure 5. ALED1642GW simplified block diagram
6.1 Equivalent circuits of inputs and outputs
LE and PWCLK input terminals have pull-down and pull-up connection respectively. CLK
and SDI must be connected to the external circuit to fix the logic level.
AM13691V1
UVLO
& POR
Configuration
register
Channel driver
Timing control
Turn ON/OFF
Gradual delay
…………
Current gain
adjustment
SDI
CLK
LE
V
DD
GND
R-EXT
SDO
OUT0
OUT1
OUT2
OUT14
OUT15
16 output channels
PWM
counter
PWCLK
Thermal
shutdown
Current
Ref.
Control Logic &
Data Registers
Error
detection
Simplified internal block diagram ALED1642GW
16/39 DocID025718 Rev 4
Figure 6. Input and output equivalent circuits
AM13692V1
PWCLK terminal LE terminal
CLK, SDI terminal SDO terminal
DocID025718 Rev 4 17/39
ALED1642GW Digital blocks
39
7 Digital blocks
The data input arrives through the serial Interface at each CLK rising edge. The LE signal is
used to latch the loaded data and also to address data loading to the appropriate register,
thermal flag reading and error detection. The access to the different registers or functions of
the device (configuration register , brightness register or current gain, error detection, etc.) is
achieved by using different digital keys, defined as a number of CLK pulses during which the
LE signal i s asserted. The available digital keys are listed in Table 7 and Figure 7. A typical
channel data input is shown in Figure 8.
Table 7. Digital key summary
Number # CLK rising edge when the LE is “1” Command description
1 1 – 2 Write switch (to turn on/off output channels)
2 3 – 4 Brightness data latch
3 5 – 6 Bri ghtness gl obal latc h
4 7 Wr ite co nfig ura tion register
5 8 Read configuration register
6 9 Start open error detection mode
7 10 Start short error detection mode
8 11 Start combined error detection mode
9 12 End error detection mode
10 13 Thermal error reading
11 14 Reserved
12 15 Reserved
Digital blocks ALED1642GW
18/39 DocID025718 Rev 4
Figure 7. Digital keys
Figure 8. Channel data and write switch
AM13693V1
CLK
LE
LE
LE
LE
LE
LE
LE
LE
LE
Write switch
Data latch
Global latch
Write CR
Read CR
Start open error detection
Start short error detection
Start combined detection
End error detection
LE Thermal error reading
AM13694V1
0E
0F 0C 0A0B0D 09 08 07 06 05 04 03 02 01 00
CLK
SDI
LE
16-bit data
DocID025718 Rev 4 19/39
ALED1642GW Configuration register
39
8 Configuration register
The configuration register is used to enable or disable some device features, to program
some parameters and to change other settings. The access to this register (read or write) is
managed to find a description for each bit as described in Table 8. The default value of the
configuration register (when the device is switched on or after a reset) is "0" for all bits. To
change anything in the configuration register, a 16-bit digital word must be sent (CFG - 0
represents LSB, CFG -15 the MSB).
Table 8. Configuration register
Bit Definition R/W Description Default
CFG-0
Current gain
adjustment R/W 6-bit DAC allows adjusting the device output current in 64
steps for each range (defined by CFG-6)
0
CFG-1 0
CFG-2 0
CFG-3 0
CFG-4 0
CFG-5 0
CFG-6 Current range R/W ”0” low current range
“1” high current range 0
CFG-7 Error detection
mode R/W “0” normal mode
“1” reserved mode 0
CFG-8 Shorted-LED
detection
thresholds
R/W Programmable outp ut
sh orte d-LED detection
thresholds
CFG-9 CFG-8 Th. volt.
000 1.8 V
01 2.5 V
CFG-9 R/W 10 3 V 0
11 3.5 V
CFG-10 Auto OFF
shutdown R/W “0” device always ON
”1” aut o power shutdow n active (auto OFF) 0
CFG-11 Output turn-
on/off time
R/W Programmable
output rise and fall
time (20% to 80%)
CFG-12 CFG-11 Turn-on Turn-off
00 0 30 ns 20 ns
0 1 100 ns 40 ns
CFG-12 R/W 1 0 140 ns 80 ns 0
1 1 180 ns 150 ns
CFG-13 SDO delay R/W If “0” no delay is present on SDO
If “1” the data are shifted out and they are synchronized with
the falling edge of the CLK signal 0
Configuration register ALED1642GW
20/39 DocID025718 Rev 4
8.1 Gain control (from CFG 0 to 5) and current ranges (CFG- 6)
The LED current can be programmed using an external resistor connected to GND from
R
EXT
pin and can be fixed using the dedicated bits of the configuration register (from CFG -
0 to CFG - 5 bits define the gain, while CFG - 6 bit defines the current range within the which
the gain can be adjusted). The device can regulate the current up to 36 mA and down to 0.5
mA. The accuracy of the LED current depends on the selected range and it is guaranteed in
the ranges indicated in the static electrical characteristics only (see Table 3 and 9). Wh en
the device is switched on, the selected current range and the resistor connected to the R
EXT
pin fix the default LED current:
Wher e V
REF
=1.23 V is the voltage of the R
EXT
pin and K is the mirroring current ratio, whose
value depends on the selected current range:
•K = 28 with low current range selected (CFG - 6 = "0")
•K = 80 with high current range selected (CFG - 6 = "1")
The relation between the programmed current and the current gain settings is the following:
where G is the current gain value (decimal value) defined by the dedicated bits of the
current gain register. The current gain is managed by 6-bits of the configuration register
(CFG - 0 to CFG - 5, CFG - 0 is LSB and CFG - 5 is MSB) and can be adjusted within two
ranges (selectable through the bit CFG - 6) over 64 steps. The width of each step depends
on the default current (I
ol_default
) as well as the selected R
EXT
. Finally, each step is as
follows:
CFG-14 Gradual output
delay R/W “0” a progressive delay is applied to output (10 ns per
channel)
”1” no delay is applied to output 0
CFG-15 12/16 PWM
counter R/W
“0” to select 16-bit brightness register (65536 grayscale
rightness steps).
“1” to select 12-bit brightness register (4096 grayscale
brightness steps)
0
Table 8. Configuration register (continued)
Bit Definition R/W Description Default
K
R
V
I
EXT
REF
defaultOL
⋅=
_
)(
_stepdefaultOLOL
IGII Δ⋅+=
DocID025718 Rev 4 21/39
ALED1642GW Configuration register
39
The Table 9 shows an example of the current setting with an external resistance (R
EXT
) = 11
K:
The Table 10 shows an example of current setting and gain control with R
EXT
= 11 k, see
also Figure 9.
The external programming resistance must be connected as close as possible to the related
device pins (R
EXT
and GND) to reduce as minimum as possible the routing length and
prevent reference noise injection and electromagnetic interferences. Moreover, a direct
connection to the device GND pin reduces the possible output current variation when the
total device ground current changes (load effect).
Table 9. Example of current ranges
R
EXT
[K] CFG-6 CFG-0 to CFG-5 LED current
(1)
[mA]
1. The indicated values may be slightly different on the current device.
Accuracy
Low range 11 0 000000 3.1 mA ± 4% ch-to-ch
11 0 111111 12.5 mA -
High range 11 1 000000 8.9 mA
11 1 011010 20 mA ± 3% ch-to-ch
Table 10. Gain steps for the curr ent range selected by R
EXT
= 11 kΩ
CFG-6 CFG(0 to 5) LED current
(1)
[mA]
1. The indicated values may be slightly different on the current device.
Low range
0 000000 3.131
0 000001 3.280
………
0 111111 12.524
High range
1 000000 8.945
1 000001 9.371
………
1 111111 35.782
Configuration register ALED1642GW
22/39 DocID025718 Rev 4
Figure 9. Channel current vs. gain register value
8.2 Error detection mode (CFG-7)
S topping the normal activity of the display and turning on all driver channels allows the error
detection to be performed and failed LED or display defects to be checked.
The error detection is active when the CFG -7 bit of the configuration register is "0". The
diagnostics is performed as shown in Figure 10:
•The LED has to be selected turning on the relative channel on the switch register
(powering on or off the output channels); the brightness register value for this channel
cannot be zero.
•The normal error detection has to be selected in the configuration register (CFG-7=
"0"). The appropriate digital key to choose the type of detection (open, short or
combined) must be sent (see Table 7).
•After the error detection starts, the channel under testing has to be turned on at least 1
µs
(the LED is at the nominal current). Please note that, the output power-on depends
on PWCLK signal and in several applications this signal is not synchronized with the
serial interface clock (CLK pin). Therefore, to be sure that, between the detection start
and the detection end, the output power-on is 1 µs and moreover , that last power-on, in
the interval, starts at least 0.5 µs before the detection end pattern (see Figure 11), it is
suggested that the error detection should be performed just after the device startup
(brightness counter reset) with all channels ON, before applying PWCLK signal..
•The result of the detection ("0" indicates a fault condition) is shifted out from SDO in 16
clock pulses after the "detection end command" is provided, first output bit represents
channel 15 (error data can be read in a way similar to configuration register data
reading as shown on Figure 12, 13, 14 and 15).
AM13695V1
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
11 K R=0
11 K R=1
18 K R=0
IOUTOUT vs. gain
(R = range selection, REXT = 11 K or 18 K)
Gain register decimal value
I
OUTOUT
(mA) (mA)
18 K R=1
DocID025718 Rev 4 23/39
ALED1642GW Configuration register
39
Figure 10. Error detection action sequence
Figure 11. Error detection power-on timing
AM13696V1
Normal detection sequence
Read error detection result on
SDO in 16 clock pulses after
detection end command
Turn on LED by PWCLK
pulses for at least 1 µ s
Send open, short or combined
error detection start command
by LE digital keys
Select LED to be turned on and
checked in switch register
data; brightness for selected
channels cannot be zero.
Select normal error detection mode
on CFG register (bit 7 = “0”)
Send error detection end
command by LE digital key
AM13697V1
0.5us Det.
End
Det.
Start
It must contain 1us output power ON
1us
SPI pattern
Output Current
x0000 < BRT < xFFFF
Configuration register ALED1642GW
24/39 DocID025718 Rev 4
Figure 12. Configuration register reading
sequence Figure 13. Configuration register reading
sequence (zoom)
CFG Reg programming CFG Reg reading command CFG Reg data
C1=CLK
C2=SDI
C3=LE
C4=SDO
First CLK pulse
after CFG Reg
reading command
CFG Reg data
C1=CLK
C2=SDI
C3=LE
C4=SDO
First CLK pulse
after CFG Reg
reading command
Figure 14. Configuration register reading
sequen ce - SDO delay act ives Figure 15. Configuration register reading
sequence - SDO delay actives (zoom)
CFG Reg programming CFG Reg reading command CFG Reg data
C1=CLK
C2=SDI
C3=LE
C4=SDO
First CLK pulse
after CFG Reg
reading command
Sync. change
CFG13=1
C1=CLK
C2=SDI
C3=LE
C4=SDO
CFG Reg data
First CLK pulse
after CFG Reg
reading command
DocID025718 Rev 4 25/39
ALED1642GW Configuration register
39
8.3 Error detection conditions
During the error detection phases for each channel, the following checks have to be
performed:
– The output current in open detection mode (digital key: 9 CLK rising edges when
LE is "1")
– The output voltage in short detection (digital key: 10 CLK rising edges when LE is
"1")
– Both parameters (output voltage and current) in combined error detection mode
(digital key: 11 CLK rising edges when LE is "1").
The thresholds for the error diagnostics are listed in Table 11:
8.4 Auto-wakeup/auto power shutdown (CFG-10)
This feature reduces the power consumption when all outputs are OFF. It is active when the
CFG -10 bit of configuration register is "1". The auto power shutdown (auto OFF) starts
when the data latched is "0" for all channels, and device is active again (wakeup) at the first
latched data string including at least one bit = "1" (at least one channel ON). Timings for
shutdown and wakeup are present in the dynamics feature table. While the auto power
shutdown is active, the device ignores any other command except the channel power-on.
8.5 Programmable turn-on/turn-off time (CFG-11/12)
The device gives the possibility to program the turn-on and turn-off time of the current
generators. Four different values can be selected using CFG -12 and CFG-11 bits of the
configuration register (see Table 8) to fit the application requirements: 30/20 ns (00), 100/40
ns (01), 140/80 ns (10) and 180/150 ns (11). The selected value refers to T
ON
(current rise
time) and T
OFF
(current fall time).
Table 11. Diagnostic thresholds
Error detection
modes Checked
malfunction CFG-9 CFG-8 Thresholds (V)
Min. Typ. Max.
Open
detection
Combined mode
Open line or output
short to GND xx-
I
OUT
≤ 0.5 x I
OUT
programmed -
Short
detection Short on LED or short
to V-LED
001.15V
OUT
≥ 1.8 2.05
012.25V
OUT
≥ 2.5 2.75
102.75V
OUT
≥ 3.0 3.25
113.25V
OUT
≥ 3.5 3.80
Configuration register ALED1642GW
26/39 DocID025718 Rev 4
Figure 16. Output T
ON
(current r is e ti me) CFG -
12 = CFG - 11 = 0 Figure 17. Output T
OFF
(current fall time) CFG -
12 = CFG - 11 = 0
AM13698V1
AM13699V1
Figure 18. Output T
ON
(current rise time) CFG -
12 = CFG - 11 = 1 Figure 19. Output T
OFF
(current fall time) CFG -
12 = CFG - 11 = 1
AM13700V1
AM13701V1
DocID025718 Rev 4 27/39
ALED1642GW Configuration register
39
8.6 SDO delay (CFG-13)
Usually in SDO terminal, data are shifted out the rising edge of CLK signal (with a
propagation delay of about 15 ns - signal (a) in Figure 20). The device has the possibility to
shift data out the falling edge of the CLK signal (with few ns of propagation delay - signal (b)
in Figure 20). This feature is active when CFG -13 bit of the configuration register is "1".
Default setting for this bit is "0" hence the SDO delay is not activated by default. This feature
is particularly useful when some devices are connected in daisy chain configuration with
mismatched propagation delays, between CLK and SDO data path (board routing).
Figure 20. SDO delay
8.7 Gradual output delay (CFG-14)
The gradual output delay consists of turning on gradually the current generators avoiding to
turn on all channels at the same time.
When PWM counter enables the device channels, the outputs can be turned on
simultaneously or with a progressive delay. Thanks to configuration register CFG -14 bit, the
user can decide to put a delay among outputs (10 ns from each channel to the next one,
around 150 ns between first and last channel). The typical output timing is shown in
Figure 21. This feature prevents the inrush current and reduces the bypass capacitor value.
AM13702V1
(a)
(b)
(a) Data shifted out of the SDO with the device propagation delay
(b) Data shifted out of the SDO by the falling edge of the CLK
Configuration register ALED1642GW
28/39 DocID025718 Rev 4
Figure 21. Gradual output delay
8.8 PWM counter setting and brightness register (CFG-15)
The brightness of each channel can be adjusted through a 12/16-bit PWM grayscale
brightness control according to the PWM counter selection (configuration register CFG -15
bit). Brightness data is loaded by the SDI pin in a 16-bit shift register. Once 16-bit has been
loaded (first input bit of brightness word is MSB, 16
th
bit is LSB), the digital word is moved to
the corresponding temporary buffer (first word is the brightness of channel 15, the last one
is for channel 0) using the appropriate key shown in Table 7 ("data latch"). One "data latch"
key must follow each 16-bit brightness word except the last one. When the last brightness
word is loaded (channel 0 brightness data), the key indicated as "global latch" in Table 7
must be used. This action moves the word from the shift register to the temporary buffer
through the OUT0 and, at the same time, transfers all data of the 16 temporary buffers (16
x16-bit string) to the corresponding brightness registers (see also Figure 23).
The PWM signals are generated by comparing the content of the brightness registers to a
16-bit or 12-bit counter, according to the CFG-15 bit status. The counter's clock source is
provided to the PWCLK pin. In case of selection of 12-bit PWM counter, the four most
significant bits of each brightness data word are ignored. However, each of sixteen
brightness data words must be 16-bit long.The brightness register default value is "0",
unless this value is changed, the LED brightness is minimum. Figure 22 shows this function
in the schematic.
PWCLK must be a square wave signal, duty cycle is not important but the minimum width
has to be above 20 ns, max. frequency has to be 30 MHz (pay attention the minimum output
ON time). Just after the device startup (brightness counter reset), before applying PWCLK
signal, all channels are in power-on condition if the brightness register values are not
zeroed.
AM13703V1
DocID025718 Rev 4 29/39
ALED1642GW Configuration register
39
Figure 22. PWCLK counter and comparator
Figure 23. Brightness register setting
AM13704V1
AM13705V1
0E
0F 0C 0A0B0D 09 08 07 06 05 04 03 02 01 00
BRT14 BRT13BRT15 BRT01BRT02BRT03
256-bit brightness data
stream
CLK
SDI
LE
16-bit Data Word
Data latch
CLK
SDI
LE
Global latch
0E
0F 0C 0A0B0D 09 08 07 06 05 04 03 02 01 00
BRT00
MSB LSB
Thermal flag ALED1642GW
30/39 DocID025718 Rev 4
9 Thermal flag
The device has a thermal control logic providing a flag status when the internal temperature
exceeds 150 °C (if temperature increases over 170 °C a thermal shutdown protects the
device). This status can be read running the digital key "thermal error reading", holding the
LE hi gh for 13 CLK ri sing ed ges (s ee Figure 24). If t herma l alert is asser ted, a 16 -bit st ring =
"1" is sent by SDO. The error data is uploaded into EDR register and this error notification is
ready to be streamed through SDO to next 16 CLK rising edges. Hence, thermal flag status
can be:
Figure 24. Thermal flag status
Device temperature SDO
under 150 °C “0000 0000 0000 0000”
over 150 °C “1111 1111 1111 1111”
Thermal
Flag Status
Previous data
13 Clock pulses with LE asserted
AM13706V1
DocID025718 Rev 4 31/39
ALED1642GW Dropout voltage
39
10 Dropout voltage
In order to correctly regulate the channel current, a minimum output voltage (V
DROP
) across
each current generator must be guaranteed.
The Figure 25 and Table 12 show the minimum V
DROP
related to the regulated current;
these measurements have been recorded with just one output ON. When more than one
output is active the drop voltage increases. At 36 mA per channel, the minimum output
voltage must be increased about 200 mV.
A V
DROP
, lower than the minimum recommended, implies the regulation of a current lower
than the expected one. However an excess of V
DROP
increases the power dissipation.
Figure 25. Typical channel dropout voltage vs. output current (V
DD
= 3.3 V)
Table 12. Minimum dropout voltage for some current values
Out put curr ent [ mA] Minimum V
DROP
@ V
DD
= 3.3 V
[mV]
370
9180
12 250
20 410
36 730
40 820
45 955
50 1070
AM13707V1
0
200
400
600
800
1000
1200
0 5 10 15 20 25 30 35 40 45 50 55
V
DROP
[mV]
IOUT [mA]
Drop vs. I
OUT
@ V
DD
= 3.3 V, T= 25
° C
(only one channel ON)
Package information ALED1642GW
32/39 DocID025718 Rev 4
11 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
DocID025718 Rev 4 33/39
ALED1642GW Package information
39
11.1 TSSOP24 exposed pad package information
Figure 26. TSSOP24 exposed pad outline
7100778_D
Package information ALED1642GW
34/39 DocID025718 Rev 4
Table 13. TSSOP24 exposed pad mechanical data
Dim. mm
Min. Typ. Max.
A1.20
A1 0.15
A2 0.80 1.00 1.05
b0.19 0.30
c0.09 0.20
D 7.70 7.80 7.90
D1 4.80 5.00 5.2
E 6.20 6.40 6.60
E1 4.30 4.40 4.50
E2 3.00 3.20 3.40
e0.65
L 0.45 0.60 0.75
L1 1.00
k0 8
aaa 0.10
DocID025718 Rev 4 35/39
ALED1642GW Package information
39
11.2 TSSOP24 exposed pad packing information
Figure 27. TSSOP24 exposed pad tape and reel outline
Package information ALED1642GW
36/39 DocID025718 Rev 4
Table 14. TSSOP24 exposed pad tape and reel mechanical data
Dim. mm
Min. Typ. Max.
A - 330
C 12.8 - 13.2
D 20.2 -
N 60 -
T - 22.4
Ao 6.8 - 7
Bo 8.2 - 8.4
Ko 1.7 - 1.9
Po 3.9 - 4.1
P 11.9 - 12.1
DocID025718 Rev 4 37/39
ALED1642GW Ordering information
39
12 Ordering information
Table 15. Ordering information
Order code Package Packing
ALED1642GWXTTR TSS OP24 exposed pad 2500 parts per reel
Revision history ALED1642GW
38/39 DocID025718 Rev 4
13 Revision history
Table 16. Document revision history
Date Revision Changes
07-Jan-2014 1 Initial release.
03-Mar-2014 2 Modified footnote1 in Table 5: Switching characteristics.
Added footnote 2 in Table 5: Switching characteristics
and footnote 5 in Table 4: Electrical characteristics.
05-Jun-2014 3 Updated Table 13: TSSOP24 exposed pad mechanical
data.
Minor text changes.
16-Nov-2015 4 Updated features in cover page.
Modifi ed foot note 2 in Table 3: Thermal characteristics.
Minor text changes.
DocID025718 Rev 4 39/39
ALED1642GW
39
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