Vishay Siliconix
Si9730
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
www.vishay.com
1
End of Life. Last Available Purchase Date is 31-Dec-2014
Dual-Cell Lithium Ion Battery Control IC
FEATURES
• Over-Charge Protection
• Over-Discharge Protection
• Short Circuit Current Limiting
• Battery Open-Circuit Center Tap Protection
• Cell Voltage Balancing
• Undervoltage Lockout
• Individual Cell Voltage Monitoring
• Low Operating Current (30 µA) and Shutdown Current
(1 µA)
• Internal N-Channel MOSFET Driver
• High Noise Immunity
• Accurate (± 1.19 %) Over-Charge Voltage Detection
• Four Different Cell Types Covered
DESCRIPTION
The Si9730 monitors the charging and discharging of dual-
cell lithium-ion battery packs (carbon or coke chemistry)
ensuring that battery capacity is fully utilized while ensuring
safe operation. The Si9730 provides protection against over-
charge, over-discharge, and short circuit conditions which
are hazardous to the battery and the environment.
Battery voltages of each individual cell are monitored at the
center-tap connection by an internal A/D converter through
the VC pin. If one or both of the cells is determined to be
overcharged, an internal cell balancing network "bleeds" off
current at 15 µA until both cells are charged to the same
maximum level. Depending on the condition of each cell, the
Si9730 will switch two external source-connected N-Channel
MOSFETs on or off to allow the cells to be charged or to pro-
vide current to the load.
The Si9730 is available in an 8-pin SOIC package with an
operating temperature range of - 25 to 85 °C. The Si9730 is
available in both standard and lead (Pb)-free packages.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
VDD
Cell Balancing
Network
A/D
Converter OUT
Oscillator
VC
1.2 VREF
VSS
Undervoltage
Lockout
Control
Logic
Timer
CDELAY
Time Out
CLK
DCO
IS
VSS
VM
SOUT
GS Generator
ILIMIT
VM
C
+
VC1
−
+
VC2
−
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Document Number: 70658
S-40135-Rev. F, 16-Feb-04
Vishay Siliconix
Si9730 End of Life. Last Available Purchase Date is 31-Dec-2014
Stresses beyond those listed under “Absolut e Maximum Ratings” may cause permanent damage to t he device. These are stress rating s only, and functional opera tion
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
VMVDD - 1.5 V to VDD + 15 V
V
VDD VSS - 0.3 V to VSS + 12 V
VCVSS - 0.3 V to VDD + 0.3 V
IS
(VSS VM)V
M - 0.3 V to VDD + 0.3 V
(VM VSS )V
SS - 0.3 V to VDD + 0.3 V
Maximum Operating Junction Temperature 125 °C
Power Dissipation 200 mW
Thermal Impedance (PJA)80 °C/W
Storage Temperature - 55 to 150 °C
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
CVC < 10 pF from VC to VDD and VSS , Total
CDOpen to 1.0 µF
RIS series resistance to sense resistor < 27 k
DCO Load Capacitance 0 to 2000 pF
VDD to VSS 9V
VDD to VM12
Operating Temperature Range - 25 to 85 °C
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
Limits
TA = - 25 to 85 °C Unit
MinaTypbMaxa
Power Supply
Supply Current, Charging Operation IDD_C VC1 = VC2 = 2.6 V, VDD - VM = 8.4 V 60
µA
Supply Current, Normal Operation IDD VC1 = VC2 = 4.05 V, VM = VSS 30
IDD_UVL VM = VDD, VC1 = VC2 = 1.7 V 1
Undervoltage Lockout Threshold VUVL Measured at VDD - VSS (Falling)
VC1 = VC2, VDD - VM = 5.5 V 3.5 3.7 4.0 V
VM Leakage Current IVM_UVL VC1 = VC2 = 1.7 V, VDD = VM1µA
VM Operating Current IVM VC1 = VC2 = 2.6 V, VDD - VM = 8.4 V 30
Control Logic
DCO Output High Voltage VOH IOH = - 10 µA, VC1 = VC2 = 3.3 V
VDD - VM = 6.6 V VDD - 0.1 V
DCO Rise Time (10 % to 80 %) trVC1 = 2 V, VC2 = 2.4 V
VDD - VM = 8.4 V CL = 500 pF, DCO to VSS
7.5 µs
DCO Fall Time (80 % to 10 %) tf1
DCO Output Low Voltage VOL IOL = 10 µA
VM = VDD
VC1 = 2 V, VC2 = 2.4 V VSS + 0.4
V
VM = VSS
VC1 = VC2 = 4.4 V, IS = VDD VM + 0.52
Analog Section
Current-Limit
Comparator Trip Point VILIMIT VC1 = VC2 = 4.05 V, VM = VSS + 0.25 V
IS Rising, TA = 25 °C 25.5 28 32 mV
Current-Limit
Comparator Temperature Coefficient dVILIMIT/dT 0.18 %/°C
Current-Limit
Comparator Response Time tILIMIT VC1 = VC2 = 3.3 V, VM = VSS + 0.25 V
CL = 50 pF, DCO to VSS, See Figure 2 25 µs
Current Limit
Comparator Input Bias Current IIS VC1 = VC2 = 3.3 V, VDD = VM, VIS = VSS - 125 nA
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
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Vishay Siliconix
Si9730
End of Life. Last Available Purchase Date is 31-Dec-2014
Notes:
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. Guaranteed by design, not subject to production test.
SPECIFICATIONS
Parameter Symbol
Test Conditions
Unless Otherwise Specified
Limits
TA = - 25 to 85 °C Unit
MinaTypbMaxa
Analog Section (cont’d)
Over-Charge Detect
Threshold (Rising)
A
Suffix
VOC1
Cell 1
VC2 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.15 4.20 4.25
V
TA = - 25 °C 4.1 4.27
TA = 85 °C 4.1 4.27
VOC2
Cell 2
VC1 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.15 4.20 4.25
TA = - 25 °C 4.1 4.27
TA = 85 °C 4.1 4.27
B
Suffix
VOC1
Cell 1
VC2 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.2 4.25 4.30
TA = - 25 °C 4.15 4.32
TA = 85 °C 4.15 4.32
VOC2
Cell 2
VC1 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.2 4.25 4.30
TA = - 25 °C 4.15 4.32
TA = 85 °C 4.15 4.32
C
Suffix
VOC1
Cell 1
VC2 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.18 4.22 4.25
TA = - 25 °C 4.12 4.30
TA = 85 °C 4.12 4.25
VOC2
Cell 2
VC1 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.18 4.22 4.25
TA = - 25 °C 4.12 4.30
TA = 85 °C 4.12 4.25
D
Suffix
VOC1
Cell 1
VC2 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.28 4.32 4.35
TA = - 25 °C 4.22 4.40
TA = 85 °C 4.22 4.35
VOC2
Cell 2
VC1 = 4.05 V
VDD - VM = 8.6 V
TA = 25 °C 4.28 4.32 4.35
TA = - 25 °C 4.22 4.40
TA = 85 °C 4.22 4.35
Over-Charge Threshold Difference |VOC1 - VOC2|20
mV
Over-Charge Detect
Threshold Hysteresisc
Cell 1 VOC_H1 VDD - VM = 8 6 V VC2 = 4.05 V 10
Cell 2 VOC_H2 VC1 = 4.05 V 10
Over-Discharge Detect
Threshold (Falling)
Cell 1 VODC1
VM = VSS
VC2 = 2.6 V 2.1 2.2 2.3 V
Cell 2 VODC2 VC1= 2.6 V 2.1 2.2 2.3
Cell Balancing Current Cell 1 IBAL1 VC1 = 4.4 V, VC2 = 4.05 V 91530
µA
Cell 2 IBAL2 VC2 = 4.4 V, VC1 = 4.05 V 91530
Timer Charge Current ITIMER(C) VC2 = 3.3 V, VM = VSS
VC = VSS, TA = 25 °C - 0.5
Timer Discharge Current ITIMER(D) VC1 = VC2 = 3.3 V, VDD = VM
VDD - VC = 6.1 V, TA = 25 °C 1.0 mA
DL2 Time (Over-Charge) tDL2OC VC1 = 4.05 V, VDD - VM = 10 V
CD = 500 pF, TA = 25 °C, See Figure 4 27 40 60
ms
DL2 Time (Over-Discharge) tDL2ODC
VC1 = 2.6 V, VM = VSS, CD = 500 pF
TA = 25 °C, See Figure 5 27 40 60
External Short Circuit Sense Current IVMSHORT VC1 = VC2 = 4.4 V, VM = VDD 30 300 µA
Reset Threshold VRTH VC1 = VC2 = 4.05 V, See Figure 3 42 60 100 mV
Center Tap, Average Bias Current IVC VC1 = VC2 = 4.05 V, VM = VDD - 2 2 µA
Overcharge Load Detect tOCC VC1 = VC2 = 4.4 V, CD = 500 pF
CL = 500 pF, DCO to VSS, See Figure 1 40 µs
Power-Down Charger Detect
Threshold VCHPD VC1 = 2 V, VC2 = 2.4 V, See Figure 6 1.1 V
DCO Pulse Width tPW CL = 500 pF, DCO to VSS, See Figure 7 520 µs
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Document Number: 70658
S-40135-Rev. F, 16-Feb-04
Vishay Siliconix
Si9730 End of Life. Last Available Purchase Date is 31-Dec-2014
TIMING DIAGRAMS
Figure 1. OC Load Detect
tOCC
VSS
VM Waveform
DCO Waveform
200 mV
High
VSS
50 %
50 %
tr 100 nS
Figure 2. Current-Limit Comparator Response Time
Figure 4. DL2 Time (Over-Charge)
Figure 6. Power-Down Charger Detect Threshold
VSS
IS Input
VSS
VDD
DCO Waveform
60 mV
50 %
50 %
tr 100 nS
tILIMIT
VSS
t30
VC2 Waveform
C Waveform
4.0 V
4.4 V
tDL20C
32
=x
30 t30
131
VCHPD
VSS
VM Waveform
High
Low
DCO Waveform
VCHPD = VSS - VM at DCO Transition
+
−
Figure 3. Reset Threshold
Figure 5. DL2 Time (Over-Discharge)
Figure 7. Load Detection in Overcharge Mode
VSS
VRTH
VDD
VM Waveform
(After Short is
Removed)
VDD
VSS
DCO Waveform
VRTH = VM- VSS at DCO Transition
VSS
t30
VC2 Waveform
C Waveform
2.0 V
2.6 V
tDL20DC
32
=x
30 t30
131
VSS
VM Waveform ^VRTH
DCO Waveform
VSS
VDD
tpw
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
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Vishay Siliconix
Si9730
End of Life. Last Available Purchase Date is 31-Dec-2014
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
DL2 Period (Over Charge) vs. Capacitance
Over Current Sense Voltage
vs. Current Sense Time
Load Detect Time vs. VM - VSS
0.1
1.0
10.0
100.0
TA = 85 °C
- 25 °C
CD - Capacitance (µF)
0.01 0.1 1
tDL20C -)s( emiT
25 °C
0
20
40
60
80
100
120
20 40 60 80 100
VIS - VSS (mV)
TIMILI
t(µS)
3.5
4.0
4.5
5.0
5.5
6.0
6.5
50 75 100 125 150 175 200
VM- VSS (mV)
tCCO (µs)
DL2 Period (Over Discharge) vs. Capacitance
Reset Threshold vs. Temperature
Overcharge Threshold
vs. Opposing Cell Voltage
0.1
1.0
10.0
100.0
CD - Capacitance (µF)
TA = 85 °C - 25 °C
0.01 0.1 1
tDL20C -)s( emiT
25 °C
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
- 25 0 25 50 75 100
Temperature (°C)
-)dezilamro
N
( d
loh
s
e
rh
T
VH
T
R
4.1950
4.1975
4.2000
4.2025
4.2050
2.5 3.0 3.5 4.0
Opposing Cell Voltage (V)
)
V
(
V dlo
h
serh
T
egrah
c
r
e
v
OC
C
O
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Document Number: 70658
S-40135-Rev. F, 16-Feb-04
Vishay Siliconix
Si9730 End of Life. Last Available Purchase Date is 31-Dec-2014
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
PIN CONFIGURATION
DCO Rise and Fall Times vs. Capacitance
0.01
0.10
1.00
10.00
100.00
1000.00
Fall
Rise
T
A
= 85 °C
T
A
= - 25 °C
(µs) e m i T
DCO Capacitance (pF)
100 1000 10000
VMDCO
NC VSS
VDD IS
CDVC
SO-8
5
6
7
8
Top View
2
3
4
1
ORDERING INFORMATION
Part Number VOC1/2 Typ. Temp Range
Si9730ABY-T1 4.20 V
- 25° to 85 °C
Si9730ABY-T1-E3 (Lead Free)
Si9730BBY-T1 4.25 V
Si9730BBY-T1-E3 (Lead Free)
Si9730CBY-T1 4.22 V
Si9730CBY-T1-E3 (Lead Free)
Si9730DBY-T1 4.32 V
Si9730DBY-T1-E3 (Lead Free)
PIN DESCRIPTION
Pin Number Symbol Description
1VMNegative Battery Pack Terminal - connection for external negative terminal of the battery pack.
2 NC No Connection, do not connect this pin.
3VDD Dual Cell Positive Terminal - connection for positive terminal of dual series connected LiI+ cells.
4CD
Delay Capacitor Connection - an external capacitor connected across CD and Vss allows additional charge time
(DL2, see Detailed Description ) after a charge error has occurred. Suggested capacitor values are shown in
DL2 Period vs. Capacitance Curves.
5VCDual Cell Center Tap Connection - monitors individual battery voltages for overcharge and overdischarge errors.
6Is
Current Sense Comparator Input - monitors load current for short circuit conditions . If VILIMIT is exceeded, then
DCO opens the low-side switch, disconnecting the cell
7VSS Dual Cell Negative Terminal - connection for negative terminal of dual series connected LiI+ cells.
8DCO
Low-side Switch Gate Driver Output - drives the gate of two external source connected N-Channel MOSFETs.
DCO swings from VOL to VDD.
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
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Vishay Siliconix
Si9730
End of Life. Last Available Purchase Date is 31-Dec-2014
DETAILED DESCRIPTION
Overview
The purpose of the Si9730 is to safely and reliably control the
charging and discharging of a two-cell lithium-ion battery
(carbon or coke chemistry). It provides protection against all
possible fault conditions, including:
• external short circuits
• reversed charger
• overcharged cell or cells
• undervoltage
• battery open center-tap
General Concepts
The Si9730 operates by connecting or disconnecting the
negative terminal of the battery to the negative side of the
load and/or charger (see Figure 8); that is, it does ground
side switching. It is important to bear the distinction between
these two "grounds" in mind in order to understand the oper-
ation of the Si9730. The switching is accomplished by con-
trolling two "back-to-back" MOSFETs: having the two
MOSFETs in this arrangement is mandatory to ensure that
current cannot flow in either direction when the MOSFETs
are off. To turn the switch on, the Si9730 applies a gate-
source voltage to both MOSFETs (from the DCO pin) that is
high with respect to the sources. The Si9730 DCO signal is
referenced to the VM pin while the battery is being charged,
and to the Vss pin while the battery is being discharged. The
Si9730 causes the DCO to be referenced to the lower of the
two voltages. This prevents the switch from turning on or off
unintentionally.
The Si9730 is designed to operate only with a current-limited
lithium-ion battery charger. Specifically, the battery charger
must have an open-circuit voltage that does not exceed the
absolute maximum IC voltage, and it must have a limited
short-circuit current that does not exceed the allowed
charging current of the battery.
The following descriptions cover all the common operational
scenarios; additional information on unusual battery condi-
tions can be found in the state transition table.
Normal Charging
The cells are in normal charging conditions if a) both cells are
above the Over-Discharge Detect Threshold (VODC ~ 2.2 V);
b) both cells are under the Over-Charge Detect Threshold
(VOC ~ 4.2 V); and c) the center tap is connected to the VC
pin. When a charger is present in these conditions, the switch
will be on, charging the cells at the current limit of the char-
ger.
Normal Discharging
The cells are in normal discharging conditions if a, b, and c
above are satisfied, and if in addition d) the load current is
less than the discharge current limit. With no charger pres-
ent, the switch will be on, discharging the cells and powering
the load.
Overcharged Cell(s) Charging
The most destructive condition that a LiI+ cell can experience
is overcharging. If the cell becomes overcharged beyond its
recommended limits, it can become permanently disabled.
If one or both cells rise above the over-charge detect thresh-
old (VOC1 and VOC2), and a charger is present, the Si9730
will open the switch (to prevent further charging) and begin
bleeding off charge (15 µA typical) from the overcharged cell
or cells.
The details of this operation depend on the fact that the volt-
age level of lithium-ion batteries drops for a short time after
charging ceases (due to momentary changes in battery
chemistry, ESR, etc.). Because of this recovery, the Si9730
allows the battery to continue charging for a short time (the
overcharge time, tDL2OC). This additional charge time only
occurs if the overcharge condition persists for more than
8 msec (two periods of an internal 4msec oscillator). TDL2OC
is determined by the capacitor attached to the CD pin, see
Figure 8.
Once the overcharge time has ended, the switch is opened,
preventing the battery from further overcharging. Now, the
Si9730 begins bleeding current off the overcharged cell or
cells (IBAL1 and IBAL2), as long as a charger is present. Even-
tually, the cell(s) will return into their normal range, and
charging will begin, starting the whole cycle over again.
Overcharged Cell(s) Discharging
If one or more cells is overcharged, and a load is connected,
the switch is turned on, permitting the battery to power the
load.
Over-Discharged Cell(s) Discharging
Repeated over-discharging of LiI+ cells can cause irrevers-
ible reactions in the cells which lead to decreased cycle life.
To avoid this, if one or both cells becomes over-discharged
(VCELL < VODC) and no charger is present, the Si9730 opens
the switch to prevent further discharging, and goes into a
shutdown mode in which it draws minute power from the bat-
tery (IDD_UVL < 1 µA).
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Document Number: 70658
S-40135-Rev. F, 16-Feb-04
Vishay Siliconix
Si9730 End of Life. Last Available Purchase Date is 31-Dec-2014
Over-Discharged Cell(s) Charging
If one or both cells is over-discharged, and a charger is pres-
ent, charging can begin, and so the Si9730 closes the switch.
However, removal of the charger in this condition could
potentially damage the battery if the removal is not recog-
nized and the cells are discharged. Since the voltage drop
across the switch is small, the Si9730 actually cycles the
switch at a 7/8 duty cycle; during the 1/8 time when the
switch is open, the IC checks that the charger is still present.
Once both cells are back into the normal operating range,
normal charging resumes.
Undervoltage Charging
If for some reason the battery drops below about 3.7 V
(VUVL), there is insufficient voltage for the Si9730 to properly
monitor fault conditions. Of course, the switch is already
open, since VUVL < VODC x 2. However, when a charger is
detected, the Si9730 recovers and goes into an undervoltage
mode. (A charger is detected if the VS pin is higher than the
VM pin by at least VCHPD = 1.1 V, see Figure 6). In this under-
voltage mode, the switch is on at a 1/8 duty cycle, to limit the
power dissipation across the switch, and, again, to detect the
continuing presence of the charger.
Once the battery voltage is above VUVL, the charging contin-
ues in the over-discharged state.
Output Short
If too much current is drawn from the battery due to a load
short, the switch must be opened quickly to prevent damage
to the battery. The Si9730 monitors the load current by look-
ing at the voltage across an external sense resistor (see Fig-
ure 8). If the voltage across the sense resistor exceeds
VILIMIT ~ 28 mV, the switch is opened. The Si9730 leaves the
switch open until the load is completely removed.
Of course, the IC must have some way of detecting that the
load has been removed. For this purpose, a small current
(IVMSHORT) passes through the Si9730, from pin VM to pin
VSS once the short is detected and the switch is turned off.
The IVMSHORT current causes the voltage on the VM pin to
equal the voltage on the VDD pin while the short is present,
or the voltage on the VM pin to equal the voltage on the VSS
pin if the short is removed. If the short is not removed, IVMS-
HORT current will continue to flow until the battery voltage
becomes overdischarged. Once the short is removed, the IC
is allowed to turn the switch back on.
The current limit threshold has a temperature coefficient of
0.18 %/°C. This can partially compensate for a copper circuit
board trace being used as the sense resistor.
Open Center Tap
An open center tap is a mechanical failure of the battery pack
such that the Si9730’s VC pin is disconnected from the center
point of the two-cell battery. If this connection is open, the IC
opens the switch, as it cannot measure the cell voltages in
this condition. The switch is left open until connection is re-
established. If the battery is under-voltaged and the charger
is present in this case, the battery is allowed to charge even
with the center tap open. In this state, batteries are almost
impossible to damage by 1/8 duty cycle charging. Once the
battery voltage reaches the over-discharged voltage, the
switch is turned off.
State Transition Table
The number of different states of the Si9730 can seem over-
whelming at first. This state transition table will help to orga-
nize thinking about the different operational conditions of the
IC, by listing each possible transition from one condition to
another.
Reading the table is straightforward. There are two cells con-
stituting the battery, one with its positive terminal connected
to VDD and its negative terminal connected to VC, referred to
as the high cell (see Figure 8); and one cell with its positive
terminal connected to VC and its negative terminal con-
nected to VSS, referred to as the low cell. Each cell can be in
one of three voltages:
• Over-discharge (ODC), where VCELL < VODC;
• Normal Operation (NO), where
VODC < VCELL < VOC;
or
• Overcharge (OC), where VOC < VCELL.
Additionally, the battery as a whole can be undervoltage
(UV), where VBATTERY < VUVL. Note that this final condition
is not necessarily (though normally) mutually exclusive with
the other cell conditions: if one cell were at 0 V, the other cell
could be in NO, and the battery could still be in UV.
The charger can be either present (ON) or not present (OFF);
the "X" in the table means the condition is true regardless of
the state of the charger. The load current can be either 0,
normal (0 < ILOAD < IILIMIT) or a short (IILIMIT< ILOAD) where
IILIMIT is set by VILIMIT/RSENSE; the "X" in the table refers to
a load current that can be either 0 or normal. Finally, the
switch can be either ON, OFF, or cycling at either 1/8 or 7/8
duty cycle, where the duty cycle refers to the portion of the
period when the switch is on; the notation On->On simply
means that the switch does not change state, it remains on;
the notation ->Off means that the switch turns off regardless
of its previous state.
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
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Vishay Siliconix
Si9730
End of Life. Last Available Purchase Date is 31-Dec-2014
STATE TRANSITION TABLE
High-Cell Voltage Low-Cell Voltage Charger On/Off Load Current Switch State
NO NO Off>On X On->On
NO->OC NO Off 0 On->Off
NO NO->OC Off 0 On->Off
NO->OC NO Off Normal Cycles at very high duty cycle
NO NO->OC Off Normal Cycles at very high duty cycle
OC NO Off->On X Off->Off
NO OC Off->On X Off->Off
OC OC Off->On X Off->Off
NO NO Off Normal->Short On->Off
OC NO Off Normal->Short On->Off
NO OC Off Normal->Short On->Off
NO->ODC NO Off 0 On->Off
NO NO->ODC Off 0 On->Off
NO->ODC NO Off Normal On->Off
NO NO->ODC Off Normal On->Off
ODC NO Off->On X Off->Cycle at 7/8 duty cycle
NO ODC Off->On X Off->Cycle at 7/8 duty cycle
ODC ODC Off->On X Off->Cycle at 7/8 duty cycle
UV Off->On X Off->Cycle at 1/8 duty cycle
NO->ODC OC Off 0 Cycle->Off
OC NO->OC Off 0 Off
NO NO V<0 X Off
UV On Center Tap->Open Cycle at 1/8 duty cycle
ODC ODC X Center Tap->Open -.>Off
NO ODC X Center Tap->Open -.>Off
ODC NO X Center Tap->Open -.>Off
NO NO X Center Tap->Open -.>Off
OC OC X Center Tap->Open -.>Off
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Document Number: 70658
S-40135-Rev. F, 16-Feb-04
Vishay Siliconix
Si9730 End of Life. Last Available Purchase Date is 31-Dec-2014
APPLICATION CIRCUIT
GENERAL CONSIDERATIONS
Figure 8 shows a typical application of the Si9730, controlling
a 2-cell lithium-ion battery (carbon or coke chemistry). Spe-
cifics of the selection of MOSFETs, current sensing resistor,
and output capacitor are detailed below. In addition, there
are several typical features of this circuit to be observed.
First, each connection from a cell to the IC has a 100 resis-
tor in series with it. The purpose of the resistor is to ensure
that in the unlikely event of the IC shorting, the cells them-
selves will not see a short. The maximum size of this resis-
tance is set by the current drain of the IC; for example, the
VDD pin draws a maximum of 60 µA, which will drop
V = 60 µA * 100 = 6 mV across the resistor. This drop con-
stitutes an error in the measured cell voltage, and so the
resistor must be small enough that the error voltage is
acceptable.
A second typical feature demonstrated in Figure 8 is the cur-
rent sense filter formed by RIS and C2. This provides a noise
filter, to prevent the Si9730 from opening the connection to
the battery if there is noise on its current sense pin. It also
causes a delay in the response of the IC to a genuine over-
current, the amount of the delay being inversely proportional
to the amount of overcurrent, since the Is pin senses a volt-
age. Increasing this filter’s time constant could be used to
allow short-time surges of current out of the battery without
compromising its ability to protect the battery.
Figure 8. Typical 2 -Cell Circuit
V
DD
Cell Balancing
Network
A/D
Converter OUT
Oscillator
V
C
1.2 VREF
V
SS
Undervoltage
Lockout
Control
Logic
Timer
C
DELAY
Time Out
CLK
DCO
I
S
V
SS
V
M
S
OUT
I
LIMIT
C
D
Comparator
Cell 1
V
C1
Cell 2
V
C2
Current
Sense
14 MΩ Filter
Si9936DY
C
2
0.47 µ F
GS Gen.
C
V
M
100 Ω
100 Ω
100 Ω
R
IS
47 kΩ
1 8
6
7
5
3 4
C
1
0.1 µ F
Load
Chgr.
8.4 V
1 A
Si9730 10 µ F
+
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
www.vishay.com
11
Vishay Siliconix
Si9730
End of Life. Last Available Purchase Date is 31-Dec-2014
Output Capacitor
Depending on the MOSFET selected, the Si9730 can open
the switch quite rapidly, in a matter of a few microseconds.
However, the various monitoring operations take 10-100
times longer than this, and the basic period of the Si9730’s
oscillator is 4 msec. In order to prevent false readings by the
Si9730, it is necessary to attach a capacitor across the out-
put of the battery charger/load (this is not in parallel with the
battery, because of the switch). A 10 µF capacitor is recom-
mended for this purpose; see Figure 8.
Selecting a Current Sense Resistor
The current sense resistor should be selected based on the
maximum current the battery can source or charge at; above
this current, the Si9730 will open the switch, disconnecting
the battery from its load or charger.
Rsense = VILIMIT/IILIMIT 28 mV/IILIMIT
Of course, the resistor must be rated to take the power dissi-
pated in it as well:
PRSENSE = IILIMIT* VILIMIT 28 mV * IILIMIT
For example, suppose that the maximum current the battery
will see is 1.8 A. Then, ILIMIT might be chosen to be 2 A. We
would then select a resistor of
RSENSE = 28 mV/2 A = 14 m.
The power dissipation in this resistor is
PRSENSE = 28 mV * 2 A = 56 mW
and so a 100 mW surface mount resistor would be suitable.
Another possibility is to use a thin copper trace as the
sense resistor. The copper has a temperature coefficient of
0.39 %/°C, but this is partially compensated for by the tem-
perature coefficient of the current limit comparator in the
Si9730, which is 0.18 %/°C. A simple formula for selecting a
trace to act as a current sensor is:
For example, to get a 14 m. resistor, we need length/width
= 28; with a trace width of 0.01", the length of the trace
should be 0.28".
MOSFET Selection
Two MOSFETs in series, with their sources and gates con-
nected together, are used as the switch. This prevents cur-
rent from flowing in either direction when the gate is low; if
only one MOSFET were used, the body diode could conduct
current in the opposing direction.
LITTLE FOOT MOSFETs are recommended for this appli-
cation, because of their size, performance and cost benefits.
SO-8 and TSSOP-8 MOSFETs allow for space efficient
designs with performance equal to or better than their DPAK
and TO-220 predecessors. Further, their availability from
multiple sources permits a cost effective solution.
There are two important parameters to consider in MOSFET
selection: gate threshold voltage; and on-resistance, which
determines power dissipation.
Even when the DCO pin of the Si9730 is low, the specifica-
tion allows its value to be as high as 0.4 V. If this voltage were
close to the gate threshold voltage, leakage current through
the MOSFETs could be hundreds of microamps, which
would result in the battery quickly becoming discharged. To
ensure that leakage is minimized, N-Channel MOSFETs with
a minimum gate threshold voltage of 0.8 V should be chosen.
On resistance of the MOSFETs needs to be selected to limit
power dissipation into the MOSFETs’ package. For example,
a dual MOSFET SO-8 package is rated at 2 W, and a dual
MOSFET TSSOP-8 package is rated at 1 W (both at 25 °C;
if the ambient temperature is higher, the allowable power dis-
sipation in these packages is less). For example, if the max-
imum current is 2 A, and a dual MOSFET SO-8 package is
being used, the maximum on-resistance of the two MOS-
FETs in series must not exceed
1 W = (2 A)2 * RON
or RON = 0.25 ; each MOSFET can be allotted half of this,
RON = 125 m. Account must also be taken of the fact that
MOSFETs’ on-resistance is a function of temperature; a con-
servative approach would give a discount of 1/3,
RON =125m * (2/3) = 80 m per MOSFET.
A list of recommended MOSFETs, which Vishay Siliconix
supplies, follows.
R0.5 mΩlength
width 1 oz. Copper
x
www.vishay.com
12
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
Vishay Siliconix
Si9730 End of Life. Last Available Purchase Date is 31-Dec-2014
N-CHANNEL MOSFET SELECTION GUIDE
Part Number rDS (on) () at
VGS = 10 V
rDS(on) () at
VGS = 4.5 V ID (A) VGS(th) (V) Config. Package
Recommended
Application Current
(A) at 25 °C
Si4410DY 0.0135 0.020 10 1.0 Single SO-8 9
Si4412DY 0.028 0.042 7 1.0 Single SO-8 6.3
Si6434DQ 0.028 0.042 5.6 1.0 Single TSSOP-8 4.9
Si4936DY 0.037 0.055 5.8 1.0 Dual SO-8 3.5
Si9936DY 0.050 0.080 5 1.0 Dual SO-8 2.9
Si6954DQ 0.065 0.095 3.9 1.0 Dual TSSOP-8 1.9
Figure 9. 4-Cell Battery Circuit
8
7
6
5
1
2
3
4
Si9730
470 nF
10 nF
47 kΩ
100 Ω
100 Ω
100 Ω
V
M
N
C
V
DD
C
D
DCO
V
SS
I
S
V
C
8
7
6
5
1
2
3
4
Si9730
V
M
N
C
V
DD
C
D
DCO
V
SS
I
S
V
C
100 Ω
15 MΩ
Si9936
10 nF
100 Ω
100 Ω
15 MΩ
47 kΩ
Si9936
V -
V +
100 µ F
100 µ F
+
+
470 nF
Document Number: 70658
S-40135-Rev. F, 16-Feb-04
www.vishay.com
13
Vishay Siliconix
Si9730
End of Life. Last Available Purchase Date is 31-Dec-2014
Four Cell Application
Figure 9 shows a method for using the Si9730 in a 4-cell
application. Basically, this is two complete 2-cell circuits
stacked in series. Each half of the complete circuit monitors
its own 2-cell portion of the battery, and opens its own MOS-
FET switch under any of the appropriate conditions. Observe
that the total percent power loss in this circuit is identical to
that in the 2-cell application; although there are now two sets
of MOSFETs in series, there is also double the battery volt-
age, and so total efficiency is the same.
One novel feature of this 4-cell circuit is the increase in the
size of the bypass capacitors. Each half of the circuit retains
its own output cap, to reduce noise seen by the circuit. Since
the two halves interact with each other (when one opens its
switch, the other one is also opened), there can be additional
noise, which must be rejected for proper operation. The
capacitors have been increased to 100 µF for this reason;
remember that they must be rated to take the full maximum
voltage rating of the charger, not half of it, since if one switch
is closed and the other open, the charger (minus two cells’
voltage drop, which might be zero) is applied across the
other capacitor.
A second addition on this circuit is the (optional) two zeners,
one each for each Si9730, placed from VDD to VM. These are
necessary only if the charger voltage is higher than the 15 V
absolute maximum of the IC plus two cells’ voltage drop. Just
as with the capacitor, if one switch is open and the other
closed, the IC will see this charger voltage, and must be pro-
tected. The power rating of the zener can be inferred by
observing that the current through it is limited by the 100
resistor. A trade off can be made here between the power
rating of the zener, which can be decreased by increasing
the resistor value, and the accuracy of the voltage measure-
ment by the Si9730, which can be increased by decreasing
the resistor value.
Reset from Shutdown
There are two specialized conditions that can place the
Si9730 in shutdown mode. The first condition can occur
when the circuit is first attached to a battery in the factory.
When the IC comes up, it will be in the undervoltage shut-
down mode. The Si9730 may also enter this mode when the
ambient temperature drops and the battery is nearly in UV.
When the temperature drops, the battery pack voltage will
drop and the IC may enter the shutdown mode. In either
case, the Si9730 must be reset by raising the VSS pin higher
than the VM pin by VCPHD. Figure 10 shows a circuit that
resets the circuit once it has entered the shutdown mode.
The circuit works by initially connecting the 0.1 µF capacitor
to the battery’s center tap and placing the switch in position
#1. Although the MOSFETs are open, the 1 m resistor is
sufficient to allow the capacitor to charge up in about 300 -
400 msec. Once the capacitor is charged, the switch is
placed in position #2, momentarily making VSS higher than
VM, thus placing the Si9730 in the normal operating mode.
The entire circuit provides a leakage of only a few micro-
amps, which is much lower than the self discharge current of
the LiIon battery.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?70658.
Figure 10. Factory Startup Circuit
8
7
6
5
1
2
3
4
Si9730
VM
NC
VDD
CD
DCO
VSS
IS
VC
1 MΩ
0.1 µF
#1#2
SPDT
15 MΩ
Vishay Siliconix
Package Information
Document Number: 71192
11-Sep-06
www.vishay.com
1
DIM
MILLIMETERS INCHES
Min Max Min Max
A 1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
4
3
12
5
6
87
HE
h x 45
C
All Leads
q0.101 mm
0.004"
L
BA
1
A
e
D
0.25 mm (Gage Plane)
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
S
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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particular product with the properties described in the product specification is suitable for use in a particular application.
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