Single-Supply, Rail-to-Rail
Low Power FET-Input Op Amp
AD822
Rev. I
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FEATURES
True single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 5 V to 30 V
Dual-supply capability from ±2.5 V to ±15 V
High load drive
Capacitive load drive of 350 pF, G = +1
Minimum output current of 15 mA
Excellent ac performance for low power
800 µA maximum quiescent current per amplifier
Unity-gain bandwidth: 1.8 MHz
Slew rate of 3 V/s
Good dc performance
800 µV maximum input offset voltage
2 µV/°C typical offset voltage drift
25 pA maximum input bias current
Low noise
13 nV/√Hz @ 10 kHz
No phase inversion
APPLICATIONS
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 14-bit data acquisition systems
Medical instrumentation
Low power references and regulators
CONNECTION DIAGRAM
1
2
3
4
8
7
6
5
AD822
OUT1
–IN1
+IN1
V–
V+
OUT2
–IN2
+IN2
00874-001
Figure 1. 8-Lead PDIP (N Suffix);
8-Lead MSOP (RM Suffix);
and 8-Lead SOIC_N (R Suffix)
GENERAL DESCRIPTION
The AD822 is a dual precision, low power FET input op amp
that can operate from a single supply of 5 V to 30 V or dual
supplies of ±2.5 V to ±15 V. It has true single-supply capability
with an input voltage range extending below the negative rail,
allowing the AD822 to accommodate input signals below
ground in the single-supply mode. Output voltage swing
extends to within 10 mV of each rail, providing the maximum
output dynamic range.
FRE QUENC Y ( Hz )
1
10 10k
1k
100
INPUT VOLTAGE NOISE (nV/Hz)
100
10
00874-002
Figure 2. Input Voltage Noise vs. Frequency
Offset voltage of 800 µV maximum, offset voltage drift of 2 µV/°C,
input bias currents below 25 pA, and low input voltage noise
provide dc precision with source impedances up to a gigaohm.
The 1.8 MHz unity-gain bandwidth, –93 dB THD at 10 kHz,
and 3 V/µs slew rate are provided with a low supply current of
800 µA per amplifier.
AD822
Rev. I | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
Maximum Power Dissipation ................................................... 10
ESD Caution ................................................................................ 10
Typical Performance Characteristics ........................................... 11
Applications Information .............................................................. 18
Input Characteristics .................................................................. 18
Output Characteristics............................................................... 18
Single-Supply Voltage-to-Frequency Converter .................... 19
Single-Supply Programmable Gain Instrumentation
Amplifier ..................................................................................... 20
Low Dropout Bipolar Bridge Driver ........................................ 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
1/10—Rev. H to Rev. I
Changes to Features Section and General Description Section . 1
Changes to Endnote 1, Table 1 ........................................................ 5
Changes to Endnote 1, Table 2 ........................................................ 7
Changes to Endnote 1, Table 3 ........................................................ 9
Deleted Table 4; Renumbered Sequentially ................................ 10
Changes to Table 5 .......................................................................... 12
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
Deleted 3 V, Single-Supply Stereo Headphone Driver Section . 22
Deleted Figure 50; Renumbered Sequentially ............................ 22
8/08—Rev. G to Rev H.
Changes to Features Section and General Description Section . 1
Changed VO to VOUT Throughout ................................................... 4
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 8
Changes to Table 5 .......................................................................... 12
Added Table 6; Renumbered Sequentially .................................. 12
Changes to Figure 13 Caption ....................................................... 14
Changes to Figure 29, Figure 31, and Figure 35 ......................... 17
Changes to Figure 36 ...................................................................... 18
Changed Application Notes Section to Applications
Information Section ....................................................................... 20
Changes to Figure 46 and Figure 47 ............................................. 21
Changes to Figure 49 ...................................................................... 22
Changes to Figure 51 ...................................................................... 23
6/06—Rev. F to Rev. G
Changes to Features .......................................................................... 1
Changes to Table 4 .......................................................................... 10
Changes to Table 5 .......................................................................... 12
Changes to Table 6 .......................................................................... 22
10/05—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Outline Dimensions .................................................. 24
Updated Ordering Guide .............................................................. 24
1/03—Data sheet changed from Rev. D to Rev. E
Edits to Specifications ....................................................................... 2
Edits to Figure 10 ............................................................................ 16
Updated Outline Dimensions ....................................................... 17
10/02—Data sheet changed from Rev. C to Rev. D
Edits to Features ................................................................................. 1
Edits to Ordering Guide ................................................................... 6
Updated SOIC Package Outline ................................................... 17
8/02—Data sheet changed from Rev. B to Rev. C
All Figures Updated ................................................................ Global
Edits to Features ................................................................................. 1
Updated All Package Outlines ...................................................... 17
7/01—Data sheet changed from Rev. A to Rev. B
All Figures Updated ................................................................ Global
CERDIP References Removed ....................................... 1, 6, and 18
Additions to Product Description ................................................... 1
8-Lead SOIC and 8-Lead MSOP Diagrams Added ...................... 1
Deletion of AD822S Column ........................................................... 2
Edits to Absolute Maximum Ratings and Ordering Guide ......... 6
Removed Metallization Photograph ............................................... 6
AD822
Rev. I | Page 3 of 24
The AD822 drives up to 350 pF of direct capacitive load as a
follower and provides a minimum output current of 15 mA.
This allows the amplifier to handle a wide range of load conditions.
Its combination of ac and dc performance, plus the outstanding
load drive capability, results in an exceptionally versatile amplifier
for the single-supply user.
The AD822 is available in two performance grades. The A grade
and B grade are rated over the industrial temperature range of
−40°C to +85°C.
The AD822 is offered in three varieties of 8-lead packages:
PDIP, MSOP, and SOIC_N.
90
100
10
0%
.
........ .... .... .... .... .... .... .... ....
........ .... .... .... .... .... .... .... ....
V
OUT
5V
0V
(GND)
1V 20µs
1V
1V
0
0874-003
Figure 3. Gain-of-2 Amplifier; VS = 5 V, 0 V,
VIN = 2.5 V Sine Centered at 1.25 V, RL = 100 Ω
AD822
Rev. I | Page 4 of 24
SPECIFICATIONS
VS = 0 V, 5 V @ TA = 25°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted.
Table 1.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 mV
Maximum Offset Over Temperature 0.5 1.2 0.5 0.9 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = 0 V to 4 V 2 25 2 10 pA
At TMAX 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
At TMAX 0.5 0.5 nA
Open-Loop Gain VOUT = 0.2 V to 4 V
R
L = 100 kΩ 500 1000 500 1000 V/mV
TMIN to TMAX 400 400 V/mV
R
L = 10 kΩ 80 150 80 150 V/mV
TMIN to TMAX 80 80 V/mV
R
L = 1 kΩ 15 30 15 30 V/mV
TMIN to TMAX 10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
f = 0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ to 2.5 V
f = 10 kHz VOUT = 0.25 V to 4.75 V −93 −93 dB
DYNAMIC PERFORMANCE
Unity-Gain Frequency 1.8 1.8 MHz
Full Power Response VOUT p-p = 4.5 V 210 210 kHz
Slew Rate 3 3 V/μs
Settling Time
To 0.1% VOUT = 0.2 V to 4.5 V 1.4 1.4 μs
To 0.01% VOUT = 0.2 V to 4.5 V 1.8 1.8 μs
MATCHING CHARACTERISTICS
Initial Offset 1.0 0.5 mV
Maximum Offset Over Temperature 1.6 1.3 mV
Offset Drift 3 3 μV/°C
Input Bias Current 20 10 pA
Crosstalk @ f = 1 kHz RL = 5 kΩ −130 –130 dB
Crosstalk @ f = 100 kHz RL = 5 kΩ −93 –93 dB
INPUT CHARACTERISTICS
Input Voltage Range1, TMIN to TMAX −0.2 +4 −0.2 +4 V
Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 2 V 66 80 69 80 dB
TMIN to TMAX V
CM = 0 V to 2 V 66 66 dB
AD822
Rev. I | Page 5 of 24
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE I
SINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH I
SOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE ISINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH I
SOURCE = 2 mA 80 110 80 110 mV
TMIN to TMAX 160 160 mV
VOL – VEE I
SINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH I
SOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 15 15 mA
TMIN to TMAX 12 12 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current, TMIN to TMAX 1.24 1.6 1.24 1.6 mA
Power Supply Rejection V+ = 5 V to 15 V 66 80 70 80 dB
TMIN to TMAX 66 70 dB
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
AD822
Rev. I | Page 6 of 24
VS = ±5 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 2.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 mV
Maximum Offset Over Temperature 0.5 1.5 0.5 1 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = −5 V to +4 V 2 25 2 10 pA
At TMAX 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
At TMAX 0.5 0.5 nA
Open-Loop Gain VOUT = −4 V to +4 V
R
L = 100 kΩ 400 1000 400 1000 V/mV
TMIN to TMAX 400 400 V/mV
R
L = 10 kΩ 80 150 80 150 V/mV
TMIN to TMAX 80 80 V/mV
R
L = 1 kΩ 20 30 20 30 V/mV
TMIN to TMAX 10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
f = 0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ
f = 10 kHz VOUT = ±4.5 V −93 −93 dB
DYNAMIC PERFORMANCE
Unity-Gain Frequency 1.9 1.9 MHz
Full Power Response VOUT p-p = 9 V 105 105 kHz
Slew Rate 3 3 V/μs
Settling Time
to 0.1% VOUT = 0 V to ±4.5 V 1.4 1.4 μs
to 0.01% VOUT = 0 V to ±4.5 V 1.8 1.8 μs
MATCHING CHARACTERISTICS
Initial Offset 1.0 0.5 mV
Maximum Offset Over Temperature 3 2 mV
Offset Drift 3 3 μV/°C
Input Bias Current 25 10 pA
Crosstalk @ f = 1 kHz RL = 5 kΩ −130 −130 dB
Crosstalk @ f = 100 kHz RL = 5 kΩ −93 −93 dB
INPUT CHARACTERISTICS
Input Voltage Range1, TMIN to TMAX −5.2 +4 −5.2 +4 V
Common-Mode Rejection Ratio (CMRR) VCM = −5 V to +2 V 66 80 69 80 dB
TMIN to TMAX V
CM = −5 V to +2 V 66 66 dB
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
AD822
Rev. I | Page 7 of 24
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE ISINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH I
SOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE I
SINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH I
SOURCE = 2 mA 80 110 80 110 mV
TMIN to TMAX 160 160 mV
VOL − VEE I
SINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH I
SOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 15 15 mA
TMIN to TMAX 12 12 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current, TMIN to TMAX 1.3 1.6 1.3 1.6 mA
Power Supply Rejection VSY = ±5 V to ±15 V 66 80 70 80 dB
TMIN to TMAX 66 70 dB
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
AD822
Rev. I | Page 8 of 24
VS = ±15 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 3.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.4 2 0.3 1.5 mV
Maximum Offset Over Temperature 0.5 3 0.5 2.5 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = 0 V 2 25 2 12 pA
V
CM = −10 V 40 40 pA
At TMAX V
CM = 0 V 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 12 pA
At TMAX 0.5 0.5 nA
Open-Loop Gain VOUT = −10 V to +10 V
R
L = 100 kΩ 500 2000 500 2000 V/mV
TMIN to TMAX 500 500 V/mV
R
L = 10 kΩ 100 500 100 500 V/mV
TMIN to TMAX 100 100 V/mV
R
L = 1 kΩ 30 45 30 45 V/mV
TMIN to TMAX 20 20 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
f = 0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ
f = 10 kHz VOUT = ±10 V −85 −85 dB
DYNAMIC PERFORMANCE
Unity-Gain Frequency 1.9 1.9 MHz
Full Power Response VOUT p-p = 20 V 45 45 kHz
Slew Rate 3 3 V/μs
Settling Time
to 0.1% VOUT = 0 V to ±10 V 4.1 4.1 μs
to 0.01% VOUT = 0 V to ±10 V 4.5 4.5 μs
MATCHING CHARACTERISTICS
Initial Offset 3 2 mV
Maximum Offset Over Temperature 4 2.5 mV
Offset Drift 3 3 μV/°C
Input Bias Current 25 12 pA
Crosstalk @ f = 1 kHz RL = 5 kΩ −130 −130 dB
Crosstalk @ f = 100 kHz RL = 5 kΩ −93 −93 dB
INPUT CHARACTERISTICS
Input Voltage Range1, TMIN to TMAX −15.2 +14 −15.2 +14 V
Common-Mode Rejection Ratio (CMRR) VCM = −15 V to +12 V 70 80 74 90 dB
TMIN to TMAX V
CM = −15 V to +12 V 70 74 dB
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
AD822
Rev. I | Page 9 of 24
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE I
SINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH I
SOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE I
SINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH I
SOURCE = 2 mA 80 110 80 110 mV
TMIN to TMAX 160 160 mV
VOL − VEE I
SINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH I
SOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 20 20 mA
TMIN to TMAX 15 15 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current, TMIN to TMAX 1.4 1.8 1.4 1.8 mA
Power Supply Rejection VSY = ±5 V to ±15 V 70 80 70 80 dB
TMIN to TMAX 70 70 dB
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
AD822
Rev. I | Page 10 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation
8-Lead PDIP (N) Observe derating curves
8-Lead SOIC_N (R) Observe derating curves
8-Lead MSOP (RM) Observe derating curves
Input Voltage1 ((V+) + 0.2 V) to
((V−) − 20 V)
Output Short-Circuit Duration Indefinite
Differential Input Voltage ±30 V
Storage Temperature Range (N) –65°C to +125°C
Storage Temperature Range (R, RM) –65°C to +150°C
Operating Temperature Range
A Grade and B Grade –40°C to +85°C
Lead Temperature
(Soldering, 60 sec)
260°C
1 See the Input Characteristics section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type θJA Unit
8-lead PDIP (N) 90 °C/W
8-lead SOIC_N (R) 160 °C/W
8-lead MSOP (RM) 190 °C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD822 is limited by the associated rise in junction temperature.
For plastic packages, the maximum safe junction temperature is
145°C. If these maximums are exceeded momentarily, proper
circuit operation is restored as soon as the die temperature is
reduced. Leaving the device in the overheated condition for an
extended period can result in device burnout. To ensure proper
operation, it is important to observe the derating curves shown
in Figure 27.
While the AD822 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature is not exceeded under all conditions. With power
supplies ±12 V (or less) at an ambient temperature of 25°C or
less, if the output node is shorted to a supply rail, then the
amplifier is not destroyed, even if this condition persists for an
extended period.
ESD CAUTION
AD822
Rev. I | Page 11 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE (mV)
70
0
–0.5 –0.4
NUMBER OF UN ITS
–0.3 –0.2 –0.1 0
60
50
40
30
20
10
0.1 0.2 0.3 0.4 0.5
V
S
= 0V, 5V
00874-004
Figure 4. Typical Distribution of Offset Voltage (390 Units)
OF F S ET VOLTAG E DRIFT ( µ V / °C)
16
6
0
–12 10–10
% IN BIN
–8 –6 –4 –2
14
8
4
2
12
10
86420
V
S
= ±5V
V
S
= ±15V
00874-005
Figure 5. Typical Distribution of Offset Voltage Drift (100 Units)
I NPUT BIAS CURRENT (pA)
50
20
01
NUMBER O F UNITS
45
25
15
5
35
30
10
40
0 2345678910
00874-006
Figure 6. Typical Distribution of Input Bias Current (213 Units)
COMM O N-MO DE V OLTAGE ( V )
5
0
–5–5 5
–4
INPUT BIAS CURRE NT (pA)
–3 –2 –1 0 1 2 3 4
V
S
= ±5V V
S
= 0V, +5V AND ±5V
00874-007
Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = 5 V, 0 V, and
VS = ±5 V
COMM O N-MO DE VOLTAG E ( V)
1k
100
0.1
–16 16–12
INPUT BIAS CURRE NT (pA)
–8 –4 0 4 8 12
10
1
00874-008
Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = ±15 V
TEMPERAT URE ( °C)
100k
0.120 14040
INPUT BIAS CURRE NT ( pA)
60 80 100 120
10k
1k
100
10
1
00874-009
Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0 V
AD822
Rev. I | Page 12 of 24
LOAD RESISTANCE ()
10M
1M
10k
100 100k
OPEN-LOOP GAIN (V/V)
100k
1k 10k
V
S
= 0V, +5V
V
S
= ±15V
V
S
= 0V, +3V
00874-010
Figure 10. Open-Loop Gain vs. Load Resistance
TEMPERATURE (°C)
10M
1M
10k
–60 140–40
OPEN-LOOP GAIN (V/V)
–20 0 20 40 60 80 100 120
100k
R
L
= 100k
R
L
= 10k
R
L
= 600
V
S
= ±15V
V
S
= 0V, +5V
V
S
= ±15V
V
S
= 0V, +5V
V
S
= ±15V
V
S
= 0V, +5V
00874-011
Figure 11. Open-Loop Gain vs. Temperature
OUT PUT VOLTAGE (V)
300
–300
–16 16–12
INPUT ERROR VOLTAGE (V )
–8 –4 0 4 8 12
200
100
0
–100
–200
R
L
= 100k
R
L
= 10k
R
L
= 600
00874-012
Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads
OUTPUT VOLTAGE FROM SUPPLY RAILS (mV)
40
20
–40 60
INPUT ERROR VOLTAGE (µV)
120 180 240
0
–20
POS RAIL
NEG RAI L
NEG RAIL
NEG RAIL
POS RAIL
R
L
= 20kR
L
= 2k
R
L
= 100k
POS
RAIL
0 300
00874-013
Figure 13. Input Error Voltage with Output Voltage Within 300 mV of Either
Supply Rail for Various Resistive Loads; VS = ±5 V
FRE QUENC Y ( Hz )
1k
100
110 1k
10
110k100
INPUT VOLTAGE NOISE (nV/Hz)
00874-014
Figure 14. Input Voltage Noise vs. Frequency
FRE QUENC Y ( Hz )
–
40
–50
–110
100 100k1k
THD (dB)
10k
–70
–80
–90
–100
–60
RL = 10k
ACL = –1
VS = 0V, +3V; VOUT = 2.5V p-p
VS = ±15V; VOUT = 20V p-p
VS = ±5V; VOUT = 9V p-p
VS = 0V, +5V; VOUT = 4. 5V p-p
00874-015
Figure 15. Total Harmonic Distortion (THD) vs. Frequency
AD822
Rev. I | Page 13 of 24
FRE QUENC Y ( Hz )
100
–20
80
60
40
20
0
10 10M100
OPEN-LOOP GAIN (dB)
1k 10k 100k 1M
100
–20
80
60
40
20
0
PHASE M ARGI N ( Degrees)
PHASE
GAIN
C
L
= 100p F
R
L
= 2k
00874-016
Figure 16. Open-Loop Gain and Phase Margin vs. Frequency
FREQUENCY (Hz)
1k
100
100 10M1k
OUTPUT IMPE DANCE ( )
10k 100k 1M
10
1
0.1
0.01
A
CL
= +1
V
S
= ±15V
00874-017
Figure 17. Output Impedance vs. Frequency
SETTLING TIME (µs)
16
12
–16 051
OUTPUT SWING FROM 0TO ±VOLTS
234
0
–4
–8
–12
8
4
ERROR
1%
0.1%
1%
0.01%
0.01%
0
0874-018
Figure 18. Output Swing and Error vs. Settling Time
90
80
0
40
30
20
10
60
50
70
COMMON- MODE RE JE CTI ON (dB)
FREQ UE NC Y (Hz) 10M100 1k 10k 100k 1M10
V
S
= ±15V
V
S
= 0V, +5V
V
S
= 0V, +3V
00874-019
Figure 19. Common-Mode Rejection vs. Frequency
+125°C –55°C
+25°C
POSITIVE
RAIL
NEGATIVE
RAIL
COMMON-MODE VOLTAGE FROM SUPPLY RAILS (V)
5
4
0–1 3
COMMON-MODE ERROR VOLTAGE (mV)
3
2
1–55°C +125°C
210
00874-020
Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from
Supply Rails (VS − VCM)
LOAD CURRENT ( mA)
1000
100
00.001 1000.01
OUTPUT S
A
TUR
A
TION VOL
T
AGE (mV )
0.1 1 10
10
V
S
– V
OH
V
OL
– V
S
00874-021
Figure 21. Output Saturation Voltage vs. Load Current
AD822
Rev. I | Page 14 of 24
TEMPERATURE (°C)
1000
100
1
–60 140–40
OUTPUT S
A
TUR
A
TI O N VOLTAG E (mV)
–20 0 20 40 60 80 100 120
10
I
SOURCE
= 10mA
I
SINK
= 10mA
I
SOURCE
= 1mA
I
SINK
= 1mA
I
SOURCE
= 10µA
I
SINK
= 10µA
00874-022
Figure 22. Output Saturation Voltage vs. Temperature
TEMPERATURE (°C)
80
40
0
–60 140–40 –20 0 20 40 60 80 100 120
SHO
R
T-CIRCUIT CURRE NT LIMIT (mA)
70
60
20
10
50
30 +
–
–
+
+
–OUT
V
S
= ±15V
V
S
= ±15V
V
S
= 0V, +5V
V
S
= 0V, +3V
V
S
= 0V, +5V V
S
= 0V, +3V
00874-023
Figure 23. Short-Circuit Current Limit vs. Temperature
TOTAL SUPPLY VOLTAGE (V)
1600
04
QUI E S CE NT CURRENT (µA)
1400
800
600
400
200
1200
1000
T = + 125 °C
T = +25°C
T = –55°C
3632282420161208
00874-024
Figure 24. Quiescent Current vs. Supply Voltage vs. Temperature
FREQUENCY (Hz)
100
0
10 10M100
PO WER SUP PLY REJE CTION (dB)
1k 10k 100k 1M
90
60
30
20
10
80
70
50
40
+PSRR
–PSRR
00874-025
Figure 25. Power Supply Rejection vs. Frequency
FREQUENCY (Hz)
30
25
0
10k 10M100k
OUTPUT V OLTAGE ( V )
1M
20
15
10
5
V
S
= ±15V
V
S
= 0V, +5V
V
S
= 0V, +3V
R
L
= 2k
00874-026
Figure 26. Large Signal Frequency Response
AMBIENT TEMPE RATURE (°C)
2.4
1.2
0.4
–60 –40 –20 0 20 40 60 80
2.2
1.4
1.0
0.6
1.8
1.6
0.8
2.0
0.2
0
8-L EAD PDI P
8-L EAD SOIC
8-LE AD M S OP
TOTAL POWER DISSIP
A
TION (W)
00874-027
Figure 27. Maximum Power Dissipation vs. Temperature for Packages
AD822
Rev. I | Page 15 of 24
FRE QUENCY (Hz)
–
70
–140300 1M1k 3k 10k 30k 100k 300k
–80
–100
–110
–120
–130
–90
CROSSTALK (d B)
00874-028
Figure 28. Crosstalk vs. Frequency
VIN
RLVOUT
100pF
8
V
+0.01µF
40.01µF
1/2
AD822
+
–
00874-029
Figure 29. Unity-Gain Follower
0%
100
90
10
5V 10µs
00874-030
Figure 30. 20 V p-p, 25 kHz Sine Wave Input; Unity-Gain Follower; VS = ±15 V,
RL = 600 Ω
V+
20V p -
p
2
3
8
5
6
20k2.2k
5k
5k
V
OUT
CROSSTAL K = 20 lo g V
OUT
10V
IN
0.1µF 1µF
0.1µF 1µF
V–
V
IN
+
–
1/2
AD822
1
+
–
1/2
AD822
7
00874-031
Figure 31. Crosstalk Test Circuit
0%
100
90
10
5V 5µs
00874-032
Figure 32. Large Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ
10
0%
100
90
10mV 500ns
00874-033
Figure 33. Small Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ
GND
10
0%
100
90
1V 2µs
00874-034
Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step
4
V
IN
R
L
V
OUT
100pF
8
+0.01µF
1/2
AD822
+
–
0
0874-035
Figure 35. Unity-Gain Follower
AD822
Rev. I | Page 16 of 24
20k
10k
4
100pF
V
IN
R
L
V
OUT
8
V+ 0.01µF
+
–
1/2
AD822
00874-036
Figure 36. Gain-of-Two Inverter
GND
10
0%
100
90
2µs1V
00874-037
Figure 37. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step
GND
10
0%
100
90
10mV 2µs
00874-038
Figure 38. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mV Step,
Centered 40 mV above Ground, RL = 10 kΩ
GND
10
0%
100
90
10mV 2µs
0
0874-039
Figure 39. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mV Step,
Centered 20 mV Below Ground, RL = 10 kΩ
GND
10
0%
100
90
1V 2µs
00874-040
Figure 40. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step,
Centered −1.25 V Below Ground, RL = 10 kΩ
G
ND
10
0%
100
90
500mV 10µs
00874-041
Figure 41. VS = 3 V, 0 V; Gain-of-2 Inverter, VIN = 1.25 V, 25 kHz, Sine Wave
Centered at −0.75 V, RL = 600 Ω
AD822
Rev. I | Page 17 of 24
(a)
GND
V
IN
V
OUT
5V
R
P
90
100
10
0%
........ .... .... .... .... .... .... .... ....
........ .... .... .... .... .... .... .... ....
1V 10µs
1V
(b)
GND
+Vs
90
100
10
0%
....
.... .... .... ... ... .... .... .... ....
....
.... .... .... .... .... .... .... .... ....
1V 10µs
1V
1V
00874-042
Figure 42. (a) Response with RP = 0; VIN from 0 V to +VS
(b) VIN = 0 V to +VS + 200 mV
VOUT = 0 V to +VS
RP = 49.9 kΩ
AD822
Rev. I | Page 18 of 24
APPLICATIONS INFORMATION
INPUT CHARACTERISTICS
In the AD822, N-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input common-
mode voltage extends from 0.2 V below −VS to 1 V less than +VS.
Driving the input voltage closer to the positive rail causes a loss
of amplifier bandwidth (as can be seen by comparing the large
signal responses shown in Figure 34 and Figure 37) and increased
common-mode voltage error as illustrated in Figure 20.
The AD822 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 42 shows the response of an
AD822 voltage follower to a 0 V to 5 V (+VS) square wave input.
The input and output are superimposed. The output tracks the
input up to +VS without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output waveform.
For input voltages greater than +VS, a resistor in series with the
AD822 noninverting input prevents phase reversal, at the expense
of greater input voltage noise. This is illustrated in Figure 42.
Because the input stage uses N-channel JFETs, input current
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS − 0.4 V, then the input current reverses direction as
internal device junctions become forward biased. This is illu-
strated in Figure 7.
A current limiting resistor should be used in series with the input
of the AD822 if there is a possibility of the input voltage exceed-
ing the positive supply by more than 300 mV, or if an input voltage
is applied to the AD822 when +VS or −VS = 0 V. The amplifier is
damaged if left in that condition for more than 10 seconds. A 1 kΩ
resistor allows the amplifier to withstand up to 10 V of conti-
nuous overvoltage and increases the input voltage noise by a
negligible amount.
Input voltages less than −VS are a completely different story. The
amplifier can safely withstand input voltages 20 V below the
negative supply voltage if the total voltage from the positive
supply to the input terminal is less than 36 V. In addition, the
input stage typically maintains picoampere (pA) level input
currents across that input voltage range.
The AD822 is designed for 13 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure 14). This noise performance, along with the
AD822 low input current and current noise, means that the
AD822 contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 43.
100k
0.1
10k
1k
100
10
1
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
1kHz
AMPLIFIER-GENERATED
NOISE
10Hz
10k 100k 1M 10M 100M 1G 10G
SOURCE IMPE DANCE ( )
INPUT VOL
T
AGE NOI SE (µ V)
RESISTOR JOHNSON
NOISE
00874-043
Figure 43. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
The AD822 unique bipolar rail-to-rail output stage swings within
5 mV of the negative supply and 10 mV of the positive supply with
no external resistive load. The approximate output saturation
resistance of the AD822 is 40 Ω sourcing and 20 Ω sinking, which
can be used to estimate output saturation voltage when driving
heavier current loads. For instance, when sourcing 5 mA, the
saturation voltage to the positive supply rail is 200 mV; when
sinking 5 mA, the saturation voltage to the negative rail is 100 mV.
The open-loop gain characteristic of the amplifier changes as a
function of resistive load, as shown in Figure 10 to Figure 13.
For load resistances over 20 kΩ, the AD822 input error voltage
is virtually unchanged until the output voltage is driven to 180 mV
of either supply.
If the AD822 output is overdriven so that either of the output
devices are saturated, the amplifier recovers within 2 s of its
input returning to the linear operating region of the amplifier.
Direct capacitive loads interact with the effective output imped-
ance of the amplifier to form an additional pole in the amplifier
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. The worst case occurs when the
amplifier is used as a unity-gain follower. Figure 44 shows the
AD822 pulse response as a unity-gain follower driving 350 pF.
This amount of overshoot indicates approximately 20° of phase
margin—the system is stable, but nearing the edge. Configurations
with less loop gain, and as a result less loop bandwidth, are
much less sensitive to capacitance load effects.
AD822
Rev. I | Page 19 of 24
90
........ .... .... .... .... .... .... .... ....
........ .... .... .... .... .... .... .... ....
100
0%
10
20mV 2µs
00874-044
Figure 44. Small Signal Response of AD822 as
Unity-Gain Follower Driving 350 pF
Figure 45 is a plot of noise gain vs. capacitive load that results in
a 20° phase margin for the AD822. Noise gain is the inverse of
the feedback attenuation factor provided by the feedback
network in use.
1
2
3
4
5
300 1k 3k 10k 30k
CAPACITI V E LOAD FO R 20° PHAS E M ARGIN ( pF )
NOISE GAIN 1+ R
F
R
1
R1
R
F
C
L
00874-045
Figure 45. Noise Gain vs. Capacitive Load Tolerance
Figure 46 shows a method for extending capacitance load drive
capability for a unity-gain follower. With these component
values, the circuit drives 5000 pF with a 10% overshoot.
20pF
100
20k
8
4
V
IN
+0.01µF
V
OUT
0.01µF C
L
1/2
AD822
+
–
V–
00874-046
Figure 46. Extending Unity-Gain Follower Capacitive Load Capability
Beyond 350 pF
SINGLE-SUPPLY VOLTAGE-TO-FREQUENCY
CONVERTER
The circuit shown in Figure 47 uses the AD822 to drive a low
power timer that produces a stable pulse of width t1. The positive
going output pulse is integrated by R1 and C1 and used as one
input to the AD822 that is connected as a differential integrator.
The other input (nonloading) is the unknown voltage, VIN. The
AD822 output drives the timer trigger input, closing the overall
feedback loop.
2
3
4
6
5U3A
U3B
C3
0.1
µF
123
4
OUT2
OUT1
U1 C1
U2
CMO S 555
THR
TR
DIS
GND
OUT
CV
1
23
4
5
6
7
8
RV+
C4
0.01µF
R3
116k
0.01 µF, 2%
CMOS
74HCO4
RSCALE
10k
U4
REF02
VREF = 5V
10V
C5
0.1µF
R2
499k
1%
R1
499k
1%
VIN
C2
0.01µF
2%
0V TO 2.5V
FULL SCALE
1/2
AD822B
+
–
NOTES
1. fOUT = VIN/(VREF × t1), t1 = 1.1 × R3 × C6.
2. R3 = 1% METAL FILM <50ppm/°C TC.
3. RSCALE = 10% 20T FILM <100ppm/°C TC.
4. t1= 33µF F O R fOUT = 20kHz @ V IN = 2.0V.
= 25kHz
f
SAS SHOW N.
00874-047
Figure 47. Single-Supply Voltage-to-Frequency Converter
Typical AD822 bias currents of 2 pA allow M range source
impedances with negligible dc errors. Linearity errors on the
order of 0.01% full scale can be achieved with this circuit. This
performance is obtained with a 5 V single supply that delivers
less than 1 mA to the entire circuit.
AD822
Rev. I | Page 20 of 24
SINGLE-SUPPLY PROGRAMMABLE GAIN
INSTRUMENTATION AMPLIFIER
The AD822 can be configured as a single-supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 3 V or dual supplies up to ±15 V. Using only one AD822 rather
than three separate op amps, this circuit is cost and power efficient.
The 2 pA bias currents of the AD822 FET inputs minimize
offset errors caused by high unbalanced source impedances.
An array of precision thin film resistors sets the in-amp gain to
be either 10 or 100. These resistors are laser trimmed to ratio
match to 0.01% and have a maximum differential TC of 5 ppm/°C.
Table 6. In-Amp Performance
Parameters VS = 3 V, 0 V VS = ±5 V
CMRR 74 dB 80 dB
Common-Mode Voltage Range −0.2 V to +2 V −5.2 V to +4 V
3 dB BW
G = 10 180 kHz 180 kHz
G = 100 18 kHz 18 kHz
tSETTLING
2 V Step 2 μs
5 V Step 5 μs
Noise @ f = 1 kHz
G = 10 270 nV/√Hz 270 nV/√Hz
G = 100 2.2 μV/√Hz 2.2 μV/√Hz
ISUPPLY (Total) 1.10 mA 1.15 mA
90
100
10
0%
........ .... .... ... ... .... .... .... ....
....
.... .... .... .... .... .... .... .... ....
1V
5µs
00874-048
Figure 48. Pulse Response of In-Amp to a 500 mV p-p Input Signal;
VS = 5 V, 0 V; Gain = 0
G = 100
G = 100G = 10 G = 10
1
2
34
5
6
7
+
–
+
–
00874-049
OHMTEK
PART # 1043
R5
9k
R4
1k
R3
1k
R2
9k
R1
90kR6
90k
V
REF
V+0.1µF
1/2
AD822
1/2
AD822
V
OUT
+
–
+
–
V
IN1
V
IN2
R
P
1k
R
P
1k
(G = 10) V
OUT
= (V
IN1
– V
IN2
)+V
REF
1+ R6
R4 + R5
()
(G = 100) V
OUT
= (V
IN1
– V
IN2
)+V
REF
R5 + R6
R4
1+
()
Figure 49. A Single-Supply Programmable Instrumentation Amplifier
LOW DROPOUT BIPOLAR BRIDGE DRIVER
The AD822 can be used for driving a 350 Ω Wheatstone bridge.
Figure 50 shows one-half of the AD822 being used to buffer the
AD589, a 1.235 V low power reference. The output of 4.5 V can
be used to drive an analog-to-digital converter (ADC) front end.
The other half of the AD822 is configured as a unity-gain inverter
and generates the other bridge input of −4.5 V. Resistor R1 and
Resistor R2 provide a constant current for bridge excitation. The
AD620 low power instrumentation amplifier is used to condition
the differential output voltage of the bridge. The gain of the AD620
is programmed using an external resistor RG and determined by
1
k9.49
G
R
G
+1.235V
49.9kR1
20
25.4k1%
10k1% 350
350
350350RG
AD589
10k1%
10k1%
R2
20
–4.5V
GND
+5V
–5V
1/2
AD822
+
–
+
–
1/2
AD822
8
3
2
1
+
+V
S
–V
S
VREF
V+
V–
V–
+
–
AD620
+
–
2
345
6
7
0.1F
0.1F
1F
1F
++
++
6
5
7
4
TO A/D CONVERTER
REFERENCE I NPUT
00874-051
Figure 50. Low Dropout Bipolar Bridge Driver
AD822
Rev. I | Page 21 of 24
OUTLINE DIMENSIONS
COM PLI ANT TO JE DE C S TANDARDS MS-001
CONT ROLLING DIM E NS IONS ARE IN INCHES; M IL L IMETER DI MENSIONS
(IN PARENTHESES) ARE RO UNDED- OF F INCH E QUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPROP RIATE FOR USE IN DESIGN.
CORNER LE ADS MAY BE CONFIG URED AS WHOL E O R HAL F LE ADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2. 92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 (2.54)
BSC
0.400 ( 10 .16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1 .52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 51. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 53. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD822
Rev. I | Page 22 of 24
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD822AN −40°C to +85°C 8-Lead PDIP N-8
AD822ANZ −40°C to +85°C 8-Lead PDIP N-8
AD822AR −40°C to +85°C 8-Lead SOIC_N R-8
AD822AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD822AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD822ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD822ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD822ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD822ARMZ −40°C to +85°C 8-Lead MSOP RM-8 #B4A
AD822ARMZ-REEL −40°C to +85°C 8-Lead MSOP RM-8 #B4A
AD822BR −40°C to +85°C 8-Lead SOIC_N R-8
AD822BR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD822BR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD822BRZ −40°C to +85°C 8-Lead SOIC_N R-8
AD822BRZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD822BRZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
1 Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked.
SPICE model is available at www.analog.com.
AD822
Rev. I | Page 23 of 24
NOTES
AD822
Rev. I | Page 24 of 24
NOTES
©1993–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00874-0-1/10(I)