SRI2K 13.56 MHz short-range contactless memory chip with 2048-bit EEPROM and anticollision functions Features ISO 14443-2 Type B air interface compliant ISO 14443-3 Type B frame format compliant 13.56 MHz carrier frequency 847 kHz subcarrier frequency 106 Kbit/second data transfer 8 bit Chip_ID based anticollision system 2 count-down binary counters with automated antitearing protection 64-bit Unique Identifier 2048-bit EEPROM with Write Protect feature Read_block and Write_block (32 bits) Internal tuning capacitor 1million erase/write cycles 40-year data retention Self-timed programming cycle 5 ms typical programming time September 2011 - Unsawn wafer - Bumped and sawn wafer Doc ID 15779 Rev 3 1/45 www.st.com 1 Contents SRI2K Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 3 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 3.2 4 AC1, AC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input data transfer from the reader to the SRI2K (request frame) . . . . . . . 9 3.1.1 Character transmission format for request frame . . . . . . . . . . . . . . . . . . 9 3.1.2 Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output data transfer from the SRI2K to the reader (answer frame) . . . . . 11 3.2.1 Character transmission format for answer frame . . . . . . . . . . . . . . . . . . 11 3.2.2 Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.3 Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Resettable OTP area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 32-bit binary counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 EEPROM area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 System area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4.1 OTP_Lock_Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4.2 Fixed Chip_ID (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 SRI2K operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 SRI2K states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/45 6.1 Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 Inventory state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 Deselected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 15779 Rev 3 SRI2K Contents 6.6 7 Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 8 Deactivated state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Description of an anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . 24 SRI2K commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 Initiate() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 Pcall16() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 Slot_marker(SN) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 Select(Chip_ID) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5 Completion() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6 Reset_to_inventory() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.7 Read_block(Addr) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.8 Write_block (Addr, Data) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.9 Get_UID() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10 Power-on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix A ISO-14443 Type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . 41 Appendix B SRI2K command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Doc ID 15779 Rev 3 3/45 List of tables SRI2K List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. 4/45 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRI2K memory mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Standard anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Command code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Doc ID 15779 Rev 3 SRI2K List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Die floor plan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10% ASK modulation of the received wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRI2K request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Wave transmitted using BPSK subcarrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Answer end of frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Resettable OTP area (addresses 0 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write_block update in Standard mode (binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write_block update in Reload mode (binary format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Binary counter (addresses 5 to 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Countdown example (binary format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 EEPROM (addresses 7 to 63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 State transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SRI2K Chip_ID description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Example of an anticollision sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Initiate frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pcall16 request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pcall16 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pcall16 frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Slot_marker request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Slot_marker response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Slot_marker frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 29 Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Select response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Select frame exchange between reader and SRI2K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Completion request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Completion response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Completion frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset_to_inventory request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset_to_inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset_to_inventory frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . 32 Read_block request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read_block response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read_block frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 33 Write_block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Write_block response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Write_block frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 35 Get_UID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Get_UID response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Doc ID 15779 Rev 3 5/45 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. 6/45 SRI2K 64-bit unique identifier of the SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Get_UID frame exchange between reader and SRI2K. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SRI2K synchronous timing, transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Initiate frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pcall16 frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Slot_marker frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 42 Select frame exchange between reader and SRI2K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Completion frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reset_to_inventory frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . 43 Read_block frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 43 Write_block frame exchange between reader and SRI2K . . . . . . . . . . . . . . . . . . . . . . . . . 43 Get_UID frame exchange between reader and SRI2K. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Doc ID 15779 Rev 3 SRI2K 1 Description Description The SRI2K is a contactless memory, powered by an externally transmitted radio wave. It contains a 2048-bit user EEPROM. The memory is organized as 64 blocks of 32 bits. The SRI2K is accessed via the 13.56 MHz carrier. Incoming data are demodulated and decoded from the received amplitude shift keying (ASK) modulation signal and outgoing data are generated by load variation using bit phase shift keying (BPSK) coding of a 847 kHz subcarrier. The received ASK wave is 10% modulated. The data transfer rate between the SRI2K and the reader is 106 kbit/s in both reception and emission modes. The SRI2K follows the ISO 14443 part 2 type B recommendation for the radio-frequency power and signal interface. Figure 1. Logic diagram SRI2K Power Supply Regulator 2 Kbit User EEPROM AC1 ASK Demodulator BPSK Load Modulator AC0 AI15575 The SRI2K is specifically designed for short range applications that need re-usable products. The SRI2K includes an anticollision mechanism that allows it to detect and select tags present at the same time within range of the reader. The anticollision is based on a probabilistic scanning method using slot markers. Using the STMicroelectronics single chip coupler, CRX14, it is easy to design a reader and build a contactless system. Table 1. Signal names Signal names Description AC1 Antenna coil AC0 Antenna coil Doc ID 15779 Rev 3 7/45 Signal description SRI2K The SRI2K contactless EEPROM can be randomly read and written in block mode (each block containing 32 bits). The instruction set includes the following nine commands: Read_block Write_block Initiate Pcall16 Slot_marker Select Completion Reset_to_inventory Get_UID The SRI2K memory is organized in three areas, as described in Figure 3. The first area is a resettable OTP (one time programmable) area in which bits can only be switched from 1 to 0. Using a special command, it is possible to erase all bits of this area to 1. The second area provides two 32-bit binary counters which can only be decremented from FFFF FFFFh to 0000 0000h, and gives a capacity of 4,294,967,296 units per counter. The last area is the EEPROM memory. It is accessible by block of 32 bits and includes an auto-erase cycle during each Write_block command. Figure 2. Die floor plan AC0 AC1 AI09055 2 Signal description 2.1 AC1, AC0 The pads for the Antenna Coil. AC1 and AC0 must be directly bonded to the antenna. 8/45 Doc ID 15779 Rev 3 SRI2K Data transfer 3 Data transfer 3.1 Input data transfer from the reader to the SRI2K (request frame) The reader must generate a 13.56 MHz sinusoidal carrier frequency at its antenna, with enough energy to "remote-power" the memory. The energy received at the SRI2K's antenna is transformed into a supply voltage by a regulator, and into data bits by the ASK demodulator. For the SRI2K to decode correctly the information it receives, the reader must 10% amplitude-modulate the 13.56 MHz wave before sending it to the SRI2K. This is represented in Figure 3. The data transfer rate is 106 Kbits/s. Figure 3. 10% ASK modulation of the received wave DATA BIT TO TRANSMIT TO THE SRI2K 10% ASK MODULATION OF THE 13.56MHz WAVE, GENERATED BY THE READER Transfer time for one data bit is 1/106 kHz AI15576 3.1.1 Character transmission format for request frame The SRI2K transmits and receives data bytes as 10-bit characters, with the least significant bit (b0) transmitted first, as shown in Figure 4. Each bit duration, an ETU (elementary time unit), is equal to 9.44 s (1/106 kHz). These characters, framed by a start of frame (SOF) and an end of frame (EOF), are put together to form a command frame as shown in Figure 10. A frame includes an SOF, commands, addresses, data, a CRC and an EOF as defined in the ISO 14443-3 Type B Standard. If an error is detected during data transfer, the SRI2K does not execute the command, but it does not generate an error frame. Figure 4. SRI2K request frame character format b0 1 ETU Start "0" b1 LSb b2 b3 b4 b5 b6 Information Byte b7 b8 b9 MSb Stop "1" ai07664 Doc ID 15779 Rev 3 9/45 Data transfer SRI2K Table 2. 3.1.2 Bit description Bit Description Value b0 Start bit used to synchronize the transmission b0 = 0 b1 to b8 Information byte (command, address or data) The information byte is sent with the least significant bit first b9 Stop bit used to indicate the end of a character b9 = 1 Request start of frame The SOF described in Figure 5 is composed of: one falling edge, followed by 10 ETUs at logic-0, followed by a single rising edge, followed by at least 2 ETUs (and at most 3) at logic-1. Figure 5. ETU Request start of frame b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 0 0 0 0 0 0 0 0 0 0 1 1 ai07665 3.1.3 Request end of frame The EOF shown in Figure 6 is composed of: one falling edge, followed by 10 ETUs at logic-0, followed by a single rising edge. Figure 6. ETU Request end of frame b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 0 0 0 0 0 0 0 0 0 0 ai07666 10/45 Doc ID 15779 Rev 3 SRI2K 3.2 Data transfer Output data transfer from the SRI2K to the reader (answer frame) The data bits issued by the SRI2K use backscattering. Backscattering is obtained by modifying the SRI2K current consumption at the antenna (load modulation). The load modulation causes a variation at the reader antenna by inductive coupling. With appropriate detector circuitry, the reader is able to pick up information from the SRI2K. To improve loadmodulation detection, data is transmitted using a BPSK encoded, 847 kHz subcarrier frequency s as shown in Figure 7, and as specified in the ISO 14443-2 Type B Standard. Figure 7. Wave transmitted using BPSK subcarrier modulation Data Bit to be Transmitted to the Reader Or 847kHz BPSK Modulation Generated by the SRI2K BPSK Modulation at 847kHz During a One-bit Data Transfer Time (1/106kHz) 3.2.1 ai15580 Character transmission format for answer frame The character format is the same as for input data transfer (Figure 4). The transmitted frames are made up of an SOF, data, a CRC and an EOF (Figure 10). As with an input data transfer, if an error occurs, the reader does not issue an error code to the SRI2K, but it should be able to detect it and manage the situation. The data transfer rate is 106 Kbits/second. 3.2.2 Answer start of frame The SOF described in Figure 8 is composed of: followed by 10 ETUs at logic-0 followed by 2 ETUs at logic-1 Figure 8. ETU Answer start of frame b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 0 0 0 0 0 0 0 0 0 0 1 1 ai07665 Doc ID 15779 Rev 3 11/45 Data transfer 3.2.3 SRI2K Answer end of frame The EOF shown in Figure 9 is composed of: Figure 9. followed by 10 ETUs at logic-0, followed by 2 ETUs at logic-1. Answer end of frame ETU b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 0 0 0 0 0 0 0 0 0 0 1 1 ai07665 3.3 Transmission frame Between the request data transfer and the answer data transfer, all ASK and BPSK modulations are suspended for a minimum time of t0 = 128/S. This delay allows the reader to switch from Transmission to Reception mode. It is repeated after each frame. After t0, the 13.5 6MHz carrier frequency is modulated by the SRI2K at 847 kHz for a period of t1 = 128/S to allow the reader to synchronize. After t1, the first phase transition generated by the SRI2K forms the start bit (`0') of the answer SOF. After the falling edge of the answer EOF, the reader waits a minimum time, t2, before sending a new request frame to the SRI2K. Figure 10. Example of a complete transmission frame Sent by the Reader SOF 12 bits Cmd Data CRC CRC EOF 10 bits 10 bits 10 bits 10 bits 10 bits at 106kb/s SOF fs=847.5kHz t DR Sent by the SRI2K SOF Sync t0 t1 128/fs 128/fs 12 bits Data CRC CRC EOF 10 bits 10 bits 10 bits 12 bits t2 Input data transfer using ASK Output data transfer using BPSK AI15577 12/45 Doc ID 15779 Rev 3 SRI2K 3.4 Data transfer CRC The 16-bit CRC used by the SRI2K is generated in compliance with the ISO14443 Type B recommendation. For further information, please see Appendix A. The initial register contents are all 1s: FFFFh. The two-byte CRC is present in every request and in every answer frame, before the EOF. The CRC is calculated on all the bytes between SOF (not included) and the CRC field. Upon reception of a request from a reader, the SRI2K verifies that the CRC value is valid. If it is invalid, the SRI2K discards the frame and does not answer the reader. Upon reception of an answer from the SRI2K, the reader should verify the validity of the CRC. In case of error, the actions to be taken are the reader designer's responsibility. The CRC is transmitted with the least significant byte first and each byte is transmitted with the least significant bit first. Figure 11. CRC transmission rules LSByte MSByte LSbit MSbit LSbit CRC 16 (8 bits) MSbit CRC 16 (8 bits) ai07667 Doc ID 15779 Rev 3 13/45 Memory mapping 4 SRI2K Memory mapping The SRI2K is organized as 64 blocks of 32 bits as shown in Table 3. All blocks are accessible by the Read_block command. Depending on the write access, they can be updated by the Write_block command. A Write_block updates all the 32 bits of the block. Table 3. Block Addr SRI2K memory mapping MSB b31 32-bit block b24 b23 b16 b15 0 32 bits Boolean area 1 32 bits Boolean area 2 32 bits Boolean area 3 32 bits Boolean area 4 32 bits Boolean area 5 32 bits binary counter 6 32 bits binary counter 7 User area 8 User area 9 User area 10 User area 11 User area 12 User area 13 User area 14 User area 15 User area 16 User area ... User area 63 User area 255 OTP_Lock_Reg ST Reserved LSB b8 b7 b0 Description Resettable OTP bits Count down counter Lockable EEPROM EEPROM Fixed Chip_ID (Option) System OTP bits UID0 64 bits UID area UID1 14/45 Doc ID 15779 Rev 3 ROM SRI2K 4.1 Memory mapping Resettable OTP area In this area contains five individual 32-bit Boolean words (see Figure 12 for a map of the area). A Write_block command will not erase the previous contents of the block as the write cycle is not preceded by an auto-erase cycle. This feature can be used to reset selected bits from 1 to 0. All bits previously at 0 remain unchanged. When the 32 bits of a block are all at 0, the block is empty, and cannot be updated any more. See Figure 13 and Figure 14 for examples of the result of the Write_block command in the resettable OTP area. Figure 12. Resettable OTP area (addresses 0 to 4) Block address MSb b31 32-bit block b16 b15 b24 b23 0 32-bit Boolean area 1 32-bit Boolean area 2 32-bit Boolean area 3 32-bit Boolean area 4 32-bit Boolean area LSb b0 b8 b7 Description Resettable OTP bit ai07657b Figure 13. Write_block update in Standard mode (binary format) b31 b0 Previous data stored in block 1 ... 1 1 0 1 0 1 1 1 1 1 0 1 1 Data to be written 1 ... 1 0 0 1 0 1 1 0 0 1 1 1 1 New data stored in block 1 ... 1 0 0 1 0 1 1 0 0 1 0 1 1 ai07658 The five 32-bit blocks making up the resettable OTP area can be erased in one go by adding an auto-erase cycle to the Write_block command. An auto-erase cycle is added each time the SRI2K detects a Reload command. The Reload command is implemented through a specific update of the 32-bit binary counter located at block address 6 (see "Section 4.2: 32bit binary counters" for details). Figure 14. Write_block update in Reload mode (binary format) b31 b0 Previous data stored in block 1 ... 1 1 0 1 0 1 1 1 1 1 0 1 1 Data to be written 1 ... 1 1 1 1 0 1 1 0 0 1 1 1 1 New data stored in block 1 ... 1 1 1 1 0 1 1 0 0 1 1 1 1 ai07659 Doc ID 15779 Rev 3 15/45 Memory mapping 4.2 SRI2K 32-bit binary counters The two 32-bit binary counters located at block addresses 5 and 6, respectively, are used to count down from 232 (4096 million) to 0. The SRI2K uses dedicated logic that only allows the update of a counter if the new value is lower than the previous one. This feature allows the application to count down by steps of 1 or more. The initial value in Counter 5 is FFFF FFFEh and is FFFF FFFFh in Counter 6. When the value displayed is 0000 0000h, the counter is empty and cannot be reloaded. The counter is updated by issuing the Write_block command to block address 5 or 6, depending on which counter is to be updated. The Write_block command writes the new 32-bit value to the counter block address. Figure 16 shows examples of how the counters operate. The counter programming cycles are protected by automated antitearing logic. This function allows the counter value to be protected in case of power down within the programming cycle. In case of power down, the counter value is not updated and the previous value continues to be stored. Figure 15. Binary counter (addresses 5 to 6) Block Address MSb b31 32-bit block b16 b15 b24 b23 LSb b0 b8 b7 5 32-bit binary counter 6 32-bit binary counter Description Count down Counter ai07660b Figure 16. Countdown example (binary format) b31 b0 Initial data 1 ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1-unit decrement 1 ... 1 1 1 1 1 1 1 1 1 1 1 1 0 1-unit decrement 1 ... 1 1 1 1 1 1 1 1 1 1 1 0 1 1-unit decrement 1 ... 1 1 1 1 1 1 1 1 1 1 1 0 0 8-unit decrement 1 ... 1 1 1 1 1 1 1 1 1 0 1 0 0 Increment not allowed 1 ... 1 1 1 1 1 1 1 1 1 1 0 0 0 ai07661 The counter with block address 6 controls the Reload command used to reset the resettable OTP area (addresses 0 to 4). Bits b31 to b21 act as an 11-bit Reload counter; whenever one of these 11 bits is updated, the SRI2K detects the change and adds an Erase cycle to the Write_block command for locations 0 to 4 (see the "Resettable OTP area" paragraph). The Erase cycle remains active until a Power-off or a Select command is issued. The SRI2K's resettable OTP area can be reloaded up to 2 047 times (211-1). 16/45 Doc ID 15779 Rev 3 SRI2K 4.3 Memory mapping EEPROM area The 57 blocks between addresses 7 and 63 are EEPROM blocks of 32 bits each (228 bytes in total). (See Figure 17 for a map of the area.) These blocks can be accessed using the Read_block and Write_block commands. The Write_block command for the EEPROM area always includes an auto-erase cycle prior to the write cycle. Blocks 7 to 15 can be write-protected. Write access is controlled by the 8 bits of the OTP_Lock_Reg located at block address 255 (see "OTP_Lock_Reg" for details). Once protected, these blocks (7 to 15) cannot be unprotected. Figure 17. EEPROM (addresses 7 to 63) Block Block address Address MSb MSb b31 b31 b24 b23 b24 b23 32-bit block 32-bit Block b16 b15 b16 b15 7 7 User area User Area 8 8 User area User Area 9 9 User area User Area 1010 User area User Area 1111 User area User Area 1212 User area User Area 1313 User area User Area 1414 User area User Area 1515 User area User Area 1616 User area User Area ... ... User area User Area 12763 User area User Area b8b8 b7b7 LSb LSb b0b0 Description Description Lockable Lockable EEPROM EEPROM EEPROM EEPROM Ai07662c Ai15578 4.4 System area This area is used to modify the settings of the SRI2K. It contains 3 registers: OTP_Lock_Reg, Fixed Chip_ID and ST Reserved. See Figure 18 for a map of this area. A Write_block command in this area will not erase the previous contents. Selected bits can thus be set from 1 to 0. All bits previously at 0 remain unchanged. Once all the 32 bits of a block are at 0, the block is empty and cannot be updated any more. Doc ID 15779 Rev 3 17/45 Memory mapping SRI2K Figure 18. System area Block address 255 MSb b31 32-bit block b24 b23 OTP_Lock_Reg b16 b15 LSb b8 b7 ST reserved b0 Fixed Chip_ID (Option) Description OTP ai07663b 4.4.1 OTP_Lock_Reg The 8 bits, b31 to b24, of the System area (block address 255) are used as OTP_Lock_Reg bits in the SRI2K. They control the write access to the 9 EEPROM blocks with addresses 7 to 15 as follows: When b24 is at 0, blocks 7 and 8 are write-protected When b25 is at 0, block 9 is write-protected When b26 is at 0, block 10 is write-protected When b27 is at 0, block 11 is write-protected When b28 is at 0, block 12 is write-protected When b29 is at 0, block 13 is write-protected When b30 is at 0, block 14 is write-protected When b31 is at 0, block 15 is write-protected. The OTP_Lock_Reg bits cannot be erased. Once write-protected, EEPROM blocks behave like ROM blocks and cannot be unprotected. 4.4.2 Fixed Chip_ID (Option) The SRI2K is provided with an anticollision feature based on a random 8-bit Chip_ID. Prior to selecting an SRI2K, an anticollision sequence has to be run to search for the Chip_ID of the SRI2K. This is a very flexible feature, however the searching loop requires time to run. For some applications, much time could be saved by knowing the value of the SRI2K Chip_ID beforehand, so that the SRI2K can be identified and selected directly without having to run an anticollision sequence. This is why the SRI2K was designed with an optional mask setting used to program a fixed 8-bit Chip_ID to bits b7 to b0 of the system area. When the fixed Chip_ID option is used, the random Chip_ID function is disabled. 18/45 Doc ID 15779 Rev 3 SRI2K 5 SRI2K operation SRI2K operation All commands, data and CRC are transmitted to the SRI2K as 10-bit characters using ASK modulation. The start bit of the 10 bits, b0, is sent first. The command frame received by the SRI2K at the antenna is demodulated by the 10% ASK demodulator, and decoded by the internal logic. Prior to any operation, the SRI2K must have been selected by a Select command. Each frame transmitted to the SRI2K must start with a start of frame, followed by one or more data characters, two CRC bytes and the final end of frame. When an invalid frame is decoded by the SRI2K (wrong command or CRC error), the memory does not return any error code. When a valid frame is received, the SRI2K may have to return data to the reader. In this case, data is returned using BPSK encoding, in the form of 10-bit characters framed by an SOF and an EOF. The transfer is ended by the SRI2K sending the 2 CRC bytes and the EOF. Doc ID 15779 Rev 3 19/45 SRI2K states 6 SRI2K SRI2K states The SRI2K can be switched into different states. Depending on the current state of the SRI2K, its logic will only answer to specific commands. These states are mainly used during the anticollision sequence, to identify and to access the SRI2K in a very short time. The SRI2K provides 6 different states, as described in the following paragraphs and in Figure 19. 6.1 Power-off state The SRI2K is in Power-off state when the electromagnetic field around the tag is not strong enough. In this state, the SRI2K does not respond to any command. 6.2 Ready state When the electromagnetic field is strong enough, the SRI2K enters the Ready state. After Power-up, the Chip_ID is initialized with a random value. The whole logic is reset and remains in this state until an Initiate() command is issued. Any other command will be ignored by the SRI2K. 6.3 Inventory state The SRI2K switches from the Ready to the Inventory state after an Initiate() command has been issued. In Inventory state, the SRI2K will respond to any anticollision commands: Initiate(), Pcall16() and Slot_marker(), and then remain in the Inventory state. It will switch to the Selected state after a Select(Chip_ID) command is issued, if the Chip_ID in the command matches its own. If not, it will remain in Inventory state. 6.4 Selected state In Selected state, the SRI2K is active and responds to all Read_block(), Write_block() and Get_UID() commands. When an SRI2K has entered the Selected state, it no longer responds to anticollision commands. So that the reader can access another tag, the SRI2K can be switched to the Deselected state by sending a Select(Chip_ID2) with a Chip_ID that does not match its own, or it can be placed in Deactivated state by issuing a Completion() command. Only one SRI2K can be in Selected state at a time. 6.5 Deselected state Once the SRI2K is in Deselected state, only a Select(Chip_ID) command with a Chip_ID matching its own can switch it back to Selected state. All other commands are ignored. 6.6 Deactivated state When in this state, the SRI2K can only be turned off. All commands are ignored. 20/45 Doc ID 15779 Rev 3 SRI2K SRI2K states Figure 19. State transition diagram Power-off Out of field On field Ready Chip_ID8bits = RND Initiate() Out of field Inventory Out of field Initiate() or Pcall16() or Slot_marker(SN) or Select(wrong Chip_ID) Select(Chip_ID) Reset_to_inventory() Out of field Select(Chip_ID) Selected Deselected Completion() Out of field Deactivated Select( Chip_ID) Select(Chip_ID) Read_block() Write_block() Get_UID() AI10879b Doc ID 15779 Rev 3 21/45 Anticollision 7 SRI2K Anticollision The SRI2K provides an anticollision mechanism that searches for the Chip_ID of each device that is present in the reader field range. When known, the Chip_ID is used to select an SRI2K individually, and access its memory. The anticollision sequence is managed by the reader through a set of commands described in Section 5: SRI2K operation: Initiate() Pcall16() Slot_marker(). The reader is the master of the communication with one or more SRI2K device(s). It initiates the tag communication activity by issuing an Initiate(), Pcall16() or Slot_marker() command to prompt the SRI2K to answer. During the anticollision sequence, it might happen that two or more SRI2K devices respond simultaneously, so causing a collision. The command set allows the reader to handle the sequence, to separate SRI2K transmissions into different time slots. Once the anticollision sequence has completed, SRI2K communication is fully under the control of the reader, allowing only one SRI2K to transmit at a time. The Anticollision scheme is based on the definition of time slots during which the SRI2K devices are invited to answer with minimum identification data: the Chip_ID. The number of slots is fixed at 16 for the Pcall16() command. For the Initiate() command, there is no slot and the SRI2K answers after the command is issued. SRI2K devices are allowed to answer only once during the anticollision sequence. Consequently, even if there are several SRI2K devices present in the reader field, there will probably be a slot in which only one SRI2K answers, allowing the reader to capture its Chip_ID. Using the Chip_ID, the reader can then establish a communication channel with the identified SRI2K. The purpose of the anticollision sequence is to allow the reader to select one SRI2K at a time. The SRI2K is given an 8-bit Chip_ID value used by the reader to select only one among up to 256 tags present within its field range. The Chip_ID is initialized with a random value during the Ready state, or after an Initiate() command in the Inventory state. The four least significant bits (b0 to b3) of the Chip_ID are also known as the Chip_slot_number. This 4-bit value is used by the Pcall16() and Slot_marker() commands during the anticollision sequence in the Inventory state. Figure 20. SRI2K Chip_ID description b7 b6 b5 b4 b3 b2 b1 b0 8-bit Chip_ID b0 to b3: Chip_slot_number ai07668b Each time the SRI2K receives a Pcall16() command, the Chip_slot_number is given a new 4-bit random value. If the new value is 0000b, the SRI2K returns its whole 8-bit Chip_ID in its answer to the Pcall16() command. The Pcall16() command is also used to define the slot number 0 of the anticollision sequence. When the SRI2K receives the Slot_marker (SN) command, it compares its Chip_slot_number with the Slot_number parameter (SN). If they match, the SRI2K returns its Chip_ID as a response to the command. If they do not, the SRI2K does not answer. The Slot_marker(SN) command is used to define all the anticollision slot numbers from 1 to 15. 22/45 Doc ID 15779 Rev 3 S O F Doc ID 15779 Rev 3 Time Comment Timing SRI devices Reader PCALL 16 Request E O F No collision t2 E O F <-> Answer Chip_ID X0h <-> S O F > t0 + t1 < Slot 0 S O F Slot Marker (1) E O F t0 + t1 <-> < Answer Chip_ID X1h Collision S Answer O Chip_ID F X1h S O F Slot 1 E O F E O F t2 <-> > S O F Slot Marker (2) E O F t3 > No Answer < < Slot 2 > S O F ... ... Slot N E O F <-> t0 + t1 E O F t2 Slot Marker (15) <-> S O F < S O F No collision Answer Chip_ID XFh Slot 15 > t2 <-> Ai10883 E O F > SRI2K Anticollision Figure 21. Description of a possible anticollision sequence 1. The value X in the answer Chip_ID means a random hexadecimal character from 0 to F. 23/45 Anticollision 7.1 SRI2K Description of an anticollision sequence The anticollision sequence is initiated by the Initiate() command which triggers all the SRI2K devices that are present in the reader field range, and that are in Inventory state. Only SRI2K devices in Inventory state will respond to the Pcall16() and Slot_marker(SN) anticollision commands. A new SRI2K introduced in the field range during the anticollision sequence will not be taken into account as it will not respond to the Pcall16() or Slot_marker(SN) command (Ready state). To be considered during the anticollision sequence, it must have received the Initiate() command and entered the Inventory state. Table 4 shows the elements of a standard anticollision sequence. (See Figure 22 for an example.) Table 4. Standard anticollision sequence Step 1 Init: Send Initiate(). - If no answer is detected, go to step1. - If only 1 answer is detected, select and access the SRI2K. After accessing the SRI2K, deselect the tag and go to step1. - If a collision (many answers) is detected, go to step2. Step 2 Slot 0 Send Pcall16(). - If no answer or collision is detected, go to step3. - If 1 answer is detected, store the Chip_ID, Send Select() and go to step3. Step 3 Slot 1 Send Slot_marker(1). - If no answer or collision is detected, go to step4. - If 1 answer is detected, store the Chip_ID, Send Select() and go to step4. Step 4 Slot 2 Send Slot_marker(2). - If no answer or collision is detected, go to step5. - If 1 answer is detected, store the Chip_ID, Send Select() and go to step5. Step N Send Slot_marker(3 up to 14)... Slop N - If no answer or collision is detected, go to stepN+1. - If 1 answer is detected, store the Chip_ID, Send Select() and go to stepN+1. Send Slot_marker(15). Step 17 Slot 15 - If no answer or collision is detected, go to step18. - If 1 answer is detected, store the Chip_ID, Send Select() and go to step18. Step 18 All the slots have been generated and the Chip_ID values should be stored into the reader memory. Issue the Select(Chip_ID) command and access each identified SRI2K one by one. After accessing each SRI2K, switch them into Deselected or Deactivated state, depending on the application needs. - If collisions were detected between Step2 and Step17, go to Step2. - If no collision was detected between Step2 and Step17, go to Step1. After each Slot_marker() command, there may be several, one or no answers from the SRI2K devices. The reader must handle all the cases and store all the Chip_IDs, correctly decoded. At the end of the anticollision sequence, after Slot_marker(15), the reader can start working with one SRI2K by issuing a Select() command containing the desired Chip_ID. If a collision is detected during the anticollision sequence, the reader has to generate a new sequence in order to identify all unidentified SRI2K devices in the field. The anticollision sequence can stop when all SRI2K devices have been identified. 24/45 Doc ID 15779 Rev 3 SRI2K Anticollision Figure 22. Example of an anticollision sequence Command Tag 1 Tag 2 Tag 3 Tag 4 Tag 5 Tag 6 Tag 7 Tag 8 Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID Chip_ID 30h Each tag gets a random Chip_ID Each tag get a new random Chip_ID. All tags answer: collisions All CHIP_SLOT_NUMBERs get a new random value Slot0: only one answer 30h Tag3 is identified READY State 28h 75h 40h 01h 02h FEh A9h 7Ch INITIATE () 40h 13h 3Fh 4Ah 50h 48h 52h 7Ch 45h 12h 30h 43h 55h 43h 53h 73h PCALL16() SELECT(30h) Comments SLOT_MARKER(1) Slot1: no answer SLOT_MARKER(2) 12h Slot2: only one answer SELECT(12h) 12h Tag2 is identified 43h SLOT_MARKER(3) 43h 53h 73h SLOT_MARKER(4) SLOT_MARKER(5) Slot3: collisions Slot4: no answer 45h 55h Slot5: collisions SLOT_MARKER(6) Slot6: no answer SLOT_MARKER(N) SlotN: no answer SLOT_MARKER(F) PCALL16() 40h 41h 53h 42h 40h 50h 74h 50h SlotF: no answer All CHIP_SLOT_NUMBERs get a new random value Slot0: collisions SLOT_MARKER(1) 41h Slot1: only one answer SELECT(41h) 41h Tag4 is identified SLOT_MARKER(2) 42h Slot2: only one answer SELECT(42h) 42h Tag6 is identified SLOT_MARKER(3) 53h Slot3: only one answer SELECT(53h) 53h Tag5 is identified SLOT_MARKER(4) 74h Slot4: only one answer SELECT(74h) 74h Tag8 is identified SLOT_MARKER(N) SlotN: no answer PCALL16() All CHIP_SLOT_NUMBERs get a new random value Slot0: only one answer 41h 50h 50h SELECT(50h) 50h Tag7 is identified 41h Slot1: only one answer but already found for tag4 43h SlotN: no answer All CHIP_SLOT_NUMBERs get a new random value Slot0: only one answer SLOT_MARKER(3) 43h Slot3: only one answer SELECT(43h) 43h Tag1 is identified SLOT_MARKER(1) SLOT_MARKER(N) PCALL16() All tags are identified Doc ID 15779 Rev 3 ai07669 25/45 SRI2K commands 8 SRI2K SRI2K commands See the paragraphs below for a detailed description of the commands available on the SRI2K. The commands and their hexadecimal codes are summarized in Table 5. A brief is given in Appendix B. Table 5. Command code Hexadecimal code 26/45 Command 06h-00h Initiate() 06h-04h Pcall16() x6h Slot_marker (SN) 08h Read_block(Addr) 09h Write_block(Addr, Data) 0Bh Get_UID() 0Ch Reset_to_inventory 0Eh Select(Chip_ID) 0Fh Completion() Doc ID 15779 Rev 3 SRI2K 8.1 SRI2K commands Initiate() command Command code = 06h - 00h Initiate() is used to initiate the anticollision sequence of the SRI2K. On receiving the Initiate() command, all SRI2K devices in Ready state switch to Inventory state, set a new 8-bit Chip_ID random value, and return their Chip_ID value. This command is useful when only one SRI2K in Ready state is present in the reader field range. It speeds up the Chip_ID search process. The Chip_slot_number is not used during Initiate() command access. Figure 23. Initiate request format SOF Initiate 06h CRCL 00h CRCH 8 bits EOF 8 bits AI07670b Request parameter: No parameter Figure 24. Initiate response format SOF Chip_ID CRCL 8 bits 8 bits CRCH EOF 8 bits AI07671 Response parameter: Chip_ID of the SRI2K Figure 25. Initiate frame exchange between reader and SRI2K Reader SRI2K SOF 06h 00h CRCL CRCH EOF <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15581 Doc ID 15779 Rev 3 27/45 SRI2K commands 8.2 SRI2K Pcall16() command Command code = 06h - 04h The SRI2K must be in Inventory state to interpret the Pcall16() command. On receiving the Pcall16() command, the SRI2K first generates a new random Chip_slot_number value (in the 4 least significant bits of the Chip_ID). Chip_slot_number can take on a value between 0 an 15 (1111b). The value is retained until a new Pcall16() or Initiate() command is issued, or until the SRI2K is powered off. The new Chip_slot_number value is then compared with the value 0000b. If they match, the SRI2K returns its Chip_ID value. If not, the SRI2K does not send any response. The Pcall16() command, used together with the Slot_marker() command, allows the reader to search for all the Chip_IDs when there are more than one SRI2K device in Inventory state present in the reader field range. Figure 26. Pcall16 request format SOF Pcall16 06h CRCH CRCL 04h 8 bits EOF 8 bits AI07673b Request parameter: No parameter Figure 27. Pcall16 response format SOF Chip_ID CRCL 8 bits 8 bits CRCH EOF 8 bits AI07671 Response parameter: Chip_ID of the SRI2K Figure 28. Pcall16 frame exchange between reader and SRI2K Reader SRI2K SOF 06h 04h CRCL CRCH EOF <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15582 28/45 Doc ID 15779 Rev 3 SRI2K 8.3 SRI2K commands Slot_marker(SN) command Command code = x6h The SRI2K must be in Inventory state to interpret the Slot_marker(SN) command. The Slot_marker byte code is divided into two parts: b3 to b0: 4-bit command code with fixed value 6. b7 to b4: 4 bits known as the Slot_number (SN). They assume a value between 1 and 15. The value 0 is reserved by the Pcall16() command. On receiving the Slot_marker() command, the SRI2K compares its Chip_slot_number value with the Slot_number value given in the command code. If they match, the SRI2K returns its Chip_ID value. If not, the SRI2K does not send any response. The Slot_marker() command, used together with the Pcall16() command, allows the reader to search for all the Chip_IDs when there are more than one SRI2K device in Inventory state present in the reader field range. Figure 29. Slot_marker request format SOF Slot_marker CRCL X6h 8 bits CRCH EOF 8 bits AI07675b Request parameter: x: Slot number Figure 30. Slot_marker response format SOF Chip_ID CRCL 8 bits 8 bits CRCH EOF 8 bits AI07671 Response parameters: Chip_ID of the SRI2K Figure 31. Slot_marker frame exchange between reader and SRI2K Reader SRI2K SOF X6h CRCL CRCH EOF <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15583 Doc ID 15779 Rev 3 29/45 SRI2K commands 8.4 SRI2K Select(Chip_ID) command Command code = 0Eh The Select() command allows the SRI2K to enter the Selected state. Until this command is issued, the SRI2K will not accept any other command, except for Initiate(), Pcall16() and Slot_marker(). The Select() command returns the 8 bits of the Chip_ID value. An SRI2K in Selected state, that receives a Select() command with a Chip_ID that does not match its own is automatically switched to Deselected state. Figure 32. Select request format SOF Chip_ID Select 0Eh CRCL 8 bits CRCH 8 bits EOF 8 bits AI07677b Request parameter: 8-bit Chip_ID stored during the anticollision sequence Figure 33. Select response format SOF Chip_ID CRCL 8 bits 8 bits CRCH EOF 8 bits AI07671 Response parameters: Chip_ID of the selected tag. Must be equal to the transmitted Chip_ID Figure 34. Select frame exchange between reader and SRI2K Reader SOF 0Eh Chip_ID CRCL CRCH EOF SRI2K <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15584 30/45 Doc ID 15779 Rev 3 SRI2K 8.5 SRI2K commands Completion() command Command code = 0Fh On receiving the Completion() command, an SRI2K in Selected state switches to Deactivated state and stops decoding any new commands. The SRI2K is then locked in this state until a complete reset (tag out of the field range). A new SRI2K can thus be accessed through a Select() command without having to remove the previous one from the field. The Completion() command does not generate a response. All SRI2K devices not in Selected state ignore the Completion() command. Figure 35. Completion request format SOF Completion CRCL CRCH 8 bits 8 bits 0Fh EOF AI07679b Request parameters: No parameter Figure 36. Completion response format No response AI07680b Figure 37. Completion frame exchange between reader and SRI2K Reader SOF 0Fh CRCL CRCH EOF SRI2K No Response ai15585 Doc ID 15779 Rev 3 31/45 SRI2K commands 8.6 SRI2K Reset_to_inventory() command Command code = 0Ch On receiving the Reset_to_inventory() command, all SRI2K devices in Selected state revert to Inventory state. The concerned SRI2K devices are thus resubmitted to the anticollision sequence. This command is useful when two SRI2K devices with the same 8-bit Chip_ID happen to be in Selected state at the same time. Forcing them to go through the anticollision sequence again allows the reader to generates new Pcall16() commands and so, to set new random Chip_IDs. The Reset_to_inventory() command does not generate a response. All SRI2K devices that are not in Selected state ignore the Reset_to_inventory() command. Figure 38. Reset_to_inventory request format SOF Reset_to_inventory CRCL CRCH 0Ch 8 bits 8 bits EOF AI07682b Request parameter: No parameter Figure 39. Reset_to_inventory response format No response AI07680b Figure 40. Reset_to_inventory frame exchange between reader and SRI2K Reader SOF 0Ch CRCL CRCH EOF SRI2K No Response ai15586 32/45 Doc ID 15779 Rev 3 SRI2K 8.7 SRI2K commands Read_block(Addr) command Command code = 08h On receiving the Read_block command, the SRI2K reads the desired block and returns the 4 data bytes contained in the block. Data bytes are transmitted with the least significant byte first and each byte is transmitted with the least significant bit first. The address byte gives access to the 64 blocks of the SRI2K (addresses 0 to 63). Read_block commands issued with a block address from 64 to 127 will generate a nonsignificative answer. Read_block commands issued with a block address above 127 will not be interpreted and the SRI2K will not return any response, except for the System area located at address 255. The SRI2K must have received a Select() command and be switched to Selected state before any Read_block() command can be accepted. All Read_block() commands sent to the SRI2K before a Select() command is issued are ignored. Figure 41. Read_block request format SOF Address Read_block 08h 8 bIts CRCL 8 bits CRCH EOF 8 bits AI07684b Request parameter: Address: block addresses from 0 to 63, or 255 Figure 42. Read_block response format SOF Data 1 Data 2 Data 3 Data 4 CRCL CRCH 8 bIts 8 bIts 8 bIts 8 bIts 8 bits 8 bIts EOF AI07685b Response parameters: Data 1: Less significant data byte Data 2: Data byte Data 3: Data byte Data 4: Most significant data byte Figure 43. Read_block frame exchange between reader and SRI2K Reader SRI2K S O F 08h ADDR E CRCL CRCH O F S <-t0-><-t1-> O DATA DATA 2 1 F DATA 3 E DATA CRC CRC L H O 4 F ai15587 Doc ID 15779 Rev 3 33/45 SRI2K commands 8.8 SRI2K Write_block (Addr, Data) command Command code = 09h On receiving the Write_block command, the SRI2K writes the 4 bytes contained in the command to the addressed block, provided that the block is available and not writeprotected. Data bytes are transmitted with the least significant byte first, and each byte is transmitted with the least significant bit first. The address byte gives access to the 64 blocks of the SRI2K (addresses 0 to 63). Write_block commands issued with a block address above 63 will not be interpreted and the SRI2K will not return any response, except for the System area located at address 255. The result of the Write_block command is submitted to the addressed block. See the following Figures for a complete description of the Write_block command: Figure 12: Resettable OTP area (addresses 0 to 4). Figure 15: Binary counter (addresses 5 to 6). Figure 17: EEPROM (addresses 7 to 63). The Write_block command does not give rise to a response from the SRI2K. The reader must check after the programming time, tW, that the data was correctly programmed. The SRI2K must have received a Select() command and be switched to Selected state before any Write_block command can be accepted. All Write_block commands sent to the SRI2K before a Select() command is issued, are ignored. Figure 44. Write_block request format SOF Write_block 09h Address Data 1 Data 2 Data 3 Data 4 CRCL CRCH 8 bIts 8 bIts 8 bIts 8 bIts 8 bIts 8 bits 8 bIts EOF AI07687b Request parameters: Address: block addresses from 0 to 63, or 255 Data 1: Less significant data byte Data 2: Data byte Data 3: Data byte Data 4: Most significant data byte. Figure 45. Write_block response format No response AI07680b 34/45 Doc ID 15779 Rev 3 SRI2K SRI2K commands Figure 46. Write_block frame exchange between reader and SRI2K Reader SOF 09h ADDR DATA DATA 1 2 DATA 3 DATA CRC CRC EOF L H 4 No Response SRI2K ai15588 8.9 Get_UID() command Command code = 0Bh On receiving the Get_UID command, the SRI2K returns its 8 UID bytes. UID bytes are transmitted with the least significant byte first, and each byte is transmitted with the least significant bit first. The SRI2K must have received a Select() command and be switched to Selected state before any Get_UID() command can be accepted. All Get_UID() commands sent to the SRI2K before a Select() command is issued, are ignored. Figure 47. Get_UID request format SOF Get_UID CRCL CRCH 0Bh 8 bits 8 bits EOF AI07693b Request parameter: No parameter Figure 48. Get_UID response format SOF UID 0 UID 1 UID 2 UID 3 8 bits 8 bIts 8 bIts 8 bIts UID 4 8 bIts UID 5 8 bIts UID 6 8 bIts UID 7 8 bIts CRCL CRCH 8 bits 8 bIts EOF AI07694 Response parameters: UID 0: Less significant UID byte UID 1 to UID 6: UID bytes UID 7: Most significant UID byte. Doc ID 15779 Rev 3 35/45 SRI2K commands SRI2K Unique identifier (UID) Members of the SRI2K family are uniquely identified by a 64-bit unique identifier (UID). This is used for addressing each SRI2K device uniquely after the anticollision loop. The UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. It is a read-only code, and comprises (as summarized in Figure 49): an 8-bit prefix, with the most significant bits set to D0h an 8-bit IC manufacturer code (ISO/IEC 7816-6/AM1) set to 02h (for STMicroelectronics) a 6-bit IC code set to 00 1111b = 15d for SRI2K a 42-bit unique serial number Figure 49. 64-bit unique identifier of the SRI2K Most significant bits 63 55 47 41 D0h 02h 15d Least significant bits 0 Unique Serial Number ai15579 Figure 50. Get_UID frame exchange between reader and SRI2K Reader S E O 0Bh CRCL CRCH O F F SRI2K S E <-t0-><-t1-> O UID UID UID UID UID UID UID UID CRCL CRCH O 0 1 2 3 4 5 6 7 F F ai15589 8.10 Power-on state After power-on, the SRI2K is in the following state: 36/45 It is in the low-power state. It is in Ready state. It shows highest impedance with respect to the reader antenna field. It will not respond to any command except Initiate(). Doc ID 15779 Rev 3 SRI2K 9 Maximum rating Maximum rating Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute maximum ratings Symbol Parameter Wafer (kept in its antistatic bag) TSTG, tSTG Storage conditions Min. Max. Unit 15 25 C 23 months Supply current on AC0 / AC1 -20 20 mA VMAX Input voltage on AC0 / AC1 -7 7 V Electrostatic discharge voltage(1) Machine model -100 100 V VESD Human body model -1000 1000 V ICC 1. Mil. Std. 883 - Method 3015 Doc ID 15779 Rev 3 37/45 DC and ac parameters 10 SRI2K DC and ac parameters Table 7. Operating conditions Symbol TA Table 8. Symbol Parameter Min. Max. Unit -20 85 C Ambient operating temperature DC characteristics Parameter Condition Min Typ Unit 3.5 V VCC Regulated voltage ICC Supply current (active in read) VCC = 3.0 V 100 A ICC Supply current (active in write) VCC = 3.0 V 250 A VRET Retromodulation induced voltage ISO 10373-6 CTUN Internal tuning capacitor Table 9. Symbol fCC 2.5 Max 20 13.56 MHz 64 pF AC characteristics(1) Parameter Condition External RF signal frequency MICARRIER Carrier modulation index MI=(A-B)/(A+B) tRFR, tRFF 10% Rise and Fall times tRFSBL mV Minimum pulse width for Start bit tJIT ASK modulation data jitter tMIN CD Minimum time from carrier generation to first data Min Max Unit 13.553 13.567 MHz 8 14 % 0.8 2.5 s ETU = 128/fCC Coupler to SRI2K 9.44 -2 s +2 5 ms fS Subcarrier frequency fCC/16 847.5 kHz t0 Antenna reversal delay 128/fS 151 s t1 Synchronization delay 128/fS 151 s t2 Answer to new request delay 14 ETU 132 0 tDR Time between request characters Coupler to SRI2K tDA Time between answer characters SRI2K to coupler tW Programming time for write s 57 0 s s With no auto-erase cycle (OTP) 3 ms With auto-erase cycle (EEPROM) 5 ms Binary counter decrement 7 ms 1. All timing measurements were performed on a reference antenna with the following characteristics: External size: 75 mm x 48 mm Number of turns: 3 Width of conductor: 1 mm Space between 2 conductors: 0.4 mm Value of the coil: 1.4 H Tuning Frequency: 14.4 MHz. 38/45 s Doc ID 15779 Rev 3 SRI2K DC and ac parameters Figure 51. SRI2K synchronous timing, transmit and receive ASK Modulated signal from the Reader to the Contactless device A tRFF B tRFR cc tRFSBL tMIN CD FRAME Transmission between the reader and the contactless device tDR 1 tDR 0 DATA 1 EOF FRAME Transmitted by the reader in ASK 847KHz FRAME Transmitted by the SRI2K in BPSK t0 SOF 11 0 t1 tDA DATA 10 DATA 10 tDA Data jitter on FRAME Transmitted by the reader in ASK tJIT tJIT tJIT tJIT tJIT 0 START tRFSBL tRFSBL tRFSBL tRFSBL tRFSBL ai15590 Doc ID 15779 Rev 3 39/45 Part numbering 11 SRI2K Part numbering Table 10. Ordering information scheme Example: SRI2K - W4 /1GE Device type SRI2K Package W4 = 180 m 15 m unsawn wafer SBN18 = 180 m 15 m bumped and sawn wafer on 8-inch frame Customer code 1GE = generic product xxx = customer code after personalization Note: Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 40/45 Doc ID 15779 Rev 3 SRI2K ISO-14443 Type B CRC calculation Appendix A ISO-14443 Type B CRC calculation #include <stdio.h> #include <stdlib.h> #include <string.h> #include <ctype.h> #define BYTE unsigned char #define USHORT unsigned short unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc) { ch = (ch^(BYTE)((*lpwCrc) & 0x00FF)); ch = (ch^(ch<<4)); *lpwCrc = (*lpwCrc >> 8)^((USHORT)ch << 8)^((USHORT)ch<<3)^((USHORT)ch>>4); return(*lpwCrc); } void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE *TransmitSecond) { BYTE chBlock; USHORTt wCrc; wCrc = 0xFFFF; // ISO 3309 do { chBlock = *Data++; UpdateCrc(chBlock, &wCrc); } while (--Length); wCrc = ~wCrc; // ISO 3309 *TransmitFirst = (BYTE) (wCrc & 0xFF); *TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF); return; } int main(void) { BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i; printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1"); printf("CRC_B of [ "); for(i=0; i<4; i++) printf("%02X ",BuffCRC_B[i]); ComputeCrc(BuffCRC_B, 4, &First, &Second); printf("] Transmitted: %02X then %02X.", First, Second); return(0); Doc ID 15779 Rev 3 41/45 SRI2K command summary Appendix B SRI2K SRI2K command summary Figure 52. Initiate frame exchange between reader and SRI2K Reader SOF 06h 00h CRCL CRCH EOF SRI2K <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15581 Figure 53. Pcall16 frame exchange between reader and SRI2K Reader SOF 06h 04h CRCL CRCH EOF SRI2K <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15582 Figure 54. Slot_marker frame exchange between reader and SRI2K Reader SOF X6h CRCL CRCH EOF SRI2K <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15583 Figure 55. Select frame exchange between reader and SRI2K Reader SOF 0Eh Chip_ID CRCL CRCH EOF SRI2K <-t0-><-t1-> SOF Chip_ID CRCL CRCH EOF ai15584 Figure 56. Completion frame exchange between reader and SRI2K Reader SOF 0Fh CRCL CRCH EOF SRI2K No Response ai15585 42/45 Doc ID 15779 Rev 3 SRI2K SRI2K command summary Figure 57. Reset_to_inventory frame exchange between reader and SRI2K Reader SOF 0Ch CRCL CRCH EOF SRI2K No Response ai15586 Figure 58. Read_block frame exchange between reader and SRI2K Reader S O F 08h ADDR E CRCL CRCH O F S <-t0-><-t1-> O DATA DATA 2 1 F SRI2K DATA 3 E DATA CRC CRC L H O 4 F ai15587 Figure 59. Write_block frame exchange between reader and SRI2K Reader SOF 09h ADDR DATA DATA 1 2 DATA 3 DATA CRC CRC EOF L H 4 No Response SRI2K ai15588 Figure 60. Get_UID frame exchange between reader and SRI2K Reader SRI2K S E O 0Bh CRCL CRCH O F F S E <-t0-><-t1-> O UID UID UID UID UID UID UID UID CRCL CRCH O 0 1 2 3 4 5 6 7 F F ai15589 Doc ID 15779 Rev 3 43/45 Revision history 12 Revision history Table 11. 44/45 SRI2K Document revision history Date Revision Changes 01-Jun-2009 1 Initial release. 19-Oct-2009 2 Document promoted from Preliminary data to full datasheet status. Section 8.7: Read_block(Addr) command specified. 09-Sep-2011 3 Process technology removed from Section 1: iDescription. Updated dislaimer on last page. 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