This is information on a product in full production.
February 2016 DocID027843 Rev 2 1/64
L6986F
38 V, 1.5 A synchronous step-down switching regulator with 30 µA
quiescent current
Datasheet - production data
Features
1.5 A DC output current
4 V to 38 V operating input voltage
Low consumption mode or low noise mode
30 µA IQ at light-load (LCM VOUT = 3.3 V)
8 µA IQ-SHTDWN
Adjustable fSW (250 kHz - 2 MHz)
Output voltage adjustable from 0.85 V to VIN
Embedded output voltage supervisor
Synchronization
Adjustable soft-start time
Internal current limiting
Overvoltage protection
Output voltage sequencing
Peak current mode architecture
RDSON HS = 180 m, RDSON LS = 150 m
Thermal shutdown
Applications
Designed for 12 V and 24 V buses
Programmable logic controllers (PLCs)
Decentralized intelligent nodes
Sensors and low noise applications (LNM)
Description
The L6986F is a step-down monolithic switching
regulator able to deliver up to 1.5 A DC. The
output voltage adjustability ranges from 0.85 V to
VIN. Thanks to the P-channel MOSFET high-side
power element, the device features 100% duty
cycle operation. The wide input voltage range
meet the 5 V, 12 V and 24 V power supplies. The
“Low Consumption Mode” (LCM) is designed for
applications active during idle mode, so it
maximizes the efficiency at light-load with
controlled output voltage ripple. The “Low Noise
Mode” (LNM) makes the switching frequency
constant and minimizes the output voltage ripple
overload current range, meeting the low noise
application specification. The output voltage
supervisor manages the reset phase for any
digital load (µC, FPGA). The RST open collector
output can also implement output voltage
sequencing during the power-up phase. The
synchronous rectification, designed for high
efficiency at medium - heavy load, and the high
switching frequency capability make the size of
the application compact. Pulse by pulse current
sensing on both power elements implements an
effective constant current protection.
HTSSOP16 (RTH = 40 °C/W)
www.st.com
Contents L6986F
2/64 DocID027843 Rev 2
Contents
1 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.1 Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3.2 Output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.1 Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.2 Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6.1 LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6.2 LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.7 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OCP and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID027843 Rev 2 3/64
L6986F Contents
64
5 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4 Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3 MLF pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.5 Synchronization (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.6 Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7 Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8 Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1 HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Application schematic L6986F
4/64 DocID027843 Rev 2
1 Application schematic
Figure 1. Application schematic
DocID027843 Rev 2 5/64
L6986F Pin settings
64
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top view)
2.2 Pin description
Table 1. Pin description
No. Pin Description
1RST
The RST open collector output is driven low when the output voltage is out of regulation. The RST
is released after an adjustable time DELAY once the output voltage is over the active delay
threshold.
2VCC
Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the
embedded analog circuitry.
3 SS/INH An open collector stage can disable the device clamping this pin to GND (INH mode). An internal
current generator (4 A typ.) charges the external capacitor to implement the soft-start.
4SYNCH/
ISKP
The pin features Master / Slave synchronization in LNM (see Section 4.5.1 on page 23) and skip
current level selection in LCM (see Section 4.5.2 on page 23).
5FSW
A pull up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency.
Pinstrapping is active only before the soft-start phase to minimize the IC consumption.
6MLF
A pull up resistor (E24 series only) to VCC or pull down to GND selects the low noise mode/low
consumption mode and the active RST threshold. Pinstrapping is active only before the soft-start
phase to minimize the IC consumption.
7 COMP Output of the error amplifier. The designed compensation network is connected at this pin.
8DELAY
An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the
RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like
a Power Good.
9 FB Inverting input of the error amplifier
10 SGND Signal GND
11 PGND Power GND
Pin settings L6986F
6/64 DocID027843 Rev 2
2.3 Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
12 PGND Power GND
13 LX Switching node
14 LX Switching node
15 VIN DC input voltage
16 VBIAS
Typically connected to the regulated output voltage. An external voltage reference can be used to
supply part of the analog circuitry to increase the efficiency at light-load. Connect to GND if not
used.
- E. p. Exposed pad must be connected to SGND, PGND
Table 1. Pin description (continued)
No. Pin Description
Table 2. Absolute maximum ratings
Symbol Description Min. Max. Unit
VIN
See Table 1
-0.3 40 V
DELAY -0.3 VCC + 0.3 V
PGND SGND - 0.3 SGND + 0.3 V
SGND V
VCC -0.3 (VIN + 0.3) or (max. 4) V
SS / INH -0.3 VIN + 0.3 V
MLF -0.3 VCC + 0.3 V
COMP -0.3 VCC + 0.3 V
VOUT -0.3 10 V
FSW -0.3 VCC + 0.3 V
SYNCH -0.3 VIN + 0.3 V
VBIAS -0.3 (VIN + 0.3) or (max. 6) V
RST -0.3 VIN + 0.3 V
LX -0.3 VIN + 0.3 V
TJOperating temperature range -40 150 °C
TSTG Storage temperature range -65 to 150 °C
TLEAD Lead temperature (soldering 10 sec.) 260 °C
IHS, ILS High-side / low-side switch current 2 A
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L6986F Pin settings
64
2.4 Thermal data
2.5 ESD protection
Table 3. Thermal data
Symbol Parameter Value Unit
Rth JA
Thermal resistance junction ambient (device soldered on the
STMicroelectronics® demonstration board) 40 °C/W
Rth JC
Thermal resistance junction to exposed pad for board design
(not suggested to estimate TJ from power losses). 5 °C/W
Table 4. ESD protection
Symbol Test condition Value Unit
ESD
HBM 2 kV
MM 200 V
CDM 500 V
Electrical characteristics L6986F
8/64 DocID027843 Rev 2
3 Electrical characteristics
TJ = 25 °C, VIN = 12 V unless otherwise specified.
Table 5. Electrical characteristics
Symbol Parameter Test condition Note Min. Typ. Max. Unit
VIN Operating input voltage range 4 38
VVINH VCC UVLO rising threshold 2.7 3.5
VINL VCC UVLO falling threshold 2.4 3.5
IPK Peak current limit
Duty cycle < 20% 2.3
A
Duty cycle = 100%
closed loop operation 1.8
IVY Valley current limit 2.4
ISKIPH Programmable skip current
limit
LCM, VSYNCH = GND (1) 0.2 0.4 0.6
ISKIPL LCM, VSYNCH = VCC (2) 0.2
IVY_SNK Reverse current limit LNM or VOUT overvoltage 0.5 1 2
RDSON HS High-side RDSON ISW = 1 A 0.18 0.360
RDSON LS Low-side RDSON ISW = 1 A 0.15 0.300
fSW Selected switching frequency FSW pinstrapping before SS See Table 6: fSW selection
IFSW FSW biasing current SS ended 0 500 nA
LCM/LNM
Low noise mode /
Low consumption mode
selection
MLF pinstrapping before SS See Table 7 on page 11
IMLF MLF biasing current SS ended 0 500 nA
D Duty cycle (2) 0 100 %
TON MIN Minimum On time 80 ns
VCC regulator
VCC LDO output voltage
VBIAS = GND (no switchover) 2.9 3.3 3.6
V
VBIAS = 5 V (switchover) 2.9 3.3 3.6
SWO VBIAS threshold
(3 V< VBIAS < 5.5 V)
Switch internal supply from VIN to
VBIAS
2.85 3.2
Switch internal supply from VBIAS
to VIN
2.78 3.15
DocID027843 Rev 2 9/64
L6986F Electrical characteristics
64
Power consumption
ISHTDWN Shutdown current from VIN VSS/INH = GND 4 8 15 A
IQ OPVIN Quiescent current from VIN
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
(3) 41015
A
LCM - NO SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = GND
(3) 35 70 120
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
0.5 1.5 5
mA
LNM - NO SWO
VFB = GND (NO SLEEP)
VBIAS = GND
22.8 6
IQ OPVBIAS Quiescent current from VBIAS
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
(3) 25 50 115 A
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
0.5 1.2 5 mA
Soft-start
VINH VSS threshold SS rising 200 460 700
mV
VINH HYST VSS hysteresis 100 140
ISS CH CSS charging current
VSS < VINH OR
t < TSS SETUP OR
VEA+ > VFB
(2) 1
A
t > TSS SETUP AND
VEA+ < VFB
(2) 4
VSS START
Start of internal error amplifier
ramp 0.995 1.1 1.150 V
SSGAIN
SS/INH to internal error
amplifier gain 3
Error amplifier
VOUT Voltage feedback 0.841 0.85 0.859 V
IVOUT VOUT biasing current 50 500 nA
AVError amplifier gain (2) 100 dB
ICOMP EA output current capability ±6 ±12 ±25 A
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Note Min. Typ. Max. Unit
Electrical characteristics L6986F
10/64 DocID027843 Rev 2
Inner current loop
gCS
Current sense
transconductance (VCOMP to
inductor current gain)
Ipk = 1 A (2) 2.5 A/V
Slope compensation (4) 0.45 0.75 1 A
Overvoltage protection
VOVP Overvoltage trip (VOVP/VREF) 1.15 1.2 1.25
VOVP HYST Overvoltage hysteresis 0.5 2 5 %
Synchronization (fan out: 6 slave devices typ.)
fSYN MIN Synchronization frequency LNM; fSW = VCC 266.5 kHz
VSYN TH SYNCH input threshold LNM, SYNCH rising 0.70 1.2 V
ISYN SYNCH pull-down current LNM, VSYN = 1.2 V 0.7 mA
VSYN OUT
High level output LNM, 5 mA sinking load 1.40
V
Low level output LNM, 0.7 mA sourcing load 0.6
Reset
VTHR Selected RST threshold MLF pinstrapping before SS see Table 7
VTHR HYST RST hysteresis (2) 2%
VRST RST open collector output
VIN > VINH AND
VFB < VTH
4 mA sinking load
0.4
V
2 < VIN < VINH
4 mA sinking load 0.8
Delay
VTHD
RST open collector released
as soon as VDELAY > VTHD
VFB > VTHR 1.19 1.234 1.258 V
ID CH CDELAY charging current VFB > VTHR 12 3A
Thermal shutdown
TSHDWN
Thermal shutdown
temperature
(2) 165
°C
THYS Thermal shutdown hysteresis (2) 30
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. Not tested in production.
3. LCM enables SLEEP mode at light-load.
4. Measured at fsw = 250 kHz.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Note Min. Typ. Max. Unit
VPP gCS
DocID027843 Rev 2 11/64
L6986F Electrical characteristics
64
TJ = 25 °C, VIN = 12 V unless otherwise specified.
Table 6. fSW selection
TJ = 25 °C, VIN = 12 V unless otherwise specified.
Table 7. LNM / LCM selection
Symbol RVCC (E24 series) RGND (E24 series) Tj fSW min. fSW typ. fSW max. Unit
fSW
0 NC 225 250 275
kHz
1.8 kNC
(1)
1. Not tested in production.
285
3.3 kNC 330
5.6 kNC 380
10 kNC 435
NC 0 450 500 550
18 kNC
(1)
575
33 kNC 660
56 kNC 755
NC 1.8 k870
NC 3.3 k900 1000 1100
NC 5.6 k
(1)
1150
NC 10 k1310
NC 18 k1500(2)
2. No synchronization as slave in LNM.
NC 33 k1575 1750(2) 1925
NC 56 k1800 2000(2) 2200
Symbol RVCC
(E24 1%)
RGND
(E24 1%)
Operating
mode
VRST/VOUT
(tgt. value)
VRST
min.
VRST
typ.
VRST
max. Unit
VRST
0 NC
LCM
93% 0.779 0.791 0.802
V
8.2 kNC 80% 0.670 0.680 0.690
18 kNC 87% 0.728 0.740 0.751
39 kNC 96% 0.804 0.816 0.828
NC 0
LNM
93% 0.779 0.791 0.802
NC 8.2 k80% 0.670 0.680 0.690
NC 18 k87% 0.728 0.740 0.751
NC 39 k96% 0.804 0.816 0.828
Functional description L6986F
12/64 DocID027843 Rev 2
4 Functional description
The L6986F device is based on a “peak current mode”, constant frequency control. As
a consequence, the intersection between the error amplifier output and the sensed inductor
current generates the PWM control signal to drive the power switch.
The device features LNM (low noise mode) that is forced PWM control, or LCM (low
consumption mode) to increase the efficiency at light-load.
The main internal blocks shown in the block diagram in Figure 3 are:
Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the
device features low dropout operation
A fully integrated sawtooth oscillator with adjustable frequency
A transconductance error amplifier
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the
embedded power elements
The soft-start blocks to ramp the error amplifier reference voltage and so decreases the
inrush current at power-up. The SS/INH pin inhibits the device when driven low.
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The synchronization circuitry to manage master / slave operation and the
synchronization to an external clock
The current limitation circuit to implement the constant current protection, sensing
pulse by pulse high-side / low-side switch current. In case of heavy short-circuit the
current protection is fold back to decrease the stress of the external components
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator
FSW pinstrapping sets the switching frequency
The RST open collector output.
DocID027843 Rev 2 13/64
L6986F Functional description
64
Figure 3. Internal block diagram
4.1 Power supply and voltage reference
The internal regulator block consists of a start-up circuit, the voltage pre-regulator that
provides current to all the blocks and the bandgap voltage reference. The starter supplies
the startup current when the input voltage goes high and the device is enabled (SS/INH pin
over the inhibits threshold).
The pre-regulator block supplies the bandgap cell and the rest of the circuitry with
a regulated voltage that has a very low supply voltage noise sensitivity.
Switchover feature
The switchover scheme of the pre-regulator block features to derive the main contribution of
the supply current for the internal circuitry from an external voltage (3 V < VBIAS < 5.5 V is
typically connected to the regulated output voltage). This helps to decrease the equivalent
quiescent current seen at VIN. (Please refer to Section 4.6: Switchover feature on page 29).
4.2 Voltages monitor
An internal block continuously senses the VCC, VBIAS and VBG
. If the monitored voltages are
good, the regulator starts operating. There is also a hysteresis on the VCC (UVLO).
Functional description L6986F
14/64 DocID027843 Rev 2
Figure 4. Internal circuit
4.3 Soft-start and inhibit
The soft-start and inhibit features are multiplexed on the same pin. An internal current
source charges the external soft-start capacitor to implement a voltage ramp on the SS/INH
pin. The device is inhibited as long as the SS/INH pin voltage is lower than the VINH
threshold and the soft-start takes place when SS/INH pin crosses VSS START
. (See Figure 5:
Soft-start phase).
The internal current generator sources a 1 A typ. current when the voltage of the VCC pin
crosses the UVLO threshold. The current increases to 4 A typ. as soon as the SS/INH
voltage is higher than the VINH threshold. This feature helps to decrease the current
consumption in inhibit mode. An external open collector can be used to set the inhibit
operation clamping the SS/INH voltage below VINH threshold.
The startup feature minimizes the inrush current and decreases the stress of the power
components during the power-up phase. The ramp implemented on the reference of the
error amplifier has a gain three times higher (SSGAIN) than the external ramp present at
SS/INH pin.
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DocID027843 Rev 2 15/64
L6986F Functional description
64
Figure 5. Soft-start phase
The CSS is dimensioned accordingly with Equation 1:
Equation 1
where TSS is the soft-start time, ISS CH the charging current and VFB the reference of the
error amplifier.
The soft-start block supports the precharged output capacitor.
CSS SSGAIN
ISSCH TSS
VFB
--------------------------------34AT
SS
0.85V
---------------------------==
Functional description L6986F
16/64 DocID027843 Rev 2
Figure 6. Soft-start phase with precharged COUT
During normal operation a new soft-start cycle takes place in case of:
Thermal shutdown event
UVLO event
The device is driven in INH mode
The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 msec time
max. For complete and proper capacitor discharge in case of fault condition, a maximum
CSS = 67 nF value is suggested.
The application example in Figure 7 shows how to enable the L6986F and perform the soft-
start phase driven by an external voltage step.
Figure 7. Enable the device with external voltage step
DocID027843 Rev 2 17/64
L6986F Functional description
64
The maximum capacitor value has to be limited to guarantee the device can discharge it in
case of thermal shutdown and UVLO events (see Figure 9), so restart the switching activity
ramping the error amplifier reference voltage.
Equation 2
where:
Equation 3
The optional diode prevents to disable the device if the external source drops to ground.
RUP value is selected in order to make the capacitor charge at first approximation
independent from the internal current generator (4 A typ. current capability, see Table 5 on
page 8), so:
Equation 4
where:
Equation 5
represents the SS/INH voltage correspondent to the end of the ramp on the error amplifier
(see Figure 5); refer to Table 5 for VSS START
, VFB and SSGAIN parameters.
As a consequence the voltage across the soft-start capacitor can be written as:
Equation 6
RSS_DOWN is selected to guarantee the device stays in inhibit mode when the internal
generator sources 1 A typ. out of the SS/INH pin and VSTEP is not present:
Equation 7
so:
Equation 8
CSS
1 msec–
RSS_EQ 1VSS_FINAL 0.9 V–
600 AR
SS_EQ
–
----------------------------------------------–
ln
-------------------------------------------------------------------------------------------
RSS_EQ
RUP RDWN
RUP RDWN
+
---------------------------------= VSS_FINAL VSTEP VDIODE
–
RDWN
RUP RDWN
+
----------------------------------=
VSTEP VDIODE
–VSS END
–
RUP
----------------------------------------------------------------------- ISS CHARGE 4 A»
VSS END VSS START
VFB
SSGAIN
---------------------+=
vSS t VSS_FINAL
1
1e
t
CSS RSS_EQ
---------------------------------–
–
------------------------------------------=
RDWN ISS INHIBIT RDWN 1 AVINH 200 mV«
RDWN 100 k
Functional description L6986F
18/64 DocID027843 Rev 2
RUP and RDWN are selected to guarantee:
Equation 9
The time to ramp the internal voltage reference can be calculated from Equation 10:
Equation 10
that is the equivalent soft-start time to ramp the output voltage.
Figure 8 shows the soft-start phase with the following component selection: RUP = 180 k,
RDWN = 33 k, CSS = 200 nF, the 1N4148 is a small signal diode and VSTEP = 13 V.
Figure 8. External soft-start network VSTEP driven
The circuit in Figure 7 introduces a time delay between VSTEP and the switching activity that
can be calculated as:
Equation 11
Figure 9 shows how the device discharges the soft-start capacitor after an UVLO or thermal
shutdown event in order to restart the switching activity ramping the error amplifier reference
voltage.
VSS_FINAL 2 V VSS_END
TSS CSS RSS_EQ
VSS_FINAL VSS START
–
VSS_FINAL VSS END
–
-----------------------------------------------------------
ln=
TSS DELAY CSS RSS_EQ
VSS_FINAL
VSS_FINAL VSS START
–
-----------------------------------------------------------
ln=
DocID027843 Rev 2 19/64
L6986F Functional description
64
Figure 9. External soft-start after UVLO or thermal shutdown
Functional description L6986F
20/64 DocID027843 Rev 2
4.3.1 Ratiometric startup
The ratiometric startup is implemented sharing the same soft-start capacitor for a set of the
L6986F devices.
Figure 10. Ratiometric startup
As a consequence all the internal current generators charge in parallel the external
capacitor. The capacitor value is dimensioned accordingly with Equation 12:
Equation 12
where nL6986F represents the number of devices connected in parallel.
For better tracking of the different output voltages the synchronization of the set of
regulators is suggested.
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ISSCH TSS
VFB
-------------------------------- nL6986F 34AT
SS
0.85V
---------------------------==
DocID027843 Rev 2 21/64
L6986F Functional description
64
Figure 11. Ratiometric startup operation
Functional description L6986F
22/64 DocID027843 Rev 2
4.3.2 Output voltage sequencing
The L6986F device implements sequencing connecting the RST pin of the master device to
the SS/INH of the slave. The slave is inhibited as long as the master output voltage is
outside regulation so implementing the sequencing (see Figure 12).
Figure 12. Output voltage sequencing
High flexibility is achieved thanks to the programmable RST thresholds (Table 7 on page 11)
and programmable delay time. To minimize the component count the DELAY pin capacitor
can be also omitted so the pin works as a normal Power Good.
4.4 Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (0.85 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage.
The error amplifier output is compared with the inductor current sense information to
perform PWM control. The error amplifier also determines the burst operation at light-load
when the LCM is active.
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Table 8. Uncompensated error amplifier characteristics
Description Values
Transconductance 155 µS
Low frequency gain 100 dB
DocID027843 Rev 2 23/64
L6986F Functional description
64
4.5 Light-load operation
The MLF pinstrapping during the power-up phase determines the light-load operation (refer
to Table 7 on page 11).
4.5.1 Low noise mode (LNM)
The low noise mode implements a forced PWM operation over the different loading
conditions. The LNM features a constant switching frequency to minimize the noise in the
final application and a constant voltage ripple at fixed VIN. The regulator in steady loading
condition never skip pulses and it operates in continuous conduction mode (CCM) over the
different loading conditions thus making this operation mode ideal for noise sensitive
applications.
Figure 13. Low noise mode operation
4.5.2 Low consumption mode (LCM)
The low consumption mode maximizes the efficiency at light-load. The regulator prevents
the switching activity whenever the switch peak current request is lower than the ISKIP
threshold. As a consequence the L6986F device works in bursts and it minimizes the
quiescent current request in the meantime between the switching operation.
In LCM operation, the pin SYNCH/ISKIP level dynamically defines the ISKIP current
threshold (see Table 5 on page 8) as shown in Table 9.
Functional description L6986F
24/64 DocID027843 Rev 2
The ISKIP programmability helps to optimize the performance in terms of the output voltage
ripple or efficiency at the light-load, that are parameters which disagree each other by
definition.
A lower skip current level minimizes the voltage ripple but increases the switching activity
(time between bursts gets closer) since less energy per burst is transfered to the output
voltage at the given load. On the other side, a higher skip level reduces the switching activity
and improves the efficiency at the light-load but worsen the voltage ripple.
No difference in terms of the voltage ripple and conversion efficiency for the medium and
high load current level, that is when the device operates in the discontinuous or continuous
mode (DCM vs. CCM).
Figure 14 and Figure 15 report the efficiency measurements to highlight the ISKIPH and
ISKIPL efficiency gap at the light-load also in comparison with the LNM operation (also
called NOSKIP). The same efficiency at the medium / high load is confirmed at different
ISKIP levels.
Figure 14. Light-load efficiency comparison at different ISKIP - linear scale
Figure 15. Light-load efficiency comparison at different ISKIP - log scale
Table 9. ISKIP programmable current threshold
SYNCH / ISKIP (pin 4) ISKIP current threshold
LOW ISKIPH = 0.4 A typical
HIGH ISKIPL = 0.2 A typical
LNM
LCM ISKIPL =200mA
LCM ISKIPH =400mA
LNM
LCM ISKIPL =200mA
LCM ISKIPH =400mA
DocID027843 Rev 2 25/64
L6986F Functional description
64
Figure 16 and Figure 17 show the LCM operation at the different ISKIP level.
Figure 16 shows the ISKIPH = 400 mA typ. and so 20 mV output voltage ripple.
Figure 17 shows the ISKIPL = 200 mA typ. and so 10 mV output voltage ripple.
Figure 16. LCM operation with ISKIPH = 400 mA typ. at zero load
Figure 17. LCM operation with ISKIPL = 200 mA typ. at zero load
In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current
drawn from the input voltage can be calculated as Equation 14.
Functional description L6986F
26/64 DocID027843 Rev 2
Given the energy stored in the inductor during a burst, the voltage ripple depends on the
capacitor value:
Equation 13
Figure 18. LCM operation over loading condition (part 1)
VOUT RIPPLE
QIL
COUT
--------------
iLt dt
0
TBURST
COUT
--------------------------------------------==
DocID027843 Rev 2 27/64
L6986F Functional description
64
Figure 19. LCM operation over loading condition (part 2 - DCM)
Figure 20. LCM operation over loading condition (part 3 - DCM)
Functional description L6986F
28/64 DocID027843 Rev 2
Figure 21. LCM operation over loading condition (part 4 - DCM)
Figure 22. LCM operation over loading condition (part 5 - CCM)
DocID027843 Rev 2 29/64
L6986F Functional description
64
4.6 Switchover feature
The switchover maximizes the efficiency at the light-load that is crucial for LCM applications.
4.6.1 LCM
The LCM operation satisfies the high efficiency requirements of the battery powered
applications. In order to minimize the regulator quiescent current request from the input
voltage, the VBIAS pin can be connected to an external voltage source in the range
3 V < VBIAS < 5.5 V (see Section 4.1: Power supply and voltage reference on page 13).
In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current
drawn from the input voltage can be calculated as:
Equation 14
where IQ OP VIN, IQ OP VBIAS are defined in Table 5: Electrical characteristics on page 8
and
L6986F is the efficiency of the conversion in the working point.
4.6.2 LNM
Equation 14 is also valid when the device works in LNM and it can increase the efficiency at
the medium load since the regulator always operates in the continuous conduction mode.
4.7 Overcurrent protection
The current protection circuitry features a constant current protection, so the device limits
the maximum peak current (see Table 5) in overcurrent condition.
The L6986F device implements a pulse by pulse current sensing on both power elements
(high-side and low-side switches) for effective current protection over the duty cycle range.
The high-side current sensing is called “peak” the low-side sensing “valley”.
The internal noise generated during the switching activity makes the current sensing
circuitry ineffective for a minimum conduction time of the power element. This time is called
“masking time” because the information from the analog circuitry is masked by the logic to
prevent an erroneous detection of the overcurrent event. As a consequence, the peak
current protection is disabled for a masking time after the high-side switch is turned on, the
valley for a masking time after the low-side switch is turned on. In other words, the peak
current protection can be ineffective at extremely low duty cycles, the valley current
protection at extremely high duty cycles.
The L6986F device assures an effective overcurrent protection sensing the current flowing
in both power elements. In case one of the two current sensing circuitry is ineffective
because of the masking time, the device is protected sensing the current on the opposite
switch. Thus, the combination of the “peak” and “valley” current limits assure the
effectiveness of the overcurrent protection even in extreme duty cycle conditions.
The valley current threshold is designed higher than the peak to guarantee a proper
operation. In case the current diverges because of the high-side masking time, the low-side
power element is turned on until the switch current level drops below the valley current
IQVIN IQOPVIN
1
L6986F
--------------------VBIAS
VIN
--------------- IQOPVBIAS
+=
Functional description L6986F
30/64 DocID027843 Rev 2
sense threshold. The low-side operation is able to prevent the high-side turn on, so the
device can skip pulses decreasing the swathing frequency.
Figure 23. Valley current sense operation in overcurrent condition
Figure 23 shows the switching frequency reduction during the valley current sense
operation in case of an extremely low duty cycle (VIN = 38 V, fSW = 500 kHz short-circuit
condition).
In a worst case scenario (like Figure 23) of the overcurrent protection the switch current is
limited to:
Equation 15
where IVALLEY_TH is the current threshold of the valley sensing circuitry (see Table 5:
Electrical characteristics on page 8) and TMASK_HS is the masking time of the high-side
switch 100 nsec. typ.).
In most of the overcurrent conditions the conduction time of the high-side switch is higher
than the masking time and so the peak current protection limits the switch current.
Equation 16
IMAX = IPEAK_TH
IMAX IVALLEYTH
VIN VOUT
–
L
------------------------------TMASKHS
+=
DocID027843 Rev 2 31/64
L6986F Functional description
64
Figure 24. Peak current sense operation in overcurrent condition
The DC current flowing in the load in overcurrent condition is:
Equation 17
OCP and switchover feature
Output capacitor discharging the current flowing to ground during heavy short-circuit events
is only limited by parasitic elements like the output capacitor ESR and short-circuit
impedance.
Due to parasitic inductance of the short-circuit impedance, negative output voltage
oscillations can be generated with huge discharging current levels (see Figure 25).
IDCOC VOUT
IMAX
IRIPPLE VOUT
2
----------------------------------------– IMAX
VIN VOUT
–
2L
------------------------------TON
–==
Functional description L6986F
32/64 DocID027843 Rev 2
Figure 25. Output voltage oscillations during heavy short-circuit
Figure 26. Zoomed waveform
The VBIAS pin absolute maximum ratings (see Table 2: Absolute maximum ratings on
page 6) must be satisfied over the different dynamic conditions.
If the VBIAS is connected to GND there are no issues (see Figure 25 and Figure 26).
short-circuit current
regulated output voltage
inductor current
switching node
regulated output voltage
inductor current
short-circuit current
switching node
short-circuit current
regulated output voltage
inductor current
switching node
regulated output voltage
inductor current
short-circuit current
switching node
DocID027843 Rev 2 33/64
L6986F Functional description
64
A small resistor value (few ohms) in series with the VBIAS can help to limit the pin negative
voltage (see Figure 27) during heavy short-circuit events if it is connected to the regulated
output voltage.
Figure 27. VBIAS in heavy short-circuit event
4.8 Overvoltage protection
The overvoltage protection monitors the FB pin and enables the low-side MOSFET to
discharge the output capacitor if the output voltage is 20% over the nominal value.
This is a second level protection and should never be triggered in normal operating
conditions if the system is properly dimensioned. In other words, the selection of the
external power components and the dynamic performance determined by the compensation
network should guarantee an output voltage regulation within the overvoltage threshold
even during the worst case scenario in term of load transitions.
The protection is reliable and also able to operate even during normal load transitions for
a system whose dynamic performance is not in line with the load dynamic request. As
a consequence the output voltage regulation would be affected.
Figure 28 shows the overvoltage operation during a negative steep load transient for
a system designed with huge inductor value and small output capacitor. The inductor value
limits the switch current slew rate and the extra charge flowing into the small capacitor value
generates an overvoltage event. This can be considered as an example for a system with
dynamic performance not in line with the load request.
The L6986F device implements a 1 A typ. negative current limitation to limit the maximum
reversed switch current during the overvoltage operation.
VBIAS pin voltage
regulated output voltage
inductor current
switching node
(purple)
(cyan)
regulated output voltage
VBIAS pin
short-circuit current
switching node
Functional description L6986F
34/64 DocID027843 Rev 2
Figure 28. Overvoltage operation
4.9 Thermal shutdown
The shutdown block disables the switching activity if the junction temperature is higher than
a fixed internal threshold (165 °C typical). The thermal sensing element is close to the
power elements, ensuring fast and accurate temperature detection. A hysteresis of
approximately 30 °C prevents the device from turning ON and OFF continuously. When the
thermal protection runs away a new soft-start cycle will take place.
DocID027843 Rev 2 35/64
L6986F Closing the loop
64
5 Closing the loop
Figure 29. Block diagram of the loop
5.1 GCO(s) control to output transfer function
The accurate control to output transfer function for a buck peak current mode converter can
be written as:
Equation 18
where RLOAD represents the load resistance, gCS the equivalent sensing conductance of the
current sense circuitry,
p the single pole introduced by the power stage and
z the zero
given by the ESR of the output capacitor.
FH(s) accounts the sampling effect performed by the PWM comparator on the output of the
error amplifier that introduces a double pole at one half of the switching frequency.
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L
----------------------------------- mC1D–0.5–+
--------------------------------------------------------------------------------------------------------
1s
z
------+
1s
p
------+
----------------------FH
s=
Closing the loop L6986F
36/64 DocID027843 Rev 2
Equation 19
Equation 20
where:
Equation 21
Sn represents the on time slope of the sensed inductor current, Se the on time slope of the
external ramp (VPP peak-to-peak amplitude) that implements the slope compensation to
avoid sub-harmonic oscillations at duty cycle over 50%.
Se can be calculated from the parameter VPP gCS given in Table 5 on page 8.
The sampling effect contribution FH(s) is:
Equation 22
where:
Equation 23
z
1
ESR COUT
---------------------------------=
p
1
RLOAD COUT
---------------------------------------mc1D–0.5–
LC
OUT fSW
----------------------------------------------+=
mC1Se
Sn
------ +=
SeVPP gCS fSW
=
Sn
VIN VOUT
–
L
----------------------------- =
FHs 1
1s
nQp
--------------------s2
n
2
---------++
----------------------------------------------=
Qp
1
mc1D–0.5–
------------------------------------------------------------=
DocID027843 Rev 2 37/64
L6986F Closing the loop
64
5.2 Error amplifier compensation network
The typical compensation network required to stabilize the system is shown in Figure 30.
Figure 30. Transconductance embedded error amplifier
RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect
system stability but it is useful to reduce the noise at the output of the error amplifier.
The transfer function of the error amplifier and its compensation network is:
Equation 24
Where Avo = Gm · Ro
The poles of this transfer function are (if Cc >> C0 + CP):
Equation 25
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=
fPLF
1
2R0Cc
-------------------------------------=
Closing the loop L6986F
38/64 DocID027843 Rev 2
Equation 26
whereas the zero is defined as:
Equation 27
5.3 Voltage divider
The contribution of the simple voltage divider is:
Equation 28
A small signal capacitor in parallel to the upper resistor (see Figure 31) of the voltage divider
implements a leading network (fzero < fpole), sometimes necessary to improve the system
phase margin:
Figure 31. Leading network example
Laplace transformer of the leading network:
Equation 29
fPHF
1
2R0C0Cp
+
--------------------------------------------------------=
fZ
1
2RcCc
-------------------------------------=
GDIV s R2
R1R2
+
--------------------=
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R1R2
+
-------------------- 1sR
1CR1
++
1sR1R2
R1R2
+
--------------------CR1
+
-------------------------------------------------------------=
DocID027843 Rev 2 39/64
L6986F Closing the loop
64
where:
Equation 30
5.4 Total loop gain
In summary, the open loop gain can be expressed as:
Equation 31
Example 1
VIN = 12 V, VOUT = 3.3 V, ROUT = 2.2
Selecting fSW = 500 kHz, L = 6.8 µH, COUT = 20 µF and ESR = 1 m, RC= 75 k,
CC= 220 pF, CP = 2.2 pF (please refer to Table 14 on page 54), the gain and phase bode
diagrams are plotted respectively in Figure 32 and Figure 33.
Equation 32
fZ
1
2R1CR1
-----------------------------------------=
fp
1
2R1R2
R1R2
+
-------------------- CR1
-------------------------------------------------------=
fZfp
Gs GDIV sGCO sA0s=
BW 58kHz =
phase margin 670
=
Closing the loop L6986F
40/64 DocID027843 Rev 2
Figure 32. Module plot
Figure 33. Phase plot
The blue solid trace represents the transfer function including the sampling effect term (see
Equation 22 on page 36), the dotted blue trace neglects the contribution.
DocID027843 Rev 2 41/64
L6986F Closing the loop
64
5.5 Compensation network design
The maximum bandwidth of the system can be designed up to fSW/6 up to 150 kHz
maximum to guarantee a valid small signal model.
Equation 33
Equation 34
where:
Equation 35
p is defined by Equation 20 on page 36, gCS represents the current sense
transconductance (see Table 5: Electrical characteristics on page 8) and gm TYP the error
amplifier transconductance.
Equation 36
Example 2
Considering VIN = 12 V, VOUT = 3.3 V, L =6.8 H, COUT = 15F, fSW = 500 kHz, IOUT = 1 A.
The maximum system bandwidth is 80 kHz. Assuming to design the compensation network
to achieve a system bandwidth of 70 kHz:
Equation 37
Equation 38
so accordingly with Equation 34 and Equation 36:
Equation 39
Equation 40
The gain and phase bode diagrams are plotted respectively in Figure 32 and Figure 33.
BW min fSW
6
---------150kHz;
=
RC
2BW COUT VOUT
0.85V gCS gm TYP
----------------------------------------------------------------=
fPOLE
p
2
-----------=
CC
5
2RCBW
--------------------------------------=
fPOLE 3.5kHz=
RLOAD
VOUT
IOUT
-------------- 3.3==
RC68k=
CC165pF 180pF=
Closing the loop L6986F
42/64 DocID027843 Rev 2
Figure 34. Magnitude plot for Example 2
Figure 35. Phase plot for Example 2
DocID027843 Rev 2 43/64
L6986F Application notes
64
6 Application notes
6.1 Output voltage adjustment
The error amplifier reference voltage is 0.85 V typical.
The output voltage is adjusted accordingly with Equation 41 (see Figure 36):
Equation 41
Cr1 capacitor is sometimes useful to increase the small signal phase margin (please refer to
Section 5.5: Compensation network design).
Figure 36. L6986F application circuit
6.2 Switching frequency
A resistor connected to the FSW pin features the selection of the switching frequency. The
pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is
pinstrapped and then driven floating in order to minimize the quiescent current from VIN.
Please refer toTable 6: fSW selection on page 11 to identify the pull-up / pull-down resistor
value. fSW = 250 kHz / fSW = 500 kHz preferred codifications don't require any external
resistor.
6.3 MLF pin
A resistor connected to the MLF pin features the selection of the between low noise mode /
low consumption mode and the different RST thresholds. The pinstrapping is performed at
power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven
floating in order to minimize the quiescent current from VIN.
Please refer to Table 7 on page 11 to identify the pull-up / pull-down resistor value. (LNM,
RST threshold 93%) / (LCM, RST threshold 93%) preferred codifications don't require any
external resistor.
VOUT 0.85 1 R1
R2
-------+
=
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44/64 DocID027843 Rev 2
6.4 Voltage supervisor
The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the
regulated output voltage and keeps the RST open collector output in low impedance as long
as the VOUT is out of regulation. In order to ensure a proper reset of digital devices with
a valid power supply, the device can delay the RST assertion with a programmable time.
Figure 37. Voltage supervisor operation
The comparator monitoring the FB voltage has four different programmable thresholds
(80%, 87%, 93%, 96% nominal output voltage) for high flexibility (see Section 6.3: MLF pin
on page 43 and Table 7 on page 11).
When the RST comparator detects the output voltage is in regulation, a 2 A internal current
source starts to charge an external capacitor to implement a voltage ramp on the DELAY
pin. The RST open collector is then released as soon as VDELAY = 1.234 V (see Figure 37).
The CDELAY is dimensioned accordingly with Equation 42:
Equation 42
The maximum suggested capacitor value is 270 nF.
CDELAY
ISSCH TDELAY
VDELAY
------------------------------------------2AT
DELAY
1.234V
-------------------------------------==
DocID027843 Rev 2 45/64
L6986F Application notes
64
6.5 Synchronization (LNM)
Beating frequency noise is an issue when multiple switching regulators populate the same
application board. The L6986F synchronization circuitry features the same switching
frequency for a set of regulators simply connecting their SYNCH pin together, so preventing
beating noise. The master device provides the synchronization signal to the others since the
SYNCH pin is I/O able to deliver or recognize a frequency signal.
For proper synchronization of multiple regulators, all of them have to be configured with the
same switching frequency (see Table 6 on page 11), so the same resistor connected at the
FSW pin.
In order to minimize the RMS current flowing through the input filter, the L6986F device
provides a phase shift of 180° between the master and the SLAVES. If more than two
devices are synchronized, all slaves will have a common 180° phase shift with respect to
the master.
Considering two synchronized L6986F which regulates the same output voltage
(i.e.: operating with the same duty cycle), the input filter RMS current is optimized and is
calculated as:
Equation 43
The graphical representation of the input RMS current of the input filter in the case of two
devices with 0° phase shift (synchronized to an external signal) or 180° phase shift
(synchronized connecting their SYNCH pins) regulating the same output voltage is provided
in Figure 38. To dimension the proper input capacitor please refer to Section 6.6.1: Input
capacitor selection on page 50.
Figure 38. Input RMS current
IRMS
IOUT
2
------------2D 1 2D– if D < 0.5
IOUT
2
------------2D 1–22D– if D > 0.5
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Application notes L6986F
46/64 DocID027843 Rev 2
Figure 39 shows two regulators not synchronized.
Figure 39. Two regulators not synchronized
Figure 40 shows the same regulators working synchronized. The MASTER regulator (LX2
trace) delivers the synchronization signal (SYNCH1, SYNCH2 pins are connected together)
to the SLAVE device (LX1). The SLAVE regulator works in phase with the synchronization
signal which is out of phase with the MASTER switching operation.
Figure 40. Two regulators synchronized
DocID027843 Rev 2 47/64
L6986F Application notes
64
Multiple L6986F can be synchronized to an external frequency signal fed to the SYNCH pin.
In this case the regulator set is phased to the reference and all the devices will work with 0°
phase shift.
The frequency range of the synchronization signal is 275 kHz - 1.4 MHz and the minimum
pulse width is 100 nsec (see Figure 41).
Figure 41. Synchronization pulse definition
Since the slope compensation contribution that is required to prevent subharmonic
oscillations in peak current mode architecture depends on the switching frequency, it is
important to select the same oscillator frequency for all regulators (all of them operate as
SLAVE) as close as possible to the frequency of the reference signal (please refer to
Table 6: fSW selection on page 11). As a consequence all the regulators have the same
resistor value connected to the FSW pin, so the slope compensation is optimized
accordingly with the frequency of the synchronization signal. The slope compensation
contribution is latched at power-up and so fixed during the device operation.
The L6986F normally operates in MASTER mode, driving the SYNCH line at the selected
oscillator frequency as shown in Figure 42 and Figure 39.
In SLAVE mode the L6986F sets the internal oscillator at 250 kHz typ. (see Table 6 on
page 11 - first row) and drives the line accordingly.
Figure 42. L6986F synchronization driving capability
In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the
normal operation, the external master must drive the SYNCH pin with a clock signal
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48/64 DocID027843 Rev 2
frequency higher than the maximum oscillator spread (refer to Table 6 on page 11) for at
least 10 internal clock cycles.
For example: selecting RFSW = 0 to GND
the device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it
is able to synchronize to a clock signal in the range 275 kHz - 1.4 MHz (see Figure 41).
Anyway it is suggested to limit the frequency range within ± 20% FSW resistor nominal
frequency (see details in text below). If not spread spectrum is required, all the regulators
synchronize to a frequency higher to the maximum oscillator spread (550 kHz in the
example).
The device keeps operating in slave mode as far as the master is able to drive the SYNCH
pin faster than 275 kHz (maximum oscillator spread for 250 kHz oscillator), otherwise it goes
back into MASTER mode at the nominal oscillator frequency after successfully driving one
pulse at 250 kHz (see Figure 43) in the SYNCH line.
Figure 43. Slave to master mode transition
The external master can force a latched SLAVE mode driving the SYNCH pin low at power-
up, before the soft-start starts the switching activity. So the oscillator frequency is 250 kHz
typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise
counts to design the slope compensation. The same considerations above are also valid.
Table 10. Example of oscillator frequency selection from Table 6
Symbol RVCC (E24 series) RGND (E24 series) fSW min. fSW typ. fSW max.
fSW NC 0 450 500 550
250kHz typ.
SLAVE mode stand alone operation at nominal fsw
SYNCH signal
switching node
DocID027843 Rev 2 49/64
L6986F Application notes
64
The master driving capability must be able to provide the proper signal levels at the SYNCH
pin (see Table 5 on page 8 - Synchronization section):
Low level < VSYN THL= 0.7 V sinking 5 mA
High level > VSYN THH = 1.2 V sourcing 0.7 mA
Figure 44. Master driving capability to synchronize the L6986F
As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the
slope compensation is dimensioned accordingly with FSW resistors so, even if the L6986F
supports synchronization over the 275 kHz - 1.4 MHz frequency range, it is important to limit
the switching operation around a working point close to the selected frequency (FSW
resistor).
As a consequence, to guarantee the full output current capability and to prevent the
subharmonic oscillations the master must limit the driving frequency range within ± 20% of
the selected frequency.
A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the
peak current capability (see IPK parameter in Tabl e 5) since the internal slope compensation
signal may be saturated.
In order to guarantee the synchronization as a slave over distribution, temperature and the
output load, the external clock frequency must be lower than 1.4 MHz.
Application notes L6986F
50/64 DocID027843 Rev 2
6.6 Design of the power components
6.6.1 Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage
of the application. During the switching activity a pulsed current flows into the input capacitor
and so its RMS current capability must be selected accordingly with the application
conditions. Internal losses of the input filter depends on the ESR value so usually low ESR
capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so
contributes to higher conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 44
Where IOUT is the maximum DC output current, D is the duty cycles,
is the efficiency. This
function has a maximum at D = 0.5 and, considering = 1, it is equal to IOUT/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 45
Equation 46
Where
VHIGH_SIDE and
VLOW_SIDE are the voltage drops across the embedded switches.
The peak-to-peak voltage across the input filter can be calculated as:
Equation 47
In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target
VPP can be written as follows:
Equation 48
IRMS IOUT 1D
----–
D
----=
DMAX
VOUT VLOWSIDE
+
VINMIN VLOWSIDE VHIGHSIDE
–+
------------------------------------------------------------------------------------------------=
DMIN
VOUT VLOWSIDE
+
VINMAX VLOWSIDE VHIGHSIDE
–+
--------------------------------------------------------------------------------------------------=
VPP
IOUT
CIN fSW
-------------------------1D
----–
D
---- ESR IOUT IL
++=
CIN
IOUT
VPP fSW
--------------------------1D
----–
D
----=
DocID027843 Rev 2 51/64
L6986F Application notes
64
Considering this function has its maximum in D = 0.5:
Equation 49
Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter
in the order of 5% VIN_MAX.
6.6.2 Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage
ripple (please refer to Section 6.6.3). Usually the inductor value is selected in order to keep
the current ripple lower than 20% - 40% of the output current over the input voltage range.
The inductance value can be calculated by Equation 50:
Equation 50
Where TON and TOFF are the on and off time of the internal power switch. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 6.6.1: Input capacitor selection to calculate minimum duty). So fixing IL = 20%
to 40% of the maximum output current, the minimum inductance value can be calculated:
Equation 51
where fSW is the switching frequency 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IOUT = 2 A and fSW = 500 kHz the minimum
inductance value to have IL = 30% of IOUT is about 8.2 µH.
The peak current through the inductor is given by:
Equation 52
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
Table 11. Input capacitors
Manufacturer Series Size Cap value (F) Rated voltage (V)
TDK
C3225X7S1H106M 1210 10 50
C3216X5R1H106M 1206
Taiyo Yuden UMK325BJ106MM-T 1210
CINMIN
IOUT
4V
PPMAX fSW
----------------------------------------------=
IL
VIN VOUT
–
L
------------------------------TON
VOUT
L
-------------- TOFF
==
LMIN
VOUT
ILMAX
------------------- 1D
MIN
–
FSW
-----------------------=
ILPKIOUT
IL
2
--------+=
Application notes L6986F
52/64 DocID027843 Rev 2
In Table 12 some inductor part numbers are listed.
6.6.3 Output capacitor selection
The triangular shape current ripple (with zero average value) flowing into the output
capacitor gives the output voltage ripple, that depends on the capacitor value and the
equivalent resistive component (ESR). As a consequence the output capacitor has to be
selected in order to have a voltage ripple compliant with the application requirements.
Table 12. Inductors
Manufacturer Series Inductor value (H) Saturation current (A)
Coilcraft XAL50xx 2.2 to 22 6.5 to 2.7
XAL60xx 2.2 to 22 12.5 to 4
DocID027843 Rev 2 53/64
L6986F Application notes
64
The voltage ripple equation can be calculated as:
Equation 53
Usually the resistive component of the ripple can be neglected if the selected output
capacitor is a multi layer ceramic capacitor (MLCC).
The output capacitor is important also for loop stability: it determines the main pole and the
zero due to its ESR. (see Section 5: Closing the loop on page 35 to consider its effect in the
system stability).
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.6 A, fSW = 500 kHz (resulting by the
inductor value) and COUT = 10 F MLCC:
Equation 54
The output capacitor value has a key role to sustain the output voltage during a steep load
transient. When the load transient slew rate exceeds the system bandwidth, the output
capacitor provides the current to the load. In case the final application specifies high slew
rate load transient, the system bandwidth must be maximized and the output capacitor has
to sustain the output voltage for time response shorter than the loop response time.
In Table 13 some capacitor series are listed.
Table 13. Output capacitors
Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)
MURATA
GRM32 22 to 100 6.3 to 25 < 5
GRM31 10 to 47 6.3 to 25 < 5
PANASONIC
ECJ 10 to 22 6.3 < 5
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 < 5
VOUT ESR ILMAX
ILMAX
8C
OUT fSW
---------------------------------------+=
VOUT
VOUT
------------------ 1
VOUT
-------------- ILMAX
COUT fSW
------------------------------ 1
33
------ 06
810F 500kHz
--------------------------------------------------
15mV
3.3
----------------0.45%===
Application board L6986F
54/64 DocID027843 Rev 2
7 Application board
The reference evaluation board schematic is shown in Figure 45.
Figure 45. Evaluation board schematic
The additional input filter (C16, L3, C15, L2, C14) limits the conducted emission on the
power supply.
TJHOBM(/%
QPXFS(/%
7
7*/@'-5
1(/%
7*/@'-5
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6 -'
345
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4:/$)
'48
.-'
$0.1
%&-":
'#
4(/%
1(/% 1(/%
-9
-9
7*/
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&1
-
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$ V' 7
$ V'7
51 345
$
O'
- V)
+
3 L
3 /.
$
O'
- V)
$ /.
3
/.
51
44*/)
-" /.
3 L
$ /.
$ V' 7
3 +
51
7*/
51 (/%
+
51
(/%
3
$ V'
51 7065
$ Q
3 .
51
7*/@&.*
3 /.
$ V'
$" /.
+
$ V'
$
O'
$ V' 7
$
/.
$ Q
51
4:/$)
3 /.
3 L
+
3
".
Table 14. Bill of material
Reference Part number Description Manufacturer
C1, C9, C10 CGA5L3X5R1H106K 10 F - 1206 - 50 V - X5R - 10% TDK
C2 C2012X7S2A105K 1 F - 0805 - 50 V - X7S - 10% TDK
C3 470 nF - 50 V - 0603
C4 2.2 pF - 50 V - 0603
C5 68 nF - 50 V - 0603
C6 10 nF - 50 V - 0603
C7 Not mounted
C8 220 pF - 50V - 0603
C14, C15, C16 C3216X7R1H475K 4.7 F - 1206 - 50 V - X7R - 10% TDK
C11, C13, C13A Not mounted
R1, R4 0 - 0603
R6 1 M - 1%- 0603
R7 82 k - 1% - 0603
R8 75 k - 1% - 0603
DocID027843 Rev 2 55/64
L6986F Application board
64
Figure 46 and Figure 47 show the magnitude and phase margin Bode’s plots related
toTable 14.
The small signal dynamic performance in this configuration is:
Equation 55
R9 240 k - 1% - 0603
R11 10 - 1% - 0603
R2, R3, R5, R10 Not mounted
L1 XAL5050-682MEC 6.8 HCoilcraft
L2 XAL4030-472MEC 4.7 HCoilcraft
L3 MPZ2012S221A EMC bead TDK
J1 Open
J2 Open
J3 Closed Switchover enabled
J4 Open
J5 To adjust the ISKIP current level in
LCM operation. Leave open in LNM
U1 L6986F STM
Table 14. Bill of material (continued)
Reference Part number Description Manufacturer
BW 58kHz =
phase margin 670
=
Application board L6986F
56/64 DocID027843 Rev 2
Figure 46. Magnitude Bode’s plot
Figure 47. Phase margin Bode’s plot
DocID027843 Rev 2 57/64
L6986F Application board
64
Figure 48. Top layer
Figure 49. Bottom layer
Efficiency curves L6986F
58/64 DocID027843 Rev 2
8 Efficiency curves
Figure 50. Efficiency: VIN = 13.5 V - VOUT = 3.3 V - fsw = 500 kHz
Figure 51. Efficiency curves: VIN = 13.5 V - VOUT = 3.3 V - fsw = 500 kHz (log scale)
Figure 52. Efficiency curves: VIN = 13.5 V - VOUT = 5 V - fsw = 500 kHz
DocID027843 Rev 2 59/64
L6986F Efficiency curves
64
Figure 53. Efficiency curves: VIN = 13.5 V - VOUT = 5 V - fsw = 500 kHz (log scale)
Figure 54. Efficiency curves: VIN = 24 V - VOUT = 3.3 V - fsw = 500 kHz
Figure 55. Efficiency curves: VIN = 24 V - VOUT = 3.3 V - fsw = 500 kHz (log scale)
Efficiency curves L6986F
60/64 DocID027843 Rev 2
Figure 56. Efficiency curves: VIN = 24 V - VOUT = 5 V - fsw = 500 kHz
Figure 57. Efficiency curves: VIN = 24 V - VOUT = 5 V - fsw = 500 kHz (log scale)
DocID027843 Rev 2 61/64
L6986F Package information
64
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
9.1 HTSSOP16 package information
Figure 58. HTSSOP16 package outline
Package information L6986F
62/64 DocID027843 Rev 2
. Table 15. HTSSOP16 package mechanical data
Symbol
Dimensions (mm)
Min. Typ. Max.
A1.20
A1 0.15
A2 0.80 1.00 1.05
b 0.19 0.30
c 0.09 0.20
D 4.90 5.00 5.10
D12.833.2
E 6.20 6.40 6.60
E1 4.30 4.40 4.50
E22.833.2
e0.65
L 0.45 0.60 0.75
L1 1.00
k 0.00 8.00
aaa 0.10
DocID027843 Rev 2 63/64
L6986F Order codes
64
10 Order codes
11 Revision history
Table 16. Order codes
Part numbers Package Packaging
L6986F
HTSSOP16
Tube
L6986FTR Tape and reel
Table 17. Document revision history
Date Revision Changes
06-May-2015 1 Initial release.
18-Feb-2016 2
Updated Table 3: Thermal data on page 7 (added Rth JC).
Updated Table 6: fSW selection on page 11 (added note 2.
below table).
Updated Section 6.5: Synchronization (LNM) on page 45
(replaced value of “range” “2 MHz” by “1.4 MHz”, added text).
L6986F
64/64 DocID027843 Rev 2
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