10-/12-/14-Bit, 125 MSPS
Dual TxDAC+ Digital-to-Analog Converters
Data Sheet AD9763/AD9765/AD9767
FEATURES
10-/12-/14-bit dual transmit digital-to-analog converters (DACs)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual-port or interleaved data
On-chip 1.2 V reference
5 V or 3.3 V operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
GENERAL DESCRIPTION
The AD9763/AD9765/AD9767 are dual-port, high speed,
2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates
two high quality TxDAC+® cores, a voltage reference, and digital
interface circuitry into a small 48-lead LQFP. The AD9763/
AD9765/AD9767 offer exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9763/AD9765/AD9767 have been optimized for
processing I and Q data in communications applications. The
digital interface consists of two double-buffered latches as well
as control logic. Separate write inputs allow data to be written to
the two DAC ports independent of one another. Separate clocks
control the update rate of the DACs.
A mode control pin allows the AD9763/AD9765/AD9767 to
interface to two separate data ports, or to a single interleaved
high speed data port. In interleaving mode, the input data
stream is demuxed into its original I and Q data and then
latched. The I and Q data is then converted by the two DACs
and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the
Gain Control Mode section for important date code
information on this feature.
FUNCTIONAL BLOCK DIAGRAM
1
LATCH
1
DAC
BIAS
GENERATOR SLEEP
DIGITAL
INTERFACE
AD9763/
AD9765/
AD9767
PORT1
PORT2
MODE
2
DAC
2
LATCH IOUTB2
IOUTA2
IOUTB1
IOUTA1
CLK1AVDD ACOM
GAINCTRL
FSADJ2
FSADJ1
REFIO
REFERENCE
00617-001
WRT1/IQWRT
WRT2/IQSEL
CLK2/IQ RESET
DCOM1/
DCOM2
DVDD1/
DVDD2
Figure 1.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or dif-
ferential applications. Both DACs of the AD9763, AD9765, or
AD9767 can be simultaneously updated and can provide a
nominal full-scale current of 20 mA. The full-scale currents
between each DAC are matched to within 0.1%.
The AD9763/AD9765/AD9767 are manufactured on an
advanced, low cost CMOS process. They operate from a single
supply of 3.3 V to 5 V and consume 380 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9763/AD9765/AD9767 are members of a pin-
compatible family of dual TxDACs providing 8-, 10-, 12-,
and 14-bit resolution.
2. Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high
performance DACs for each part is optimized for low
distortion performance and provides flexible transmission
of I and Q information.
3. Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
4. Low Power. Complete CMOS dual DAC function operates on
380 mW from a 3.3 V to 5 V single supply. The DAC full-scale
current can be reduced for lower power operation, and a sleep
mode is provided for low power idle periods.
5. On-Chip Voltage Reference. The AD9763/AD9765/AD9767
each include a 1.20 V temperature-compensated band gap
voltage reference.
6. Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767
each feature a flexible dual-port interface, allowing dual or
interleaved input data.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1999-2011 Analog Devices, Inc. All rights reserved.
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 2 of 44
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Dynamic Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
AD9763........................................................................................ 11
AD9765........................................................................................ 14
AD9767........................................................................................ 17
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Functional Description.............................................................. 21
Reference Operation .................................................................. 22
Gain Control Mode.................................................................... 22
Setting the Full-Scale Current................................................... 22
DAC Transfer Function ............................................................. 23
Analog Outputs........................................................................... 23
Digital Inputs .............................................................................. 24
DAC Timing................................................................................ 24
Sleep Mode Operation............................................................... 26
Power Dissipation....................................................................... 26
Applying the AD9763/AD9765/AD9767.................................... 28
Output Configurations .............................................................. 28
Differential Coupling Using a Transformer............................ 28
Differential Coupling Using an Op Amp................................ 28
Single-Ended, Unbuffered Voltage Output............................. 29
Single-Ended, Buffered Voltage Output Configuration........ 29
Power and Grounding Considerations.................................... 29
Applications Information.............................................................. 31
VDSL Example Applications Using the
AD9765 and AD9767 ................................................................ 31
Quadrature Amplitude Modulation (QAM) Example Using
the AD9763 ................................................................................. 32
CDMA ......................................................................................... 33
Evaluation Board ............................................................................ 34
General Description................................................................... 34
Schematics................................................................................... 34
Evaluation Board Layout........................................................... 40
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
Revision History: AD9763/AD9765/AD9767
8/11—Rev. F to Rev. G
Changes to Gain Control Mode Section and Setting the Full-
Scale Current Section..................................................................... 22
Changes to DAC Transfer Function Section............................... 23
Changes to Power Supply Rejection Section............................... 29
6/09—Rev. E to Rev. F
Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91,
Deleted Original Figure 91 to Figure 94...................................... 34
1/08—Revision E: Initial Combined Version
Revision History: AD9763
1/08—Rev. D to Rev. E
Combined with AD9765 and AD9767 Data Sheets.......Universal
Changes to Figure 1...........................................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Added Figure 4 and Figure 5............................................................9
Changes to Table 6.......................................................................... 10
Change to Typical Performance Characteristics Section
Conditions Statement .................................................................... 11
Added Figure 23 to Figure 56 ....................................................... 14
Added Note to Figure 58 ............................................................... 20
Changes to Functional Description Section ............................... 22
Changes to Figure 59 and Figure 60............................................. 22
Changes to Gain Control Mode Section ..................................... 22
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 3 of 44
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section.......................................................22
Changes to DAC Transfer Section ................................................23
Change to Analog Outputs Section ..............................................24
Changes to Dual-Port Mode Timing............................................24
Changes to Interleaved Mode Timing Section............................25
Added Figure 64 ..............................................................................25
Change to Differential Coupling Using a Transformer Section .....28
Changes to Power and Grounding Considerations Section............30
Added VDSL Example Applications Using the AD9765 and
AD9767 Section...............................................................................31
Added Figure 79 to Figure 82 ........................................................31
Changes to Figure 84 ......................................................................32
Changes to CDMA Section............................................................33
Changes to Figure 85 Caption .......................................................33
Changes to Figure 86 ......................................................................34
Changes to Figure 88 ......................................................................36
Changes to Ordering Guide...........................................................40
9/06—Rev. C to Rev. D
Updated Format.................................................................. Universal
Renumbered Figures..........................................................Universal
Changes to Specifications Section...................................................3
Changes to Applications Section...................................................21
Updated Outline Dimensions........................................................32
Changes to Ordering Guide...........................................................32
10/01—Rev. B to Rev. C
Changes to Figure 29 ......................................................................21
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
Revision History: AD9765
1/08—Rev. C to Rev. E
Combined with AD9763 and AD9767 Data Sheets ...... Universal
Changes to Figure 1...........................................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Change to Absolute Maximum Ratings .........................................8
Added Figure 3 and Figure 5 ...........................................................9
Changes to Table 6 ..........................................................................10
Added Figure 6 to Figure 22 ..........................................................11
Added Figure 40 to Figure 56 ........................................................17
Added Note to Figure 58 ................................................................20
Changes to Functional Description Section ................................22
Changes to Reference Operation Section ....................................22
Changes to Figure 59 and Figure 60 .............................................22
Changes to Gain Control Mode Section ......................................22
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section.......................................................22
Changes to DAC Transfer Section ................................................23
Changes to Interleaved Mode Timing Section............................25
Added Figure 64 ..............................................................................25
Changes to Power and Grounding Considerations Section............30
Added Figure 80 and Figure 82 .....................................................31
Changes to Quadrature Amplitude Modulation (QAM)
Example Using the AD9763 Section.............................................32
Changes to Figure 83 and Figure 84 .............................................32
Changes to CDMA Section............................................................33
Changes to Figure 85 Caption .......................................................33
Changes to Figure 86 ......................................................................34
Changes to Figure 88 ......................................................................36
Changes to Ordering Guide...........................................................40
9/06—Rev. B to Rev. C
Updated Format ................................................................. Universal
Changes to Figure 2 ..........................................................................5
Changes to Figure 3 ..........................................................................7
Changes to Functional Description Section................................12
Changes to Figure 25 and Figure 26 .............................................15
Changes to Figure 28 and Figure 29 .............................................16
Changes to Power Dissipation Section.........................................17
Changes to Power and Grounding Considerations Section......19
Changes to Figure 39 ......................................................................19
Changes to Figure 45 ......................................................................22
Changes to Evaluation Board Section ..........................................24
Changes to Figure 47 ......................................................................24
Updated Outline Dimensions........................................................30
Changes to Ordering Guide...........................................................30
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
8/99—Revision 0: Initial Version
Revision History: AD9767
1/08—Rev. C to Rev. E
Combined with AD9763 and AD9765 Data Sheets ...... Universal
Changes to Figure 1 ..........................................................................1
Changes to Features Section............................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Change to Absolute Maximum Ratings .........................................8
Added Figure 3 and Figure 4 ...........................................................9
Changes to Table 6 ..........................................................................10
Added Figure 6 to Figure 39 ..........................................................11
Added Note to Figure 58................................................................20
Changes to Functional Description Section................................22
Changes to Reference Operation Section ....................................22
Changes to Figure 59 and Figure 60 .............................................22
Changes to Gain Control Mode Section......................................22
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section ......................................................22
Changes to DAC Transfer Section ................................................23
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 4 of 44
Changes to Dual-Port Mode Timing ........................................... 24
Changes to Interleaved Mode Timing Section ........................... 25
Added Figure 64.............................................................................. 25
Change to Differential Coupling Using a Transformer Section......28
Changes to Power and Grounding Considerations Section............30
Added Figure 79 and Figure 81..................................................... 31
Added to Quadrature Amplitude Modulation (QAM)
Example Using the AD9763 Section............................................ 32
Added Figure 83 and Figure 84..................................................... 32
Changes to CDMA Section ........................................................... 33
Changes to Figure 85 Caption....................................................... 33
Changes to Figure 86...................................................................... 34
Changes to Figure 88...................................................................... 36
Changes to Ordering Guide .......................................................... 40
10/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 2...........................................................................5
Changes to Figure 3...........................................................................7
Changes to Functional Description Section ............................... 12
Changes to Figure 25 and Figure 26............................................. 15
Changes to Figure 28 and Figure 29............................................. 16
Changes to Power Dissipation Section ........................................ 18
Changes to Figure 39...................................................................... 19
Changes to Power and Grounding Considerations Section ..... 19
Changes to Figure 45...................................................................... 22
Changes to Figure 47...................................................................... 24
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide.......................................................... 28
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
8/99—Revision 0: Initial Version
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 5 of 44
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
AD9763 AD9765 AD9767
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 10 12 14 Bits
DC ACCURACY1
Integral Linearity Error (INL) −1 ±0.1 +1 LSB
TA = 25°C −1.5 ±0.4 +1.5 −3.5 ±1.5 +3.5 LSB
TMIN to TMAX −2.0 +2.0 −4.0 +4.0 LSB
Differential Nonlinearity (DNL) LSB
TA = 25°C −0.5 ±0.07 +0.5 −0.75 ±0.3 +0.75 −2.5 ±1.0 +2.5 LSB
TMIN to TMAX −1.0 +1.0 −3.0 +3.0 LSB
ANALOG OUTPUT
Offset Error −0.02 +0.02 −0.02 +0.02 −0.02 +0.02 % of FSR
Gain Error Without Internal Reference −2 ±0.25 +2 −2 ±0.25 +2 −2 ±0.25 +2 % of FSR
Gain Error with Internal Reference −5 ±1 +5 −5 ±1 +5 −5 ±1 +5 % of FSR
Gain Match −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 % of FSR
−0.14 +0.14 −0.14 +0.14 −0.14 +0.14 dB
Full-Scale Output Current2 2.0 20.0 2.0 20.0 2.0 20.0 mA
Output Compliance Range −1.0 +1.25 −1.0 +1.25 −1.0 +1.25 V
Output Resistance 100 100 100 kΩ
Output Capacitance 5 5 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 1.14 1.20 1.26 1.14 1.20 1.26 V
Reference Output Current3 100 100 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 0.1 1.25 0.1 1.25 V
Reference Input Resistance 1 1 1 MΩ
Small-Signal Bandwidth 0.5 0.5 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 0 0 ppm of FSR/°C
Gain Drift Without Internal Reference ±50 ±50 ±50 ppm of FSR/°C
Gain Drift with Internal Reference ±100 ±100 ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ±50 ±50 ppm/°C
POWER SUPPLY
Supply Voltages
AVDD 3 5 5.5 3 5 5.5 3 5 5.5 V
DVDD1, DVDD2 2.7 5 5.5 2.7 5 5.5 2.7 5 5.5 V
Analog Supply Current (IAVDD) 71 75 71 75 71 75 mA
Digital Supply Current (IDVDD)4 5 7 5 7 5 7 mA
Digital Supply Current (IDVDD)5 15 15 15 mA
Supply Current Sleep Mode (IAVDD) 8 12.0 8 12.0 8 12.0 mA
Power Dissipation4 (5 V, IOUTFS = 20 mA) 380 410 380 410 380 410 mW
Power Dissipation5 (5 V, IOUTFS = 20 mA) 420 450 420 450 420 450 mW
Power Dissipation6 (5 V, IOUTFS = 20 mA) 450 450 450 mW
Power Supply Rejection Ratio7—AVDD –0.4 +0.4 –0.4 +0.4 –0.4 +0.4 % of FSR/V
Power Supply Rejection Ratio7—DVDD –0.025 +0.025 –0.025 +0.025 –0.025 +0.025 % of FSR/V
OPERATING RANGE –40 +85 –40 +85 –40 +85 °C
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4 Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz.
5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz.
6 Measured as unbuffered voltage output with IOUTFS = 20 mA and RLOAD = 50 Ω at IOUTA and IOUTB, fCLK = 100 MSPS, and fOUT = 40 MHz.
7 ±10% power supply variation.
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 6 of 44
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω
doubly terminated, unless otherwise noted.
Table 2.
AD9763 AD9765 AD9767
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLK) 125 125 125 MSPS
Output Settling Time (tST) to 0.1%1 35 35 35 ns
Output Propagation Delay (tPD) 1 1 1 ns
Glitch Impulse 5 5 5 pV-s
Output Rise Time (10% to 90%)1 2.5 2.5 2.5 ns
Output Fall Time (90% to 10%)1 2.5 2.5 2.5 ns
Output Noise (IOUTFS = 20 mA) 50 50 50 pA/√Hz
Output Noise (IOUTFS = 2 mA) 30 30 30 pA/√Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLK = 100 MSPS, fOUT = 1.00 MHz
0 dBFS Output 69 78 70 81 71 82 dBc
–6 dBFS Output 74 77 77 dBc
–12 dBFS Output 69 72 73 dBc
–18 dBFS Output 61 70 70 dBc
fCLK = 65 MSPS, fOUT = 1.00 MHz 79 81 82 dBc
fCLK = 65 MSPS, fOUT = 2.51 MHz 78 79 80 dBc
fCLK = 65 MSPS, fOUT = 5.02 MHz 75 78 79 dBc
fCLK = 65 MSPS, fOUT = 14.02 MHz 66 68 70 dBc
fCLK = 65 MSPS, fOUT = 25 MHz 55 55 55 dBc
fCLK = 125 MSPS, fOUT = 25 MHz 67 67 67 dBc
fCLK = 125 MSPS, fOUT = 40 MHz 60 60 70 dBc
Spurious-Free Dynamic Range Within a Window
fCLK = 100 MSPS, fOUT = 1.00 MHz; 2 MHz Span 78 85 80 90 82 91 dBc
fCLK = 50 MSPS, fOUT = 5.02 MHz; 10 MHz Span 80 88 88 dBc
fCLK = 65 MSPS, fOUT = 5.03 MHz; 10 MHz Span 82 88 88 dBc
fCLK = 125 MSPS, fOUT = 5.04 MHz; 10 MHz Span 82 88 88 dBc
Total Harmonic Distortion
fCLK = 100 MSPS, fOUT = 1.00 MHz −77 −69 −80 –70 −81 −71 dBc
fCLK = 50 MSPS, fOUT = 2.00 MHz −77 −78 −79 dBc
fCLK = 125 MSPS, fOUT = 4.00 MHz −74 −75 −83 dBc
fCLK = 125 MSPS, fOUT = 10.00 MHz −72 −75 −80 dBc
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output 76 80 80 dBc
−6 dBFS Output 74 79 79 dBc
−12 dBFS Output 71 77 78 dBc
−18 dBFS Output 67 75 76 dBc
Channel Isolation
fCLK = 125 MSPS, fOUT = 10 MHz 85 85 85 dBc
fCLK = 125 MSPS, fOUT = 40 MHz 77 77 77 dBc
1 Measured single-ended into 50 Ω load.
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 7 of 44
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V 3.5 5 V
Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V 2.1 3 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V 0 1.3 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V 0 0.9 V
Logic 1 Current −10 +10 μA
Logic 0 Current −10 +10 μA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (tLPW, tCPW) 3.5 ns
Timing Diagram
See Table 3 and the DAC Timing section for more information about the timing specifications.
DATA IN
(WRT2) (WRT1/IQWRT)
(CLK2) (CLK1/IQCLK)
t
PD
I
OUTA
OR
I
OUTB
t
S
t
H
t
LPW
t
CPW
00617-002
Figure 2. Timing Diagram for Dual and Interleaved Modes
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 8 of 44
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4. θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
With
Respect To Rating
AVDD ACOM −0.3 V to +6.5 V
DVDD1, DVDD2 DCOM1/DCOM2 −0.3 V to +6.5 V
ACOM DCOM1/DCOM2 −0.3 V to +0.3 V
AVDD DVDD1/DVDD2 −6.5 V to +6.5 V
MODE,
CLK1/IQCLK,
CLK2/IQRESET,
WRT1/IQWRT,
WRT2/IQSEL
DCOM1/DCOM2 −0.3 V to DVDD1/
DVDD2 + 0.3 V
Digital Inputs DCOM1/DCOM2 −0.3 V to DVDD1/
DVDD2 + 0.3 V
IOUTA1/IOUTA2,
IOUTB1/IOUTB2
ACOM −1.0 V to AVDD + 0.3 V
REFIO, FSADJ1,
FSADJ2
ACOM −0.3 V to AVDD + 0.3 V
GAINCTRL, SLEEP ACOM −0.3 V to AVDD + 0.3 V
Junction
Temperature
150°C
Storage
Temperature
Range
−65°C to +150°C
Lead Temperature
(10 sec)
300°C
Table 5. Thermal Resistance
Package Type θJA Unit
48-Lead LQFP 91 °C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Data Sheet AD9763/AD9765/AD9767
| Page 9 of 44
48
MODE
Rev. G
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
47
AVDD
46
IOUTA1
45
IOUTB1
44
FSADJ1
43
REFIO
42
GAINCTRL
41
FSADJ2
40
IOUTB2
39
IOUTA2
38
ACOM
37
SLEEP
35 NC
34 NC
33 NC
30 DB2P2
31 DB1P2
32 DB0P2 (LSB)
36 NC
29 DB3P2
28 DB4P2
27 DB5P2
25 DB7P2
26 DB6P2
2
DB8P1
3
DB7P1
4
DB6P1
7
DB3P1
6
DB4P1
5
DB5P1
1
DB9P1 (MSB)
8
DB2P1
9
DB1P1
10
DB0P1 (LSB)
12
NC
11
NC
NC = NO CONNECT
13
NC
14
NC
15
DCOM1
16
DVDD1
17
WRT1/IQWRT
18
CLK1/IQCLK
19
CLK2/IQRESET
20
WRT2/IQSEL
21
DCOM2
22
DVDD2
23
DB9P2 (MSB)
24
DB8P2
PIN 1
AD9763
TOP VIEW
(Not to Scale)
0
0617-003
48
MODE
Figure 3. AD9763 Pin Configuration
47
AVDD
46
I
OUTA1
45
I
OUTB1
44
FSADJ1
43
REFIO
42
GAINCTRL
41
FSADJ2
40
I
OUTB2
39
I
OUTA2
38
ACOM
37
SLEEP
35
NC
34
DB0P2 (LSB)
33
DB1P2
30
DB4P2
31
DB3P2
32
DB2P2
36
NC
29
DB5P2
28
DB6P2
27
DB7P2
25
DB9P2
26
DB8P2
2
DB10P1
3
DB9P1
4
DB8P1
7
DB5P1
6
DB6P1
5
DB7P1
1
DB11P1 (MSB)
8
DB4P1
9
DB3P1
10
DB2P1
12
DB0P1 (LSB)
11
DB1P1
13
NC = NO CONNECT
NC
14
NC
15
DCOM1
16
DVDD1
17
WRT1/IQWRT
18
CLK1/IQCLK
19
CLK2/IQRESET
20
WRT2/IQSEL
21
DCOM2
22
DVDD2
23
DB11P2 (MSB)
24
PIN 1
AD9765
TOP VIEW
(Not to Scale)
DB10P2
0
0617-004
Figure 4. AD9765 Pin Configuration
48
MODE
47
AVDD
46
I
OUTA1
45
I
OUTB1
44
FSADJ1
43
REFIO
42
GAINCTRL
41
FSADJ2
40
I
OUTB2
39
I
OUTA2
38
ACOM
37
SLEEP
35
DB1P2
34
DB2P2
33
DB3P2
30
DB6P2
31
DB5P2
32
DB4P2
36
DB0P2 (LSB)
29
DB7P2
28
DB8P2
27
DB9P2
25
DB11P2
26
DB10P2
2
DB12P1
3
DB11P1
4
DB10P1
7
DB7P1
6
DB8P1
5
DB9P1
1
DB13P1 (MSB)
8
DB6P1
9
DB5P1
10
DB4P1
12
DB2P1
11
DB3P1
13
DB1P1
14
DB0P1 (LSB)
15
DCOM1
16
DVDD1
17
WRT1/IQWRT
18
CLK1/IQCLK
19
CLK2/IQRESET
20
WRT2/IQSEL
21
DCOM2
22
DVDD2
23
DB13P2 (MSB)
24
DB12P2
PIN 1
AD9767
TOP VIEW
(Not to Scale)
0
0617-005
Figure 5. AD9767 Pin Configuration
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 10 of 44
Table 6. Pin Function Descriptions
Pin No.
AD9763 AD9765 AD9767 Mnemonic Description
1 to 10 1 to 12 1 to 14 DBxP1 Data Bit Pins (Port 1)
11 to 14,
33 to 36
13, 14,
35, 36
N/A NC No Connect
15, 21 15, 21 15, 21 DCOM1, DCOM2 Digital Common
16, 22 16, 22 16, 22 DVDD1, DVDD2 Digital Supply Voltage
17 17 17 WRT1/IQWRT Input Write Signal for PORT 1 (IQWRT in Interleaving Mode)
18 18 18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode)
19 19 19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode)
20 20 20 WRT2/IQSEL Input Write Signal for PORT 2 (IQSEL in Interleaving Mode)
23 to 32 23 to 34 23 to 36 DBxP2 Data Bit Pins (Port 2)
37 37 37 SLEEP Power-Down Control Input
38 38 38 ACOM Analog Common
39, 40 39, 40 39, 40 IOUTA2, IOUTB2 Port 2 Differential DAC Current Outputs
41 41 41 FSADJ2 Full-Scale Current Output Adjust for DAC2
42 42 42 GAINCTRL Master/Slave Resistor Control Mode
43 43 43 REFIO Reference Input/Output
44 44 44 FSADJ1 Full-Scale Current Output Adjust for DAC1
45, 46 45, 46 45, 46 IOUTB1, IOUTA1 Port 1 Differential DAC Current Outputs
47 47 47 AVDD Analog Supply Voltage
48 48 48 MODE Mode Select (1 = dual port, 0 = interleaved)
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 11 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
AD9763
AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist,
unless otherwise noted.
90
80
50
f
CLK
= 5MSPS
60
70
SFDR (dBc)
1 10 100
f
OUT
(MHz)
f
CLK
= 25MSPS
f
CLK
= 65MSPS
f
CLK
= 125MSPS
00617-006
Figure 6. SFDR vs. fOUT @ 0 dBFS
80
75
70
65
0dBFS
SFDR (dBc)
–6dBFS
–12dBFS
0 0.5 1.0 1.5 2.0 2.5
f
OUT
(MHz)
00617-007
Figure 7. SFDR vs. fOUT @ 5 MSPS
02 1246810
60
80
75
70
65
0dBFS
SFDR (dBc)
f
OUT
(MHz)
–12dBFS
–6dBFS
00617-008
Figure 8. SFDR vs. fOUT @ 25 MSPS
50
80
75
70
60
55
65
SFDR (dBc)
0 5 10 15 20 25 30 35
fOUT
(MHz)
0dBFS
–6dBFS
–12dBFS
00617-009
Figure 9. SFDR vs. fOUT @ 65 MSPS
50
80
75
70
60
55
65
SFDR (dBc)
0 10203040506070
f
OUT
(MHz)
0dBFS
–6dBFS
–12dBFS
0
0617-010
Figure 10. SFDR vs. fOUT @ 125 MSPS
50
80
75
70
60
55
65
SFDR (dBc)
I
OUTFS
= 20mA
I
OUTFS
= 10mA
I
OUTFS
= 5mA
0 5 10 15 20 25 30 35
f
OUT
(MHz)
0
0617-011
Figure 11. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 12 of 44
55
85
60
70
65
75
80
5.91MHz/65MSPS
11.37MHz/125MSPS
910kHz/10MSPS
2.27MHz/25MSPS
SFDR (dBc)
–20 –16 –12 –8 –4 0
AOUT (dBFS)
0
0617-012
Figure 12. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
60
80
65
70
55
75
85
SFDR (dBc)
–20 –16 –12 –8 –4 0
AOUT (dBFS)
5MHz/25MSPS
1MHz/5MSPS
2MHz/10MSPS
13MHz/65MSPS
25MHz/125MSPS
00617-013
Figure 13. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
80
70
55
65
75
60
6.75MHz/7.25MHz @ 65MSPS
16.9MHz/18.1MHz @ 125MSPS
SFDR (dBc)
–20 –16 –12 –8 –4 0
A
OUT
(dBFS)
3.38MHz/3.36MHz @ 25MSPS
0.965MHz/1.035MHz @ 7MSPS
00617-014
Figure 14. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
55
60
65
70
SINAD (dBc)
fCLK
(MSPS)
20 40 60 80 100 120 140
I
OUTFS
= 20mA
I
OUTFS
= 10mA
I
OUTFS
= 5mA
00617-015
Figure 15. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
CODE
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
INL (LSB)
0 200 400 600 800 1000
0
0617-016
Figure 16. Typical INL
CODE
–0.10
–0.05
0
0.05
0.25
0.30
0.20
0.15
0.10
DNL (LSB)
0 200 400 600 800 1000
00617-017
Figure 17. Typical DNL
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 13 of 44
80
75
50
70
65
60
55
45
85
–60 –40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
SFDR (dBc)
f
OUT
= 1MHz
f
OUT
= 10MHz
f
OUT
= 25MHz
f
OUT
= 40MHz
f
OUT
= 60MHz
00617-018
Figure 18. SFDR vs. Temperature @ fCLK = 125 MSPS, 0 dBFS
0.05
–0.05
0.03
0
–0.03
1.0
–1.0
0.5
0
–0.5
OFFSET ERROR (%FS)
GAIN ERROR (%FS)
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
GAIN ERROR
OFFSET ERROR
00617-019
Figure 19. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
SFDR (dBm)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
FREQUENCY (MHz)
0 1020304
00617-020
0
Figure 20. Single-Tone SFDR @ fCLK = 125 MSPS
SFDR (dBm)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0 1020304
00617-021
0
Figure 21. Dual-Tone SFDR @ fCLK = 125 MSPS
SFDR (dBm)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
0 1020304
00617-022
0
Figure 22. Four-Tone SFDR @ fCLK = 125 MSPS
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 14 of 44
AD9765
AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to
Nyquist, unless otherwise noted.
90
50
60
70
80
110
SFDR (dBc)
fOUT
(MHz)
100
0
0617-023
fCLK
= 125MSPS
fCLK
= 65MSPS
fCLK
= 25MSPS
fCLK
= 5MSPS
Figure 23. SFDR vs. fOUT @ 0 dBFS
95
75
80
85
90
1.00 2.252.001.751.501.25
SFDR (dBc)
f
OUT (MHz)
0dBFS
–6dBFS –12dBFS
0
0617-024
Figure 24. SFDR vs. fOUT @ 5 MSPS
90
85
80
75
70
65
60
01108642
SFDR (dBc)
f
OUT (MHz)
2
0dBFS
–6dBFS
–12dBFS
0
0617-025
Figure 25. SFDR vs. fOUT @ 25 MSPS
85
80
75
70
65
55
60
50
0330252015105
SFDR (dBc)
f
OUT (MHz)
5
0dBFS
–6dBFS
–12dBFS
0
0617-026
Figure 26. SFDR vs. fOUT @ 65 MSPS
85
80
75
70
65
55
60
50
07605040302010
SFDR (dBc)
f
OUT (MHz)
0
0dBFS
–6dBFS
–12dBFS
0
0617-027
Figure 27. SFDR vs. fOUT @ 125 MSPS
85
80
75
70
65
55
60
50
03252015105
SFDR (dBc)
f
OUT (MHz)
0
IOUTFS = 10mA
IOUTFS = 20mA
IOUTFS = 5mA
0
0617-028
Figure 28. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 15 of 44
90
85
80
75
70
65
60
–20 0–5–10–15
SFDR (dBc)
AOUT (dBFS)
0.91MHz/10MSPS
5.91MHz/65MSPS
2.27MHz/25MSPS
11.37MHz/125MSPS
00617-029
Figure 29. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
90
85
80
75
70
65
55
60
–20 0–5–10–15
SFDR (dBc)
AOUT (dBFS)
1MHz/5MSPS
2MHz/10MSPS
5MHz/25MSPS
13MHz/65MSPS
25MHz/125MSPS
00617-030
Figure 30. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
80
75
70
65
55
60
–20 0–5–10–15
SFDR (dBc)
A
OUT
(dBFS)
3.38MHz/3.36MHz@25MSPS
0.965MHz/1.035MHz@7MSPS
6.75MHz/7.25MHz@65MSPS
16.9MHz/18.1MHz@125MSPS
00617-031
Figure 31. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
75
70
65
60
55
20 140120100806040
SINAD (dBc)
f
CLK
(MSPS)
I
OUTFS
= 20mA
I
OUTFS
= 10mA
I
OUTFS
= 5mA
0
0617-032
Figure 32. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
0.6
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 40001000 2000 3000
INL (LSB)
CODE
00617-033
Figure 33. Typical INL
0.05
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0 4000350030002500200015001000500
DNL (LSB)
CODE
00617-034
Figure 34. Typical DNL
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 16 of 44
85
45
50
55
60
65
70
75
80
–60 –40 –20 0 20 40 60 80 100
SFDR (dBc)
TEMPERATURE (°C)
f
OUT
= 1MHz
f
OUT
= 10MHz
f
OUT
= 25MHz
f
OUT
= 40MHz
f
OUT
= 60MHz
00617-035
Figure 35. SFDR vs. Temperature @ 125 MSPS, 0 dBFS
0.05
0.03
0
–0.03
–0.05
1.0
0.5
0
–1.0
–0.5
–40–200 20406080
OFFSET ERROR (%FS)
GAIN ERROR (%FS)
TEMPERATURE (°C)
GAIN ERROR
OFFSET ERROR
00617-036
Figure 36. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
10
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
04302010
SFDR (dBm)
FREQUENCY (MHz)
0
00617-037
Figure 37. Single-Tone SFDR @ fCLK = 125 MSPS
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
04302010
SFDR (dBm)
FREQUENCY (MHz)
0
00617-038
Figure 38. Dual-Tone SFDR @ fCLK = 125 MSPS
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
04302010
SFDR (dBm)
FREQUENCY (MHz)
0
00617-039
Figure 39. Four-Tone SFDR @ fCLK = 125 MSPS
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 17 of 44
AD9767
AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to
Nyquist, unless otherwise noted.
90
50
60
70
80
110
SFDR (dBc)
f
OUT
(MHz)
100
0
0617-040
f
CLK
= 125MSPS
f
CLK
= 65MSPS
f
CLK
= 25MSPS
f
CLK
= 5MSPS
Figure 40. SFDR vs. fOUT @ 0 dBFS
90
75
80
85
022.01.51.00.5
SFDR (dBc)
f
OUT
(MHz)
.5
0dBFS
–6dBFS
–12dBFS
0
0617-041
Figure 41. SFDR vs. fOUT @ 5 MSPS
90
85
80
75
70
65
60
01108642
SFDR (dBc)
f
OUT
(MHz)
2
0dBFS
–6dBFS
–12dBFS
0
0617-042
Figure 42. SFDR vs. fOUT @ 25 MSPS
85
80
75
70
65
55
60
50
0330252015105
SFDR (dBc)
f
OUT
(MHz)
5
0dBFS
–6dBFS
–12dBFS
0
0617-043
Figure 43. SFDR vs. fOUT @ 65 MSPS
85
80
75
70
65
55
60
50
07605040302010
SFDR (dBc)
f
OUT
(MHz)
0
0dBFS
–6dBFS
–12dBFS
0
0617-044
Figure 44. SFDR vs. fOUT @ 125 MSPS
90
85
80
75
70
65
55
60
50
0330252015105
SFDR (dBc)
f
OUT
(MHz)
5
I
OUTFS
= 10mA
I
OUTFS
= 5mA
I
OUTFS
= 20mA
0
0617-045
Figure 45. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 18 of 44
90
85
80
75
70
65
60
–20 0–5–10–15
SFDR (dBc)
A
OUT
(dBFS)
910kHz/10MSPS
5.91MHz/65MSPS
2.27MHz/25MSPS
11.37MHz/125MSPS
00617-046
Figure 46. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
90
85
80
75
70
60
50
65
55
–20 0–5–10–15
SFDR (dBc)
A
OUT
(dBFS)
5MHz/25MSPS
1MHz/5MSPS
2MHz/10MSPS
13MHz/65MSPS
25MHz/125MSPS
00617-047
Figure 47. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
85
80
75
70
65
50
55
60
–25 –20 0–5–10–15
SFDR (dBc)
A
OUT
(dBFS)
3.38MHz/3.63MHz@25MSPS
0.965MHz/1.035MHz@7MSPS
6.75MHz/7.25MHz@65MSPS
16.9MHz/18.1MHz@125MSPS
00617-048
Figure 48. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
75
70
65
60
55
20 140120100806040
SINAD (dBc)
f
CLK
(MSPS)
I
OUTFS
= 20mA
I
OUTFS
= 10mA
I
OUTFS
= 5mA
0
0617-049
Figure 49. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
2.5
2.0
1.5
1.0
0.5
–1.5
–1.0
–0.5
0
0 160004000 8000 12000
INL (LSB)
CODE
00617-050
Figure 50. Typical INL
0.4
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0.2
0
0 1000800600400200
DNL (LSB)
CODE
00617-051
Figure 51. Typical DNL
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 19 of 44
85
45
50
55
60
65
70
75
80
–60 –40 –20 0 20 40 60 80 100
SFDR (dBc)
TEMPERATURE (°C)
f
OUT
= 1MHz
f
OUT
= 10MHz
f
OUT
= 25MHz
f
OUT
= 40MHz
f
OUT
= 60MHz
00617-052
Figure 52. SFDR vs. Temperature @ 125 MSPS, 0 dBFS
0.05
0.03
0
–0.03
–0.05
1.0
0.5
0
–1.0
–0.5
–40–200 20406080
OFFSET ERROR (%FS)
GAIN ERROR (%FS)
TEMPERATURE (°C)
GAIN ERROR
OFFSET ERROR
00617-053
Figure 53. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
10
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
04302010
SFDR (dBm)
FREQUENCY (MHz)
0
00617-054
Figure 54. Single-Tone SFDR @ fCLK = 125 MSPS
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
04302010
SFDR (dBm)
FREQUENCY (MHz)
0
00617-055
Figure 55. Dual-Tone SFDR @ fCLK = 125 MSPS
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
04302010
SFDR (dBm)
FREQUENCY (MHz)
0
00617-056
Figure 56. Four-Tone SFDR @ fCLK = 125 MSPS
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 20 of 44
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized to
full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal of
zero. For IOUTA, 0 mA output is expected when the inputs are all 0s.
For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Gain Error
Gain error is the difference between the actual and ideal output
spans. The actual span is determined by the output when all inputs
are set to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits may cause either output stage
saturation or breakdown resulting in nonlinear performance.
Temperatu re D r i f t
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in part per million (ppm)
of full-scale range (FSR) per degree Celsius. For reference drift,
the drift is reported in ppm per degree Celsius (ppm/°C).
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from nominal to minimum and maximum
specified voltages.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolts per second (pV-s).
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal.
It is expressed as a percentage or in decibels (dB).
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 21 of 44
THEORY OF OPERATION
5
V
CLK1/IQCLK CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH CHANNEL 2 LATCH
MODE
MULTIPLEXING LOGIC
5V
GAINCTRL ACOM
SLEEP
AD9763/
AD9765/
AD9767
R
SET
1
2kΩ
0.1µF
R
SET
2
2kΩ
CLK
DIVIDER
DAC1
LATCH
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
WRT1/
IQWRT
RETIMED CLOCK OUTPUT*
LECROY 9210
PULSE
GENERATOR
50Ω
DIGITAL
DATA
TEKTRONIX
AWG2021
w/OPTION 4
WRT2/
IQSEL
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
PORT 1 PORT 2
I
OUTA1
I
OUTB1
I
OUTA2
I
OUTB2
DAC2
LATCH
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
Mini-Circuits
T1-1T
50Ω50Ω
00617-057
DVDD1/
DVDD2
DCOM1/
DCOM2
DVDD1/DVDD2
DCOM1/DCOM2
Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767,
Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
0.1µF
5
V
CLK1/IQCLK CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH CHANNEL 2 LATCH
MODE
MULTIPLEXING LOGIC
5V
GAINCTRL
SLEEP
ACOM
DIGITAL DATA INPUTS
NOTES
1. IN THIS CONFIGURATION, THE 22nF CAPACITOR AND 256Ω RESISTOR ARE NOT REQUIRED BECAUSE R
SET
= 2kΩ.
R
SET
1
2kΩ
I
REF
1
R
SET
2
2kΩ
I
REF
2
WRT1/
IQWRT
WRT2/
IQSEL
I
OUTB2
I
OUTA2
I
OUTB1
I
OUTA1
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK
DIVIDER
DAC1
LATCH
DAC2
LATCH
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
V
DIFF
= V
OUT
A – V
OUT
B
V
OUT
1A
V
OUT
1B
V
OUT
2A
V
OUT
2B
R
L
1A
50Ω
R
L
1B
50Ω
R
L
2A
50Ω
R
L
2B
50Ω
00617-058
PORT 1 PORT 2
DVDD1/
DVDD2
DCOM1/
DCOM2
AD9763/
AD9765/
AD9767
Figure 58. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 58 shows a simplified block diagram of the AD9763/
AD9765/AD9767. The AD9763/AD9765/AD9767 consist of
two DACs, each one with its own independent digital control
logic and full-scale output current control. Each DAC contains
a PMOS current source array capable of providing up to 20 mA
of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 k).
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9763/AD9765/AD9767
have separate power supply inputs (that is, AVDD and DVDD1/
DVDD2) that can operate independently at 3.3 V or 5 V. The
digital section, which is capable of operating up to a 125 MSPS
clock rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 22 of 44
The full-scale output current of each DAC is regulated by
separate reference control amplifiers and can be set from
2 mA to 20 mA via an external network connected to the full
scale adjust (FSADJ) pin. The external network, in combination
with both the reference control amplifier and voltage reference
(VREFIO) sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current (IOUTFS) is 32 × IREF.
REFERENCE OPERATION
The AD9763/AD9765/AD9767 contain an internal 1.20 V band
gap reference. This can easily be overridden by a low noise external
reference with no effect on performance. REFIO serves as either
an input or output, depending on whether the internal or an
external reference is used. To use the internal reference, simply
decouple the REFIO pin to ACOM with a 0.1 µF capacitor. The
internal reference voltage is present at REFIO. If the voltage at
REFIO is used elsewhere in the circuit, an external buffer amplifier
with an input bias current of less than 100 nA should be used. An
example of the use of the internal reference is shown in Figure 59.
AD9763/
AD9765/
AD9767
REFERENCE
SECTION
AVDDGAINCTRL
REFIO
FSADJ1/
FSADJ2 ACOM
CURRENT
SOURCE
ARRAY
1.2V
REF
I
REF
0.1µF
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
ADDITIONAL
EXTERNAL
LOAD
R
SET
256Ω
22nF
00617-059
Figure 59. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 60. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. The 0.1 µF
compensation capacitor is not required because the internal
reference is overridden and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
I
REF
R
SET
AVDDGAINCTRL
REFIO
FSADJ1/
FSADJ2 ACOM
AVDD
CURRENT
SOURCE
ARRAY
EXTERNAL
REFERENCE
1.2V
REF
0
0617-060
AD9763/
AD9765/
AD9767
REFERENCE
SECTION
256Ω
22nF
Figure 60. External Reference Configuration Gain Control Mode
GAIN CONTROL MODE
The AD9763/AD9765/AD9767 has two gain control modes,
independent and master/slave. If the GAINCTRL terminal is low
(connected to ground), the full-scale currents of DAC1 and DAC2
are set separately using two different RSET resistors. One resistor
is connected to the FSADJ1 terminal, and the other resistor is
connected to the FSADJ2 terminal. This is independent mode.
If the GAINCTRL terminal is set high (connected to AVDD),
the full-scale currents of DAC1 and DAC2 are set to the same value
using one RSET resistor. In master/slave mode, full-scale current
for both DAC1 and DAC2 is set via the FSADJ1 terminal.
SETTING THE FULL-SCALE CURRENT
Both of the DACs in the AD9763/AD9765/AD9767 contain a
control amplifier that is used to regulate the full-scale output
current (IOUTFS). The control amplifier is configured as a V-I
converter, as shown in Figure 59, so that its current output (IREF)
is determined by the ratio of the VREFIO and an external resistor,
RSET.
IREF = VREFIO/RSET
The DAC full-scale current, IOUTFS, is an output current 32 times
larger than the reference current, IREF.
IOUTFS = 32 × IREF
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 µA and
625 µA. The wide adjustment range of IOUTFS provides several
benefits. The first relates directly to the power dissipation of the
AD9763/AD9765/AD9767, which is proportional to IOUTFS (refer to
the Power Dissipation section). The second relates to the 20 dB
adjustment, which is useful for system gain control purposes.
To ensure that the AD9763/AD9765/AD9767 performs properly,
connect a 22 nF capacitor and 256  resistor network (shown in
Figure 59 and Figure 60) from the FSADJ1 terminal to ground
and from the FSADJ2 terminal to ground.
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 23 of 44
DAC TRANSFER FUNCTION
Both DACs in the AD9763/AD9765/AD9767 provide comple-
mentary current outputs, IOUTA and IOUTB. IOUTA provides a near
full-scale current output (IOUTFS) when all bits are high (that is,
DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/
AD9767, respectively), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA and
IOUTB is a function of both the input code and IOUTFS. IOUTA for the
AD9763, AD9765, and AD9767, respectively, can be expressed as
IOUTA = (DAC CODE/1024) × IOUTFS (1)
IOUTA = (DAC CODE/4096) × IOUTFS
IOUTA = (DAC CODE/16,384) × IOUTFS
IOUTB for the AD9763, AD9765, and AD9767, respectively, can be
expressed as
IOUTB = ((1023 − DAC CODE)/1024) × IOUTFS (2)
IOUTB = ((4095 − DAC CODE)/4096) × IOUTFS
IOUTB = ((16,383 − DAC CODE)/16,384) × IOUTFS
where DAC CODE = 0 to 1024, 0 to 4095, or 0 to 16,384 (decimal
representation).
IOUTFS is a function of the reference current (IREF). This is nominally
set by a reference voltage (VREFIO) and an external resistor (RSET).
It can be expressed as
IOUTFS = 32 × IREF (3)
where IREF is set as discussed in the Setting the Full-Scale
Current section.
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and IOUTB
should be directly connected to matching resistive loads (RLOAD)
that are tied to the analog common (ACOM). Note that RLOAD
can represent the equivalent load resistance seen by IOUTA or IOUTB,
as is the case in a doubly terminated 50  or 75  cable. The single-
ended voltage output appearing at the IOUTA and IOUTB nodes is
VOUTA = IOUTA × RLOAD (5)
VOUTB = IOUTB × RLOAD (6)
Note that the full-scale value of VOUTA and VOUTB must not
exceed the specified output compliance range to maintain the
specified distortion and linearity performance.
VDIFF = (IOUTA − IOUTB) × RLOAD (7)
Equation 7 highlights some of the advantages of operating the
AD9763/AD9765/AD9767 differentially. First, the differential
operation helps cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (that is, VOUTA or VOUTB), thus providing twice the signal
power to the load.
The gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the
AD9763/AD9765/AD9767 can be enhanced by selecting
temperature tracking resistors for RLOAD and RSET due to their
ratiometric relationship.
ANALOG OUTPUTS
The complementary current outputs, IOUTA and IOUTB, in each
DAC can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load
resistor (RLOAD) as described in Equation 5 through Equation 7.
The differential voltage (VDIFF) existing between VOUTA and VOUTB
can be converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance of the
AD9763/AD9765/AD9767 is optimum and specified using a
differential transformer-coupled output in which the voltage
swing at IOUTA and IOUTB is limited to ±0.5 V. If a single-ended
unipolar output is desired, select IOUTA.
The distortion and noise performance of the AD9763/AD9765/
AD9767 can be enhanced when it is configured for differential
operation. The common-mode error sources of both IOUTA and
IOUTB can be significantly reduced by the common-mode rejection
of a transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform
increases. This is due to the first-order cancellation of various
dynamic common-mode distortion mechanisms, digital feed-
through, and noise.
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load, assuming no source termination. Because
the output currents of IOUTA and IOUTB are complementary, they
become additive when processed differentially. A properly selected
transformer allows the AD9763/AD9765/AD9767 to provide the
required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associated
with the current sources and is typically 100 k in parallel with
5 pF. It is also slightly dependent on the output voltage (that is,
VOUTA and VOUTB) due to the nature of a PMOS device. As a result,
maintaining IOUTA and/or IOUTB at a virtual ground via an I-V
op amp configuration results in the optimum dc linearity. Note that
the INL/DNL specifications for the AD9763/AD9765/AD9767 are
measured with IOUTA maintained at a virtual ground via an op amp.
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 24 of 44
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the
AD9763/AD9765/AD9767.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. When IOUTFS is decreased
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at IOUTA and IOUTB
does not exceed 0.5 V. Applications requiring the AD9763/
AD9765/AD9767 output (that is, VOUTA and/or VOUTB) to extend its
output compliance range must size RLOAD accordingly. Operation
beyond this compliance range adversely affects the linearity
performance of the AD9763/AD9765/AD9767 and
subsequently degrades its distortion performance.
DIGITAL INPUTS
The digital inputs of the AD9763/AD9765/AD9767 consist of
two independent channels. For the dual-port mode, each DAC has
its own dedicated 10-/12-/14-bit data port: WRT line and CLK line.
In the interleaved timing mode, the function of the digital control
pins changes as described in the Interleaved Mode Timing
section. The 10-/12-/14-bit parallel data inputs follow straight
binary coding, where the most significant bits (MSBs) are DB9P1
and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765,
and DB13P1 and DB13P2 for the AD9767, and the least significant
bits (LSBs) are DB0P1 and DB0P2 for all three parts. IOUTA produces
a full-scale output current when all data bits are at Logic 1. IOUTB
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
DAC TIMING
The AD9763/AD9765/AD9767 can operate in two timing modes,
dual and interleaved, which are described in the following
sections. The block diagram in Figure 61 represents the latch
architecture in the interleaved timing mode.
IQSEL
IQWRT
DAC1
INTERLEAVED
DATA IN, PORT 1
IQCLK
IQRESET
DAC2
÷2
PORT 1
INPUT
LATCH
PORT 2
INPUT
LATCH
DEINTERLEAVED
DATA OUT
DAC1
LATCH
DAC2
LATCH
00617-061
Figure 61. Latch Structure in Interleaved Mode
Dual-Port Mode Timing
When the MODE pin is at Logic 1, the AD9763/AD9765/AD9767
operates in dual-port mode (refer to Figure 57). The AD9763/
AD9765/AD9767 functions as two distinct DACs. Each DAC
has its own completely independent digital input and control lines.
The AD9763/AD9765/AD9767 features a double-buffered data
path. Data enters the device through the channel input latches.
This data is then transferred to the DAC latch in each signal
path. After the data is loaded into the DAC latch, the analog
output settles to its new value.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK must occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns must be
maintained from the rising edge of WRT to the rising edge of CLK.
Timing specifications for dual-port mode are shown in Figure 62
and Figure 63.
DATA IN
W
RT1/WRT2
CLK1/CLK2
t
PD
I
OUTA
OR
I
OUTB
t
S
t
H
t
LPW
t
CPW
00617-062
Figure 62. Dual-Port Mode Timing
DATA IN
W
RT1/WRT2
CLK1/CLK2
XX
D1 D2 D3 D4
IOUTA
OR
IOUTB
D1 D2 D3 D4 D5
00617-063
Figure 63. Dual-Port Mode Timing
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 25 of 44
Interleaved Mode Timing
When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767
operate in interleaved mode (refer to Figure 61). In addition,
WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2
functions as IQSEL, and CLK2 functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic level
of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or
to Channel Latch 2 (IQSEL = 0). For proper operation, IQSEL
must change state only when IQWRT and IQCLK are low.
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the next rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.
Similar to the order of CLK and WRT in dual-port mode,
IQCLK must occur before or simultaneously with IQWRT.
Timing specifications for interleaved mode are shown in Figure 64
and Figure 66.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDDx), or
VTHRESHOLD = DVDDx/2(±20%)
DATA IN
IQSEL
IQWRT
IQCLK
I
OUTA
OR
I
OUTB
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
500 ps
500 ps
t
S
t
H
t
PD
t
LPW
t
H
*
00617-064
Figure 64. 5 V or 3.3 V Interleaved Mode Timing
At 5 V it is permissible to drive IQWRT and IQCLK together as
shown in Figure 65, but at 3.3 V the interleaved data transfer is
not reliable.
DATA IN
IQSEL
IQWRT
IQCLK
I
OUTA
OR
I
OUTB
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
t
H
*
t
S
t
H
t
PD
t
LPW
00617-065
Figure 65. 5 V Only Interleaved Mode Timing
IQSEL
IQWRT
IQCLK
IQRESET
xx
xx
D1
D2
D3
D4
xx D1 D2 D3 D4 D5
INTERLEAVED
DATA
DAC OUTPUT
PORT 1
DAC OUTPUT
PORT 2
00617-066
Figure 66. Interleaved Mode Timing
The internal digital circuitry of the AD9763/AD9765/AD9767
is capable of operating at a digital supply of 3.3 V or 5 V. As a
result, the digital inputs can also accommodate TTL levels when
DVDD1/DVDD2 is set to accommodate the maximum high
level voltage (VOH(MAX)) of the TTL drivers. A DVDD1/DVDD2
of 3.3 V typically ensures proper compatibility with bipolar TTL
logic families. Figure 67 shows the equivalent digital input
circuit for the data and clock inputs. The sleep mode input is
similar, with the exception that it contains an active pull-down
circuit, thus ensuring that the AD9763/AD9765/AD9767
remains enabled if this input is left disconnected.
DIGITAL
INPUT
DVDD1
00617-067
Figure 67. Equivalent Digital Input
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 26 of 44
Because the AD9763/AD9765/AD9767 is capable of being clocked
up to 125 MSPS, the quality of the clock and data input signals
are important in achieving the optimum performance. Operating
the AD9763/AD9765/AD9767 with reduced logic swings and a
corresponding digital supply (DVDD1/DVDD2) results in the
lowest data feedthrough and on-chip digital noise. The drivers of
the digital data interface circuitry should be specified to meet the
minimum setup and hold times of the AD9763/AD9765/AD9767
as well as its required minimum and maximum input logic level
thresholds.
Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion
of a low value (that is, 20  to 100 ) resistor network between
the AD9763/AD9765/AD9767 digital inputs and driver outputs
can be helpful in reducing any overshooting and ringing at the
digital inputs that contribute to digital feedthrough. For longer
board traces and high data update rates, stripline techniques
with proper impedance and termination resistors should be
considered to maintain “clean” digital inputs.
The external clock driver circuitry provides the AD9763/AD9765/
AD9767 with a low-jitter clock input meeting the minimum
and maximum logic levels while providing fast edges. Fast clock
edges help minimize jitter manifesting itself as phase noise on a
reconstructed waveform. Therefore, the clock input should be
driven by the fastest logic family suitable for the application.
Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This
typically results in a slight degradation in the phase noise, which
becomes more noticeable at higher sampling rates and output
frequencies. In addition, at higher sampling rates, the 20%
tolerance of the digital logic threshold should be considered,
because it affects the effective clock duty cycle and,
subsequently, cuts into the required data setup and hold times.
Input Clock and Data Timing Relationship
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9763/AD9765/AD9767 are rising
edge triggered and therefore exhibit SNR sensitivity when the
data transition is close to this edge. The goal when applying the
AD9763/AD9765/AD9767 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 68 shows the relationship of SNR
to clock placement with different sample rates. Note that at the
lower sample rates, much more tolerance is allowed in clock
placement; much more care must be taken at higher rates.
80
70
60
50
40
30
20
10
0
–4 –3 –2 –1 0 1 2 3 4
SNR (dBc)
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE (ns)
AD9763
AD9765
AD9767
00617-068
Figure 68. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
SLEEP MODE OPERATION
The AD9763/AD9765/AD9767 has a power-down function that
turns off the output current and reduces the supply current to less
than 8.5 mA over the specified supply range of 3.3 V to 5 V and
over the full operating temperature range. This mode can be
activated by applying a Logic Level 1 to the SLEEP pin. The
SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital
input also contains an active pull-down circuit that ensures the
AD9763/AD9765/AD9767 remains enabled if this input is left
disconnected. The AD9763/AD9765/AD9767 require less than
50 ns to power down and approximately 5 s to power back up.
POWER DISSIPATION
The power dissipation (PD) of the AD9763/AD9765/AD9767 is
dependent on several factors, including
• the power supply voltages (AVDD and DVDD1/DVDD2)
• the full-scale current output (IOUTFS)
• the update rate (fCLK)
• the reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current (IAVDD) and the digital supply current (IDVDD).
IAVD D is directly proportional to IOUTFS, as shown in Figure 69,
and is insensitive to fCLK.
Conversely, IDVDD is dependent on the digital input waveform,
the fCLK, and the digital supply (DVDD1/DVDD2). Figure 70
and Figure 71 show IDVDD as a function of full-scale sine wave
output ratios (fOUT/fCLK) for various update rates with DVDD1 =
DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively. Note
that IDVDD is reduced by more than a factor of 2 when
DVDD1/DVDD2 is reduced from 5 V to 3.3 V.
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 27 of 44
80
70
90
50
40
30
20
10
0252015105
I
AVDD
(mA)
I
OUTFS
00617-069
.5
Figure 69. IAVDD vs. IOUTFS
35
30
25
20
15
10
5
0
000.40.30.20.1
I
DVDD
(mA)
RATIO (
f
OUT
/
f
CLK
)
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
0
0617-070
Figure 70. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 5 V
18
16
14
12
10
8
6
4
2
0
000.40.30.20.1
I
DVDD
(mA)
RATIO (
f
OUT
/
f
CLK
)
.5
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
0
0617-071
Figure 71. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 3.3 V
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 28 of 44
APPLYING THE AD9763/AD9765/AD9767
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations
for the AD9763/AD9765/AD9767, with IOUTFS set to a nominal
20 mA, unless otherwise noted. For applications requiring the
optimum dynamic performance, a differential output configuration
is suggested. A differential output configuration can consist of
either an RF transformer or a differential op amp configuration.
The transformer configuration provides the optimum high
frequency performance and is recommended for any application
allowing for ac coupling. The differential op amp configuration
is suitable for applications requiring dc coupling, bipolar
output, signal gain, and/or level shifting within the bandwidth
of the chosen op amp.
A single-ended output is suitable for applications requiring
a unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor (RLOAD) referred to as ACOM. This configuration
may be more suitable for a single-supply system requiring a
dc-coupled, ground-referred output voltage. Alternatively, an
amplifier can be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This configura-
tion provides the best dc linearity because IOUTA or IOUTB is
maintained at a virtual ground. Note that IOUTA provides slightly
better performance than IOUTB.
DIFFERENTIAL COUPLING USING A
TRANSFORMER
An RF transformer can be used as shown in Figure 72 to
perform a differential-to-single-ended signal conversion. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the pass band of the transformer. An RF transformer
such as the Mini-Circuits® T1-1T provides excellent rejection of
common-mode distortion (that is, even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios can also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
R
LOAD
AD9763/
AD9765/
AD9767
I
OUTA
I
OUTB
Mini-Circuits
T1-1T
OPTIONAL
R
DIFF
00617-072
Figure 72. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically
around ACOM and must be maintained with the output compli-
ance range of the AD9763/AD9765/AD9767 to achieve the
specified performance. A differential resistor (RDIFF) can be
inserted in applications where the output of the transformer is
connected to the load (RLOAD) via a passive reconstruction filter
or cable. RDIFF is determined by the transformer’s impedance
ratio and provides the proper source termination that results in a
low VSWR. Approximately half the signal power will be dissipated
across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used as shown in Figure 73 to perform a
differential-to-single-ended conversion. The AD9763/AD9765/
AD9767 is configured with two equal load resistors (RLOAD) of
25  each. The differential voltage developed across IOUTA and
IOUTB is converted to a single-ended signal via the differential
op amp configuration. An optional capacitor can be installed
across IOUTA and IOUTB, forming a real pole in a low-pass filter.
The addition of this capacitor often enhances the op amp’s
distortion performance by preventing the DAC’s high-slewing
output from overloading the op amp’s input.
AD9763/
AD9765/
AD9767
500
Ω
500Ω
225Ω
25Ω25Ω
AD8047
I
OUTA
I
OUTB
225Ω
C
OPT
0
0617-073
Figure 73. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the
differential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
from a dual supply because its output is approximately ±1.0 V.
Select a high speed amplifier capable of preserving the
differential performance of the AD9763/AD9765/AD9767
while meeting other system level objectives (that is, cost or
power). Consider the op amp’s differential gain, gain setting
resistor values, and full-scale output swing capabilities when
optimizing this circuit.
The differential circuit shown in Figure 74 provides the
necessary level shifting required in a single-supply system.
In this case, AVDD, which is the positive analog supply for both
the AD9763/AD9765/AD9767 and the op amp, is used to level
shift the differential output of the AD9763/AD9765/AD9767 to
midsupply (that is, AVDD/2). The AD8055 is a suitable op amp
for this application.
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 29 of 44
500Ω
500Ω
225Ω
25Ω
25Ω
AD8055
IOUTA
IOUTB
225Ω
COPT
AVDD
1kΩ
AD9763/
AD9765/
AD9767
0
0617-074
Figure 74. Single-Supply DC Differential-Coupled Circuit
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 75 shows the AD9763/AD9765/AD9767 configured to
provide a unipolar output range of approximately 0 V to 0.5 V
for a doubly terminated 50  cable, because the nominal full-
scale current (IOUTFS) of 20 mA flows through the equivalent
RLOAD of 25 . In this case, RLOAD represents the equivalent load
resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected directly to ACOM or via a matching RLOAD.
Different values of IOUTFS and RLOAD can be selected as long as the
positive compliance range is adhered to. One additional
consideration in this mode is the INL (see the Analog Outputs
section). For optimum INL performance, the single-ended,
buffered voltage output configuration is suggested.
50Ω
25Ω
50Ω
V
OUTA
= 0V TO 0.5V
I
OUTFS
= 20m
A
I
OUTA
I
OUTB
AD9763/
AD9765/
AD9767
00617-075
Figure 75. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 76 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9763/AD9765/AD9767 output current. U1 maintains IOUTA
(or IOUTB) at a virtual ground, thus minimizing the nonlinear
output impedance effect on the INL performance of the DAC,
as described in the Analog Outputs section. Although this single-
ended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC update
rates may be limited by the slewing capabilities of U1. U1
provides a negative unipolar output voltage, and its full-scale
output voltage is simply the product of RFB and IOUTFS. Set the
full-scale output within U1’s voltage output swing capabilities
by scaling IOUTFS and/or RFB. An improvement in ac distortion
performance may result with a reduced IOUTFS because the signal
current U1 has to sink will be subsequently reduced.
I
OUTFS
= 10mA
U1
I
OUTA
I
OUTB
V
OUT
= I
OUTFS
× R
FB
C
OPT
200Ω
R
FB
200Ω
AD9763/
AD9765/
AD9767
00617-076
Figure 76. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
Power Supply Rejection
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 92 to Figure 93 illustrate recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9763/AD9765/AD9767
evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum of tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9763/AD9765/AD9767 AVDD supply over this frequency
range is shown in Figure 77.
90
70
85
80
75
PSRR (dB)
0.20.30.40.50.60.70.80.91.01.1
FREQUENCY (MHz)
00617-077
Figure 77. AVDD Power Supply Rejection Ratio vs. Frequency
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 30 of 44
Proper grounding and decoupling are primary objectives in any
high speed, high resolution system. The AD9763/AD9765/AD9767
features separate analog and digital supply and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, decouple the analog supply (AVDD) to
the analog common (ACOM) as close to the chip as physically
possible. Similarly, decouple the digital supply (DVDD1/DVDD2)
to the digital common (DCOM1/DCOM2) as close to the chip
as possible.
Note that the data in Figure 77 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired IOUT. PSRR is very code
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worst-
case PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 77 represents a worst-
case condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.
For those applications that require a single 5 V or 3.3 V supply
for both the analog and digital supplies, a clean analog supply
can be generated using the circuit shown in Figure 78. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained by using
low-ESR type electrolytic and tantalum capacitors.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake, all of this noise is concentrated at 250 kHz (that is, ignore
harmonics). To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC full-scale
current, IOUTFS, one must determine the PSRR in decibels using
Figure 77 at 250 kHz. To calculate the PSRR for a given RLOAD,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 77 by the scaling factor 20 × log(RLOAD).
For example, if RLOAD is 50 , the PSRR is reduced by 34 dB (that
is, the PSRR of the DAC at 250 kHz, which is 85 dB in Figure 77,
becomes 51 dB VOUT/VIN).
TTL/CMOS
LOGIC
CIRCUITS 100µF 0.1µF
AVDD
ACOM
ELECTROLYTIC
TANTALUM
CERAMIC
5V
POWER SUPPLY
FERRITE
BEADS
10µF
TO
22µF
00617-078
Figure 78. Differential LC Filter for Single 5 V and 3.3 V Applications
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 31 of 44
APPLICATIONS INFORMATION
VDSL EXAMPLE APPLICATIONS USING THE
AD9765 AND AD9767
Very high frequency digital subscriber line (VDSL) technology is
growing rapidly in applications requiring data transfer over
relatively short distances. By using quadrature amplitude
modulation (QAM) and transmitting the data in discrete multiple
tones (DMT), high data rates can be achieved.
As with other multitone applications, each VDSL tone is
capable of transmitting a given number of bits, depending on
the signal-to-noise ratio (SNR) in a narrow band around that
tone. For a typical VDSL application, the tones are evenly
spaced over the range of several kHz to 10 MHz. At the high
frequency end of this range, performance is generally limited by
cable characteristics and environmental factors such as external
interferers. Performance at the lower frequencies is much more
dependent on the performance of the components in the signal
chain. In addition to in-band noise, intermodulation from other
tones can also potentially interfere with the data recovery for
a given tone. The two graphs in Figure 79 and Figure 81
represent a 500-tone missing bin test vector, with frequencies
evenly spaced from 400 Hz to 10 MHz. This test is very
commonly done to determine if distortion limits the number of
bits that can be transmitted in a tone. The test vector has a
series of missing tones around 750 kHz, which is represented in
Figure 79, and a series of missing tones around 5 MHz, which is
represented in Figure 81. In both cases, the spurious-free
dynamic range (SFDR) between the transmitted tones and the
empty bins is greater than 60 dB.
–
20
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
0.665 0.8250.8050.7850.7650.7450.7250.7050.685
(dBm)
FREQUENCY (MHz)
00617-079
Figure 79. AD9765 Notch in Missing Bin at 750 kHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–
20
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
0.665 0.8250.8050.7850.7650.7450.7250.7050.685
(dBm)
FREQUENCY (MHz)
00617-080
Figure 80. AD9767 Notch in Missing Bin at 750 kHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–
30
–120
–110
–100
–90
–80
–70
–60
–50
–40
4.85 4.90 4.95 5.00 5.05 5.10 5.15
(dBm)
FREQUENCY (MHz)
00617-081
Figure 81. AD9765 Notch in Missing Bin at 5 MHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–
20
–120
–100
–80
–60
–40
4.85 4.90 4.95 5.00 5.05 5.10 5.15
(dBm)
FREQUENCY (MHz)
00617-082
Figure 82. AD9767 Notch in Missing Bin at 5 MHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 32 of 44
QUADRATURE AMPLITUDE MODULATION (QAM)
EXAMPLE USING THE AD9763
QAM is one of the most widely used digital modulation
schemes in digital communications systems. This modulation
technique can be found in FDM as well as spread spectrum
(that is, CDMA) based systems. A QAM signal is a carrier
frequency that is modulated in both amplitude (that is, AM
modulation) and phase (that is, PM modulation). It can be
generated by independently modulating two carriers of
identical frequency but with a 90° phase difference. This results
in an in-phase (I) carrier component and a quadrature (Q) carrier
component at a 90° phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier frequency.
A common and traditional implementation of a QAM modulator
is shown in Figure 83. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components. Each component is then typically
applied to a Nyquist filter before being applied to a quadrature
mixer. The matching Nyquist filters shape and limit each
component’s spectral envelope while minimizing intersymbol
interference. The DAC is typically updated at the QAM symbol
rate, or at a multiple of the QAM symbol rate if an interpolating
filter precedes the DAC. The use of an interpolating filter typically
eases the implementation and complexity of the analog filter, which
can be a significant contributor to mismatches in gain and phase
between the two baseband channels. A quadrature mixer
modulates the I and Q components with the in-phase and
quadrature carrier frequency and then sums the two outputs
to provide the QAM signal.
QUADRATURE
MODULATOR
DAC
10
10
DAC
CARRIER
FREQUENCY
NYQUIST
FILTERS
TO
MIXER
DSP
OR
ASIC
Σ
0°
90°
00617-083
Figure 83. Typical Analog QAM Architecture
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 84 helps improve the
matching between the I and Q channels, and it shows a path for
upconversion using the AD8346 quadrature modulator. The
AD9763 provides both I and Q DACs a common reference that
improves the gain matching and stability. RCAL can be used to
compensate for any mismatch in gain between the two channels.
The mismatch can be attributed to the mismatch between RSET1
and RSET2, the effective load resistance of each channel, and/or
the voltage offset of the control amplifier in each DAC. The
differential voltage outputs of both DACs in the AD9763 are
fed into the respective differential inputs of the AD8346 via
matching networks.
AD9763/
AD9765/
AD9767
00617-084
I
OUT
A
I
OUT
B
I
OUT
A
I
OUT
B
DCOM1/
DCOM2
DVDD1/
DVDD2
AVDD VPBF
BBIP
BBIN
BBQP
BBQN
LOIP
LOIN
VOUT
WRT1/IQWRT
ACOM
+
SPECTRUM ANALYZER
AD8346
CLK1/IQCLK
PORT Q PORT I
DIGITAL INTERFACE
I
DAC
WRT2/IQSEL
C
FILTER
VDIFF = 1.82V p-p
RLRL
RB
RB
RB
RL
RL
RL
RL
LA
LA
LA
LA
RL
CA
CA
RB
RA RA
RA
RL
RB
RA
0 TO I
OUTFS
AD8346
AVDD
AD976x
A
VDD
TEKTRONIX
AWG2021
WITH
OPTION 4
I DAC
LATCH
Q DAC
LATCH
Q
DAC
NOTES
1. DAC FULL-SCALE OUTPUT CURRENT = I
OUTFS
.
2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS
WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE
FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.
V
MOD
V
DAC
DIFFERENTIAL
RLC FILTER
RL = 200Ω
RA = 2500Ω
RB = 500Ω
RP = 200Ω
CA = 280pF
CB = 45pF
LA = 10µH
I
OUTFS
= 11mA
AVDD = 5.0V
VCM = 1.2V
RL
CB
0.1µF
RA
CB
PHASE
SPLITTER
ROHDE & SCHWARZ
FSEA30B
OR EQUIVALENT
ROHDE & SCHWARZ
SIGNAL GENERATOR
SLEEP FSADJ1 FSADJ2MODE REFIO
2kΩ
20kΩ
0.1µF
256Ω
22nF
2kΩ
20kΩ
256Ω
22nF
Figure 84. Baseband QAM Implementation Using an AD9763 and an AD8346
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 33 of 44
I and Q digital data can be fed into the AD9763 in two ways. In
dual-port mode, the digital I information drives one input port,
and the digital Q information drives the other input port. If no
interpolation filter precedes the DAC, the symbol rate is the rate
at which the system clock drives the CLK and WRT pins on the
AD9763. In interleaved mode, the digital input stream at Port 1
contains the I and the Q information in alternating digital words.
Using IQSEL and IQRESET, the AD9763 can be synchronized to
the I and Q data streams. The internal timing of the AD9763 routes
the selected I and Q data to the correct DAC output. In interleaved
mode, if no interpolation filter precedes the AD9763, the symbol
rate is half that of the system clock driving the digital data stream
and the IQWRT and IQCLK pins on the AD9763.
CDMA
Code division multiple access (CDMA) is an air transmit/receive
scheme in which the signal in the transmit path is modulated
with a pseudorandom digital code (sometimes referred to as the
spreading code). The effect of this is to spread the transmitted
signal across a wide spectrum. Similar to a discrete multitone
(DMT) waveform, a CDMA waveform containing multiple
subscribers can be characterized as having a high peak to average
ratio (that is, crest factor), thus demanding highly linear
components in the transmit signal path. The bandwidth of the
spectrum is defined by the CDMA standard being used, and in
operation it is implemented by using a spreading code with
particular characteristics.
Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference with
other signals being transmitted by air. Regulatory bodies define a
spectral mask outside of the transmit band, and the ACP must fall
under this mask. If distortion in the transmit path causes the
ACP to be above the spectral mask, filtering or different
component selection is needed to meet the mask requirements.
Figure 85 shows the results of using the AD9763/AD9765/
AD9767 with the AD8346 to reconstruct a wideband CDMA
signal centered at 2.4 GHz. The baseband signal is sampled at
65 MSPS and has a chip rate of 8 MHz.
cu1
==
–80
–120
–70
–90
–110
–50
–60
–100
–40
CENTER 2.4GHz
–130
–
30
(dB)
C0
c11
FREQUENCY
cu1
C0
c11
SPAN 30MHz3MHz
00617-085
Figure 85. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS, Recreated at
2.4 GHz, Adjacent Channel Power >60 dBm
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 34 of 44
EVALUATION BOARD
GENERAL DESCRIPTION
The AD9763/AD9765/AD9767-EBZ is an evaluation board
for the AD9763/AD9765/AD9767 10-/12-/14-bit dual DAC.
Careful attention to layout and circuit design, combined with a
prototyping area, allow the user to easily and effectively evaluate
the AD9763/AD9765/AD9767 in any application where a high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9763/
AD9765/AD9767 in various configurations. Possible output
configurations include transformer coupled, resistor terminated,
and single-ended and differential outputs. The digital inputs can be
used in dual-port or interleaved mode and are designed to be
driven from various word generators, with the on-board option
to add a resistor network for proper load termination. When
operating the AD9763/AD9765/AD9767, best performance is
obtained by running the digital supply (DVDD1/DVDD2) at
3.3 V and the analog supply (AVDD) at 5 V.
SCHEMATICS
00617-086
L1
BEADBEAD
VAL
VOLT
DCASE VAL
VOLT
DCASE
DGND
C10C9
DVDD AVDD
2
TB1
1
TB1
BLK
BLKBLKBLK
RED
RED
BLKBLKBLK
BLK
AVDDIN
AGND
L2
DVDDIN 3
TB1
4
TB1
R5
R2
R1
RCO M
R3
R4
R6
R7
R8
R9
R2
R1
RCO M
R3
R4
R5
R6
R7
R8
R9
R2
R1
RCO M
R3
R4
R5
R6
R7
R8
R9
R2
R1
RCO M
R3
R4
R5
R6
R7
R8
R9
22
22 22 22
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
22
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1
RP16
RP10RP15 RP9
INP1
INP31
INP32
INP33
INP34
INCK2
INP36
INP35
INP4
INP3
INP2
INP8
INP7
INP6
INP5
INP26
INP25
INP24
INP23
INP30
INP29
INP28
INP27
INP12
INP11
INP10
INP9
INCK1
INP14
INP13
Figure 86. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (1)
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 35 of 44
00617-091
OUT
DVDD
1K
U2
U2
JP2
DCLKIN2 DVDD
CC0805CC0805
CLK
CLR
PRE Q
Q_
J
K
DVDD
14
10
9
712
13
11
U6
SN74F112
DVDD;16
DGND;8
.1UF
C7
.01UF
C8
RC0805
RC0805
RC0805
RC0805
JP16
JP5
JP4
JP3
R4
5050
R1
JP17
50
R13
R3
50
R2
50
DVDD
DVDD
CC0805
CC0805
RC0603RC0603
RC0603
T1-1TCUP
RC0603
1KR17 R1 8 1K
R16
1K
R19
C19 .1
C18 .1
RC0805
SMA 200UP
SMA 200UP
SMA 200UP
SMA 200UP
RC0603
RT2IN
IQSEL
RESET
CLK2IN
1QCLK
CLK1IN
IQWRT
RT1IN
SLEEP
R6 3 50
JP13
1
2
34
5
6
T3
S4
DGND;3,4,5
S3
DGND;3,4,5
S2
DGND;3,4,5
S1
DGND;3,4,5
WHT
WHT
WHT
WHT
JP14
WHT
DS90LV048B
SO16
+IN
-IN
OUT
JP9
DCLKIN1
1
2
15
U2
7
8DS90LV048B
SO16
+IN
-IN
OUT
OUT
CC0805 CC0805
DVDD
C34
.01UF
C33
.1UF
10
A
B
C
1
3
CLK
CLR
PRE Q
Q_
J
K
2
SW1
3
1
26
5
4
U6
15
SN74F112
A
B
C
2
/2 CLOCK DIVIDER
CLK2
3
1
SW2
DVDD
WRT1
WRT2
DVDD;16
DGND;8
CLK1
SLEEP
JP1
DVDD
RC0603
12
13
DS90LV048B
EN
GND
VCC
EN
DS90LV048B
SO16
+IN
-IN
DS90LV048B
SO16
+IN
-IN
VAL
R30
DVDD
3
14
4
5
11
6
U2
16
9
SO16
U2
Figure 87. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (2)
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 36 of 44
00617-092
2
2
2
2
SMAEDGE
AGND2;3,4,5
SMAEDGE
J2
AGND2;3,4,5
JP22
JP21
J1
8
3
4
9
10
13
14
2
1
5
6
15
16
11
7
12
ENBL
G1A
G1B
G2
G3
G4A
G4B
IBBN
IBBP
LOIN
LOIP
QBBN
QBBP
VOUT
VPS1
VPS2
AD834 9
U3
AGND2;17
LC0805
LC0805
CC0805CC0805
O2N
O2P
C24
PNDPND
C23
L6 DNP
DNPL5
2
CC0603
C30
.1UF
2
CC0603CC0603
BCASE
A
VDD2
10V
10UF
C20
.1UF
C29
C27
100PF
LC0805
LC0805
CC0805CC0805
O1N
O1P
DNP
12C22C
DNP
DNPL4
L3 DNP
RC0603
RC0603
RC0603
CC0603
DNP
C32
JP20
BLK
RC0603
ETC1-1-13
SP
CC0603 CC0603
RC0603
2
LOCAL OSC INPUT
AGND2
TP5
50
R20
JP18
C26 100PF
100PFC25
5
43
1
T4
RED
2
RC0603
RC0603 RC0603
RC0603
CC0603
CC0603
RC0603
MODULATED OUTPUT
AVDD2
TP6
AVDD2
R23 51 DNP
C31
JP19
100PF
C28 0R27
R22 DNP51R21
R29 0
R28
1K
R25 51
51R26
DNPR24
Figure 88. Modulator on AD9763/AD9765/AD9767 Evaluation Board
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 37 of 44
00617-093
HDR040RA
HDR040RA
RIBBON RA
9
87
65
40
4
39
38 37
36 35
34 33
32 31
30
3
29
28 27
26 25
24 23
22 21
20
2
19
18 17
16 15
14 13
12 11
10
1
P1
10 710 RP6
SPARES
10
10
10
10
10
10
10 116RP6
152RP5
134RP5
116RP5
9
8RP5
152RP6
134RP6
10 98 RP6
10
10
10
10
10
10
10
512
RP6
161RP5
143RP5
125RP5
107RP5
116
RP6
314
RP6
INCK1
INP1
INP3
INP2
INP4
INP5
INP6
INP7
INP8
INP9
INP10
INP11
INP12
INP13
INP14
DUTP13
DCLKIN1
DUTP14
DUTP12
DUTP11
DUTP10
DUTP9
DUTP8
DUTP7
DUTP6
DUTP5
DUTP4
DUTP3
DUTP2
DUTP1
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
R62
470
R60
470 470
R57 R54
470 470
R53 R52
470 470
R51 R33
470470
R49R50
470470
R55R56
470
R58
470470
R59
470
R61
Figure 89. Digital Input Signaling (1)
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 38 of 44
00617-087
10
512
RP8
10
116
RP7
10
152RP7
10
314
RP7
10
512
RP7
10
710
RP7
10
116
RP8
10
314
RP8
10
134RP7
10
116RP7
10 98 RP7
10
152RP8
10
134RP8
10
116RP8
10 98 RP8
10 710 RP8
HDR040RA
HDR040RA
RIBBON RA
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
56
78
9
P2
SPARES
INP34
INP33
INP32
INP31
INP30
INP29
INP28
INP27
INP26
INP25
INP24
INP23
INP35
INP36
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
DCLKIN2
DUTP23
DUTP24
DUTP33
DUTP31
DUTP29
DUTP27
DUTP25
DUTP26
DUTP30
DUTP28
DUTP32
DUTP34
DUTP35
DUTP36
INCK2
470
R4 1 R42
470
R48
470 470
R4 7 R46
470 470
R4 5 R44
470 470
R4 3 R40
470470
R39R38
470
R37
470470
R36
470
R35R34
470
Figure 90. Digital Input Signaling (2)
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 39 of 44
00617-088
U1
CC0805
VAL
CC0805 CC0805
.1UF
C13C11 C12
.01UF
AVDD
CC0805
SMA 200UP
AGND;3,4,5
OUT2
S11
.1UF
C14
WHT
REFIO
SLEEP
DUTP27
DUTP28
DUTP29
DUTP30
DUTP31
DUTP32
DUTP33
DUTP34
DUTP35
DUTP25
DUTP26
DUTP36
BA
MODE
DVDD 13
2
JP8
AD9763/65/67
ACOM
AVDD
CLK1
CLK2
DB0P1
DB0P2
DB10P1
DB10P2
DB11P1
DB11P2
DB12P1
DB12P2
DB13P1MSB
DB13P2MSB
DB1P1
DB1P2
DB2P1
DB2P2
DB3P1
DB3P2
DB4P1
DB4P2
DB5P1
DB5P2
DB6P1
DB6P2
DB7P1
DB7P2
DB8P1
DB8P2
DB9P1
DB9P2
DCOM1
DCOM2
DVDD1
DVDD2
FSADJ1
FSADJ2
IA1
IB2
IB1
IA2
MODE
REFIO
ACOM1
SLEEP
WRT1
WRT2
38
47
18
19
14
36
4
26
3
25
2
24
1
23
13
35
12
34
11
33
10
32
9
31
8
30
7
29
6
28
5
27
15
21
16
22
44
41
46
40
45
39
48
43
42
37
17
20
WRT2
WRT1
DUTP5
DUTP6
DUTP7
DUTP8
DUTP9
DUTP10
DUTP11
DUTP12
DUTP13
DUTP23
DUTP1
DUTP24
DUTP2
DUTP3
DUTP4
DUTP14
CLK2
CLK1
WHT
CC0805
RC0805
RC0805
SMA 200UP
AGND;3,4,5
RC07CUP
CC0805
RC0805
T1-1TCUP
1
2
34
5
6
T5
BL1
OUT1
R31 10
JP23
10PF
C4
VAL
R11
O1P
O1N
JP6 JP7
WHT
S6
R6
5050
R5 C5
10PF
CC0805
RC0805
RC0805
RC07CUP
RC0805
CC0805 CC0805
RC0805
CC0805
RC0805
RC0805
RC0805
T1-1TCUP
1
2
34
5
6
T6
10R32
JP24
BL3
1.92KR10
BL2
R15 256
22NF
C16
WHT
O2P 50
R8
10PF
C6
10PF
C15
R9 1.92K
VAL
R12
50
R7
JP10
R14 256
22NF
C17
BL4
JP12 JP11
O2N
WHT
BA
VAL
CC0805 CC0805 CC0805
ACOM
DVDD
C3
.1UF
.01UF
C2C1 2
31 JP15
AVDD
Figure 91. Device Under Test/Analog Output Signal Conditioning
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 40 of 44
EVALUATION BOARD LAYOUT
00617-089
Figure 92. Assembly, Top Side
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 41 of 44
00617-090
Figure 93. Assembly, Bottom Side
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 42 of 44
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 94. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9763ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9763ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9763-EBZ Evaluation Board
AD9765AST –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9765ASTRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9765ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9765ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9765-EBZ Evaluation Board
AD9767ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9767ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9767-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 43 of 44
NOTES
AD9763/AD9765/AD9767 Data Sheet
Rev. G | Page 44 of 44
NOTES
©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00617-0-8/11(G)