AT52BR3224AT - Atmel Corporation

Features

•32-Mbit Flash and 4-Mbit/8-Mbit SRAM

•Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package

•2.7V to 3.3V Operating Voltage

Flash

•2.7V to 3.3V Read/Write

•Access Time – 70 ns

•Sector Erase Architecture

– Sixty-three 32K WordSectors with Individual Write Lockout

– Eight 4K Word Sectors with Individual Write Lockout

•Fast Word Program Time – 15 µs

•Sector Erase Time – 300 ms

•Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase of a

Different Sector

– Supports Reading Any Word by Suspending Programming of Any Other Word

•Low-power Operation

–12 mA Active

– 13 µA Standby

•Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

•VPP Pin for Write Protection and Accelerated Program/Erase Operations

•RESET Input for Device Initialization

•Sector Lockdown Support

•Top or Bottom Boot Block Configuration Available

•128-bit Protection Register

•Minimum 100,000 Erase Cycles

SRAM

•4-megabit (256K x 16)/8-megabit (512K x 16)

•2.7V to 3.3V VCC

•70 ns Access Time

•Fully Static Operation and Tri-state Output

•1.2V (Min) Data Retention

•Industrial Temperature Range

Device Number

Flash Boot

Location

Flash Plane

Architecture

SRAM

Configuration

AT52BR3224A Bottom 32M 256K x 16

AT52BR3224AT Top 32M 256K x 16

AT52BR3228A Bottom 32M 512K x 16

AT52BR3228AT Top 32M 512K x 16

32-megabit

Flash

+ 4-megabit/

8-megabit

SRAM

Stack Memory

AT52BR3224A

AT52BR3224AT

AT52BR3228A

AT52BR3228AT

Preliminary

Rev. 3338B–STKD–6/03

2AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Pin Configuration

AT52BR3224A(T)/

AT52BR3228A(T)

(Top View)

Pin Name Function

A0 - A17 Flash/SRAM Common Address Input for 4M SRAM

A0 - A18 Flash/SRAM Common Address Input for 8M SRAM

A19 - A20 Flash Address Input

CE Flash Chip Enable

OE Flash Output Enable

WE Flash Write Enablee

RESET Flash Reset

RDY/BUSY Flash READY/BUSY Output

VPP Flash Power Supply for Accelerated Program/Erase Operations

VCC Flash Power

GND Flash Ground

I/O0 - I/O15 Data Inputs/Outputs

NC No Connect

SLB SRAM Lower Byte

SUB SRAM Upper Byte

SVCC SRAM Power

SGND SRAM Ground

SCS1 SRAM Chip Select 1

SCS2 SRAM Chip Select 2

SWE SRAM Write Enable

SOE SRAM Output Enable

123456789101112

A20

A16

SGND

SLB

A18

A11

RDY/BUSY

RES

VPP

SUB

A17

A15

A10

A19

SOE

A14

I/O11

A13

I/O15

I/O13

I/O12

I/O9

A12

SWE

I/O6

SCS2

I/O10

I/O8

GND

I/O14

I/O4

SVCC

I/O2

I/O0

I/O7

I/O5

VCC

I/O3

I/O1

SCS1

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Block Diagram

Description The AT52BR3224A(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM (orga-

nized as 256K x 16) in a stacked 66-ball CBGA package. The AT52BR3228A(T) combines a

32-megabit Flash (2M x 16) and an 8-megabit SRAM (organized as 512K x 16) in a stacked

66-ball CBGA package. The stacked modules operate at 2.7V to 3.3V in the industrial temper-

ature range.

32-Mbit

FLASH

4/8-Mbit

SRAM

ADDRESS

DATA

RESET

RDY/BUSY

SCS1

SCS2

WE SWESOEOE

Absolute Maximum Ratings

Temperature under Bias.................................. -40°C to +85°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature .................................... -55°C to +150°C

All Input Voltages

except VPP and RESET

(including NC Pins)

with Respect to Ground .....................................-0.2V to +3.3V

Voltage on VPP

with Respect to Ground ..................................-0.2V to + 6.25V

Voltage on RESET

with Respect to Ground ...................................-0.2V to +13.5V

All Output Voltages

with Respect to Ground .....................................-0.2V to +0.2V

DC and AC Operating Range

AT52BR3224A(T)/3228A(T)-70

Operating Temperature (Case) Industrial -40°C - 85°C

VCC Power Supply 2.7V to 3.3V

4AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

32-megabit

Flash Memory

Description

The 32-megabit Flash is a a 2.7-volt memory organized as 2,097,152 words of 16 bits each.

The memory is divided into 71 sectors for erase operations. The device has CE and OE con-

trol signals to avoid any bus contention. This device can be read or reprogrammed using a

single power supply, making it ideally suited for in-system programming.

The device powers on in the read mode. Command sequences are used to place the device in

other operation modes such as program and erase. The device has the capability to protect

the data in any sector (see “Sector Lockdown” section).

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend

feature. This feature will put the erase or program on hold for any amount of time and let the

user read data from or program data to any of the remaining sectors within the memory. The

end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by

the toggle bit.

The VPP pin provides data protection. When the VPP input is below 0.4V, the program and

erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase opera-

tions can be performed.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement

of entering the three-byte program sequence is offered to further improve programming time.

After entering the six-byte code, only single pulses on the write control lines are required for

writing into the device. This mode (Single Pulse Word Program) is exited by powering down

the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back

to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not

work while in this mode; if entered they will result in data being programmed into the device. It

is not recommended that the six-byte code reside in the software of the final product but only

exist in external programming code.

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Block Diagram

IDENTIFIER

STATUS

DATA

COMPARATOR

OUTPUT

MULTIPLEXER

OUTPUT

BUFFER

INPUT

BUFFER

COMMAND

DATA

Y-GATING

WRITE STATE

MACHINE PROGRAM/ERASE

VOLTAGE SWITCH

RESET

RDY/BUSY

VPP

VCC

GND

Y-DECODER

X-DECODER

INPUT

BUFFER

ADDRESS

LATCH

I/O0 - I/O15

A0 - A20

MAIN

MEMORY

6AT52BR3224A(T)/3228A(T)

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Device

Operation

READ: The 32-Mbit Flash memory is accessed like an EPROM. When CE and OE are low

and WE is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the “Command Definition in Hex” table on page 14 (I/O8 - I/O15 are

don’t care inputs for the command codes). The command sequences are written by applying a

low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address

is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the

first rising edge of CE or WE. Standard microprocessor write timings are used. The address

locations used in the command sequences are not affected by entering the command

sequences.

RESET: A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is tEC.

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71 sec-

tors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a sector is tSEC. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating immediately.

WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”)

on a word-by-word basis. Programming is accomplished via the internal device command reg-

ister and is a four-bus cycle operation. The device will automatically generate the required

internal program pulses.

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Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the

erase or program operation was performed successfully.

VPP PIN: The circuitry of the 32-Mbit Flash is designed so that the device cannot be pro-

grammed or erased if the VPP voltage is less that 0.4V. When VPP is at 0.9V or above, normal

program and erase operations can be performed. The VPP pin cannot be left floating.

PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a

program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 13

and the following four sections describe the function of these bits. To provide greater flexibility

for system designers, the device contains a programmable configuration register. The configu-

ration register allows the user to specify the status bit operation. The configuration register can

be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the

part will automatically return to the read mode after a successful program or erase operation. If

the configuration register is set to a “01”, a Product ID Exit command must be given after a

successful program or erase operation before the part will return to the read mode. It is impor-

tant to note that whether the configuration register is set to a “00” or to a “01”, any

unsuccessful program or erase operation requires using the Product ID Exit command to

return the device to read mode. The default value (after power-up) for the configuration regis-

ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the

“Command Definition in Hex” table on page 14, the value of the configuration register can be

changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-

ter. The value of the configuration register will affect the operation of the I/O7 status bit as

described below.

DATA POLLING: The device features Data Polling to indicate the end of a program cycle. If

the status configuration register is set to a “00”, during a program cycle an attempted read of

the last word loaded will result in the complement of the loaded data on I/O7. Once the pro-

gram cycle has been completed, true data is valid on all outputs and the next cycle may begin.

During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7.

Once the program or erase cycle has completed, true data will be read from the device. Data

Polling may begin at any time during the program cycle. Please see “Status Bit Table” on page

13 for more details.

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the

device is actively programming or erasing data. I/O7 will go high when the device has com-

pleted a program or erase operation. Once I/O7 has gone high, status information on the other

pins can be checked.

The Data Polling status bit must be used in conjunction with the erase/program and VPP status

bit as shown in the algorithm in Figures 1 and 2 on page 11.

8AT52BR3224A(T)/3228A(T)

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TOGGLE BIT: In addition to Data Polling the device provides another method for determining

the end of a program or erase cycle. During a program or erase operation, successive

attempts to read data from the memory will result in I/O6 toggling between one and zero. Once

the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin-

ing the toggle bit may begin at any time during a program cycle. Please see “Status Bit Table”

on page 13 for more details.

The toggle bit status bit should be used in conjunction with the erase/program and VPP status

bit as shown in the algorithm in Figures 3 and 4 on page 12.

ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates

whether the program or erase operation has exceeded a specified internal pulse count limit. If

the status bit is a “1”, the device is unable to verify that an erase or a word program operation

has been successfully performed. If a program (Sector Erase) command is issued to a pro-

tected sector, the protected sector will not be programmed (erased). The device will go to a

status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera-

tion did not complete as requested. Once the erase/program status bit has been set to a “1”,

the system must write the Product ID Exit command to return to the read mode. The

erase/program status bit is a “0” while the erase or program operation is still in progress.

Please see “Status Bit Table” on page 13 for more details.

VPP STATUS BIT: The device provides a status bit on I/O3, which provides information

regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage

on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 sta-

tus bit will be a “1”. Once the VPP status bit has been set to a “1”, the system must write the

Product ID Exit command to return to the read mode. On the other hand, if the voltage level is

high enough to perform a program or erase operation successfully, the VPP status bit will out-

put a “0”. Please see “Status Bit Table” on page 13 for more details.

SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-

vents programming of data in the designated sectors once the feature has been enabled.

These sectors can contain secure code that is used to bring up the system. Enabling the lock-

down feature will allow the boot code to stay in the device while data in the rest of the device is

updated. This feature does not have to be activated; any sector’s usage as a write-protected

region is optional to the user.

At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,

the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked

down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-

ming of a sector is locked down. When the device is in the software product identification

mode (see “Software Product Identification Entry/Exit” sections on page 27), a read from

address location 00002H within a sector will show if programming the sector is locked down. If

the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program

lockdown feature has been enabled and the sector cannot be programmed. The software

product identification exit code should be used to return to standard operation.

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is

through reset or power-up cycles. After power-up or reset, the content of a sector that is

locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to

interrupt a sector or chip erase operation and then program or read data from a different sector

within the memory. After the Erase Suspend command is given, the device requires a maxi-

mum time of 15 µs to suspend the erase operation. After the erase operation has been

suspended, the system can then read data or program data to any other sector within the

device. An address is not required during the Erase Suspend command. During a sector erase

suspend, another sector cannot be erased. To resume the sector erase operation, the system

must write the Erase Resume command. The Erase Resume command is a one-bus cycle

command. The device also supports an erase suspend during a complete chip erase. While

the chip erase is suspended, the user can read from any sector within the memory that is pro-

tected. The command sequence for a chip erase suspend and a sector erase suspend are the

same.

PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the

system to interrupt a programming operation and then read data from a different word within

the memory. After the Program Suspend command is given, the device requires a maximum

of 20 µs to suspend the programming operation. After the programming operation has been

suspended, the system can then read data from any other word within the device that is not

contained in the sector in which the programming operation was suspended. An address is not

required during the program suspend operation. To resume the programming operation, the

system must write the Program Resume command. The program suspend and resume are

one-bus cycle commands. The command sequence for the erase suspend and program sus-

pend are the same, and the command sequence for the erase resume and program resume

are the same.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see “Operating Modes” on page 20 (for hardware operation) or “Software Product

Identification Entry/Exit” sections on page 27. The manufacturer and device codes are the

same for both modes.

128-BIT PROTECTION REGISTER: The device contains a 128-bit register that can be used

for security purposes in system design. The protection register is divided into two 64-bit

blocks. The two blocks are designated as block A and block B. The data in block A is

non-changeable and is programmed at the factory with a unique number. The data in block B

is programmed by the user and can be locked out such that data in the block cannot be repro-

grammed. To program block B in the protection register, the four-bus cycle Program

Protection Register command must be used as shown in the “Command Definition in Hex”

table on page 14. To lock out block B, the four-bus cycle Lock Protection Register command

must be used as shown in the “Command Definition in Hex” table. Data bit D1 must be zero

during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To

determine whether block B is locked out, the Product ID Entry command is given followed by a

read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one,

block B can be reprogrammed. Please see the “Protection Register Addressing Table” on

page 15 for the address locations in the protection register. To read the protection register, the

Product ID Entry command is given followed by a normal read operation from an address

within the protection register. After determining whether block B is protected or not, or reading

the protection register, the Product ID Exit command must be given prior to performing any

other operation.

10 AT52BR3224A(T)/3228A(T)

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RDY/BUSY: For the 32-Mbit Flash memory, an open-drain READY/BUSY output pin provides

another method of detecting the end of a program or erase operation. RDY/BUSY is actively

pulled low during the internal program and erase cycles and is released at the completion of

the cycle. The open-drain connection allows for OR-tying of several devices to the same

RDY/BUSY line. Please see “Status Bit Table” on page 13 for more details.

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against

inadvertent programs to the device in the following ways: (a) VCC sense: if VCC is below 1.8V

(typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the

VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c)

Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d)

Program inhibit: VPP is less than VILPP. (e) VPP power-on delay: once VPP has reached 1.65V,

program and erase operations are inhibited for 100 ns.

INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and

control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the

operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.

OUTPUT LEVELS: For the device, output high levels (VOH) are equal to VCCQ - 0.2V (not VCC).

For 2.7V - 3.6V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output levels, VCCQ

must be regulated to 2.0V ± 10%, while VCC must be regulated to 2.7V - 3.0V (for minimum

power).

AT52BR3224A(T)/3228A(T)

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Figure 1. Data Polling Algorithm

(Configuration Register = 00)

Notes: 1. VA = Valid address for programming. During a sec-

tor erase operation, a valid address is any sector

address within the sector being erased. During

chip erase, a valid address is any non-protected

sector address.

2. I/O7 should be rechecked even if I/O5 = “1”

because I/O7 may change simultaneously with

I/O5.

START

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

YES

Program/Erase

Operation

Successful,

Device in

Read Mode

Figure 2. Data Polling Algorithm

(Configuration Register = 01)

Note: 1. VA = Valid address for programming. During a sec-

tor erase operation, a valid address is any sector

address within the sector being erased. During

chip erase, a valid address is any non-protected

sector address.

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Program/Erase

Operation

Successful

YES

12 AT52BR3224A(T)/3228A(T)

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Figure 3. Toggle Bit Algorithm

(Configuration Register = 00)

Note: 1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Program/Erase

Operation

Successful

YES

Figure 4. Toggle Bit Algorithm

(Configuration Register = 01)

Note: 1. The system should recheck the toggle bit even if I/O5 =

“1” because the toggle bit may stop toggling as I/O5

changes to “1”.

START

Read I/O7 - I/O0

Toggle Bit =

Toggle?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

YES

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Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or

sector erase operation is performed on a protected sector.

2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.

Status Bit Table

Status Bit

I/O7 I/O7 I/O6 I/O5(1) I/O3(2) I/O2 RDY/BUSY

Configuration Register 00 01 00/01 00/01 00/01 00/01 00/01

Programming I/O7 0TOGGLE0010

Erasing 0 0 TOGGLE 0 0 TOGGLE 0

Erase Suspended & Read

Erasing Sector 11100TOGGLE1

Erase Suspended & Read

Non-erasing Sector DATA DATA DATA DATA DATA DATA 1

Erase Suspended &

Program Non-erasing Sector I/O7 0 TOGGLE 0 0 TOGGLE 0

14 AT52BR3224A(T)/3228A(T)

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Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8

are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11

are don’t care in the word mode.

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 18-17 for

details).

4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power

cycled.

5. Either one of the Product ID Exit commands can be used.

6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

7. The default state (after power-up) of the configuration register is “00”.

8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.

Command Definition in Hex(1)

Command

Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr DOUT

Chip Erase 6 555 AA AAA(2) 55 555 80 555 AA AAA 55 555 10

Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(3)(4) 30

Word Program 4 555 AA AAA 55 555 A0 Addr DIN

Enter Single Pulse

Program Mode 6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0

Single Pulse Word

Program 1AddrD

Sector Lockdown 6 555 AA AAA(2) 55 555 80 555 AA AAA 55 SA(3)(4) 60

Erase/Program

Suspend 1 XXX B0

Erase/Program

Resume 1 XXX 30

Product ID Entry 3 555 AA AAA 55 555 90

Product ID Exit(5) 3 555 AA AAA 55 555 F0(8)

Product ID Exit(5) 1 XXX F0(8)

Program Protection

Lock Protection

Status of Block B

Protection 4 555 AA AAA 55 555 90 80 DOUT(6)

Set Configuration

Absolute Maximum Ratings*

Temperature under Bias................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground .................................. -0.6V to +6.25V

All Output Voltages

with Respect to Ground ............................ -0.6V to VCC + 0.6V

Voltage on VPP

with Respect to Ground .................................. -0.6V to +13.0V

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Note: All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A20 - A8 = 0.

Protection Register Addressing Table

Word Use Block A7 A6 A5 A4 A3 A2 A1 A0

0 Factory A 10000001

1 Factory A 10000010

2 Factory A 10000011

3 Factory A 10000100

4 User B 10000101

5 User B 10000110

6 User B 10000111

7 User B 10001000

16 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Bottom Boot – Sector Address Table

Sector

x16

Address Range (A20 - A0)

SA0 00000 - 00FFF

SA1 01000 - 01FFF

SA2 02000 - 02FFF

SA3 03000 - 03FFF

SA4 04000 - 04FFF

SA5 05000 - 05FFF

SA6 06000 - 06FFF

SA7 07000 - 07FFF

SA8 08000 - 0FFFF

SA9 10000 - 17FFF

SA10 18000 - 1FFFF

SA11 20000 - 27FFF

SA12 28000 - 2FFFF

SA13 30000 - 37FFF

SA14 38000 - 3FFFF

SA15 40000 - 47FFF

SA16 48000 - 4FFFF

SA17 50000 - 57FFF

SA18 58000 - 5FFFF

SA19 60000 - 67FFF

SA20 68000 - 6FFFF

SA21 70000 - 77FFF

SA22 78000 - 7FFFF

SA23 80000 - 87FFF

SA24 88000 - 8FFFF

SA25 90000 - 97FFF

SA26 98000 - 9FFFF

SA27 A0000 - A7FFF

SA28 A8000 - AFFFF

SA29 B0000 - B7FFF

SA30 B8000 - BFFFF

SA31 C0000 - C7FFF

SA32 C8000 - CFFFF

SA33 D0000 - D7FFF

SA34 D8000 - DFFFF

SA35 E0000 - E7FFF

SA36 E8000 - EFFFF

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

SA37 F0000 - F7FFF

SA38 F8000 - FFFFF

SA39 100000 - 107FFF

SA40 108000 - 10FFFF

SA41 110000 - 117FFF

SA42 118000 - 11FFFF

SA43 120000 - 127FFF

SA44 128000 - 12FFFF

SA45 130000 - 137FFF

SA46 138000 - 13FFFF

SA47 140000 - 147FFF

SA48 148000 - 14FFFF

SA49 150000 - 157FFF

SA50 158000 - 15FFFF

SA51 160000 - 167FFF

SA52 168000 - 16FFFF

SA53 170000 - 177FFF

SA54 178000 - 17FFFF

SA55 180000 - 187FFF

SA56 188000 - 18FFFF

SA57 190000 - 197FFF

SA58 198000 - 19FFFF

SA59 1A0000 - 1A7FFF

SA60 1A8000 - 1AFFFF

SA61 1B0000 - 1B7FFF

SA62 1B8000 - 1BFFFF

SA63 1C0000 - 1C7FFF

SA64 1C8000 - 1CFFFF

SA65 1D0000 - 1D7FFF

SA66 1D8000 - 1DFFFF

SA67 1E0000 - 1E7FFF

SA68 1E8000 - 1EFFFF

SA69 1F0000 -1F7FFF

SA70 1F8000 - 1FFFF

Bottom Boot – Sector Address Table (Continued)

Sector

x16

Address Range (A20 - A0)

18 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Top Boot – Sector Address Table

Sector

x16

Address Range (A20 - A0)

SA0 00000 - 07FFF

SA1 08000 - 0FFFF

SA2 10000 - 17FFF

SA3 18000 - 1FFFF

SA4 20000 - 27FFF

SA5 28000 - 2FFFF

SA6 30000 - 37FFF

SA7 38000 - 3FFFF

SA8 40000 - 47FFF

SA9 48000 - 4FFFF

SA10 50000 - 57FFF

SA11 58000 - 5FFFF

SA12 60000 - 67FFF

SA13 68000 - 6FFFF

SA14 70000 - 77FFF

SA15 78000 - 7FFFF

SA16 80000 - 87FFF

SA17 88000 - 8FFFF

SA18 90000 - 97FFF

SA19 98000 - 9FFFF

SA20 A0000 - A7FFF

SA21 A8000 - AFFFF

SA22 B0000 - B7FFF

SA23 B8000 - BFFFF

SA24 C0000 - C7FFF

SA25 C8000 - CFFFF

SA26 D0000 - D7FFF

SA27 D8000 - DFFFF

SA28 E0000 - E7FFF

SA29 E8000 - EFFFF

SA30 F0000 - F7FFF

SA31 F8000 - FFFFF

SA32 100000 - 107FFF

SA33 108000 - 10FFFF

SA34 110000 - 117FFF

SA35 118000 - 11FFFF

SA36 120000 - 127FFF

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

SA37 128000 - 12FFFF

SA38 130000 - 137FFF

SA39 138000 - 13FFFF

SA40 140000 - 147FFF

SA41 148000 - 14FFFF

SA42 150000 - 157FFF

SA43 158000 - 15FFFF

SA44 160000 - 167FFF

SA45 168000 - 16FFFF

SA46 170000 - 177FFF

SA47 178000 - 17FFFF

SA48 180000 - 187FFF

SA49 188000 - 18FFFF

SA50 190000 - 197FFF

SA51 198000 - 19FFFF

SA52 1A0000 - 1A7FFF

SA53 1A8000 - 1AFFFF

SA54 1B0000 - 1B7FFF

SA55 1B8000 - 1BFFFF

SA56 1C0000 - 1C7FFF

SA57 1C8000 - 1CFFFF

SA58 1D0000 - 1D7FFF

SA59 1D8000 - 1DFFFF

SA60 1E0000 - 1E7FFF

SA61 1E8000 - 1EFFFF

SA62 1F0000 - 1F7FFF

SA63 1F8000 - 1F8FFF

SA64 1F9000 - 1F9FFF

SA65 1FA000 - 1FAFFF

SA66 1FB000 - 1FBFFF

SA67 1FC000 - 1FCFFF

SA68 1FD000 - 1FDFFF

SA69 1FE000 - 1FEFFF

SA70 1FF000 - 1FFFFF

Top Boot – Sector Address Table (Continued)

Sector

x16

Address Range (A20 - A0)

20 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms on page 25.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 001FH (x16), Device Code: 00C8H (x16)-Bottom Boot; 00C9H (x16)-Top Boot.

5. See details under “Software Product Identification Entry/Exit” on page 27.

6. VIHPP (min) = 0.9V; VIHPP (max) = 3.6V.

7. VILPP (max) = 0.4V.

DC and AC Operating Range

32-Mbit Flash

Operating

Temperature (Case) Ind. -40°C - 85°C

VCC Power Supply 2.7V to 3.6V

Operating Modes

Mode CE OE WE RESET VPP Ai I/O

Read VIL VIL VIH VIH XAiD

OUT

Program/Erase(2) VIL VIH VIL VIH VIHPP(6) Ai DIN

Standby/Program Inhibit VIH X(1) XV

IH X X High-Z

Program Inhibit

XXV

IH VIH X

IL XV

IH X

XXX V

IH VILPP(7)

Output Disable X VIH XV

IH X High-Z

Reset XXX V

IL X X High-Z

Product Identification

Hardware VIL VIL VIH VIH

A1 - A20 = VIL, A9 = VH(3), A0 = VIL Manufacturer Code(4)

A1 - A20 = VIL, A9 = VH(3), A0 = VIH Device Code(4)

Software(5) VIH

A0 = VIL, A1 - A20 = VIL Manufacturer Code(4)

A0 = VIH, A1 - A20 = VIL Device Code(4)

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Note: 1. In the erase mode, ICC is 65 mA.

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

ILI Input Load Current VIN = 0V to VCC 10 µA

ILO Output Leakage Current VI/O = 0V to VCC 10 µA

ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC 13 25 µA

ICC(1) VCC Active Read Current f = 5 MHz; IOUT = 0 mA 12 25 mA

ICC1 VCC Programming Current 45 mA

IPP1 VPP Input Load Current 10 µA

VIL Input Low Voltage 0.6 V

VIH Input High Voltage 2.0 V

VOL1 Output Low Voltage IOL = 2.1 mA 0.45 V

VOL2 Output Low Voltage IOL = 1.0 mA 0.20 V

VOH1 Output High Voltage

IOH = -400 µA

VCCQ < 2.6V

VCCQ ≥ 2.6V

VCCQ - 0.2

2.4

VOH2 Output High Voltage

IOH = -100 µA

VCCQ < 2.6V

VCCQ ≥ 2.6V

VCCQ - 0.1

2.5

22 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change

without impact on tACC.

3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

AC Read Characteristics

Symbol Parameter

32-Mbit Flash

UnitsMin Max

tRC Read Cycle Time 70 ns

tACC Address to Output Delay 70 ns

tCE(1) CE to Output Delay 70 ns

tOE(2) OE to Output Delay 0 40 ns

tDF(3)(4) CE or OE to Output Float 0 25 ns

tOH

Output Hold from OE, CE or Address,

whichever occurred first 0ns

tRO RESET to Output Delay 100 ns

OUTPUT

VALID

OUTPUT HIGH Z

RESET

OE tOE

tCE

ADDRESS VALID

tDF

tOH

tACC

tRO

ADDRESS

tRC

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Input Test Waveforms and Measurement Level

tR, tF < 5 ns

Output Test Load

Note: This parameter is characterized and is not 100% tested.

Pin Capacitance

f = 1 MHz, T = 25°C(1)

Symbol Typ Max Units Conditions

CIN 46pFV

IN = 0V

COUT 812pFV

OUT = 0V

24 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

AC Word Load Waveforms

WE Controlled

CE Controlled

AC Word Load Characteristics

Symbol Parameter Min Max Units

tAS, tOES Address, OE Setup Time 0 ns

tAH Address Hold Time 35 ns

tCS Chip Select Setup Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE)35ns

tDS Data Setup Time 35 ns

tDH, tOEH Data, OE Hold Time 0 ns

tWPH Write Pulse Width High 35 ns

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Program Cycle Waveforms

Sector or Chip Erase Cycle Waveforms

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.

(See note 3 under “Command Definitions in Hex” on page 14.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

tBP Word Programming Time 15 150 µs

tAS Address Setup Time 0ns

tAH Address Hold Time 35 ns

tDS Data Setup Time 35 ns

tDH Data Hold Time 0ns

tWP Write Pulse Width 35 ns

tWPH Write Pulse Width High 35 ns

tWC Write Cycle Time 70 ns

tRP Reset Pulse Width 500 ns

tEC Chip Erase Cycle Time 80 400 seconds

tSEC1 Sector Erase Cycle Time (4K Word Sectors) 0.3 3.0 seconds

tSEC2 Sector Erase Cycle Time (32K Word Sectors) 1.2 5.0 seconds

tES Erase Suspend Time 15 µs

tPS Program Suspend Time 20 µs

PROGRAM CYCLE

INPUT

DATA

ADDRESS

555 555

AAA

WPH

A0 - A20

DATA

555

(1)

80 Note 3

55 55

555 555 Note 2

WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5

AAA AAA

WPH

A0-A20

DATA

555

26 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in “AC Read Characteristics” on page 22.

Data Polling Waveforms

Notes: 1. These parameters are characterized and not 100% tested.

2. See tOE spec in “AC Read Characteristics” on page 22.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tWR Write Recovery Time 0 ns

A0-A20

I/O7

tDH

tOEH

tOE HIGH Z

An An An An An

tWR

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 50 ns

tWR Write Recovery Time 0 ns

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Software Product Identification Entry(1)

Software Product Identification Exit(1)(6)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), and A11 - A20 (Don’t

Care).

2. A1 - A20 = VIL. Manufacturer Code is read for A0 = VIL;

Device Code is read for A0 = VIH.

3. The device does not remain in identification mode if powered

down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 001FH(x16)

Device Code: 00C8 (x16)-Bottom Boot

00C9H (x16)-Top Boot.

6. Either one of the Product ID Exit commands can be used.

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 90

ADDRESS 555

ENTER PRODUCT

IDENTIFICATION

MODE

(2)(3)(5)

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA F0

ADDRESS 555

EXIT PRODUCT

IDENTIFICATION

MODE(4)

OR LOAD DATA F0

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE(4)

Sector Lockdown Enable Algorithm(1)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A20

(Don’t Care).

2. Sector Lockdown feature enabled.

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 80

ADDRESS 555

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 60

SECTOR ADDRESS

PAUSE 200 µs(2)

28 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

4-megabit

SRAM

Description

The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K

words by 16 bits. The SRAM uses high-performance full CMOS process technology and is

designed for high-speed and low-power circuit technology. It is particularly well-suited for the

high-density low-power system application. This device has a data retention mode that guar-

antees data to remain valid at a minimum power supply voltage of 1.2V.

Features

•Fully Static Operation and Tri-state Output

•TTL Compatible Inputs and Outputs

•Battery Backup

– 1.2V (Min) Data Retention

Block Diagram

Voltage (V) Speed (ns)

Operation

Current/ICC (mA)

(Max)

Standby

Current (µA)

(Max)

Temperature

(°C)

2.7 - 3.3 70 3 10 -40 - 85

MEMORY ARRAY

256K X 16

I/O0

SUB

SLB

SOE

SCS2

SCS1

SWE

DATA I/O BUFFER

SENSE AMP WRITE DRIVER

I/O7

I/O8

I/O15

ROW DECODER

COLUMN

DECODER

BLOCK

DECODER

PRE DECODER

ADD INPUT BUFFER

A17

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

stress rating only and the functional operation of the device under these or any other conditions above those indicated in the

operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may

affect reliability.

Notes: 1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)

2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is

LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8

- I/O15.

Note: 1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.

Absolute Maximum Ratings(1)

Symbol Parameter Rating Unit

VIN, VOUT Input/Output Voltage -0.3 to 3.6 V

VCC Power Supply -0.3 to 4.6 V

TAOperating Temperature -40 to 85 °C

TSTG Storage Temperature -55 to 150 °C

PDPower Dissipation 1.0 W

Truth Table

SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode

I/O Pin

PowerI/O0 - I/O7 I/O8 - I/O15

H(1) X

XXXXDeselected High-Z High-Z StandbyX(1) L

XX HH

L(1) HHH

Output Disabled High-Z High-Z ActiveHL

LHLX

Write

DIN High-Z

Active

HL High-Z D

LL DIN DIN

DIN High-Z

LHHL

Read

DOUT High-Z

Active

HL High-Z D

OUT

LL DOUT DOUT

DOUT High-Z

Recommended DC Operating Condition

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 2.7 3.0 3.3 V

VSS Ground 0 0 0 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VIL(1) Input Low Voltage -0.3(1) 0.6 V

30 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Note: 1. These parameters are sampled and not 100% tested.

DC Electrical Characteristics

TA = -40°C to 85°C

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current VSS < VIN < VCC -1 1 µA

ILO Output Leakage Current VSS < VOUT < VCC,

SCS1 = VIH or SCS2=VIL or

SOE = VIH or SWE = VIL or

SUB = VIH, SLB = VIH

-1 1 µA

ICC Operating Power Supply Current SCS1 = VIL, SCS2=VIH,

VIN = VIH or VIL, II/O = 0 mA

3mA

ICC1 Average Operating Current SCS1 = VIL, SCS2 = VIH,

VIN = VIH or VIL, Cycle Time = Min

100% Duty, II/O = 0 mA

15 mA

SCS1 < 0.2V, SCS2 > VCC - 0.2V

VIN < 0.2V or VIN > VCC - 0.2V,

Cycle Time = 1 µs

100% Duty, II/O = 0 mA

2mA

ISB Standby Current (TTL Input) SCS1 = VIH or SCS2 = VIL or

SUB, SLB = VIH

VIN = VIH or VIL

300 µA

ISB1 Standby Current (CMOS Input) SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

10 µA

VOL Output Low IOL = 2.1 mA 0.4 V

VOH Output High IOH = -1.0 mA 2.4 V

Capacitance(1)

(Temp = 25°C, f = 1.0 MHz)

Symbol Parameter Condition Max Unit

CIN Input Capacitance (Add, SCS1,

SCS2, SLB, SUB, SWE, SOE)

VIN = 0 V 8 pF

COUT Output Capacitance (I/O) VI/O = 0 V 10 pF

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

AC Characteristics

TA = -40°C to 85°C, Unless Otherwise Specified

# Symbol Parameter

70 ns

UnitMin Max

RC Read Cycle Time 70 ns

AA Address Access Time 70 ns

ACS Chip Select Access Time 70 ns

OE Output Enable to Output Valid 35 ns

BA SLB, SUB Access Time 70 ns

CLZ Chip Select to Output in Low Z 10 ns

OLZ Output Enable to Output in Low Z 5 ns

BLZ SLB, SUB Enable to Output in Low Z 10 ns

CHZ Chip Deselection to Output in High Z 0 25 ns

10 tOHZ Out Disable to Output in High Z 0 25 ns

11 tBHZ SLB, SUB Disable to Output in High Z 0 25 ns

12 tOH Output Hold from Address Change 10 ns

13 tWC Write Cycle Time 30 ns

14 tCW Chip Selection to End of Write 30 ns

15 tAW Address Valid to End of Write 30 ns

16 tBW SLB, SUB Valid to End of Write 30 ns

17 tAS Address Setup Time 0 ns

18 tWP Write Pulse Width 30 ns

19 tWR Write Recovery Time 0 ns

20 tWHZ Write to Output in High Z 0 20 ns

21 tDW Data to Write Time Overlap 20 ns

22 tDH Data Hold from Write Time 0 ns

23 tOW Output Active from End of Write 5 ns

AC Test Conditions

TA = - 4 0 °C to 85°C, Unless Otherwise Specified

Parameter Value

Input Pulse Level 0.4V to 2.2V

Input Rise and Fall Time 5 ns

Input and Output Timing Reference Level 1.5V

Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW CL = 5 pF + 1 TTL Load

Others CL = 30 pF + 1 TTL Load

32 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

AC Test Loads

Note: Including jig and scope capacitance.

DOUT

1728 Ohm

1029 Ohm

VTM = 2.8V

(1)

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Timing Diagrams

Read Cycle 1(1),(4)

Read Cycle 2(1),(2),(4)

Read Cycle 3(1),(2),(4)

Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active

status.

2. SOE = VIL.

3. Transition is measured ± 200 mV from steady state voltage. This parameter is sampled and not 100% tested.

4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the

standby, low for active.

ADDRESS

SOE

SUB, SLB

SCS1

SCS2

DATA OUT HIGH-Z DATA VALID

tAA

tRC

tBA

tACS

tOE

tOLZ

tBLZ

tCLZ

tBHZ

tCHZ

tOH

tOHZ

(3)

DATA OUT

ADDRESS

tAA

PREVIOUS DATA

tOH

DATA VALID

tOH

tRC

SUB, SLB

SCS1

SCS2

DATA OUT

ACS

CLZ (3)

DATA VALID

CHZ(3)

34 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Write Cycle 1 (SWE Controlled)(1),(4),(8)

Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)

Notes: 1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.

2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be

applied.

4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after

the SWE transition, outputs remain in a high impedance state.

5. Q (data out) is the same phase with the write data of this write cycle.

6. Q (data out) is the read data of the next address.

7. Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested.

8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,

low for active.

ADDRESS

SWE

SUB, SLB

DATA IN

SCS1

SCS2

DATA OUT

tWC

tCW

tAW

tBW

tWP

tAS

tWHZ

tWR

tDW tDH

tOW

DATA VALID

HIGH-Z

tAS

(2)

(5) (5)

(3)(7)

ADDRESS

SWE

SUB, SLB

DATA IN

SCS1

SCS2

DATA OUT

tWC

tCW

tAW

tBW

tWP

tAS tWR

tDW tDH

DATA VALID

HIGH-Z

(2)

HIGH-Z

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Notes: 1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.

2. tRC is read cycle time.

Data Retention Timing Diagram 1

Data Retention Timing Diagram 2

Data Retention Electric Characteristic

TA = -40°C to 85°C

Symbol Parameter Test Condition Min Typ Max Unit

VDR VCC for Data Retention SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

1.2 3.3 V

ICCDR Data Retention Current Vcc=1.5V,

SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

0.2 6 µA

tCDR Chip Deselect to Data

Retention Time

See Data Retention Timing Diagram 0 ns

tROperating Recovery Time tRC ns

DATA RETENTION MODE

tCDR

VCC

SCS1 > VCC - 0.2V

2.7V

VDR

SCS1

VSS

VCC

2.7V

VDR

SCS2

VSS

0.4V

DATA RETENTION MODE

tCDR

SCS2 < 0.2V

36 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

8-megabit

SRAM

Description

The 8-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 512K

words by 16 bits. The SRAM uses high-performance full CMOS process technology and is

designed for high-speed and low-power circuit technology. It is particularly well-suited for the

high-density low-power system application. This device has a data retention mode that guar-

antees data to remain valid at a minimum power supply voltage of 1.2V.

Features

•Fully Static Operation and Tri-state Output

•TTL Compatible Inputs and Outputs

•Battery Backup

– 1.2V (Min) Data Retention

Block Diagram

Voltage (V) Speed (ns)

Operation

Current/ICC (mA)

(Max)

Standby

Current (µA)

(Max)

Temperature

(°C)

2.7 - 3.3 70 3 15 -40 - 85

MEMORY ARRAY

512K X 16

I/O0

SUB

SLB

SOE

SCS2

SCS1

SWE

DATA I/O BUFFER

SENSE AMP WRITE DRIVER

I/O7

I/O8

I/O15

ROW DECODER

COLUMN

DECODER

BLOCK

DECODER

PRE DECODER

ADD INPUT BUFFER

A18

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is

stress rating only and the functional operation of the device under these or any other conditions above those indicated in the

operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may

affect reliability.

Notes: 1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)

2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is

LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8

- I/O15.

Note: 1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.

Absolute Maximum Ratings(1)

Symbol Parameter Rating Unit

VIN, VOUT Input/Output Voltage -0.3 to 3.6 V

VCC Power Supply -0.3 to 4.6 V

TAOperating Temperature -40 to 85 °C

TSTG Storage Temperature -55 to 150 °C

PDPower Dissipation 1.0 W

Truth Table

SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode

I/O Pin

PowerI/O0 - I/O7 I/O8 - I/O15

H(1) X

XXXXDeselected High-Z High-Z StandbyX(1) L

XX HH

L(1) HHH

Output Disabled High-Z High-Z ActiveHL

LHLX

Write

DIN High-Z

Active

HL High-Z D

LL DIN DIN

DIN High-Z

LHHL

Read

DOUT High-Z

Active

HL High-Z D

OUT

LL DOUT DOUT

DOUT High-Z

Recommended DC Operating Condition

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 2.7 3.0 3.3 V

VSS Ground 0 0 0 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VIL(1) Input Low Voltage -0.3(1) 0.6 V

38 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Note: 1. These parameters are sampled and not 100% tested.

DC Electrical Characteristics

TA = -40°C to 85°C

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current VSS < VIN < VCC -1 1 µA

ILO Output Leakage Current VSS < VOUT < VCC,

SCS1 = VIH or SCS2=VIL or

SOE = VIH or SWE = VIL or

SUB = VIH, SLB = VIH

-1 1 µA

ICC Operating Power Supply Current SCS1 = VIL, SCS2=VIH,

VIN = VIH or VIL, II/O = 0 mA

3mA

ICC1 Average Operating Current SCS1 = VIL, SCS2 = VIH,

VIN = VIH or VIL, Cycle Time = Min

100% Duty, II/O = 0 mA

15 mA

SCS1 < 0.2V, SCS2 > VCC - 0.2V

VIN < 0.2V or VIN > VCC - 0.2V,

Cycle Time = 1 µs

100% Duty, II/O = 0 mA

2mA

ISB Standby Current (TTL Input) SCS1 = VIH or SCS2 = VIL or

SUB, SLB = VIH

VIN = VIH or VIL

0.3 mA

ISB1 Standby Current (CMOS Input) SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

15 µA

VOL Output Low IOL = 2.1 mA 0.4 V

VOH Output High IOH = -1.0 mA 2.4 V

Capacitance(1)

(Temp = 25°C, f = 1.0 MHz)

Symbol Parameter Condition Max Unit

CIN Input Capacitance (Add, SCS1,

SCS2, SLB, SUB, SWE, SOE)

VIN = 0 V 8 pF

COUT Output Capacitance (I/O) VI/O = 0 V 10 pF

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

AC Characteristics

TA = -40°C to 85°C, Unless Otherwise Specified

# Symbol Parameter

70 ns

UnitMin Max

RC Read Cycle Time 70 ns

AA Address Access Time 70 ns

ACS Chip Select Access Time 70 ns

OE Output Enable to Output Valid 35 ns

BA SLB, SUB Access Time 70 ns

CLZ Chip Select to Output in Low Z 10 ns

OLZ Output Enable to Output in Low Z 5 ns

BLZ SLB, SUB Enable to Output in Low Z 10 ns

CHZ Chip Deselection to Output in High Z 0 25 ns

10 tOHZ Out Disable to Output in High Z 0 25 ns

11 tBHZ SLB, SUB Disable to Output in High Z 0 25 ns

12 tOH Output Hold from Address Change 10 ns

13 tWC Write Cycle Time 70 ns

14 tCW Chip Selection to End of Write 60 ns

15 tAW Address Valid to End of Write 60 ns

16 tBW SLB, SUB Valid to End of Write 60 ns

17 tAS Address Setup Time 0 ns

18 tWP Write Pulse Width 50 ns

19 tWR Write Recovery Time 0 ns

20 tWHZ Write to Output in High Z 0 20 ns

21 tDW Data to Write Time Overlap 30 ns

22 tDH Data Hold from Write Time 0 ns

23 tOW Output Active from End of Write 5 ns

AC Test Conditions

TA = - 4 0 °C to 85°C, Unless Otherwise Specified

Parameter Value

Input Pulse Level 0.4V to 2.2V

Input Rise and Fall Time 5 ns

Input and Output Timing Reference Level 1.5V

Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW CL = 5 pF + 1 TTL Load

Others CL = 30 pF + 1 TTL Load

40 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

AC Test Loads

Note: Including jig and scope capacitance.

DOUT

1728 Ohm

1029 Ohm

VTM = 2.8V

(1)

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Timing Diagrams

Read Cycle 1(1),(4)

Read Cycle 2(1),(2),(4)

Read Cycle 3(1),(2),(4)

Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active

status.

2. SOE = VIL.

3. Transition is measured ± 200 mV from steady state voltage. This parameter is sampled and not 100% tested.

4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the

standby, low for active.

ADDRESS

SOE

SUB, SLB

SCS1

SCS2

DATA OUT HIGH-Z DATA VALID

tAA

tRC

tBA

tACS

tOE

tOLZ

tBLZ

tCLZ

tBHZ

tCHZ

tOH

tOHZ

(3)

DATA OUT

ADDRESS

tAA

PREVIOUS DATA

tOH

DATA VALID

tOH

tRC

SUB, SLB

SCS1

SCS2

DATA OUT

ACS

CLZ (3)

DATA VALID

CHZ(3)

42 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Write Cycle 1 (SWE Controlled)(1),(4),(8)

Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)

Notes: 1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.

2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be

applied.

4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after

the SWE transition, outputs remain in a high impedance state.

5. Q (data out) is the same phase with the write data of this write cycle.

6. Q (data out) is the read data of the next address.

7. Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested.

8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,

low for active.

ADDRESS

SWE

SUB, SLB

DATA IN

SCS1

SCS2

DATA OUT

tWC

tCW

tAW

tBW

tWP

tAS

tWHZ

tWR

tDW tDH

tOW

DATA VALID

HIGH-Z

tAS

(2)

(5) (5)

(3)(7)

ADDRESS

SWE

SUB, SLB

DATA IN

SCS1

SCS2

DATA OUT

tWC

tCW

tAW

tBW

tWP

tAS tWR

tDW tDH

DATA VALID

HIGH-Z

(2)

HIGH-Z

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Notes: 1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.

2. tRC is read cycle time.

Data Retention Timing Diagram 1

Data Retention Timing Diagram 2

Data Retention Electric Characteristic

TA = -40°C to 85°C

Symbol Parameter Test Condition Min Typ Max Unit

VDR VCC for Data Retention SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

1.2 3.3 V

ICCDR Data Retention Current Vcc = 3V,

SCS1 > VCC - 0.2V or

SCS2 < VSS + 0.2V or

SUB, SLB > VCC - 0.2V

VIN > VCC - 0.2V or

VIN < VSS + 0.2V

18µA

tCDR Chip Deselect to Data

Retention Time

See Data Retention Timing Diagram 0 ns

tROperating Recovery Time tRC ns

DATA RETENTION MODE

tCDR

VCC

SCS1 > VCC - 0.2V

2.7V

VDR

SCS1

VSS

VCC

2.7V

VDR

SCS2

VSS

0.4V

DATA RETENTION MODE

tCDR

SCS2 < 0.2V

44 AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Ordering Information

tACC (ns) Ordering Code

Flash Boot

Block Flash Plane Architecture SRAM Package Operation Range

70 AT52BR3224A-70CI Bottom 32M – Single Bank 256K x 16 66C5 Industrial

(-40° to 85°C)

70 AT52BR3224AT-70CI Top 32M – Single Bank 256K x 16 66C5 Industrial

(-40° to 85°C)

70 AT52BR3228A-70CI Bottom 32M – Single Bank 512K x 16 66C5 Industrial

(-40° to 85°C)

70 AT52BR3228AT-70CI Top 32M – Single Bank 512K x 16 66C5 Industrial

(-40° to 85°C)

Package Type

66C5 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

Packaging Information

66C5 – CBGA

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball

Pitch Chip-scale Ball Grid Array Package (CBGA) A

66C5

09/19/01

Side View

0.12

Seating Plane

Top View

Bottom View

0.60 REF

A1 Ball Corner

Øb

Marked A1 Identifier

101112

1.20 REF

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

E 9.90 10.00 10.10

E1 – 8.80 –

D 7.90 8.00 8.10

D1 – 5.60 –

A – – 1.20

A1 0.25 – –

e 0.80 BSC

Øb – 0.40 –

Printed on recycled paper.

3338B–STKD–6/03 /xM

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warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

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