TL/F/10939
100391 Low Power Single Supply Hex TTL-to-ECL Translator
July 1992
100391
Low Power Single Supply Hex TTL-to-ECL Translator
General Description
The 100391 is a hex translator for converting TTL logic lev-
els to F100K ECL logic levels. The unique feature of this
translator, is the ability to do this translation using only one
a5V supply. The differential outputs allow each circuit to be
used as an inverting/non-inverting translator, or as a differ-
ential line driver. A common enable (E), when low, holds all
inverting outputs HIGH and all non-inverting inputs LOW.
The 100391 is ideal for those mixed ECL/TTL applications
which only have a a5V supply available. When used in the
differential mode, the 100391, due to its high common mode
rejection, overcomes voltage gradients between the TTL
and ECL ground systems.
Features
YOperates from a single a5V supply
YDifferential ECL outputs
Y2000V ESD protection
YCompanion chip to 100390 hex ECL-to-TTL translator
Logic Symbol
TL/F/109391
Pin Names Description
D0–D5Data Inputs (TTL)
Q0–Q5Data Outputs (PECL)
Q0–Q5Inverting Data Outputs (PECL)
E Enable Input (TTL)
Connection Diagrams
24-Pin DIP and SOIC
TL/F/109392
28-Pin PCC
TL/F/109393
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Logic Diagram
TL/F/109395
Truth Table
Inputs Outputs
DnEQ
nQ
n
HHH L
LHL H
HLL H
LLL H
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature (TSTG)b65§Ctoa
150§C
Maximum Junction Temperature (TJ)
Ceramic a175§C
Plastic a150§C
VCC Pin Potential to
Ground Pin b0.5V to a7.0V
ECL Output Current
(DC Output HIGH) b50 mA
TTL Input Voltage (Note 3) b0.5V to a7.0V
TTL Input Current (Note 3) b30 mA to a5.0 mA
ESD (Last Passing Voltage) (Min) (Note 2) 2000V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Case Temperature (TC)
Commercial 0§Ctoa
85§C
Military b55§Ctoa
125§C
Supply Voltage (VCC) 4.5V to 5.5V
Commercial
Commercial Version
TTL-to-ECL DC Electrical Characteristics VCC ea
5.0V g10%, GND e0V
Symbol Parameter Min Typ Max Units Conditions
VOH Output HIGH Voltage VCC b1025 VCC b955 VCC b870 mV VIN eVIH (max) or VIL (min)
VOL Output LOW Voltage VCC b1890 VCC b1705 VCC b1620 mV Loading with 50Xto VCC b2V
VOHC Output HIGH Voltage VCC b1035 mV VIN eVIH (min) or VIL (max)
Corner Point High Loading with 50Xto VCC b2V
VOLC Output LOW Voltage VCC b1610 mV
Corner Point Low
VIH Input HIGH Voltage 2.0 5.0 V Over VTTL,V
EE,T
CRange
VIL Input LOW Voltage 0 0.8 V Over VTTL,V
EE,T
CRange
IIH Input HIGH Current 10 mAV
IN ea
2.7V
Breakdown Test 20 mAV
IN ea
5.5V
IIL Input LOW Current
Dnb0.8 mA VIN ea
0.5V
Eb4.2
VFCD Input Clamp b1.2 V IIN eb
18 mA
Diode Voltage
ICC VCC Supply Current 32 69 mA Inputs Open
Note 4: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.
3
DIP Package AC Electrical Characteristics
VCC e5.0V g10%
Symbol Parameter TCe0§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
tPLH Propagation Delay 0.30 1.40 0.35 1.30 0.40 1.30 ns
Figures 1, 2
tPHL Data to Output
tPLH Propagation Delay 0.40 1.50 0.45 1.40 0.50 1.40 ns
Figures 1, 2
tPHL Enable to Output
tTLH Transition Time 0.35 1.70 0.35 1.70 0.35 1.70 ns
Figures 1, 2
tTHL 20% to 80%, 80% to 20%
SOIC and PCC Package AC Electrical Characteristics
VCC e5.0V g10%
Symbol Parameter TCe0§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
tPLH Propagation Delay 0.30 1.40 0.35 1.30 0.40 1.30 ns
Figures 1
and
2
tPHL Data to Output
tPLH Propagation Delay 0.40 1.50 0.45 1.40 0.50 1.40 ns
tPHL Enable to Output
tTLH Transition Time 0.35 1.70 0.35 1.70 0.35 1.70 ns
tTHL 20% to 80%, 80% to 20%
tOSHL Maximum Skew Common Edge PCC Only
Output-to-Output Variation 750 750 750 ps (Note 1)
Data to Output Path
tOSLH Maximum Skew Common Edge PCC Only
Output-to-Output Variation 700 700 700 ps (Note 1)
Data to Output Path
tOST Maximum Skew Opposite Edge PCC Only
Output-to-Output Variation 450 450 450 ps (Note 1)
Data to Output Path
tPS Maximum Skew PCC Only
Pin (Signal) Transition Variation 525 525 525 ps (Note 1)
Data to Output Path
Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both
HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
4
Industrial Version
DC Electrical Characteristics
VCC ea
5.0V g10%, GND e0V (Note 1)
Symbol Parameter TCeb
40§CT
C
e
0
§
Ctoa
85§CUnits Conditions
Min Max Min Max
VOH Output HIGH Voltage VCC b1085 VCC b870 VCC b1025 VCC b870 mV VIN eVIH (max) or VIL (min)
VOL Output LOW Voltage VCC b1890 VCC b1575 VCC b1890 VCC b1620 mV Loading with 50Xto VCC b2V
VOHC Output HIGH Voltage VCC b1095 VCC b1035 mV VIN eVIH (min) or VIL (max)
Corner Point High Loading with 50Xto VCC b2V
VOLC Output LOW Voltage VCC b1565 VCC b1610 mV
Corner Point High
VIH Input HIGH Voltage 2.0 5.0 2.0 5.0 V
VIL Input LOW Voltage 0 0.8 0 0.8 V
IIH Input HIGH Current 10 10 mAV
IN ea
2.7V
Breakdown Test 20 20 mAV
IN ea
5.5V
IIL Input LOW Current
Dnb0.8 b0.8 mA VIN ea
0.5V
Eb4.2 b4.2
VFCD Input Clamp b1.2 b1.2 V IIN eb
18 mA
Diode Voltage
ICC VCC Supply Current 29 69 29 69 mA Inputs Open
PCC AC Electrical Characteristics
VCC ea
5.0V g10%, GND e0V
Symbol Parameter TCeb
40§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
tPLH Propagation Delay 0.20 1.50 0.35 1.30 0.40 1.30 ns
Figures 1
and
2
tPHL Data to Output
tPLH Propagation Delay 0.35 1.60 0.45 1.40 0.50 1.40 ns
tPHL Enable to Output
tTLH Transition Time 0.35 1.70 0.35 1.70 0.35 1.70 ns
tTHL 20% to 80%, 80% to 20%
Note 1: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.
5
Military Version-Preliminary
TTL-to-ECL DC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND, TCeb
55§Ctoa
125§C, VTTL ea
4.5V to a5.5V
Symbol Parameter Min Max Units TCConditions Notes
VOH Output HIGH Voltage VCC b1025 VCC b870 mV 0§Cto
a
125§C
VCC b1085 VCC b870 mV b55§CV
IN eVIH (max) Loading with 1, 2, 3
VOL Output LOW Voltage VCC b1830 VCC b1620 mV 0§Cto or VIL (min) 50Xto VCC b2.0V
a125§C
VCC b1830 VCC b1555 mV b55§C
VOHC Output HIGH Voltage VCC b1035 mV 0§Cto
a
125§C
VCC b1085 mV b55§CV
IN eVIH (min) Loading with 1, 2, 3
VOLC Output LOW Voltage VCC b1610 mV 0§Cto or VIL (max) 50Xto VCC b2.0V
a125§C
VCC b1555 mV b55§C
VIH Input HIGH Voltage 2.0 V b55§Cto 1, 2, 3, 4
a125§C
VIL Input LOW Voltage 0.8 V b55§Cto 1, 2, 3, 4
a125§C
IIH Input HIGH Current 70 mAb55§Cto V
IN ea
2.7V 1, 2, 3
125§C
IIL Input LOW Current b1.0 mA b55§Cto V
IN ea
0.5V 1, 2, 3
a125§C
VFCD Input Clamp b1.2 V b55§Cto I
IN eb
18 mA 1, 2, 3
Diode Voltage a125§C
ICC VCC Supply Current 20 70 mA b55§Cto Inputs Open 1, 2, 3
a125§C
AC Electrical Characteristics VCC ea
5.0 g10%, GND e0V
Symbol Parameter Teb
55§CT
ea
25§CT
ea
125§CUnits Conditions Notes
Min Max Min Max Min Max
tPLH Propagation Delay 0.40 2.50 0.50 2.10 0.50 2.10 ns Figures 1, 2 1, 2, 3
tPHL Data and Enable to Output
tTLH Transition Time 0.30 2.00 0.30 2.00 0.30 2.00 ns Figures 1, 2 1, 2, 3
tTHL 20% to 80%, 80% to 20%
Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing
immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be
considered a worst case condition at cold termperatures.
Note 2: Screen tested 100% on each device at b55§C, a25§C and a125§C, Subgroups 1, 2, 3, 7 and 8.
Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C and a125§C, Subgroups A1, 2, 3, 7 and 8.
Note 4: Guaranteed by applying specified input condition and testing VOH/VOL.
6
Switching Waveforms
TL/F/109396
FIGURE 1. Propagation Delay and Transition Times
Test Circuit
TL/F/109397
FIGURE 2. AC Test Circuit
Notes:
VCC eVCCA ea
2V, GNDECL eGNDTTL e3.0V
VIH e0V, VIL eb
3V
L1, L2 and L3 eequal length 50Ximpedance lines
RTe50Xterminator internal to scope
Decoupling 0.1 mF from GND to VCC,V
EE and VTTL
All unused outputs are loaded with 50Xto GND
CLeFixture and stray capacitance s3pF
7
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
100391 D C QB
Device Number (Basic) Special Variations
QB eMilitary Grade Device with
Package Code Environmental and Burn-In
DeCeramic Dual-In-Line Processing
QePlastic-Leaded Chip Carrier (PCC)
PePlastic Dual-In-Line Temperature Range
SeSmall Outline (SOIC) C eCommercial (0§Ctoa
85§C)
IeIndustrial (b40§Ctoa
85§C)
PCC Only
MeMilitary (b55§Ctoa
125§C)
8
Physical Dimensions inches (millimeters)
24-Lead Small Outline Integrated Circuit (S)
NS Package Number M24B
24-Lead Plastic Dual-In-Line Package (P)
NS Package Number N24E
9
100391 Low Power Single Supply Hex TTL-to-ECL Translator
Physical Dimensions inches (millimeters) (Continued)
28-Lead Plastic Chip Carrier (Q)
NS Package Number V28A
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