500000629 - LSI CORPORATION

HOLT INTEGRATED CIRCUITS

www.holtic.com

GENERAL DESCRIPTION

The HI-3000 is a 1 Mbps Controller Area Network (CAN)

transceiver optimized for use in aerospace applications.

It interfaces between a CAN protocol controller and the

physical wires of the bus in a CAN network.

The HI-3000 supports two modes of operation: Normal

Mode and Standby Mode. The Standby Mode is a very

low-current mode which continues to monitor bus activity

and allows an external controller to manage wake-up.

In addition, the

HI-3000 provides a SPLIT pin to give an output reference

voltage of VDD/2 which can be used for stabilizing the re-

cessive bus level when the split termination technique is

used to terminate the bus.

A TXD dominant time-out feature also protects the bus

from being driven into a permanent dominant state (so-

called “babbling idiot”) if pin TXD becomes permanently

low due to application failure.

The device also has short circuit protection to +/-58V on

CANH, CANL and SPLIT pins and ESD protection to

+/- 6kV on all pins.

The HI-3001 is identical to the HI-3000 except the SPLIT

pin is substituted with a VIO supply voltage pin. This al-

lows the HI-3001 to interface directly with controllers with

3.3V supply voltages.

The HI-3002 provides both the SPLIT and

Differential

output amplitude and current drive capability are specifi-

cally enhanced to meet the needs of long cable runs typi-

cal of aerospace applications.

Superior common-mode receiver performance makes

the device especially suitable for applications where

ground reference voltages may vary from point to point

over long distances along the CAN bus.

VIO supply

voltage pins in a compact 16-pin QFN.

All three devices are available in industrial -40 C to +85 C

and extended -55 C to +125 C temperature ranges.

“RoHS compliant” lead-free options are also available

with optional burn-in for the extended temperature range.

FEATURES

Compatible withARINC 825 and ISO 11898-5 standards.

Signaling rates up to 1Mbit/s.

Internal VDD/2 voltage source available to stabilize the

recessive bus level if split termination is used (HI-3000

SPLIT pin).

VIO input on HI-3001 allows for direct interfacing with 3.3V

controllers.

Detection of permanent dominant on TXD pin (babbling

idiot protection).

High impedance allows connection of up to 120 nodes.

Input levels compatible with 3.3V or 5V controllers.

CANH, CANL and SPLIT pins short-circuit proof to +/-58V.

Will not disturb the bus if unpowered.

Extended temperature range and burn-in options for high

reliability applications.

·Compatible with CAN 2.0A & CAN 2.0B Specification

controllers

PIN CONFIGURATIONS (Top Views)

October 2015

( 3000 Rev. F) 10/15DS

HI-3000, HI-3001, HI-3002

1Mbps Avionics CAN Transceiver

with Low Power Standby Mode

8 - PIN PLASTIC NARROW BODY SOIC

RXD-4

GND-2

TXD-1

VDD-3

5 - SPLIT

7 - CANH

8 - STB

6 - CANL

HI-3000PSI

HI-3000PST

HI-3000PSM

RXD-4

GND-2

TXD-1

VDD-3

5 - VIO

7 - CANH

8 - STB

6 - CANL

HI-3001PSI

HI-3001PST

HI-3001PSM

16 - PIN PLASTIC 4 x 4mm QFN

HI-3002PCI

HI-3002PCT

HI-3002PCM

GND 1

GND 2

VDD 3

VDD 4

12 CANH

11 CANH

10 CANL

9 CANL

16 -

15 TXD

14 -

13 STDBY

VIO 5

RXD 6

-7

SPLIT 8

HOLT INTEGRATED CIRCUITS

HI-3000, HI-3001, HI-3002

BLOCK DIAGRAM

SIGNAL FUNCTION DESCRIPTION

TXD INPUT 100kOhm internal pull-up. Transmit Data Input.

GND POWER Chip 0V supply

VDD POWER Positive supply, 5V +/-5%. Bypass with 0.1uF ceramic capacitor.

RXD OUTPUT Receive Data Output.

CANL BUS I/O CAN Bus Line Low.

CANH BUS I/O CAN Bus Line High.

STB INPUT Standby Mode selection input. Drive STB low or connect to GND

for Normal operation. Drive STB high to select low-current Standby Mode.

SPLIT INPUT Supplies a VDD/2 output to provide recessive bus level stabilization when a split termination

(HI-3000) is used to terminate the bus.

100kOhm internal pull-up.

VIO INPUT Connect to a 3.3V supply to allow compatibility of all digital I/O (RXD, TXD, STB) with a

(HI-3001) 3.3V controller input.

PIN DESCRIPTIONS

Figure 1. HI-3000 Functional Block Diagram

V Split

Driver

TXD

Dominant

Detect

TXD

STB

RXD

GND

VDD

SPLIT

(HI-3000)

CANH

CANL

Standby

Control

Low power

Standby Rx

MUX

Main

Receiver

VIO

(HI-3001)

FUNCTIONAL DESCRIPTION

OPERATING MODES

The HI-3000 provides two modes of operation which are

selectable via the STB pin. Table 1 summarizes the modes.

due to an unpowered node with high leakage from the bus

lines to ground), the split circuit will force the recessive

voltage to VDD/2.

Short-circuit protection is provided on the CANH, CANL and

SPLIT pins. These

The short circuit current is limited

to less than 200mAtypical.

A timer circuit prevents the bus lines being driven into a

permanent dominant state, which would result in a situation

blocking all bus traffic. This could happen in the case of the

TXD pin becoming permanently low due to a hardware or

application failure. The timer is triggered by a negative edge

on the TXD pin (start of dominant state). If the TXD pin is not

set high (recessive state) after a typical time of 2ms, the

transmitter outputs will be disabled, driving the bus lines into

the recessive state. The timer is reset by a positive edge on

the TXD pin. Note that the minimum TXD dominant time-out

time, tdom = 300μs, defines the minimum possible bit rate of

40kbit/s (the CAN protocol specifies a maximum of 11

successive dominant bits 5 successive dominant bits

immediately followed by an error frame).

Pin TXD has a pull up in order to force a recessive level if pin

TXD is left open.

Pins TXD and STB will become floating if power is lost. This

will prevent reverse currents via these pins.

INTERNAL PROTECTION FEATURES

Short-circuit protection

TXD permanent dominant time-out

Fail-safe features

pins are protected from ESD to over 6KV

(HBM) and from shorts between -58V and +58V continuous,

as specified in ISO 11898-5.

−

Normal Mode

Normal mode is selected by setting the STB pin to a LOW

logic level (GND). In this mode, the transceiver transmits and

receives data in the usual way from the CANH and CANL bus

lines. The differential receiver converts the analog bus data

to digital data which is output on the RXD pin (Note: the RXD

output on HI-3001 is compatible with 3.3V controllers if the

VIO pin is connected to a 3.3V supply).

Standby Mode

Standby Mode is selected by setting the STB pin to a HIGH

logic level. In this mode, the transmitter is switched off and a

low power differential receiver monitors the bus lines for

activity. A dominant signal of more than 3 s will be reflected

on the RXD pin as a logic LOW, where it may be detected by

the host as a wake-up request. The device will not leave

standby mode until the host forces the STB pin to a logic low.

The SPLIT pin provides a stable VDD/2 DC voltage. This

pin can be used to stabilize the recessive common mode

voltage by connecting the SPLIT pin to the center tap of the

split termination (see figure 7). In the case of a recessive

bus voltage dropping below the ideal value of VDD/2 (e.g.

SPLIT Circuit

MODE STB pin

Normal LOW

Standby HIGH

HOLT INTEGRATED CIRCUITS

Table 1 - Operating Modes

HI-3000, HI-3001, HI-3002

HOLT INTEGRATED CIRCUITS

tRdom

TIMING DIAGRAMS

DIFF(BUS)

CANH CANL

Dominant

0.9V

0.5V

RXD

HIGH

LOW

50% 50%

CANH

CANL

Recessive

TXD

HIGH

LOW

tdr(TXD)

tdf(TXD)

tdf(RXD) tdr(RXD)

tProp1 tProp2

Timing Delays

TXD dominant time-out feature

CANH

CANL

TXD

HIGH

LOW

recessive

dominant

transmitter

enabled

tdom(TXD)

transmitter disabled

HI-3000, HI-3001, HI-3002

DC ELECTRICAL CHARACTERISTICS

V = 5V 5%, Operating temperature range (unless otherwise noted). Positive currents flow into the IC.DD ±

LIMITS

PARAMETER CONDITIONS UNIT

SYMBOL

V Supply Current I Recessive: V = V 6 10 mA

MIN TYP MAX

POWER SUPPLIES

DD DD TXD DD

Dominant: V = 0 V 50 70 mA

Standby Mode:

TXD

DRIVER

V=V 15 30 μA

V Supply Current I 100 μA

HIGH-level input voltage (see Note 1) V 80%V V + 0.5 V

LOW-level input voltage V 0.5 20%V V

HIGH-level input current I V = V or VIO 5 0 + 5 μA

LOW-level input current I V = 0 V 50 150 μA

HIGH-level output voltage (RXD Pin) (see Note 1) V I = 1mA 90%V V

LOW-level output voltage (RXD Pin) V I = 1mA 0 0.1 10%V V

Output voltage (SPLIT Pin) V 100 μA < I < 100 μA 0.45V 0.5V 0.55V V

Standby leakage current (SPLIT Pin) I -5 +5 μA

CANH dominant output voltage V V = 0 V 3 3.6 4.25 V

CANL dominant output voltage V V = 0 V (See Fig. 2) 0.5 1.4 1.75 V

Recessive output voltage V ,

V V = V , R = 0 (See Fig. 2) 0.5V 3 V

Bus output voltage in standby V V = V , R = 0 (See Fig. 2) -0.1 0.1 V

Dominant differential output voltage V V = 0 V, 45 < R < 65 1.5 1.8 3 V

Recessive differential output voltage V V = V , no load (See Fig. 2) 50 0 50 mV

TXD DD

IO IO

IH DD DD

IL DD

IH TXD DD

IL TXD

OH OH DD

OL OL DD

SPLIT SPLIT DD DD DD

STB

O(CANH) TXD

O(CANL) TXD

CANH(r)

CANL(r) TXD DD L DD

STB TXD DD L

DIFF(d)(o) TXD L

DIFF(r)(o) TXD DD

DIGITAL INPUTS (Pins TXD, STB)

DIGITAL OUTPUTS

V Supply Voltage (see Note 1) V 2.7 5.5 VIO IO

−

−−

−

ΩΩ

−

NOTES:

1. Human Body Model (HBM).

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

2. Junction Temperature T is defined as T = T + P

J J AMB × R , where T is the ambient or operating temperature, P is the power dissipation and R is

a fixed thermal resistance value which depends on the package and circuit board mounting conditions

th AMB th

ABSOLUTE MAXIMUM RATINGS

Maximum Junction Temperature

Storage Temperature Range: ................................... -65°C to +150°C

Reflow Soldering Temperature: ................................................. 260°C

Operating Temperature Range: (Industrial).........................-40°C to +85°C

(Hi-Temp)........................-55°C to +125°C

......................................................175°C

Supply Voltage, VDD, VIO : .....................................................................7V

Current at Input pins

DC Voltages at TXD, RXD and STB ..............................-0.5V to V +0.5V

: ...............................

......................................................-100mA to +100mA

DC Voltages at CANH, CANL and SPLIT -58V to +58V

Internal Power Dissipation: ..............................................................900mW

Electrostatic Discharge (ESD) , All pins ..........................................+/- 6kV

(Voltages referenced to GND = 0V)

HI-3000, HI-3001, HI-3002

HOLT INTEGRATED CIRCUITS

NOTE:

1. When V is connected (HI-3001 or HI-3002), power supply limits are referenced wrt V rather than V . If V < 3.3V, V must be at least 2.5V.

IO IO DD IO IH

DC ELECTRICAL CHARACTERISTICS (cont.)

V = 5V 5%, Operating temperature range. Positive currents flow into the IC.DD ±

LIMITS

PARAMETER CONDITIONS UNIT

SYMBOL MIN TYP MAX

Input leakage current, unpowered node I , I V = 0 V

200 + 200 μA

CANH CANL DD

Matching of dominant output voltage,

V V V V (See Fig. 4) 100 -40 150 mV

Steady state common mode output voltage V V = 0V, R = 60 (See Fig. 5) 0.5V 3 V

DD O(CANH) O(CANL) OM

OC(ss) STB L DD

−− −

Ω2

Short-circuit steady-state output current I V = +58V, V open -20 20 mA

V = -58V, V openV -200 100 mA

V = +58V, V open 100 200 mA

V = -58V, V open (See Fig. 6) -20 20 mA

Differential receiver threshold voltage V 12V<V ,V <+12V 500 700 900 mV

Differential hysteresis voltage V 12V<V ,V <+12V 50 120 200 mV

Differential hysteresis voltage in Standby mode V 12V<V ,V <+12V 500 1150 mV

V=V=5V

Differential input resistance R V = V

12V<V ,V <+12V 2 50 75 k

Common mode input resistance R V = V

12V<V ,V <+12V 1 30 45 k

RV=V3+3%

OS(ss) CANH CANL

CANH CANL

CANL CANH

Th(Rx)(diff) CANH CANL

Hys(Rx)(diff) CANH CANL

Hys(Stb)(diff) CANH CANL

CANH CANL

IN(DIFF) TXD DD

CANH CANL

IN(CM) TXD DD

CANH CANL

IN(CM)(m) CANH CANL

RECEIVER

−

−5Ω

Deviation between common mode input resistance

between CANH and CANL −

HOLT INTEGRATED CIRCUITS

HI-3000, HI-3001, HI-3002

AC ELECTRICAL CHARACTERISTICS

V = 5V 5%, Operating temperature range. Positive currents flow into the IC.DD ±

NOTES:

1. All currents into the device pins are positive; all currents out of the device pins are negative.

2. All typicals are given for V = 5V, T = 25°C.

3. Guaranteed by design but not tested.

DD A

LIMITS

PARAMETER CONDITIONS UNIT

SYMBOL MIN TYP MAX

Delay TXD to bus active t 40 90 ns

dr(TXD)

Bit time t 1 25 μs

Bit rate f 40 1000 kHz

Common mode input capacitance C V = V , 1Mbit/s data rate 20 pF

Differential input capacitance C V = V , 1Mbit/s data rate 10 pF

Delay TXD to bus inactive t See Timing Diagrans 40 90 ns

Delay bus active to RXD t 30 70 ns

Delay bus inactive to RXD t 70 150 ns

Propagation delay TXD to RXD (recessive to dominant) t 70 160 ns

Propagation delay TXD to RXD (dominant to recessive) t 110 240 ns

TXD permanent dominant time-out t V = 0 V 0.3 2 6 ms

TXD permanent dominant timer reset time t Rising edge on TXD while in

permanent dominant state 1 μs

Dominant time required on bus for wake up from standby t 0.5 3 5 μs

Bit

IN(CM) TXD DD

DIFF(CM) TXD DD

df(TXD)

df(RXD)

dr(RXD)

Prop1

Prop2

dom TXD

Rdom

wake

VO(CANH)

VO(CANL)

Transceiver

RLVDIFF(d)(o)

TXD

STB

CANH 300 +/- 1%W

300 +/- 1%W

CANL

VDIFF(d)(o)

-12V <= V <= +12V

TEST

Transceiver

TXD

STB

VO(CANH)

VO(CANL)

Transceiver

RLVDIFF(d)(o)

VV-V +

OM DD O(CANH)

O(CANL)

STB

TXD

HOLT INTEGRATED CIRCUITS

Application and Test Information

Figure 3. CAN Bus Driver (Dominant) Test Circuit

Figure 4. Driver Output Symmetry Test.

Figure 2. CAN Bus Driver Circuit

Recessive

Dominant

~2.5V

~3.5V:VO(CANH)

~1.5V: V

O(CANL)

HI-3000, HI-3001, HI-3002

HOLT INTEGRATED CIRCUITS

Application and Test Information

Figure 6. CAN Bus Driver Short-Circuit Test. (Note: V1 is a pulse from 0V to V with duty cycle

of 99% such that permanent dominant time-out is avoided).

HI-3000, HI-3001, HI-3002

Figure 5. Common Mode Output Voltage Test.

VO(CANH)

VO(CANL)

Transceiver

RLVDIFF(d)(o)

TXD

STB

V=V

OC(ss) O(CANH) +V

O(CANL)

-58V or +58V

CANH

CANL

Transceiver

TXD

HOLT INTEGRATED CIRCUITS

Application and Test Information

Figure 7. Typical Application Connections

Controller

TXD

RXD

VDD

Regulator

VBAT

GND

TXD

RXD

VDD

GND

STB CANL

CANH

SPLIT

R/2L

(optional)

CAN BUS

HI-3000

Controller

TXD

RXD

VDD

3.3V

Regulator

VBAT

GND

TXD

RXD

VIO

GND

STB CANL

CANH

CAN BUS

HI-3001

VDD

HI-3000, HI-3001, HI-3002

HOLT INTEGRATED CIRCUITS

ORDERING INFORMATION

HI-300xxxxx

TEMPERATURE

RANGE

FLOW BURN

-40°C TO +85°C

-55°C TO +125°C

YES

-55°C TO +125°C NO

PART

NUMBER

PACKAGE

DESCRIPTION

16 PIN PLASTIC4x4mmQFN(16PCS) (HI-3002 only)

PART

NUMBER

8 PIN PLASTIC NARROW BODY SOIC (8HN) (HI-3000 or HI-3001 only)

8 PIN CERDIP (8D) not available Pb-free (HI-3000 or HI-3001 only)

LEAD

FINISH

PART

NUMBER

100% Matte Tin (Pb-free, RoHS compliant)

Tin / Lead (Sn / Pb) Solder

Blank

DESCRIPTION

PART

NUMBER

VIO pin option

3001

SPLIT pin option

3000

Both SPLIT and VIO pins available

3002

HI-3000, HI-3001, HI-3002

HOLT INTEGRATED CIRCUITS

P/N Rev Date Description of Change

3000 NEW 02/15/11 Initial Release

A 04/29/11 Corrected heat-sink note on QFN package drawing.

B 09/09/11 Update pad and heat-sink dimensions for 16-lead QFN package (16PCS)

C 12/18/12 Change high-level digital input voltage (VIH) to 80%VDD (or VIO) and low

20%VDD (or VIO). Update SOIC-8 and SOIC-16 package drawings.

D 10/30/14 Added "Compatible with CAN 2.0A & CAN 2.0B Specification controllers" to features.

Updated 8HN and 16PCS package drawings. Clarified Reflow Soldering Temperature in

Absolute Maximum Ratings.

E 6/19/15 Corrected package pin numbers 3 and 5 in Figure 7 HI-3001 Typical Application

Connections

F 10/14/15 Add parameter specification for VIO to DC Characteristics Table.

-level digital

input voltage (VIL) to

REVISION HISTORY

HOLT INTEGRATED CIRCUITS

8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB

(Narrow Body)

millimeters (inches)

Package Type: 8HN

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

See Detail A

0°to 8°

Detail A

PIN 1

6.00

(0.236)

3.90

(0.154)

4.90

(0.193)

0.175 ± 0.075

(0.007 ± 0.003)

1.27

(0.050)

0.835 ± 0.435

(0.033 ± 0.017)

1.25

(0.049)

0.175 ± 0.075

(0.007 ± 0.003)

0.41 ± 0.10

(0.016 ± 0.004)

BSC

BSC BSC

min.

16-PIN PLASTIC CHIP-SCALE PACKAGE millimeters(inches)

Package Type: 16PCS

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

Top View Bottom

View

Electrically isolated heat sink

pad on bottom of package

Connect to any ground or

power plane for optimum

thermal dissipation

4.000

(0.157)

BSC

4.000

(0.157)

BSC

1.000

(0.039)

max.

0.200

(0.008)

typ.

0.400 ± 0.050

(0.016 ± 0.002)

2.600 ± 0.050

(0.102 ± 0.002)

0.65

(0.0256)

BSC

0.300 ± 0.050

(0.012 ± 0.002)

2.600 ± 0.050

(0.102 ± 0.002)

PACKAGE DIMENSIONS

HOLT INTEGRATED CIRCUITS

PACKAGE DIMENSIONS

8-PIN CERDIP inches (millimeters)

Package Type: 8D

BSC = “Basic Spacing between Centers”

is theoretical true position dimension and

has no tolerance. (JEDEC Standard 95)

.380 ±.004

(9.652 ±.102)

.005 min

(.127 min)

.314 ±.003

(7.976 ±.076)

.200 max

(5.080 max)

.248 ±.003

(6.299 ±.076)

.039 ±.006

(.991 ±.154)

.163 ±.037

(4.140 ±.940)

.018 ±.006

(.457 ±.152)

.056 ±.006

(1.422 ±.152)

.015 min

(.381min)

.350 ±.030

(8.890 ±.762)

.010 ±.006

(.254 ±.152)

Base Plane

Seating Plane

.100 BSC

(2.54)