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This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC8255 PowerQUICC II™
communications processor.
The following topics are addre ssed :
Topic Page
Section 1.1, “Features” 2
Section 1.2, “Electrical and Thermal Characteristics” 5
Section 1.2.1, “DC Electrical Characteristics” 5
Section 1.2.2, “Thermal Characteristics” 9
Section 1.2.3, “Power Considerations” 9
Section 1.2.4, “AC Electrical Characteristics” 10
Section 1.3, “Clock Configuration Modes” 16
Section 1.3.1, “Local Bus Mode” 16
Section 1.4, “Pinout” 20
Section 1.5, “Package Description” 33
Section 1.6, “Ord ering Inform ation” 35
Advance Information
MPC8255EC/D
Rev. 0.4, 5/2002
MPC8255
Hardware Specifications
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MPC8255 Hardware Specifications
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Features
Figure 1 shows the block diagram for the MPC8255.
Figure 1. MPC8255 Block Diagram
1.1 Features
The major features of the MPC8255 are as follows:
• Footprint-compatible with the MPC8260
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–200 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
16 Kbytes
G2 Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Ti me rs
Parallel I/O
Baud Rate
Generators
32 Kbytes
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
4 Virtual
IDMAs
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
Local Bus
32 bits, up to 83 MHz
MCC2 FCC1 FCC2 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C
Serial Interface
2 MII
Ports
60x Bus
Dual-Port RAM
Interrupt
Controller
Time Slot Assigner
4 TDM Ports Non-Multiplexed
I/O
60x-to-Local
Bus Interface Unit
2 UTOPIA
Ports
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Features
• Separate power supply for internal logic (2.5 V in HiP3, 2.0 V in HiP4) and for I/O (3.3V)
• Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at diff erent frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
• 64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
• 32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
• System interface unit (SIU)
— Clock synt he sizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
• Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
• CPU core can be disabled and the device can be used in slave mode to an external core
• Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible
support for communications protocols
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
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Features
— Two fast communications controllers (FCC1 and FCC2) supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,
AAL1, AAL0 protoco ls, TM 4.0 CBR, VBR, UBR, ABR traf fi c t ype s, up t o 16 K ex te rnal
connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— One multichannel controller (MCC2)
– Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Fou r seri al communica tions controllers (SCCs) identical to those on th e MPC860, su pporting
the digital portions of the following pro toc ols :
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— On e inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to four T DM interfac es
– Supports one group of four TDM channels
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEP T, T1/E1, T3/E3, puls e code modulation high way, ISDN basic rate, IS DN
prim ary rate, Motorola interc hip di gital link (ID L), ge neral circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
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Electrical and Thermal Characteristics
1.2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8255.
1.2.1 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8255. Table 1 shows the maximum
electrical ratings.
Table 2 lists recommended operational voltage conditions.
Table 1. Absolute Maximum Ratings1
1 Absolute maximum ratings are stress ratings only; functional operation (see
Table 2) at the maximums is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage.
Rating Symbol Value Unit
Core supply voltage2
2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time,
including during power-on reset.
VDD -0.3 – 2.5 V
PLL supply voltage2VCCSYN -0.3 – 2.5 V
I/O supply voltage3
3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no
more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than
2.5 V during normal operation.
VDDH -0.3 – 4.0 V
Input voltage4
4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including
during power-on reset.
VIN GND(-0.3) – 3.6 V
Junction temperature Tj120 °C
Storage temperature range TSTG (-55) – (+150) °C
Table 2. Recommended Operating Conditions1
1 Caution: These are the recommended and tested operating conditions. Proper device
operating outside of these conditions is not guaranteed.
Rating Symbol Value Unit
Core supply voltage VDD 1.7 – 2.12/ 1.9–2.13
2 For devices operating at less than 233 MHz CPU, 166 MHz CPM, and 66 MHz bus
frequencies.
3 For devices operating at greater than or equal to 233 MHz CPU, 166 MHz CPM, and
66 MHz bus frequencies.
V
PLL supply voltage VCCSYN 1.7 – 2.12/ 1.9–2.13V
I/O supply voltage VDDH 3.135 – 3.465 V
Input voltage VIN GND (-0.3) – 3.465 V
Junction temperature (maximum) Tj1054
4 Note that for extended temperature parts the range is (-40)TA– 105Tj.
°C
Ambient temperature TA0–704°C
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NOTE
VDDH and VDD must track each other and both must vary in the same
direct ion—i n the p ositive direct ion ( +5% and +0 .1 Vdc) or in t he negat ive
direction (-5% and -0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or VCC).
Table 3 shows DC electrical characteristics.
Table 3. DC Electrical Characteristics
Characteristic Symbol Min Max Unit
Input high voltage, all inputs except CLKIN VIH 2.0 3.465 V
Input low voltage VIL GND 0.8 V
CLK IN input high vol tage VIHC 2.4 3.465 V
CLK IN input low voltage VILC GND 0.4 V
Input leaka ge current, VIN = VDDH1IIN —10µA
Hi-Z (off state) leakage current, VIN = VDDH1IOZ —10µA
Signal low input current, VIL = 0.8 V IL—1µA
Signal high input current, VIH = 2.0 V IH—1µA
Output high volt age, IOH = –2 mA
except XFC, UTOPIA mode, and open drain pins
In UTOPIA mode: IOH = -8.0mA
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
VOH 2.4 — V
In UTOPIA mode: IOL = 8.0mA
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
VOL —0.5V
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IOL = 7.0mA
BR BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
VOL —0.4V
Table 3. DC Electrical Characteristics (Continued)
Characteristic Symbol Min Max Unit
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IOL = 5.3mA
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0:3]/LBS[0–3]
LSDA10/LGPL0
LSDWE/LGPL1
LOE/LSDRAS/LGPL2
LSDCAS/LGPL3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
IOL = 3.2mA
L_A14
L_A15/SMI
L_A16
L_A17/CKSTP_OUT
L_A18
L_A19
L_A20
L_A21
L_A22
L_A23
L_A24
L_A25
L_A26
L_A27
L_A28/CORE_SRESET
L_A29
L_A30
L_A31
LCL_D(0-31)
LCL_DP(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
VOL —0.4V
1 The leaka ge c urren t is mea sur ed for n omina l VD DH a nd VDD or bot h VDDH an d VD D must va ry in the s ame
direction; that is, VDDH and VDD either both vary in the positive direction (+5% and +0.1 Vdc) or both vary in
the negative direction (-5% and -0.1 Vdc).
Table 3. DC Electrical Characteristics (Continued)
Characteristic Symbol Min Max Unit
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1.2.2 Thermal Characteristics
Table 4 describes ther mal ch ar ac ter istics .
1.2.3 Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from the following:
TJ = TA + (PD x θJA) (1)
where
TA = ambient temperature °C
θJA = package thermal resist ance, junction to ambient, °C/W
PD = PINT + PI/O
PINT = IDD x VDD Watts (chip internal po wer)
PI/O = power dissipation on input and output pins (determined by user)
For mo st ap plica tions PI/O < 0.3 x PINT. If PI/O is neglected, an appr oxima te r elati onshi p b etween P D and TJ
is the following :
PD = K/(TJ + 273° C) (2)
Solving equations (1) and (2) for K gives:
K = PD x (TA + 273° C) + θJA x PD2 (3)
where K is a const ant pertaini ng to the parti cular part. K can be dete rmined from equati on (3) by measuri ng
PD (at equilibrium) for a known T A. Using this value of K, the values of PD and TJ can be obtained by solving
equations (1) and (2) iteratively for any value of TA.
1.2.3.1 Layout Practices
Each VCC pin s hould be provi ded wit h a lo w-imp edance path t o the board’s power supply. Each gr ound pi n
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF
by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
asso cia te d printe d c ir cui t trace s c onnecting t o chip VCC and g round should be kept to less t han half an inch
per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.
Table 4. Thermal Characteristics
Characteristics Symbol Value Unit Air Flow
Ther mal resistance for TBGA θJA 13.071
1 Assumes a single layer board with no thermal vias
°C/W NC2
2 Natural convection
θJA 9.551°C/W 1 m/s
θJA 10.483
3 Assumes a four layer board
°C/W NC
θJA 7.783°C/W 1 m/s
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All output pins on the MPC8255 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V CC and GND circuits. Pull up all unused inputs or signals that will be inputs
during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above PD = 3W (when the ambient temperature is 70° C or
greater) to ensur e the juncti on temperatur e does not exce ed the maxi mum specifie d value. Als o note that t he
I/O power should be included when determining whether to use a heat sink.
1.2.4 AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8255 device. Note that AC timings are based on a 50-pf load. Typi cal output
buffer impedances are shown in Table 6.
Table 7 lists CPM output characteristics.
Table 5. Estimated Power Dissipation for Various Configurations1
1 Test temperature = room temperature (25° C)
Bus
(MHz) CPM
Multiplier Core CPU
Multiplier CPM
(MHz) CPU
(MHz)
PINT(W)2
2 PINT = IDD x VDD Watts
Vddl 1.8 Volts Vddl 2.0 Volts
Nominal Maximum Nominal Maximum
66.66 2 3 133 200 1.2 2 1.8 2.3
66.66 2.5 3 166 200 1.3 2.1 1.9 2.3
66.66 3 4 200 266 ——2.32.9
66.66 3 4.5 200 300 — — 2.4 3.1
83.33 2 3 166 250 — — 2.2 2.8
83.33 2 3 166 250 — — 2.2 2.8
83.33 2.5 3.5 208 291 — — 2.4 3.1
Table 6. Output Buffer Impedances1
1 These are typical values at 65° C. The impedance may vary
by ±25% with process and temperature.
Output Buffers Typical Impedance (Ω)
60x bus 40
Loc al bus 40
Memory controller 40
Parallel I/O 46
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Table 8 lists CPM input characteristics.
Note that although the specifications generally reference the rising edge of the clock, the following AC
timing diagrams also apply when the falling edge is the active edge.
Figure 2 shows the FCC external clock.
Figure 2. FCC External Clock Diagram
Table 7. AC Characteristics for CPM Outputs1
1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of
the signal. Timings are measured at the pin.
Spec_num
Max/Min Characteristic Max Delay (ns) Min Delay (ns)
66 MHz 83 MHz 66 MHz 83 MHz
sp36a/sp37a FCC outputs—in ternal clock (NM SI) 6 5.5 1 1
sp36b/sp37b FCC outputs—external clock (NMSI) 14 12 2 1
sp4 0/sp41 TDM outp uts/SI 25 16 5 4
sp38a/sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI) 19 16 1 0.5
sp38b/sp39b Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI) 19 16 2 1
sp42/sp43 PIO/TIMER/DMA outputs 14 11 1 0.5
Table 8. AC Characteristics for CPM Inputs1
1 Input specifications are measured from the 50% level of the signal to the 50% level of the rising
edge of CLKIN. Timings ar e meas ured at the pin.
Spec_num Characteristic Setup (ns) Hold (ns)
66 MHz 83 MHz 66 MHz 83 MHz
sp16a/sp17a FCC inputs—internal clock (NMSI) 10 8 0 0
sp16b/sp17b FCC inputs—external clock (NMSI) 3 2.5 3 2
sp20/sp2 1 TDM inputs/SI 15 12 12 10
sp18a/sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI) 20 16 0 0
sp18b/sp1 9b SCC/SMC/SPI/I2C inputs—extern al cl ock (NMSI) 5 4 5 4
sp22/sp23 PIO/TIMER/DMA inputs 10 8 3 3
Serial ClKin
FCC input signals
FCC output signals
sp16b sp17b
sp36b/sp37b
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Figure 3 shows the FCC internal clock.
Figure 3. FCC Internal Clock Diagram
Figure 4 shows the SCC/SMC/SPI/I2C external clock.
Figure 4. SCC/SMC/ SPI/I2C External Clock Diagram
Figure 5 shows the SCC/SMC/SPI/I2C internal clock.
Figure 5. SCC/SMC/SPI/I2C Internal Clock Diagram
BRG_OUT
FCC input signals
FCC output signals
sp16a
sp17a
sp36a/sp37a
Serial CLKin
SCC/SMC/SPI/I2C input sig nal s
SCC/SMC/SPI/I2C outp ut signal s
sp18b sp19b
sp38b/sp39b
BRG_OUT
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp18a sp19a
sp38a/sp39a
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Figure 6 shows PIO, timer, and DMA signals.
Figure 6. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
Table 10 lists SIU output characteristics.
Table 9. AC Characteristics for SIU Inputs1
1 Input specifications are measured from the 50% level of the signal to the 50% level of
the rising edge of CLKIN. Timings are measured at the pin.
Spec_num Characteristic Setup (ns) Hold (ns)
66 MHz83 MHz66 MHz83 MHz
sp11/sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR 6511
sp12/sp10 Data bus in normal mode 5 4 1 1
sp13/sp10 Data bus in ECC and PARITY modes 8 6 1 1
sp14/sp 10 DP pins 7 6 1 1
sp15/sp10 All other pins 5 4 1 1
Table 10. AC Characteristics for SIU Outputs1
1 Output specifications are measured from the 50% level of the rising edge of CLKIN to
the 50% level of the signal. Timings are measured at the pin.
Spec_num
Max/Min Characteristic Max Delay (ns) Min Delay (ns)
66 MHz 83 MHz 66 MHz 83 MHz
sp31/sp30 PSDVAL/TEA/TA 760.50.5
sp32/sp30 ADD/ADD_atr./BADDR/CI/GBL/WT 8 6.5 0.5 0.5
sp33a/sp30 Data bus 6.5 6.5 0.5 0.5
sp33b/sp30 DP 8 7 0.5 0.5
sp34/sp30 memc signals/ALE 6 5 0.5 0.5
sp35/sp30 all other signals 6 5.5 0.5 0.5
CLKin
PIO/TIMER/DMA input signals
TIMER/DMA output signals
sp22 sp23
sp42/sp43
PIO output signa ls
sp42/sp43
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Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Figure 7 shows TDM input and output signals.
Figure 7. TDM Signal Diagram
Figure 8 shows the interaction of several bus signals.
Figure 8. Bus Signals
Serial CLKin
TDM input signals
TDM output signals
sp20 sp21
sp40/sp41
CLKin
AACK/ARTRY/TA/TS/TEA/
DATA bus normal mode
All other input signals
PSDVAL/TEA/TA output signals
ADD/ADD_atr/BADDR/CI/
DATA bus output signals
All other output signals
sp11
sp12
sp15
sp10
sp10
sp10
sp30
sp30
sp30
sp30
sp32
sp33a
sp35
DBG/BG/BR input signals
GBL/WT output signals
sp31
input signal
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Figure 9 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 9. Parity Mode Diagram
Figure 10 shows signal behavior in MEMC mode.
Figure 10. MEMC Mode Diagram
NOTE
Generall y, all MPC8255 bus a nd system o utput si gnals ar e driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four int ern al t ic ks: T1 , T2, T3, and T4. T1 alwa ys occurs a t t he
rising edge, and T3 at th e fall ing ed ge, of CLKin . Howeve r, the spacing o f
T2 and T4 de pend s on th e PLL clo ck rat io sel ecte d, as sh own in Table 1 1.
CLKin
DATA bus, ECC, and PARITY mode input signals
DP mode input signal
DP mode output signal
sp13
sp10
sp14
sp10
sp33b/sp30
CLKin
V_CLK
Memory controller signals sp34/sp30
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Clock Configuration Modes
Figure 11 is a graphical representation of Table 11.
Figure 11. Internal Tick Spacing for Memory Controller Signals
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
1.3 Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 12 shows the eight basic configuration
modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins
on the data bus.
1.3.1 Local Bus Mode
Table 12 describes default clock modes for the MPC8255.
Table 11. Tick Spacing for Memory Controller Signals
PLL Clock Ratio Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2 T3 T4
1:2, 1:3, 1:4, 1:5, 1:6 1/4 CLKin 1/2 CLKin 3/4 CLKin
1:2.5 3/10 CLKin 1/2 CLKin 8/10 CLKin
1:3.5 4/14 CLKin 1/2 CLKin 11/14 CLKin
CLKin
T1 T2 T3 T4
CLKin
T1 T2 T3 T4
for 1:2.5
for 1:3.5
CLKin
T1 T2 T3 T4
for 1:2, 1:3, 1:4, 1:5, 1:6
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Clock Configuration Modes
Table 13 describes all possible clock configurations when using the hard reset configuration sequence.
Note that clock configuration changes only after POR is asserted. Note also that basic modes are shown in
boldface type.
Table 12. Clock Default Modes
MODCK[1–3] Input Clock
Frequency CPM Multiplic atio n
Factor CPM
Frequency Core Multiplication
Factor Core
Frequency
000 33 MHz 3 100 MHz 4 133 MHz
001 33 MHz 3 100 MHz 5 166 MHz
010 33 MHz 4 133 MHz 4 133 MHz
011 33 MHz 4 133 MHz 5 166 MHz
100 66 MHz 2 133 MHz 2.5 166 MHz
101 66 MHz 2 133 MHz 3 200 MHz
110 66 MHz 2.5 166 MHz 2.5 166 MHz
111 66 MHz 2.5 166 MHz 3 200 MHz
Table 13. Clock Configuration Modes1
MODCK_H–MODCK[1–3] Input Clock
Frequency2,3 CPM Multiplication
Factor2 CPM
Frequency2Core Multi plication
Factor2 Core
Frequency2
0001_000 33 MHz 2 66 MHz 4 133 MHz
0001_001 33 MHz 2 66 MHz 5 166 MHz
0001_010 33 MHz 2 66 MHz 6 200 MHz
0001_011 33 MHz 2 66 MHz 7 233 MHz
0001_100 33 MHz 2 66 MHz 8 266 MHz
0001_101 33 MHz 3 100 MHz 4133 MHz
0001_110 33 MHz 3 100 MHz 5166 MHz
0001_111 33 MHz 3 100 MHz 6 200 MHz
0010_000 33 MHz 3 100 MHz 7 233 MHz
0010_001 33 MHz 3 100 MHz 8 266 MHz
0010_010 33 MHz 4 133 MHz 4 133 MHz
0010_011 33 MHz 4 133 MHz 5 166 MHz
0010_100 33 MHz 4 133 MHz 6 200 MHz
0010_101 33 MHz 4 133 MHz 7 233 MHz
0010_110 33 MHz 4 133 MHz 8 266 MHz
0010_111 33 MHz 5 166 MHz 4 133 MHz
0011_000 33 MHz 5 166 MHz 5 166 MHz
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Clock Configuration Modes
0011_001 33 MHz 5 166 MHz 6 200 MHz
0011_010 33 MHz 5 166 MHz 7 233 MHz
0011_011 33 MHz 5 166 MHz 8 266 MHz
0011_100 33 MHz 6 200 MHz 4 133 MHz
0011_101 33 MHz 6 200 MHz 5 166 MHz
0011_110 33 MHz 6 200 MHz 6 200 MHz
0011_111 33 MHz 6 200 MHz 7 23 3 MHz
0100_000 33 MHz 6 200 MHz 8 266 MHz
0100_001 Reserved
0100_010
0100_011
0100_100
0100_101
0100_110
0100_111 Reserved
0101_000
0101_001
0101_010
0101_011
0101_100
0101_101 66 MHz 2 133 MHz 2 133 MHz
0101_110 66 MHz 2 133 MHz 2.5 166 MHz
0101_111 66 MHz 2 133 MHz 3 200 MHz
0110_000 66 MHz 2 133 MHz 3.5 233 MHz
0110_001 66 MHz 2 133 MHz 4 266 MHz
0110_010 66 MHz 2 133 MHz 4.5 300 MHz
0110_011 66 MHz 2.5 166 MHz 2 133 MHz
0110_100 66 MHz 2.5 166 MHz 2 .5 166 MHz
0110_101 66 MHz 2.5 166 MHz 3 200 MHz
0110_110 66 MHz 2.5 166 MHz 3.5 233 MHz
Table 13. C lock Configuration Modes1 (Continued)
MODCK_H–MODCK[1–3] Input Clock
Frequency2,3 CPM Multiplication
Factor2 CPM
Frequency2Core Multi plication
Factor2 Core
Frequency2
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MPC8255 Hardware Specifications
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Clock Configuration Modes
0110_111 66 MHz 2.5 166 MHz 4 266 MHz
0111_000 66 MHz 2.5 166 MHz 4.5 300 MHz
0111_001 66 MHz 3 200 MHz 2 133 MHz
0111_010 66 MHz 3 200 MHz 2.5 166 MHz
0111_011 66 MHz 3 200 MHz 3 200 MHz
0111_100 66 MHz 3 200 MHz 3.5 233 MHz
0111_101 66 MHz 3 200 MHz 4 266 MHz
0111_110 66 MHz 3 200 MHz 4.5 300 MHz
0111_111 66 MHz 3.5 233 MHz 2 133 MHz
1000_000 66 MHz 3.5 233 MHz 2.5 166 MHz
1000_001 66 MHz 3.5 233 MHz 3 200 MHz
1000_010 66 MHz 3.5 233 MHz 3.5 233 MHz
1000_011 66 MHz 3.5 233 MHz 4 266 MHz
1000_100 66 MHz 3.5 233 MHz 4.5 300 MHz
1100_000466 MHz 2 133 MH z Bypass 66 MHz
1100_001466 MHz 2.5 166 MHz Bypass 66 MHz
1100_010466 MHz 3 200 MH z Bypass 66 MHz
1 Because of speed dependencies, not all of the possible configurations in Table 13 are applicable.
2 The user should choose the input clock frequency and the multiplication factors such that the frequency of the
CPU is equal to or greater than 133 MHz (150 MHz for extended temperature parts) and the CPM ranges
between 66–233 MHz.
3 Input cloc k frequency is given only for th e purpose of refe rence. User shou ld set MODCK _H–MODCK_L so that
the resulting configuration does no t exceed the freq uency rating of the user’s part.
Example. If a pa rt is rated at 266 MHz CPU, 2 00 MHz CPM, and 66 MHz bus , any of the fol lowing ar e possibl e
(note that the three input clock frequencies are only three of many possible input clock frequencies):
1. 66 MHz in put cloc k and M ODC K_ H– MOD CK _L [0111–101] (with a c ore mu lti pli cation fa ct or o f 4 an d a C PM
multiplication factor of 3). The resulting configuration equals the part’s maximum possible frequencies of
266 MHz CPU, 200 MHz CPM, and 66 MHz bus.
2. 50 MHz input clock and MODCK_H–MODCK_L[0111–101] to achieve a configuration of 200 MHz CPU,
150 MHz CPM, and 50 MHz bus.
3. 40 MHz input clock and MODCK_H–MODCK_L[0010–011] to achieve a configuration of 200 MHz CPU,
160 MHz CPM, and 40 MHz bus.
Note that with each example, any one of several values for MODCK_H–MODCK_L could possibly be used as
long as the resulting configuration does not exceed the part’s rating.
4 At this mode the CPU PLL is bypassed (the CPU frequency equals the bus frequency).
Table 13. C lock Configuration Modes1 (Continued)
MODCK_H–MODCK[1–3] Input Clock
Frequency2,3 CPM Multiplication
Factor2 CPM
Frequency2Core Multi plication
Factor2 Core
Frequency2
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Pinout
1.4 Pinout
This section provides the pin assignments and pinout list for the MPC8255.
1.4.1 Pin Assignments
Figure 12 shows the pinout of the MPC8255’s 480 TBGA package as viewed from the top surface.
Figure 12. Pinout of the 480 TBGA Package as Viewed from the Top Surface
Figure 13 shows the side profile of the TBGA package to indicate the direction of the top surface view.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
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MPC8255 Hardware Specifications
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Pinout
Figure 13. Side View of the TBGA Package
Table 14 shows the pinout list of the MPC8255. Table 15 defines conventions and acronyms used in
Tab le 14.
Table 14. Pinout List
Pin Name Ball
BR W5
BG F4
ABB/IRQ2 E2
TS E3
A0 G1
A1 H5
A2 H2
A3 H1
A4 J5
A5 J4
A6 J3
A7 J2
A8 J1
A9 K4
A10 K3
A11 K2
A12 K1
A13 L5
A14 L4
A15 L3
A16 L2
A17 L1
A18 M5
A19 N5
Soldermask
Copper T races
Die
Copp er H eat Sp re ad er
(Oxidized fo r Insu la tion)
1.27 mm Pitch Glob -Top Dam
Wir
e
B
o
n
ds
Etched Pressure Sensitive
Die
Glob-Top Filled Area
Polymide Tape Cavity Adhesive
Attach
View
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Pinout
A20 N4
A21 N3
A22 N2
A23 N1
A24 P4
A25 P3
A26 P2
A27 P1
A28 R1
A29 R3
A30 R5
A31 R4
TT0 F1
TT1 G4
TT2 G3
TT3 G2
TT4 F2
TBST D3
TSIZ0 C1
TSIZ1 E4
TSIZ2 D2
TSIZ3 F5
AACK F3
ARTRY E1
DBG V1
DBB/IRQ3 V2
D0 B20
D1 A18
D2 A16
D3 A13
D4 E12
D5 D9
D6 A6
D7 B5
D8 A20
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
D9 E17
D10 B15
D11 B13
D12 A11
D13 E9
D14 B7
D15 B4
D16 D19
D17 D17
D18 D15
D19 C13
D20 B11
D21 A8
D22 A5
D23 C5
D24 C19
D25 C17
D26 C15
D27 D13
D28 C11
D29 B8
D30 A4
D31 E6
D32 E18
D33 B17
D34 A15
D35 A12
D36 D11
D37 C8
D38 E7
D39 A3
D40 D18
D41 A17
D42 A14
D43 B12
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
D44 A10
D45 D8
D46 B6
D47 C4
D48 C18
D49 E16
D50 B14
D51 C12
D52 B10
D53 A7
D54 C6
D55 D5
D56 B18
D57 B16
D58 E14
D59 D12
D60 C10
D61 E8
D62 D6
D63 C2
DP0/RSRV/EXT_BR2 B22
IRQ1/DP1/EXT_BG2 A22
IRQ2/DP2/TLBISYNC/EXT_DBG2 E21
IRQ3/DP3/CKSTP_OUT/EXT_BR3 D21
IRQ4/DP4/CORE_SRESET/EXT_BG3 C21
IRQ5/DP5/TBEN/EXT_DBG3 B21
IRQ6/DP6/CSE0 A21
IRQ7/DP7/CSE1 E20
PSDVAL V3
TA C22
TEA V5
GBL/IRQ1 W1
CI/BADDR29/IRQ2 U2
WT/BADDR30/IRQ3 U3
L2_HIT/IRQ4 Y4
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
CPU_BG/BADDR31/IRQ5 U4
CPU_DBG R2
CPU_BR Y3
CS0 F25
CS1 C29
CS2 E27
CS3 E28
CS4 F26
CS5 F27
CS6 F28
CS7 G25
CS8 D29
CS9 E29
CS10/BCTL1 F29
CS11/AP0 G28
BADDR27 T5
BADDR28 U1
ALE T2
BCTL0 A27
PWE0/PSDDQM0/PBS0 C25
PWE1/PSDDQM1/PBS1 E24
PWE2/PSDDQM2/PBS2 D24
PWE3/PSDDQM3/PBS3 C24
PWE4/PSDDQM4/PBS4 B26
PWE5/PSDDQM5/PBS5 A26
PWE6/PSDDQM6/PBS6 B25
PWE7/PSDDQM7/PBS7 A25
PSDA10/PGPL0 E23
PSDWE/PGPL1 B24
POE/PSDRAS/PGPL2 A24
PSDCAS/PGPL3 B23
PGTA/PUPMWAIT/PGPL4/PPBS A23
PSDAMUX/PGPL5 D22
LWE0/LSDDQM0/LBS0/H28
LWE1/LSDDQM1/LBS1/H27
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
LWE2/LSDDQM2/LBS2/H26
LWE3/LSDDQM3/LBS3/G29
LSDA10/LGPL0/ D27
LSDWE/LGPL1/ C28
LOE/LSDRAS/LGPL2/ E26
LSDCAS/LGPL3/ D25
LGTA/LUPMWAIT/LGPL4/LPBS C26
LGPL5/LSDAMUX B27
LWR D28
L_A14 N27
L_A15/SMI T29
L_A16 R27
L_A17/CKSTP_OUT R26
L_A18 R29
L_A19 R28
L_A20 W29
L_A21 P28
L_A22 N26
L_A23 AA27
L_A24 P29
L_A25 AA26
L_A26 N25
L_A27 AA25
L_A28/CORE_SRESET AB29
L_A29 AB28
L_A30 P25
L_A31 AB27
LCL_D0 H29
LCL_D1 J29
LCL_D2 J28
LCL_D3 J27
LCL_D4 J26
LCL_D5 J25
LCL_D6 K25
LCL_D7 L29
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
LCL_D8 L27
LCL_D9 L26
LCL_D10 L25
LCL_D11 M29
LCL_D12 M28
LCL_D13 M27
LCL_D14 M26
LCL_D15 N29
LCL_D16 T25
LCL_D17 U27
LCL_D18 U26
LCL_D19 U25
LCL_D20 V29
LCL_D21 V28
LCL_D22 V27
LCL_D23 V26
LCL_D24 W27
LCL_D25 W26
LCL_D26 W25
LCL_D27 Y29
LCL_D28 Y28
LCL_D29 Y25
LCL_D30 AA29
LCL_D31 AA28
LCL_DP0 L28
LCL_DP1 N28
LCL_DP2 T28
LCL_DP3 W28
IRQ0/NMI_OUT T1
IRQ7/INT_OUT/APE D1
TRST AH3
TCK AG5
TMS AJ3
TDI AE6
TDO AF5
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
TRIS AB4
PORESET AG6
HRESET AH5
SRESET AF6
QREQ AA3
RSTCONF AJ4
MODCK1/AP1/TC0/BNKSEL0 W2
MODCK2/AP2/TC1/BNKSEL1 W3
MODCK3/AP3/TC2/BNKSEL2 W4
XFC AB2
CLKIN1 AH4
PA0/RESTART1/DREQ3/FCC2_UTM_TXADDR2 AC29
PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3 AC25
PA2/CLK20/FCC2_UTM_TXADDR0/DACK3 AE28
PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2 AG29
PA4/REJECT2/FCC2_UTM_RXADDR1/DONE4 AG28
PA5/RESTART2/DREQ4/FCC2_UTM_RXADDR2 AG26
PA6/L1RSYNCA1 AE24
PA7/SMSYN2/L1TSYNCA1/L1GNTA1 AH25
PA8/SMRXD2/L1RXD0A1/L1RXDA1 AF23
PA9/SMTXD2/L1TXD0A1 AH23
PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5 AE22
PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4 AH22
PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3 AJ21
PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2 AH20
PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3 AG19
PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2 AF18
PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1 AF17
PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD AE16
PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD AJ16
PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1 AG15
PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2 AJ13
PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3 AE13
PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11 AF12
PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10 AG11
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1 AH9
PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0 AJ8
PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER AH7
PA27/FCC1_UT_RXSOC/FCC1_MII_RX_DV AF7
PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN AD5
PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER AF1
PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS AD3
PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL AB5
PB4/FCC2_UT8_RXD0/L1RSYNCA2 AD28
PB5/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2 AD26
PB6/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2 AD25
PB7/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2 AE26
PB8/FCC2_UT8_TXD3/TXD3/L1RSYNCD1 AH27
PB9/FCC2_UT8_TXD2/L1TXD2A2/L1TSYNCD1/L1GNTD1 AG24
PB10/FCC2_UT8_TXD1/L1RXDD1 AH24
PB11/FCC2_UT8_TXD0/L1TXDD1 AJ24
PB12/L1CLKOB1/L1RSYNCC1/TXD2 AG22
PB13/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2 AH21
PB14/RXD3/L1RXDC1 AG20
PB15/RXD2/L1TXDC1 AF19
PB16/L1CLKOA1/CLK18 AJ18
PB17/L1RQA1/CLK17 AJ17
PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2 AE14
PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2 AF13
PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1 AG12
PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/
L1TXD2A1 AH11
PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2 AH16
PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2 AE15
PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2 AJ9
PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1 AE9
PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2 AJ7
PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2 AH6
PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 AE3
PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/L1RSYNCB2/
FCC2_MII_TX_EN AE2
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/L1RXDB2 AC5
PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2 AC4
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 AB26
PC1/DREQ2/BRGO6/L1RQA2 AD29
PC2/FCC2_UT8_TXD3/DONE2 AE29
PC3//FCC2_UT8_TXD2/DACK2/CTS4 AE27
PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD AF27
PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS AF24
PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1 AJ26
PC7/FCC1_CTS/L1RQC1/FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/
FCC1_UTM_TXCLAV1 AJ25
PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3 AF22
PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2 AE21
PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3 AF20
PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2 AE19
PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1 AE18
PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1 AH18
PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0 AH17
PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0 AG16
PC16/CLK16/TIN4 AF15
PC17/CLK15/TIN3/BRGO8 AJ15
PC18/CLK14/TGATE2 AH14
PC19/CLK13/BRGO7 AG13
PC20/CLK12/TGATE1 AH12
PC21/CLK11/BRGO6 AJ11
PC22/CLK10/DONE1 AG10
PC23/CLK9/BRGO5/DACK1 AE10
PC24/FCC2_UT8_TXD3/CLK8/TOUT4 AF9
PC25/FCC2_UT8_TXD2/CLK7/BRGO4 AE8
PC26/CLK6/TOUT3/TMCLK AJ6
PC27/CLK5/BRGO3 AG2
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 AF3
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 AF2
PC30/FCC2_UT8_TXD3/CLK2/TOUT1 AE1
PC31/CLK1/BRGO1 AD1
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
PD4/BRGO8/L1TSYNCD1/L1GNTD1/SMRXD2 AC28
PD5/FCC1_UT16_TXD3/DONE1 AD27
PD6/FCC1_UT16_TXD4/DACK1 AF29
PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/FCC1_TXCLAV2 AF28
PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5 AG25
PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3 AH26
PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4 AJ27
PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1 AJ23
PD12/SI1_L1ST2/L1RXDB1 AG23
PD13/SI1_L1ST1/L1TXDB1 AJ22
PD14/FCC1_UT16_RXD0/L1CLKOC2/I2CSCL AE20
PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA AJ20
PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO AG18
PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI AG17
PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/S
PICLK AF16
PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/FCC1_UTM_TXCLAV3/S
PISEL/BRGO1 AH15
PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2 AJ14
PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2 AH13
PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2 AJ12
PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1 AE12
PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1 AF10
PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1 AG9
PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1 AH8
PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1 AG7
PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1 AE4
PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2 AG1
PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1 AD4
PD31/RXD1 AD2
VCCSYN AB3
VCCSYN1 B9
GNDSYN AB1
SPARE11AE11
SPARE41U5
SPARE52AF25
Table 14. Pinout List (Continued)
Pin Name Ball
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Pinout
Symbols used in Table 14 are described in Table 15.
SPARE61V4
THERMAL03AA1
THERMAL13AG4
I/O power AG21, AG14, AG8, AJ1, AJ2, AH1,
AH2, AG3, AF4, AE5, AC27, Y27,
T27, P27, K26, G27, AE25, AF26,
AG27, AH28, AH29, AJ28, AJ29,
C7, C14, C1 6, C 2 0, C23, E10, A 28,
A29, B28, B29, C27, D26, E25, H3,
M4, T3, AA4, A1, A2, B1, B2, C3,
D4, E5
Core Power U28, U29, K28, K29, A9, A19, B19,
M1, M2, Y1, Y2, AC1, AC2, AH19,
AJ19, AH10, AJ10, AJ5
Ground AA5, AF21, AF14 , AF8 , AE7, AF11,
AE17, AE23, AC26, AB25, Y26,
V25, T26, R25, P26, M25, K27, H25,
G26, D7, D10, D14, D16, D20, D23,
C9, E11, E13, E15, E19, E22, B3,
G5, H4, K5, M3, P5, T4, Y5, AA2,
AC3
1 Must be pulled down or left floating.
2 Must be pulled down or left floating. However, on HiP3 silicon that needs to be compatible with HiP4 silicon, this
pin must be pulled up or left floating.
3 For information on how to use this pin, refer to
MPC8260 PowerQUICC II Thermal Resistor Guide
available at
www.motorola.com/semiconductors.
Table 15. Symbol Legend
Symbol Meaning
OVERBAR Signals with overbars, such as TA, are active low.
UTM Indicates that a signal is part of the UTOPIA master interface.
UTS Indicates that a signal is part of the UTOPIA slave interface.
UT8 Indicate s that a signal is part of the 8- bit UTOPIA in terface.
UT16 Indicate s that a signal is part of the 16-bit UTOPIA interface.
MII Indicates that a signal is part of the media independent interface.
Table 14. Pinout List (Continued)
Pin Name Ball
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Pa ckage Desc ription
1.5 Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC8255.
1.5.1 Package Parameters
Package parameters are provided in Table 16. The package type is a 37.5 x 37.5 mm, 480-lead TBGA.
Table 16. Package Parameters
Parameter Value
Package Outline 37.5 x 37.5 mm
Interconnects 480 (29 x 29 ball array)
Pitch 1.27 mm
Nominal unmounted package height 1.55 mm
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Package Description
1.5.2 Mechanical Dimensions
Figure 14 provid es the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature
Dim Millimeters
Min Max
A1.451.65
A1 0.60 0.70
A2 0.85 0.95
A3 0.25 —
b0.650.85
D 37.50 BSC
D1 35.56 REF
e 1.27 BSC
E 37.50 BSC
E1 35.56 REF
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
maximum solder ball diameter,
parallel to primary data A.
4. Primary data A and the seating
plane are defined by the spherical
crowns of the solder balls.
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Ordering Information
1.6 Ordering Information
Figure 15 provi des an e xample of the Motoro la part numbering nomenclatur e for t he MPC8255. I n additi on
to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any
enhancement(s) in the part from the original production design. Each part number also contains a revision
code that refers to the die mask revision number and is specified in the part numbering scheme for
identification purposes only. For more information, contact your local Motorola sales office.
Figure 15. Motorola Part Number Key
Table 17. Document Revision History
Document Revision Substantive Changes
0 Initial version
0.1 • Note 2 for Table 4 (changes in italics): “...greater than
or equal to
266
MHz,
200
MHz CPM...”
• Updated Figure 15
• Table 14: footnotes added to pins at AE11, AF25, U5, and V4.
0.2 • Table 14: modified notes to pin AF25.
• Table 14: added note to pins AA1 and AG4 (Therm0 and Therm1).
0.3 • Table 2: Notes 2 and 3
• Addition of note on page 6:VDDH and VDD tracking
• Table 13: Note 3
0.4 • Corrected the 8 TDMs to 4 TDMs in the block diagram and the feature list.
Product Code
Device Number
Process Technology
Package
(ZU = 480 TBGA)
Processor Frequency
Die Revision Level
MPC 825X A
(None = 0.29 micron
C
Temperature Range
ZU XXX
(CPU/CPM/Bus)
X
A = 0.25 micron)
(Blank = 0 to 105 °C
C = -40 to 105 °C)
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MPC8255EC/D
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