XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013
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Table 10-2. Base Register Field Description (continued)
FIELD SIZE TYPE DESCRIPTION
LCtrl 1 Rd/Wr Link-active status control. This bit controls the indicated active status of the LLC section reported in the
self-ID packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of
the self-ID packet. The LLC bit in the node self-ID packet is set active only if both the LPS input is active
and the LCtrl bit is set. The LCtrl bit provides a software controllable means to indicate the LLC self-ID
active status in lieu of using the LPS input terminal. The LCtrl bit is set to 1 by hardware reset and is
unaffected by bus reset.
Note: The state of the PHY-section/LLC-section interface is controlled solely by the LPS input,
regardless of the state of the LCtrl bit. If the PHY-section/LLC-section interface is operational as
determined by the LPS input being active, received packets and status information continue to be
presented on the interface, and any requests indicated on the LREQ input are processed, even if the
LCtrl bit is cleared to 0.
C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0 on hardware
reset. After hardware reset, this bit can only be set via a software register write. This bit is unaffected by
a bus reset.
Jitter 3 Rd PHY-section repeater jitter. This field indicates the worst-case difference between the fastest and
slowest repeater data delay, expressed as (jitter + 1) 20 ns. For the XIO2213B, this field is 0.
Pwr_Class 3 Rd/Wr Node power class. This field indicates this node power consumption and source characteristics and is
replicated in the pwr field (bits 21-23) of the self-ID packet. This field is reset to the state specified by
the PC0-PC2 input terminals on a hardware reset, and is unaffected by a bus reset.
WDIE 1 Rd/Wr Watchdog interrupt enable. This bit, if set to 1, enables the port interrupt event (PIE) bit to be set when
resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits are set and
the PHY-section/LLC-section interface is nonoperational. This bit is reset to 0 by hardware reset and is
unaffected by bus reset.
ISBR 1 Rd/Wr Initiate short arbitrated bus reset. This bit, if set to 1, instructs the XIO2213B to initiate a short (1.3-ms)
arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended that
short bus reset is the only reset type initiated by software. IEC 61883-6 requires that a node initiate
short bus resets to minimize any disturbance to an audio stream.
Note: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long
bus reset being performed.
CTOI 1 Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-
ID start, and might indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset,
or by writing a 1 to this register bit. If the CTOI and WDIE bits are both set and the LLC is or becomes
inactive, the PHY section activates the LKON output to notify the LLC section to service the interrupt.
Note: If the network is configured in a loop, only those nodes that are part of the loop generate a
configuration time-out interrupt. Instead, all other nodes time out waiting for the tree-ID and/or self-ID
process to complete and then generate a state time-out interrupt and bus reset. This bit is only set when
the bus topology includes IEEE Std 1394a-2000 nodes; otherwise, IEEE Std 1394b-2002 loop healing
prevents loops from being formed in the topology.
CPSI 1 Rd/Wr Cable-power-status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low,
indicating that cable power might be too low for reliable operation. This bit is reset to 1 by hardware
reset. It can be cleared by writing a 1 to this register bit. If the CPSI and WDIE bits are both set and the
LLC section is or becomes inactive, the PHY section activates the LKON output to notify the LLC
section to service the interrupt.
STOI 1 Rd/Wr State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus
reset to occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the STOI
and WDIE bits are both set and the LLC is, or becomes, inactive, the PHY section activates the LKON
output to notify the LLC section to service the interrupt.
PEI 1 Rd/Wr Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for
any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt
enable (WDIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is
reset to 0 by hardware reset, or by writing a 1 to this register bit.
EAA 1 Rd/Wr Enable accelerated arbitration. This bit enables the XIO2213B to perform the various arbitration
acceleration enhancements defined in IEEE Std 1394a-2000 (ack-accelerated arbitration, asynchronous
fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and
is unaffected by bus reset. This bit has no effect when the device is operating in IEEE Std 1394b-2002
mode.
EMC 1 Rd/Wr Enable multispeed concatenated packets. This bit enables the XIO2213B to transmit concatenated
packets of differing speeds in accordance with the protocols defined in IEEE Std 1394a-2000. This bit is
reset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is
operating in IEEE Std 1394b-2002 mode.
182 Physical Layer (PHY) Section Copyright © 2008–2013, Texas Instruments Incorporated
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