CAT521 Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications FEATURES APPLICATIONS 8-bit DPP configured as a programmable Automated product calibration voltage source in DAC-like applications Remote control adjustment of equipment Buffered wiper output Offset, gain and zero adjustments in Non-volatile NVRAM memory wiper storage self-calibrating and adaptive control systems Output voltage range includes both supply rails Tamper-proof calibrations 1 LSB accuracy, high resolution DAC (with memory) substitute Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs DESCRIPTION The CAT521 is a 8-bit digitally-programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. settings and stored settings can be read back without disturbing the DPP's output. The CAT521 is controlled with a simple 3-wire, Microwirelike serial interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the CAT521 Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The programmable DPP has an output voltage range which includes both supply rails. The wiper is buffered by a rail to rail op amp. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be dithered to test new output values without effecting the stored The CAT521 is available in 0C to 70C commercial and -40C to 85C industrial operating temperature ranges. Both 14-pin plastic DIP and surface mount packages are available. FUNCTIONAL DIAGRAM RDY/BSY 3 PROG 7 PIN CONFIGURATION V DD V REFH 1 14 DIP Package (P) PROGRAM CONTROL VDD 1 CLK 2 SOIC Package (J) 14 VREFH VDD 1 13 NC CLK 2 DI CLK CS 2 SERIAL CONTROL WIPER CONTROL REGISTER AND NVRAM 4 + 28k SERIAL DATA OUTPUT REGISTER 12 RDY/BSY 3 12 VOUT CS 4 11 DI 5 10 DO 6 9 VREFL PROG 7 8 GND V OUT VREFH 13 NC CAT521 CAT521 5 14 RDY/BSY 3 12 VOUT NC CS 4 11 NC NC DI 5 10 NC DO 6 9 VREFL PROG 7 8 GND 6 DO CAT521 8 GND (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 VREFL 1 Doc. No. 2003, Rev. C CAT521 Operating Ambient Temperature Commercial (`C' or Blank suffix) ...... 0C to +70C Industrial (`I' suffix) ........................ -40C to +85C Junction Temperature ..................................... +150C Storage Temperature ........................ -65C to +150C Lead Soldering (10 sec max) .......................... +300C ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND ...................................... -0.5V to +7V Inputs CLK to GND ............................ -0.5V to VDD +0.5V CS to GND .............................. -0.5V to VDD +0.5V DI to GND ............................... -0.5V to VDD +0.5V RDY/BSY to GND ................... -0.5V to VDD +0.5V PROG to GND ........................ -0.5V to VDD +0.5V VREFH to GND ........................ -0.5V to VDD +0.5V VREFL to GND ......................... -0.5V to VDD +0.5V Outputs D0 to GND ............................... -0.5V to VDD +0.5V VOUT 1- 4 to GND ................... -0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V. POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating -- 400 600 A Programming, VDD = 5V -- 1600 2500 A VDD = 3V -- 1000 1600 A 2.7 -- 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD -- -- 10 A IIL Input Leakage Current VIN = 0V -- -- -10 A VIH High Level Input Voltage 2 -- VDD V VIL Low Level Input Voltage 0 -- 0.8 V Min Typ Max Units VDD -0.3 -- -- V LOGIC OUTPUTS Symbol Parameter Conditions VOH High Level Output Voltage IOH = -40A VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V -- -- 0.4 V IOL = 0.4 mA, VDD = +3V -- -- 0.4 V Doc. No. 2003, Rev. C 2 CAT521 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter RPOT Potentiometer Resistance Conditions Min Typ Max Units 28 RPOT to RPOT Match -- +0.5 Pot Resistance Tolerance k +1 % +15 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin OV VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC RISO Isolation Resistance VN Noise CH/CL Potentiometer Capacitances fc Frequency Response 300 ppm/C ppm/C nV/Hz 8/8 pF Passive Attenuator MHz AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz -- -- 3 6 10 10 s s Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL=100pF, see note 1 Analog tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2003, Rev. C CAT521 A. C. TIMING DIAGRAM to 1 2 3 4 5 t CLK H CLK t CSS t CLK L t CSH CS t CSMIN t DIS DI t DIH t DO0 t LZ DO t HZ t DO1 PROG t PS t PROG RDY/BSY t BUSY to Doc. No. 2003, Rev. C 1 2 3 4 4 5 CAT521 PIN DESCRIPTION Pin DPP addressing is as follows: Name Function 1 2 3 4 5 6 7 VDD CLK RDY/BSY CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL NC NC VOUT NC VREFH Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin EEPROM Programming Enable Input Power supply ground Minimum DAC output voltage No Connect No Connect DPP output No Connect Maximum DPP 1 output voltage DPP OUTPUT A0 A1 VOUT 1 0 DEVICE OPERATION CHIP SELECT The CAT521 is a single 8-bit configured digitally programmable potentiometer (DPPTM) whose output can be programmed to any one of 256 individual voltage steps. Once programmed, the output setting is retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPP returns to the setting stored in non-volatile memory. The DPP can be written to and read from without effecting the output voltage during the read or write cycle. The output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. Chip Select (CS) enables and disables the CAT521's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control register will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. DIGITAL INTERFACE CLOCK The CAT521 employs a 3 wire, Microwire-like serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. The CAT521 clock controls both data flow in and out of the device and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT521 internal power-on reset circuitry loads data from non-volatile memory to the DPP without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. 5 Doc. No. 2003, Rev. C CAT521 single serial data line and simplifies interfacing multiple 521s to a microprocessor. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control register. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. WRITING TO MEMORY Programming the CAT521's non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock's rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF VREF, the voltage applied between pins VREFH &VREFL, sets the DPP's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH &VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The CAT521 non-volatile memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed. BUSY READY/BUSY When saving data to non-volatile memory, the Ready/ Busy ouput (RDY/BSY) signals the start and duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT521 will ignore any data appearing at DI and no data will be output on DO. READING DATA Data is output serially by the CAT521, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 521s to share a Each time data is transferred into the DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP's output. This feature allows Ps to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory's setting is reloaded into the DPP wiper control register. Since this value is Figure 1. Writing to Memory Figure 2. Reading from Memory RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT to 1 2 3 4 5 6 7 8 9 10 11 12 N to N+1 N+2 1 2 3 4 5 6 7 8 9 10 11 12 CS CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI D6 D7 DO 1 A0 A1 CURRENT DPP DATA CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 PROG PROG RDY/BSY RDY/BSY DPP OUTPUT Doc. No. 2003, Rev. C CURRENT DPP VALUE NEW DPP VALUE NEW DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE DPP OUTPUT D0 D1 D2 D3 D4 D5 CURRENT DPP VALUE NON-VOLATILE 6 D6 D7 CAT521 Figure 3. Temporary Change in Output the same as that which had been there previously no change in the DPP's output is noticed. Had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle's conclusion. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA TEMPORARILY CHANGE OUTPUT 1 DI The CAT521 allows temporary changes in the DPP's output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA D0 DO D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT Figure 3 shows the control and data signals needed to effect a temporary output change. DPP settings may be changed as many times as required. The temporary setting remains in effect long as CS remains high. When CS returns low the DPP will return to the output value stored in non-volatile memory. CURRENT DPP VALUE NEW DPP VALUE CURRENT DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP wiper control register prior to programming. This is because the CAT521's internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. APPLICATION CIRCUITS DPP INPUT +5V Ri Vi RF VFS +15V VDD CONTROL & DATA VREFH GND VOUT - + CAT521 ANALOG OUTPUT V (R +R )-V R VOUT = DPP I F I F RI For R I = RF VOUT = 2VDPP -VI = 0.99 V VREF = 5V R I = RF MSB LSB VZERO = 0.01 V 1111 1111 255 (.98 V ---- REF) + .01 VREF= .990 VREF 255 VOUT = +4.90V 1000 0000 V = +0.02V OUT 0111 1111 128 (.98 V ---- REF) + .01 VREF= .502 VREF 255 127 ---- (.98 VREF) + .01 VREF= .498 VREF 255 V OP 07 -15V VREFL DPP OUTPUT CODE (V - V VDPP = ------ FS ZERO ) + VZERO 255 0000 0001 1 (.98 V ---- REF + .01 VREF = .014 V REF 255 0000 0000 0 (.98 V ---- REF) + .01 VREF = .010 VREF 255 V = -0.02V OUT OUT = -4.86V V = -4.90V OUT Bipolar DPP Output +5V RI RF +15V VDD CONTROL & DATA VREFH - + CAT521 GND VOUT OP 07 -15V VREFL RF VOUT = (1 + ---) V DPP RI Amplified DPP Output 7 Doc. No. 2003, Rev. C CAT521 APPLICATION CIRCUITS (Cont.) 28 - 32V V+ I > 2 mA 15K 10 F VDD CONTROL & DATA VREFH OPT 515 CAT521 GND VREF = 5.000V 1N5231B VDD LT 1029 VREFH 5.1V 10K CONTROL & DATA VREFL + CAT521 GND VREFL - MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 2003, Rev. C Digitally Controlled Voltage Reference 8 10 F 35V 0 - 25V @ 1A CAT521 ORDERING INFORMATION Prefix Device # Suffix CAT 521 J Optional Company ID Product Number Package P: PDIP J: SOIC I 2000/Reel -TE13 Tape & Reel TE13: Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) Notes: (1) The device used in the above example is a CAT521JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) 9 Doc. No. 2003, Rev. C Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: Type: 2003 C 3/22/02 Final CAT522 Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications FEATURES APPLICATIONS Two 8-bit DPPs configured as programmable Automated product calibration. voltage sources in DAC-like applications Remote control adjustment of equipment Independent reference inputs Offset, gain and zero adjustments in self- Non-volatile NVRAM memory wiper storage calibrating and adaptive control systems. Output voltage range includes both supply rails Tamper-proof calibrations. 2 independently addressable buffered DAC (with memory) substitute. output wipers 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs DESCRIPTION dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP's output. The CAT522 is a dual, 8-bit digitally-programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. The CAT522 is controlled with a simple 3-wire, microwirelike serial interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the CAT522 Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The CAT522 offers two independently programmable DPPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail opamps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be The CAT522 is available in the 0C to 70C commercial and -40C to 85C industrial operating temperature ranges. Both 14-pin plastic DIP and surface mount packages are available. PIN CONFIGURATION FUNCTIONAL DIAGRAM RDY/BSY 3 PROG DI CLK CS 7 VREFH1 VREFH2 V DD 14 1 DIP Package (P) 13 PROGRAM CONTROL VDD 1 14 VREFH1 VDD 1 14 VREFH1 CLK 2 13 VREFH2 CLK 2 13 VREFH2 RDY/BSY 3 12 VOUT1 RDY/BSY 3 12 VOUT1 CS 4 11 VOUT2 CS 4 11 VOUT2 DI 5 10 VREFL2 DI 5 10 VREFL2 DO 6 9 VREFL1 DO 6 9 VREFL1 PROG 7 8 GND PROG 7 8 GND 5 2 SERIAL CONTROL + WIPER CONTROL REGISTERS AND NVRAM 11 28K 4 + 28k SERIAL DATA OUTPUT REGISTER 12 V OUT2 SOIC Package (J) VOU T1 6 DO CAT522 CAT522 CAT522 8 GND (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 10 VREFL1 VREFL2 1 Doc. No. 2004, Rev. B CAT522 ABSOLUTE MAXIMUM RATINGS Operating Ambient Temperature Commercial (`C' or Blank suffix) ...... 0C to +70C Industrial (`I' suffix) ........................ -40C to +85C Junction Temperature ..................................... +150C Storage Temperature ........................ -65C to +150C Lead Soldering (10 sec max) .......................... +300C Supply Voltage* VDD to GND ...................................... -0.5V to +7V Inputs CLK to GND ............................ -0.5V to VDD +0.5V CS to GND .............................. -0.5V to VDD +0.5V DI to GND ............................... -0.5V to VDD +0.5V RDY/BSY to GND ................... -0.5V to VDD +0.5V PROG to GND ........................ -0.5V to VDD +0.5V VREFH to GND ........................ -0.5V to VDD +0.5V VREFL to GND ......................... -0.5V to VDD +0.5V Outputs D0 to GND ............................... -0.5V to VDD +0.5V VOUT 1- 4 to GND ................... -0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V. POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating -- 400 600 A Programming, VDD = 5V -- 1600 2500 A VDD = 3V -- 1000 1600 A 2.7 -- 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD -- -- 10 A IIL Input Leakage Current VIN = 0V -- -- -10 A VIH High Level Input Voltage 2 -- VDD V VIL Low Level Input Voltage 0 -- 0.8 V Min Typ Max Units VDD -0.3 -- -- V LOGIC OUTPUTS Symbol Parameter Conditions VOH High Level Output Voltage IOH = -40A VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V -- -- 0.4 V IOL = 0.4 mA, VDD = +3V -- -- 0.4 V Doc. No. 2004, Rev. B 2 CAT522 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter RPOT Potentiometer Resistance Conditions Min Typ Max Units 28 RPOT to RPOT Match -- +0.5 Pot Resistance Tolerance k +1 % +15 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin OV VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC RISO Isolation Resistance VN Noise CH/CL Potentiometer Capacitances fc Frequency Response 300 ppm/C ppm/C nV/Hz 8/8 pF Passive Attenuator MHz AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz -- -- 3 6 10 10 s s Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL=100pF, see note 1 Analog tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2004, Rev. B CAT522 A. C. TIMING DIAGRAM to 1 2 3 4 5 t CLK H CLK t CSS t CLK L t CSH CS t CSMIN t DIS DI t DIH t DO0 t LZ DO t HZ t DO1 PROG t PS t PROG RDY/BSY t BUSY to Doc. No. 2004, Rev. B 1 2 3 4 4 5 CAT522 PIN DESCRIPTION Pin DPP addressing is as follows: Name Function 1 2 3 4 5 6 7 VDD CLK RDY/BSY CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL1 VREFL2 VOUT2 VOUT1 VREFH2 VREFH1 Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin EEPROM Programming Enable Input Power supply ground Minimum DPP 1 output voltage Minimum DPP 2 output voltage DPP 2 output DPP 1 output Maximum DPP 2 output voltage Maximum DPP 1 output voltage DPP OUTPUT A0 A1 VOUT1 0 1 VOUT2 1 1 DEVICE OPERATION CHIP SELECT The CAT522 is a dual 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. Chip Select (CS) enables and disables the CAT522's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. DIGITAL INTERFACE CLOCK The CAT522 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. The CAT522's clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. No clock is necessary upon system power-up. The CAT522's internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. 5 Doc. No. 2004, Rev. B CAT522 single serial data line and simplifies interfacing multiple 522s to a microprocessor. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. WRITING TO MEMORY Programming the CAT522's non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock's rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF VREF, the voltage applied between pins VREFH &VREFL, sets the configured DPP's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH &VREFL are connected across the power supply rails. When using less than the full supply voltage be mindful of the limits placed on VREFL and VREFL as specified in the References section of DC Electrical Characteristics. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile cells. The CAT522's non-volatile memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed. BUSY READY/BUSY When saving data to non-volatile memory, the Ready/ Busy ouput (RDY/BSY) signals the start and duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT522 will ignore any data appearing at DI and no data will be output on DO. READING DATA Data is output serially by the CAT522, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 522s to share a Each time data is transferred into a DPP control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP's output. This feature allows Ps to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. Since this value is the Figure 1. Writing to Memory Figure 2. Reading from Memory RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 to 1 2 3 4 5 6 7 8 9 10 11 12 CS CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI D6 D7 DO 1 A0 A1 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 CURRENT DPP DATA PROG PROG RDY/BSY RDY/BSY DPP OUTPUT Doc. No. 2004, Rev. B CURRENT DPP VALUE NEW DPP VALUE NEW DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE DPP OUTPUT D0 D1 D2 D3 D4 D5 CURRENT DPP VALUE NON-VOLATILE 6 D6 D7 CAT522 Figure 3. Temporary Change in Output same as that which had been there previously no change in the DPP's output is noticed. Had the value held in the control register been different from that stored in nonvolatile memory then a change would occur at the read cycle's conclusion. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA TEMPORARILY CHANGE OUTPUT 1 DI The CAT522 allows temporary changes in DPP's output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA D0 DO D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT Figure 3 shows the control and data signals needed to effect a temporary output change. DPP wiper settings may be changed as many times as required and can be made to any of the two DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all two DPPs will return to the output values stored in non-volatile memory. CURRENT DPP VALUE NEW DPP VALUE CURRENT DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP wiper control register prior to programming. This is because the CAT522's internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. APPLICATION CIRCUITS DPP INPUT DPP OUTPUT ANALOG OUTPUT +5V Vi Ri CODE (V - V VDPP = ------ FS ZERO ) + V ZERO 255 RF +15V VDD CONTROL & DATA VREFH + CAT522 GND VREFL VOUT - VFS = 0.99 VREF VZERO = 0.01 V REF LSB 1111 1111 255 (.98 V ---- REF) + .01 VREF = .990 V REF 255 V OUT= +4.90V 1000 0000 128 (.98 V ---- ) + .01 V = .502 V REF REF REF 255 127 ---- (.98 V ) + .01 V = .498 V 255 REF REF REF 1 (.98 V ---- ) + .01 V = .014 V 255 REF REF REF V 0 (.98 V ---- ) + .01 V = .010 V REF REF REF 255 V OP 07 -15V VREF = 5V R I = RF MSB 0111 1111 VOUT = V DPP ( R i+ RF) -Vi R F Ri 0000 0001 For R i = RF VOUT = 2VDPP -Vi 0000 0000 V V OUT OUT OUT OUT = +0.02V = -0.02V = -4.86V = -4.90V Bipolar DPP Output +5V RI RF +15V VDD CONTROL & DATA VREFH - + CAT522 GND VOUT OP 07 -15V VREFL RF VOUT = (1 + ---) V DPP RI Amplified DPP Output 7 Doc. No. 2004, Rev. B CAT522 APPLICATION CIRCUITS (Cont.) VREF RC = ---------- 256 * 1 A +5V VDD VREF +5V VDD Fine adjust gives 1 LSB change in V OFFSET VREF when V OFFSET = ------ 2 VREFH +VREF VREFH + (+VREF ) - (VOFFSET ) RC = ---------------------- 1 A 127RC FINE ADJUST DPP CAT522 CAT522 RC COARSE ADJUST DPP V OFFSET (-VREF ) + (VOFFSET+ ) Ro = ---------------------- 1 A RC COARSE ADJUST DPP +V + GND VREFL +V Ro - GND 127RC FINE ADJUST DPP VOFFSET -VREF VREFL + - -V Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems 28 - 32V V+ 15K 10 F I > 2 mA 1N5231B VDD CONTROL & DATA VREF = 5.000V VREFH CAT522 VDD 5.1V 10K LT 1029 CONTROL & DATA + CAT522 GND GND VREFH VREFL - MPT3055EL LM 324 VREFL OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 2004, Rev. B 10 F 35V Digitally Controlled Voltage Reference 8 0 - 25V @ 1A CAT522 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREFH 4.7 A LM385-2.5 ISINK = 2 - 255 mA +15V + DPP +5V CONTROL & DATA 10K CAT522 1 mA steps 2N7000 - 39 1W 10K 39 1W + DPP 5 A steps 2N7000 - VREFL GND 5M 5M 3.9K 10K 10K - TIP 30 + -15V Current Sink with 4 Decades of Resolution +15V 51K + TIP 29 - 10K 10K +5V VDD VREFH 5M 5M 39 1W DPP 39 1W CONTROL & DATA - CAT522 BS170P + 5M 5M 1 mA steps 3.9K DPP GND - VREFL BS170P 5 A steps + LM385-2.5 -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution 9 Doc. No. 2004, Rev. B CAT522 ORDERING INFORMATION Prefix Device # Suffix CAT 522 J Optional Company ID Product Number Package P: PDIP J: SOIC -TE13 I Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0C to 70C) I = Industrial (-40C to 85C) Notes: (1) The device used in the above example is a CAT522JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Doc. No. 2004, Rev. B Publication #: Revison: Issue date: Type: 10 2004 B 03/21/02 Final CAT523 Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications FEATURES APPLICATIONS Two 8-bit DPPs configured as programmable Automated product calibration. voltage sources in DAC-like applications Remote control adjustment of equipment Common reference inputs Offset, gain and zero adjustments in self- Non-volatile NVRAM memory wiper storage calibrating and adaptive control systems. Output voltage range includes both supply rails Tamper-proof calibrations. 2 independently addressable buffered DAC (with memory) substitute output wipers 1 LSB accuracy, high resolution Serial microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs DESCRIPTION values without effecting the stored settings and stored settings can be read back without disturbing the DPP's output. The CAT523 is a dual, 8-bit digitally-programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. Control of the CAT523 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin allows several CAT523's to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the CAT523's TriStated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM memory Erase/ Write cycle. The two independently programmable DPPs have a common output voltage range which includes both supply rails. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output The CAT523 is available in the 0C to 70C Commercial and -40C to + 85C Industrial operating temperature ranges and offered in 14-pin plastic DIP and SOIC mount packages. PIN CONFIGURATION FUNCTIONAL DIAGRAM RDY/BSY 3 PROG 7 V DD DIP Package (P) VREFH PROGRAM CONTROL VDD 1 14 CLK 2 13 RDY/BSY 3 CS DI CLK CS 5 2 SERIAL CONTROL SOIC Package (J) 14 1 + WIPER CONTROL REGISTER AND NVRAM 13 28K DI DO V OUT1 PROG 4 + 12 28K SERIAL DATA OUTPUT REGISTER 12 CAT 4 11 523 5 10 6 9 7 8 VREFH VOUT1 VDD CLK 1 14 2 13 VOUT2 NC RDY/BSY 3 NC VREFL GND CS DI DO PROG VREFH VOUT1 12 4 CAT 11 523 5 10 6 9 VOUT2 7 GND 8 NC NC VREFL V OUT2 6 DO CAT523 8 GND (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 V REFL 1 Doc. No. 2005, Rev. B CAT523 ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND Inputs CLK to GND CS to GND DI to GND RDY/BSY to GND PROG to GND VREFH to GND VREFL to GND Outputs D0 to GND VOUT 1- 4 to GND Operating Ambient Temperature Commercial (`C' or Blank suffix) 0C to +70C Industrial (`I' suffix) -40C to +85C Junction Temperature +150C Storage Temperature -65C to +150C Lead Soldering (10 sec max) +300C -0.5V to +7V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. -0.5V to VDD +0.5V -0.5V to VDD +0.5V RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V. POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating -- 400 600 A Programming, VDD = 5V -- 1600 2500 A VDD = 3V -- 1000 1600 A 2.7 -- 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD -- -- 10 A IIL Input Leakage Current VIN = 0V -- -- -10 A VIH High Level Input Voltage 2 -- VDD V VIL Low Level Input Voltage 0 -- 0.8 V Min Typ Max Units VDD -0.3 -- -- V LOGIC OUTPUTS Symbol Parameter Conditions VOH High Level Output Voltage IOH = -40A VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V -- -- 0.4 V IOL = 0.4 mA, VDD = +3V -- -- 0.4 V Doc. No. 2005, Rev. B 2 CAT523 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter RPOT Potentiometer Resistance Conditions Min Typ Max Units 28 RPOT to RPOT Match -- +0.5 Pot Resistance Tolerance k +1 % +15 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin OV VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC RISO Isolation Resistance VN Noise CH/CL Potentiometer Capacitances fc Frequency Response 300 ppm/C ppm/C nV/Hz 8/8 pF Passive Attenuator MHz AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz -- -- 3 6 10 10 s s Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL=100pF, see note 1 Analog tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2005, Rev. B CAT523 A. C. TIMING DIAGRAM to 1 2 3 4 5 t CLK H CLK t CSS t CLK L t CSH CS t CSMIN t DIS DI t DIH t DO0 t LZ DO t HZ t DO1 PROG t PS t PROG RDY/BSY t to Doc. No. 2005, Rev. B 1 2 3 4 BUSY 4 5 CAT523 PIN DESCRIPTION Pin Name 1 2 3 4 5 6 7 VDD CLK RDY/BSY CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL NC NC VOUT2 VOUT1 VREFH DPP addressing is as follows: Function Power supply positive. Clock input pin.Clock input pin. Ready/Busy Output Chip Select Serial data input pin. Serial data output pin. EEPROM Programming Enable Input Power supply ground. Minimum DPP output voltage. No Connect. No Connect. DPP output channel 2. DPP output channel 1. Maximum DPP output voltage. DEVICE OPERATION DPP OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. The CAT523 is a dual 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT523's clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. DIGITAL INTERFACE The CAT523 employs a 3 wire, Microwire-like, serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. No clock is necessary upon system power-up. The CAT523's internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. CHIP SELECT Chip Select (CS) enables and disables the CAT523's 5 Doc. No. 2005, Rev. B CAT523 VREF followed by a two bit DPP address and eight data bits are clocked into the DPP control register via the DI pin. Data enters on the clock's rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF, the voltage applied between pins VREFH andVREFL, sets the DPP's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH andVREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. Programming is achieved by bringing PROG high for a minimum of 3 ms. PROG must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DAC control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the non-volatile memory cells. The CAT523's non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 100 years without being refreshed. /BUSY READY/BUSY When saving data to non-volatile memory, the Ready/ Busy output (RDY/BSY) signals the start and duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT523 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP's output. This feature allows Ps to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. DATA OUTPUT Data is output serially by the CAT523, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 523s to share a single serial data line and simplifies interfacing multiple 523s to a microprocessor. WRITING TO MEMORY Programming the CAT523's non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit Figure 1. Writing to Memory Figure 2. Reading from Memory to 1 2 3 4 5 6 7 8 9 10 11 12 CS NEW DPP DATA DI 1 A0 A1 CURRENT DPP DATA CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT Doc. No. 2005, Rev. B DPP OUTPUT DPP VALUE DPP VALUE CURRENT DPP VALUE NON-VOLATILE DPP VALUE 6 D6 D7 CAT523 Since this value is the same as that which had been there previously no change in the DPP's output is noticed. Had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle's conclusion. this feature, the new value must be reloaded into the DPP wiper control register prior to programming. This is because the CAT523's internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. TEMPORARILY CHANGE OUTPUT Figure 3. Temporary Change in Output The CAT523 allows temporary changes in DPP's output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA 1 DI Figure 3 shows the control and data signals needed to effect a temporary output change. DPP wiper settings may be changed as many times as required and can be made to any of the two DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all two DPPs will return to the output values stored in non-volatile memory. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA D0 DO D1 D2 D3 D4 D5 PROG DPP OUTPUT CURRENT DPP VALUE NON-VOLATILE NEW DPP VALUE VOLATILE CURRENT DPP VALUE NON-VOLATILE When it is desired to save a new setting acquired using APPLICATION CIRCUITS DPP INPUT DPP OUTPUT ANALOG OUTPUT CODE (V - V VDPP = ------ FS ZERO ) + V ZERO 255 MSB LSB 1111 1111 1000 0000 0111 1111 0000 0001 0000 0000 +5V VFS = 0.99 VREF VZERO = 0.01 V REF 255 (.98 V ---- REF) + .01 VREF = .990 VREF 255 CONTROL & DATA V 0 (.98 V ---- ) + .01 V = .010 V REF REF REF 255 V V V OUT OUT OUT OUT RF +15V VDD V OUT= +4.90V 128 (.98 V ---- ) + .01 V = .502 V REF REF REF 255 127 ---- (.98 V ) + .01 V = .498 V 255 REF REF REF 1 ---- (.98 V ) + .01 V = .014 V 255 REF REF REF Ri Vi VREF = 5V R I = RF VREFH + CAT523 = +0.02V GND VOUT - VREFL = -0.02V OP 07 -15V VOUT = V DPP ( R i+ RF) -Vi R F Ri = -4.86V For R i = RF VOUT = 2VDPP -Vi = -4.90V Bipolar DPP Output +5V Ri RF +15V VDD CONTROL & DATA VREFH - + CAT523 GND VOUT OP 07 -15V VREFL RF VOUT = (1 + ---) V DPP RI Amplified DPP Output 7 Doc. No. 2005, Rev. B CAT523 APPLICATION CIRCUITS (Cont.) +5V VREF RC = ---------- 256 * 1 A +5V VDD VREF FINE ADJUST DPP VDD Fine adjust gives 1 LSB change in V OFFSET VREF when V OFFSET = ------ 2 VREFH +VREF VREFH 127RC FINE ADJUST DPP (+VREF ) - (VOFFSET+ ) RC = ---------------------- 1 A 127RC (-VREF ) + (VOFFSET+ ) Ro = ---------------------- 1 A RC COARSE ADJUST DPP +V RC COARSE ADJUST DPP V OFFSET GND VREFL Ro VOFFSET -VREF - GND +V + + - VREFL -V Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 F 1N5231B VDD VREF = 5.000V VREFH VDD VREFH 5.1V 10K CONTROL & DATA CAT523 GND CONTROL & DATA LT 1029 VREFL CAT523 + GND - VREFL MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 2005, Rev. B Digitally Controlled Voltage Reference 8 10 F 35V 0 - 25V @ 1A CAT523 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREFH 4.7 A LM385-2.5 ISINK = 2 - 255 mA +15V + DPP +5V CONTROL & DATA 10K CAT523 1 mA steps 2N7000 - 10K 391W 39 1W + DPP 5 A steps 2N7000 - VREFL GND 5 meg 5 meg 3.9K 10K 10K - TIP 30 + -15V Current Sink with 4 Decades of Resolution +15V 51K + TIP 29 - 10K 10K +5V VDD VREFH 5 meg 5 meg 39 1W DPP 39 1W CONTROL & DATA - CAT523 BS170P + 5 meg 5 meg 1 mA steps 3.9K DPP GND - VREFL BS170P 5 A steps + LM385-2.5 -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution 9 Doc. No. 2005, Rev. B CAT523 ORDERING INFORMATION Prefix Device # Suffix CAT 523 J Optional Company ID Product Number Package P: PDIP J: SOIC I -TE13 Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) Notes: (1) The device used in the above example is a CAT523JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Doc. No. 2005, Rev. B Publication #: Revison: Issue date: Type: 10 2005 B 3/22/02 Final CAT524 Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications FEATURES APPLICATIONS Four 8-bit DPPs configured as programmable Automated product calibration voltage sources in DAC-like applications Remote control adjustment of equipment Common reference inputs Offset, gain and zero adjustments in Buffered wiper outputs self-calibrating and adaptive control systems Non-volatile NVRAM memory wiper storage Tamper-proof calibrations Output voltage range includes both supply rails DAC (with memory) substitute 4 independently addressable buffered output wipers 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs DESCRIPTION effecting the stored settings, and stored settings can be read back without disturbing the DPP's output. The CAT524 is a quad, 8-bit digitally-programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. The CAT524 is controlled with a simple 3-wire serial, Microwire-like interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the Tri-Stated CAT524 Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The four independently programmable DPPs have an output range which includes both supply rails. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without The CAT524 is available in the 0C to 70C commercial and -40C to 85C industrial operating temperature ranges. Both 14-pin plastic DIP and SOIC packages are offered. FUNCTIONAL DIAGRAM RDY/BSY 3 V DD 1 PIN CONFIGURATION V REFH 14 DIP Package (P) 28k(4) PROG 7 PROGRAM CONTROL + 13 - DI CLK CS 5 2 + SERIAL CONTROL 12 - WIPER CONTROL REGISTERS AND NVRAM V OUT1 V OUT2 VDD 1 14 13 VDD CLK 14 2 VREFH VOUT1 1 CLK 2 13 VREFH VOUT1 RDY/BSY 3 12 CAT 4 11 524 5 10 6 9 VOUT2 VOUT3 VOUT4 VREFL RDY/BSY 3 12 4 CAT 11 524 5 10 6 9 VOUT2 VOUT3 VOUT4 VREFL 7 GND CS + 11 - 4 DI DO V OUT3 PROG + 10 - SERIAL DATA OUTPUT REGISTER SOIC Package (J) 7 8 GND CS DI DO PROG 8 VOUT4 6 DO CAT524 8 GND 9 V REFL (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 2006, Rev. B CAT524 Operating Ambient Temperature Commercial (`C' or Blank suffix) 0C to +70C Industrial (`I' suffix) -40C to +85C Junction Temperature +150C Storage Temperature -65C to +150C Lead Soldering (10 sec max) +300C ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND Inputs CLK to GND CS to GND DI to GND RDY/BSY to GND PROG to GND VREFH to GND VREFL to GND Outputs D0 to GND VOUT 1- 4 to GND -0.5V to +7V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. -0.5V to VDD +0.5V -0.5V to VDD +0.5V RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V. POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating -- 400 600 A Programming, VDD = 5V -- 1600 2500 A VDD = 3V -- 1000 1600 A 2.7 -- 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD -- -- 10 A IIL Input Leakage Current VIN = 0V -- -- -10 A VIH High Level Input Voltage 2 -- VDD V VIL Low Level Input Voltage 0 -- 0.8 V Min Typ Max Units VDD -0.3 -- -- V LOGIC OUTPUTS Symbol Parameter Conditions VOH High Level Output Voltage IOH = -40A VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V -- -- 0.4 V IOL = 0.4 mA, VDD = +3V -- -- 0.4 V Doc. No. 2006, Rev. B 2 CAT524 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter RPOT Potentiometer Resistance Conditions Min Typ Max Units 28 RPOT to RPOT Match -- +0.5 Pot Resistance Tolerance k +1 % +15 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin OV VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC RISO Isolation Resistance VN Noise CH/CL Potentiometer Capacitances fc Frequency Response 300 ppm/C ppm/C nV/Hz 8/8 pF Passive Attenuator MHz AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz -- -- 3 6 10 10 s s Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL=100pF, see note 1 Analog tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2006, Rev. B Doc. No. 2006, Rev. B 4 RDY/BSY PROG DO DI CS CLK to to t LZ t DIS t CSS 1 1 t DO1 t DIH 2 2 t CLK H 3 t PROG t PS t CLK L 3 t DO0 4 t BUSY t CSH 4 t HZ t CSMIN 5 5 FROM TIMING TO Rising CS edge to D0 becoming high low impedance (active output) t LZ Rising PROG edge to next rising CLK edge Falling CS edge to D0 becoming high impedance (Tri-State) t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge t PROG Rising PROG edge to falling PROG edge t PS t HZ Rising CLK edge to D0 = high Rising CLK edge to D0 = low t DO0 t DO1 Rising CLK edge to end of data valid t DIH Max Min Min (Max) Max (Max) Max Min Min Data valid to first rising CLK edge after CS = high t DIS Min Min Rising CS edge to next rising CLK edge t CSMIN Falling CS edge to rising CS edge t CSS Min t CSH Falling CLK edge for last data bit (DI) to falling CS edge Min Min MIN/MAX t CLK L Falling CLK edge to CLK rising edge t CLK H Rising CLK edge to falling CLK edge PARAM NAME CAT524 A. C. TIMING DIAGRAM CAT524 PIN DESCRIPTION Pin Name 1 2 3 4 5 6 7 VDD CLK RDY/BSY CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL VOUT4 VOUT3 VOUT2 VOUT1 VREFH DPP addressing is as follows: Function Power supply positive. Clock input pin.Clock input pin. Ready/Busy Output Chip Select Serial data input pin. Serial data output pin. Non-volatile Memory Programming Enable Input Power supply ground. Minimum DPP output voltage. DPP output channel 4. DPP output channel 3. DPP output channel 2. DPP output channel 1. Maximum DPP output voltage. DEVICE OPERATION DPP OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. The CAT524 is a quad 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT524's clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. DIGITAL INTERFACE The CAT524 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. No clock is necessary upon system power-up. The CAT524's internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. CHIP SELECT Chip Select (CS) enables and disables the CAT524's 5 Doc. No. 2006, Rev. B CAT524 VREF (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP control register via the DI pin. Data enters on the clock's rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF, the voltage applied between pins VREFH andVREFL, sets the configured DPP's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH andVREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. Programming is achieved by bringing PROG high for a minimum of 3 ms. PROG must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the non-volatile cells. The CAT524 non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. /BUSY READY/BUSY When saving data to non-volatile memory, the Ready/ Busy ouput (RDY/BSY) signals the start and duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT524 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP's output. This feature allows Ps to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. DATA OUTPUT Data is output serially by the CAT524, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 524s to share a single serial data line and simplifies interfacing multiple 524s to a microprocessor. WRITING TO MEMORY Programming the CAT524's non-volatile memory is accomplished through the control signals: Chip Select Figure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 Figure 2. Reading from Memory 10 11 12 N N+1 N+2 to 1 2 3 4 5 6 7 8 9 10 11 12 CS CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI 1 A0 A1 CURRENT DPP DATA CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7 DO PROG DPP OUTPUT D0 D1 D2 D3 D4 D5 PROG CURRENT DPP VALUE NON-VOLATILE Doc. No. 2006, Rev. B NEW DPP VALUE VOLATILE NEW DPP VALUE NON-VOLATILE DPP OUTPUT CURRENT DPP VALUE NON-VOLATILE 6 D6 D7 CAT524 Since this value is the same as that which had been there previously no change in the DPP's output is noticed. Had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle's conclusion. this feature, the new value must be reloaded into the DPP control register prior to programming. This is because the CAT524's internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. TEMPORARILY CHANGE OUTPUT Figure 3. Temporary Change in Output The CAT524 allows temporary changes in DPP's output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA 1 DI Figure 3 shows the control and data signals needed to effect a temporary output change. DPP wiper settings may be changed as many times as required and can be made to any of the four DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPPs will return to the output values stored in non-volatile memory. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 CURRENT DPP DATA D0 DO D1 D2 D3 D4 D5 D6 D7 PROG CURRENT DPP VALUE NON-VOLATILE DPP OUTPUT NEW DPP VALUE VOLATILE CURRENT DPP VALUE NON-VOLATILE When it is desired to save a new setting acquired using APPLICATION CIRCUITS DPP INPUT DPP OUTPUT ANALOG OUTPUT CODE (V - V VDPP = ------ FS ZERO ) + V ZERO 255 MSB LSB 1111 1111 1000 0000 0111 1111 0000 0001 0000 0000 +5V Vi VFS = 0.99 VREF VZERO = 0.01 V REF VREF = 5V R I = RF 255 (.98 V ---- REF) + .01 VREF = .990 VREF 255 V 0 (.98 V ---- ) + .01 V = .010 V REF REF REF 255 V V V OUT OUT OUT OUT RF +15V VDD V OUT= +4.90V 128 (.98 V ---- ) + .01 V = .502 V REF REF REF 255 127 ---- (.98 V ) + .01 V = .498 V 255 REF REF REF 1 ---- (.98 V ) + .01 V = .014 V 255 REF REF REF Ri CONTROL & DATA VREFH CAT524 = +0.02V GND VOUT - + OP 07 -15V VREFL VDPP (Ri+ RF ) -Vi R F Ri = -0.02V VOUT = = -4.86V For R i = RF VOUT = 2VDPP -Vi = -4.90V Bipolar DPP Output +5V Ri RF +15V VDD CONTROL & DATA VREFH - CAT524 OPT 504 GND + VOUT OP 07 -15V VREFL RF VOUT = (1 + ---) V DPP RI Amplified DPP Output 7 Doc. No. 2006, Rev. B CAT524 APPLICATION CIRCUITS (Cont.) +5V VREF RC = ---------- 256 * 1 A +5V VDD VREF VREFH FINE ADJUST DPP VDD Fine adjust gives 1 LSB change in V OFFSET VREF when V OFFSET = ------ 2 +VREF VREFH 127RC FINE ADJUST DPP + (+VREF ) - (VOFFSET ) RC = ---------------------- 1 A 127RC (-VREF ) + (VOFFSET+ ) Ro = ---------------------- 1 A RC COARSE ADJUST DPP +V COARSE ADJUST DPP RC V OFFSET GND + +V Ro VOFFSET -VREF - GND VREFL + - VREFL -V Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 F VDD CONTROL & DATA 1N5231B VREF = 5.000V VREFH VDD VREFH 5.1V 10K CAT524 OPT 505 GND LT 1029 CONTROL & DATA CAT514 CAT524 GND VREFL VREFL + - MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 2006, Rev. B Digitally Controlled Voltage Reference 8 10 F 35V 0 - 25V @ 1A CAT524 APPLICATION CIRCUITS (Cont.) +5V VREF VIN 1.0 F LM 339 + 10K - VDD +5V VREFH WINDOW 1 + CAT524 V REF - WINDOW 1 DPP 1 + - 10K +5V WINDOW 2 VOUT1 + CS WINDOW 2 - + DPP 2 DI VOUT2 10K - +5V WINDOW 3 WINDOW 3 + DO - DPP 3 PROG VOUT3 + - WINDOW 4 10K +5V WINDOW 4 VOUT4 + CLK - DPP 4 WINDOW 5 + GND 10K - +5V WINDOW 5 + VREFL GND WINDOW STRUCTURE - Staircase Window Comparator +5V VIN VREF 1.0 F + LM 339 10K - VDD VREFH CAT524 +5V WINDOW 1 + VREF - WINDOW 1 DPP 1 + - 10K +5V WINDOW 2 VOUT1 + CS DI WINDOW 2 - VOUT2 + DPP 2 10K - +5V WINDOW 3 WINDOW 3 + DO PROG - DPP 3 VOUT3 + - WINDOW 4 10K +5V WINDOW 4 VOUT4 + CLK - DPP 4 WINDOW 5 + GND 10K - +5V WINDOW 5 + GND VREFL WINDOW STRUCTURE - Overlapping Window Comparator 9 Doc. No. 2006, Rev. B CAT524 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREFH 4.7 uF LM385-2.5 ISINK = 2 - 255 mA +15V + DPP +5V CONTROL & DATA 10K CAT524 1 mA steps 2N7000 - 39 1W 10K 39 1W + DPP 5 A steps 2N7000 - VREFL GND 5M 5M 3.9K 10K 10K - TIP 30 + Current Sink with 4 Decades of Resolution -15V +15V 51K + TIP 29 - 10K 10K +5V VDD VREFH 5M 5M 39 1W DPP 39 1W CONTROL & DATA - CAT524 BS170P + 5M 5M 1 mA steps 3.9K DPP GND - VREFL BS170P 5 A steps + LM385-2.5 -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution Doc. No. 2006, Rev. B 10 CAT524 APPLICATION CIRCUITS (Cont.) +12V 10K 1N914 1.0 F +12V .005 F 74C14 VCC 1N914 13 0.1 F 2.5 F TREB CAP 0.47 F 2 INPUT 1 IN 1 BASS CAP 4 0.01 F 8 0.39 F 20V IN5250B 3 Vpp VDD 1 CAT524 OPT 504 CHIP SELECT. PROGRAM DATA IN DATA OUT CLOCK 4 7 5 6 2 VREFH 14 DI DO CLK VOUT1 VOUT2 VOUT3 VOUT4 VREFL GND 13 12 11 10 VZ OUTPUT 1 10 OUT 1 LM1040 1.0 F 9 CS PROG 19 47K 14 47K 11 47K 5 47K 16 0.22 F 0.22 F 0.22 F 0.22 F LOUDNESS VOLUME BALANCE TREBLE BYPASS BASS 1 47 F 7 10 F 18 10 F 9 8 OUTPUT 2 0.47 F 23 INPUT 2 3 IN 2 BASS CAP STEREO TREB CAP 15 17 22 ENHANCE 4.7K GND GND 0.39 F 21 24 0.1 F OUT 2 0.01 F 12 Digital Stereo Control 11 Doc. No. 2006, Rev. B CAT524 ORDERING INFORMATION Prefix Device # Suffix CAT 524 J Optional Company ID Product Number Package P: PDIP J: SOIC I -TE13 Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) Notes: (1) The device used in the above example is a CAT524JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Doc. No. 2006, Rev. B Publication #: Revison: Issue date: Type: 12 2006 B 03/22/02 Final CAT525 Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications FEATURES APPLICATIONS Four 8-bit DPPs configured as programmable Automated product calibration voltage sources in DAC-like applications Remote control adjustment of equipment Independent reference inputs Offset, gain and zero adjustments in self-calibrating and adaptive control systems Buffered wiper outputs Non-volatile NVRAM memory wiper storage Tamper-proof calibrations Output voltage range includes both supply rails DAC (with memory) substitute 4 independently addressable buffered output wipers 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs DESCRIPTION test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP's output. The CAT525 is a quad 8-bit digitally programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. Control of the CAT525 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin allows several CAT525's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the CAT525's TriStated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM Memory Erase/ Write cycle. The CAT525 offers four independently programmable DPPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to The CAT525 is available in the 0C to 70C commercial and -40C to 85C industrial operating temperature ranges and offered in 20-pin plastic DIP and surface mount packages. FUNCTIONAL DIAGRAM PIN CONFIGURATION V REF H1 V REF H3 V REF H2 2 RDY/BSY 1 20 V REF H4 DIP Package (P) 19 + PROG CLK CS DI SOIC Package (J) 5 9 WIPER CONTROL REGISTERS AND NVRAM 4 6 18 - PROGRAM CONTROL + 17 - + DATA CONTROLLER 16 - VREFH2 VOUT1 VOUT2 VOUT3 7 + 15 - VOUT4 28k (ea) H.V. CHARGE PUMP CAT525 SERIAL DATA OUTPUT REGISTER 8 11 12 13 VREFL2 V REFL1 (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice DO 1 20 VREF H3 VREFH2 1 20 VREF H3 VREF H1 2 19 VREF H4 VDD 3 18 VOUT1 VOUT2 VREF H1 2 19 VREF H4 VDD 3 18 VOUT1 CLK 4 17 VOUT2 CLK 4 17 RDY/BSY 5 VOUT3 RDY/BSY 5 16 VOUT3 6 15 VOUT4 VREFL4 16 CS 6 15 VOUT4 CS DI 7 14 VREFL4 DI 7 14 DO 8 13 VREFL3 DO 8 13 VREFL3 PROG 9 12 VREFL2 PROG 9 12 VREFL2 GND 10 11 VREF L1 GND 10 11 VREF L1 CAT525 CAT525 14 VREFL4 VREFL3 1 Doc. No. 2001, Rev. B CAT525 Operating Ambient Temperature Commercial (`C' or Blank suffix) ...... 0C to +70C Industrial (`I' suffix) ........................ -40C to +85C Junction Temperature ..................................... +150C Storage Temperature ........................ -65C to +150C Lead Soldering (10 sec max) .......................... +300C ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND ...................................... -0.5V to +7V Inputs CLK to GND ............................ -0.5V to VDD +0.5V CS to GND .............................. -0.5V to VDD +0.5V DI to GND ............................... -0.5V to VDD +0.5V RDY/BSY to GND ................... -0.5V to VDD +0.5V PROG to GND ........................ -0.5V to VDD +0.5V VREFH to GND ........................ -0.5V to VDD +0.5V VREFL to GND ......................... -0.5V to VDD +0.5V Outputs D0 to GND ............................... -0.5V to VDD +0.5V VOUT 1- 4 to GND ................... -0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V. POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating -- 400 600 A Programming, VDD = 5V -- 1600 2500 A VDD = 3V -- 1000 1600 A 2.7 -- 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD -- -- 10 A IIL Input Leakage Current VIN = 0V -- -- -10 A VIH High Level Input Voltage 2 -- VDD V VIL Low Level Input Voltage 0 -- 0.8 V Min Typ Max Units VDD -0.3 -- -- V LOGIC OUTPUTS Symbol Parameter Conditions VOH High Level Output Voltage IOH = -40A VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V -- -- 0.4 V IOL = 0.4 mA, VDD = +3V -- -- 0.4 V Doc. No. 2001, Rev. B 2 CAT525 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter RPOT Potentiometer Resistance Conditions Min Typ Max Units 28 RPOT to RPOT Match -- +0.5 Pot Resistance Tolerance k +1 % +15 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin OV VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC RISO Isolation Resistance VN Noise CH/CL Potentiometer Capacitances fc Frequency Response 300 ppm/C ppm/C nV/Hz 8/8 pF Passive Attenuator MHz AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz -- -- 3 6 10 10 s s Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL=100pF, see note 1 Analog tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2001, Rev. B Doc. No. 2001, Rev. B 4 RDY/BSY PROG DO DI CS CLK to to t LZ t DIS t CSS 1 1 t DO1 t DIH 2 2 t CLK H 3 t PROG t PS t CLK L 3 t DO0 4 t BUSY t CSH 4 t HZ t CSMIN 5 5 FROM TIMING TO Rising CS edge to D0 becoming high low impedance (active output) t LZ Rising PROG edge to next rising CLK edge Falling CS edge to D0 becoming high impedance (Tri-State) t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge t PROG Rising PROG edge to falling PROG edge t PS t HZ Rising CLK edge to D0 = high Rising CLK edge to D0 = low t DO0 t DO1 Rising CLK edge to end of data valid t DIH Max Min Min (Max) Max (Max) Max Min Min Data valid to first rising CLK edge after CS = high t DIS Min Min Rising CS edge to next rising CLK edge t CSMIN Falling CS edge to rising CS edge t CSS Min t CSH Falling CLK edge for last data bit (DI) to falling CS edge Min Min MIN/MAX t CLK L Falling CLK edge to CLK rising edge t CLK H Rising CLK edge to falling CLK edge PARAM NAME CAT525 A. C. TIMING DIAGRAM CAT525 PIN DESCRIPTION Pin CDPP/DPP addressing is as follows: Name Function 1 2 3 4 5 6 7 8 9 VREFH2 VREFH1 VDD CLK RDY/BSY CS DI DO PROG 10 11 12 13 14 GND VREFL1 VREFL2 VREFL3 VREFL4 Maximum DPP 2 output voltage Maximum DPP 1 output voltage Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin Non-volatile Memory Programming Enable Input Power supply ground Minimum DPP 1 output voltage Minimum DPP 2 output voltage Minimum DPP 3 output voltage Minimum DPP 4 output voltage 15 16 17 18 19 20 VOUT4 VOUT3 VOUT2 VOUT1 VREFH4 VREFH3 DPP 4 output DPP 3 output DPP 2 output DPP 1 output Maximum DPP 4 output voltage Maximum DPP 3 output voltage DPP OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 DEVICE OPERATION impedance when not in use. The CAT525 is a quad 8-bit configured digitally programmable potentiometer (DPP/CDPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each confitured DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. CHIP SELECT Chip Select (CS) enables and disables the CAT525's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP wiper control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. DIGITAL INTERFACE The CAT525 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. CLOCK Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high No clock is necessary upon system power-up. The CAT525's internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. The CAT525's clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. 5 Doc. No. 2001, Rev. B CAT525 single serial data line and simplifies interfacing multiple 525s to a microprocessor. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. WRITING TO MEMORY Programming the CAT525's non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock's rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF VREF, the voltage applied between pins VREFH &VREFL, sets the configured DPP's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH &VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The CAT525's non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. BUSY READY/BUSY When saving data to non-volatile memory, the Ready/ Busy ouput (RDY/BSY) signals the start and duration of the erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT525 will ignore any data appearing at DI and no data will be output on DO. READING DATA Data is output serially by the CAT525, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 525s to share a Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP's output. This feature allows Ps to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. Since this value is the Figure 1. Writing to Memory Figure 2. Reading from Memory RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 to CS 1 2 3 4 5 6 7 8 9 10 11 12 CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 DI 1 A0 A1 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 CURRENT DPP DATA DO PROG D0 D1 D2 D3 D4 D5 PROG RDY/BSY RDY/BSY DPP OUTPUT Doc. No. 2001, Rev. B CURRENT DPP VALUE NEW DPP VALUE NEW DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE DPP OUTPUT CURRENT DPP VALUE NON-VOLATILE 6 D6 D7 CAT525 Figure 3. Temporary Change in Output same as that which had been there previously no change in the DPP's output is noticed. Had the value held in the control register been different from that stored in nonvolatile memory then a change would occur at the read cycle's conclusion. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA TEMPORARILY CHANGE OUTPUT 1 DI The CAT525 allows temporary changes in DPP's output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA D0 DO D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT Figure 3 shows the control and data signals needed to effect a temporary output change. DPP settings may be changed as many times as required and can be made to any of the four DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPPs will return to the output values stored in non-volatile memory. CURRENT DPP VALUE NEW DPP VALUE CURRENT DPP VALUE NON-VOLATILE VOLATILE NON-VOLATILE When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP control register prior to programming. This is because the CAT525's internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. APPLICATION CIRCUITS +5V DPP INPUT Vi RI RF CONTROL & DATA VREFH VFS = 0.99 VREF CAT525 GND V - VDPP + OUT OP 07 -15V VREFL ANALOG OUTPUT CODE (V - V VDPP = ------ FS ZERO ) + VZERO 255 +15V VDD DPP OUTPUT VOUT = VDPP ( RI+ RF) -VI R F RI For R I = RF VOUT = 2VDPP -VI MSB LSB VZERO = 0.01 VREF VREF = 5V R I = RF 1111 1111 255 (.98 V ---- REF ) + .01 VREF = .990 VREF 255 VOUT = +4.90V 1000 0000 V = +0.02V OUT 0111 1111 0000 0001 128 (.98 V ---- ) + .01 V = .502 V REF REF REF 255 127 ---- (.98 V ) + .01 V = .498 V 255 REF REF REF 1 (.98 V ---- ) + .01 V = .014 V 255 REF REF REF 0000 0000 0 (.98 V ---- ) + .01 VREF = .010 V REF REF 255 V = -4.90V OUT V = -0.02V OUT V = -4.86V OUT Bipolar DPP Output +5V RI RF +15V VDD CONTROL & DATA VREFH - + CAT525 GND VOUT OP 07 -15V VREFL RF VOUT = (1 + ---) V DPP RI AAmplified lifi d DAC DPPOOutput 7 Doc. No. 2001, Rev. B CAT525 APPLICATION CIRCUITS (Cont.) +5V VDD VREF RC = ---------- 256 * 1 A +5V VREF Fine adjust gives 1 LSB change in V OFFSET VREF when VOFFSET = ------ 2 VREFH VDD +VREF VREFH 127RC FINE ADJUST DPP + (+VREF ) - (VOFFSET ) RC = ---------------------- 1 A 127RC FINE ADJUST DPP (-VREF ) + (VOFFSET+ ) Ro = ---------------------- 1 A RC COARSE ADJUST DPP +V RC COARSE ADJUST DPP VOFFSET GND VREFL +V Ro + VOFFSET -VREF - GND + - VREFL -V Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 F VDD VREFH 1N5231B VREF = 5.000V VDD CONTROL & DATA VREFH 5.1V 10K CAT525 GND LT 1029 CONTROL & DATA VREFL CAT525 CAT525 + GND - VREFL MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 2001, Rev. B Digitally Controlled Voltage Reference 8 10 F 35V 0 - 25V @ 1A CAT525 APPLICATION CIRCUITS (Cont.) +5V VREF VIN 1.0 F + LM 339 10K - VDD +5V VREFH WINDOW 1 VREF + CAT525 - VPP WINDOW 1 DPP 1 + - 10K +5V WINDOW 2 VOUT 1 + CS WINDOW 2 - + DPP 2 DI V 2 OUT 10K - +5V WINDOW 3 WINDOW 3 + DO - DPP 3 PROG VOUT 3 + - WINDOW 4 10K +5V WINDOW 4 V 4 OUT + CLK - DPP 4 WINDOW 5 + GND 10K - +5V WINDOW 5 + VREFL GND WINDOW STRUCTURE - Staircase Window Comparator +5V VREF VIN 1.0 F VDD VREFH CAT525 VPP LM 339 + 10K - +5V WINDOW 1 + DPP 1 - VREF H CS DI WINDOW 1 V 2 OUT + DPP 2 VOUT 1 10K - +5V WINDOW 2 + DO WINDOW 2 - VOUT 4 PROG DPP 3 VOUT 3 WINDOW 3 CLK GND DPP 4 + 10K - +5V WINDOW 3 WINDOW STRUCTURE + GND VREFL - Overlapping Window Comparator 9 Doc. No. 2001, Rev. B CAT525 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREF 4.7 A LM385-2.5 ISINK = 2 - 255 mA +15V + DPP1 +5V CONTROL & DATA 10K 1 mA steps 2N7000 - 39 1W 10K CAT525 39 1W + DPP2 5 A steps 2N7000 - VREFL GND 5M 5M 3.9K 10K 10K - TIP 30 + -15V Current Sink with 4 Decades of Resolution +15V 51K + TIP 29 - 10K 10K +5V VDD VREFH 5M 5M 39 1W DPP1 39 1W CONTROL & DATA - CAT525 CAT525 5M 5M DPP2 GND BS170P + 1 mA steps 3.9K - VREFL BS170P 5 A steps + LM385-2.5 -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution Doc. No. 2001, Rev. B 10 CAT525 ORDERING INFORMATION Prefix Device # Suffix CAT 525 J Optional Company ID Product Number Package P: PDIP J: SOIC I -TE13 Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0C to 70C) I = Industrial (-40C to 85C) Notes: (1) The device used in the above example is a CAT525JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) 11 Doc. No. 2001, Rev. B Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue Date: Type: 2001 B 3/22/02 Final CAT5111 100-Tap Digitally Programmable Potentiometer (DPPTM) with Buffered Wiper FEATURES APPLICATIONS 100-position linear taper potentiometer Automated product calibration Non-volatile NVRAM wiper storage; Remote control adjustments buffered wiper Offset, gain and zero control Low power CMOS technology Tamper-proof calibrations Single supply operation: 2.5V-6.0V Contrast, brightness and volume controls Increment up/down serial interface Motor controls and feedback systems Resistance values: 10k, 50k and 100k Programmable analog functions Available in PDIP, SOIC, TSSOP and MSOP packages DESCRIPTION The CAT5111 is a single digitally programmable potentiometer (DPPTM) designed as a electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The CAT5111 contains a 100-tap series resistor array connected between two terminals RH and RL. An up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RWB. The CAT5111 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new system values without effecting the stored setting. Wiper-control of the CAT5111 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. DPPs bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit. FUNCTIONAL DIAGRAM RH VCC RH U/D INC Control and Memory + - + - RWB R WB CS Power On Recall RL RL Electronic Potentiometer Implementation GND (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 2008, Rev. I CAT5111 PIN CONFIGURATION PIN FUNCTIONS PDIP/SOIC Package INC 1 8 VCC U/D RH GND 2 3 7 CS RL 4 6 5 RWB Pin Name TSSOP Package CS VCC INC U/D 1 2 3 4 RL 8 7 6 5 RWB GND RH MSOP Package INC U/D RH GND 1 2 3 4 8 7 6 5 VCC CS RL RWB Function INC Increment Control U/D Up/Down Control RH Potentiometer High Terminal GND Ground RWB Buffered Wiper Terminal RL Potentiometer Low Terminal CS Chip Select VCC Supply Voltage PIN DESCRIPTIONS INC INC: Increment Control Input of the CAT5111 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. The INC input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D input. DEVICE OPERATION D: Up/Down Control Input U/D The CAT5111 operates like a digitally controlled potentiometer with RH and RL equivalent to the high and low terminals and RWB equivalent to the mechanical potentiometer's wiper. There are 100 available tap positions including the resistor end points, RH and RL. There are 99 resistor elements connected in series between the RH and RL terminals. The wiper terminal is connected to one of the 100 taps and controlled by three inputs, INC, U/D and CS. These inputs control a sevenbit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any highto-low transition on INC will cause the wiper to move one increment toward the RH terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the RL terminal. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the RL terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. With CS set LOW the CAT5111 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC wil increment or decrement the wiper (depending on the state of the U/D input and seven-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5111 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. RWB: Wiper Potentiometer Terminal (Buffered) RWB is the buffered wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. RL: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the RH terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. R L and R H are electrically interchangeable. With INC set low, the CAT5111 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. CS CS: Chip Select The chip select input is used to activate the control input Doc. No. 2008, Rev. I 2 CAT5111 OPERATING MODES RH INC CS U/D Operation High to Low Low High Wiper toward RH High to Low Low Low Wiper toward RL High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby -0.5V to +7V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V RWB CW CL Symbol Parameter Test Method VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up Data Retention Endurance MIL-STD-883, Test Method 3015 JEDEC Standard 17 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 1003 Min Operating Voltage Range Supply Current (Increment) ICC2 Supply Current (Write) ISB1 (2) Supply Current (Standby) Potentiometer Equivalent Circuit Typ Max 2000 100 100 1,000,000 DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified Power Supply Symbol Parameter Conditions Min VCC ICC1 RL * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS TDR NEND Rwi Operating Ambient Temperature Commercial (`C' or Blank suffix) 0C to +70C Industrial (`I' suffix) - 40C to +85C Junction Temperature +150C Storage Temperature -65C to +150C Lead Soldering (10 sec max) +300C ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC to GND Inputs CS to GND INC to GND U/D to GND RH to GND RL to GND RWB to GND CH Units Volts mA Years Stores Typ Max Units VCC = 6V, f = 1MHz, IW=0 VCC = 6V, f = 250kHz, IW=0 Programming, VCC = 6V VCC = 3V 2.5 -- -- -- -- -- -- -- -- -- 6.0 200 100 1 500 V A mA A CS=VCC-0.3V -- 75 150 A U/D, INC=VCC-0.3V or GND Logic Inputs Symbol Parameter Conditions IIH IIL VIH1 VIL1 Input Leakage Current Input Leakage Current TTL High Level Input Voltage TTL Low Level Input Voltage VIH2 CMOS High Level Input Voltage VIL2 CMOS Low Level Input Voltage NOTES: (1) (2) (3) (4) Min Typ Max Units VIN = VCC VIN = 0V 4.5V VCC 5.5V -- -- 2 0 -- -- -- -- 10 -10 VCC 0.8 A A V V 2.5V VCC 6V VCC x 0.7 -- VCC + 0.3 V -0.3 -- VCC x 0.2 V This parameter is tested initially and after a design or process change that affects the parameter. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V IW=source or sink These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2008, Rev. I CAT5111 Potentiometer Parameters Symbol RPOT Parameter Conditions Min Typ Potentiometer Resistance -10 Device 10 -50 Device 50 -00 Device 100 Pot Resistance Tolerance Max Units k 15 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 1 % INL Integral Linearity Error IW 2A 0.5 1 LSB DNL Differential Linearity Error IW 2A 0.25 0.5 LSB ROUT Buffer Output Resistance .05VCC VWB .95VCC, VCC=5V 1 IOUT Buffer Output Current .05VCC VWB .95VCC, VCC=5V 3 mA TCRPOT TC of Pot Resistance 300 ppm/oC TCRATIO Ratiometric TC TBD ppm/oC Isolation Resistance TBD RISO CRH/CRL/CRW Potentiometer Capacitances fc VWB(SWING) Doc. No. 2008, Rev. I Frequency Response Passive Attenuator, 10k Output Voltage Range IOUT100A, VCC=5V 4 0.01VCC 8/8/25 pF 1.7 MHz .99VCC CAT5111 AC CONDITIONS OF TEST VCC Range 2.5V VCC 6V Input Pulse Levels 0.2VCC to 0.7VCC Input Rise and Fall Times 10ns Input Reference Levels 0.5VCC AC OPERATING CHARACTERISTICS: VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified Symbol Parameter Min Typ(1) Max Units tCI tDI tID tIL tIH tIC tCPH tCPH tIW tCYC tR, tF(2) tPU(2) tWR CS to INC Setup U/D to INC Setup U/D to INC Hold INC LOW Period INC HIGH Period INC Inactive to CS Inactive CS Deselect Time (NO STORE) CS Deselect Time (STORE) INC to VOUT Change INC Cycle Time INC Input Rise and Fall Time Power-up to Wiper Stable Store Cycle 100 50 100 250 250 1 100 10 -- 1 -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- 5 -- -- -- -- -- -- -- -- 5 -- 500 1 10 ns ns ns ns ns s ns ms s s s msec ms A. C. TIMING CS (store) tCYC tCI tIL tIC tIH tCPH 90% INC 90% 10% tDI tID tF U/D tR MI (3) tIW RWB (1) Typical values are for TA=25C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. 5 Doc. No. 2008, Rev. I CAT5111 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 5111 Product Number 5111: Buffered 5113: Unbuffered Suffix S I Package P: PDIP S: SOIC U: TSSOP R: MSOP -10 Resistance -10: 10kohms -50: 50kohms -00: 100kohms TE13 Tape & Reel TE13: 2000/Reel Notes: (1) The device used in the above example is a CAT5111 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Doc. No. 2008, Rev. I Publication #: Revison: Issue date: Type: 6 2002 I 04/17/02 Final CAT5112 32-Tap Digitally Programmable Potentiometer (DPPTM) with Buffered Wiper FEATURES APPLICATIONS 32-position linear taper potentiometer Automated product calibration Non-volatile NVRAM wiper storage; Remote control adjustments buffered wiper Offset, gain and zero control Low power CMOS technology Tamper-proof calibrations Single supply operation: 2.5V-6.0V Contrast, brightness and volume controls Increment up/down serial interface Motor controls and feedback systems Resistance values: 10k, 50k and 100k Programmable analog functions Available in PDIP, SOIC, TSSOP and MSOP packages DESCRIPTION power is returned. The wiper can be adjusted to test new system values without effecting the stored setting. Wiper-control of the CAT5112 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The CAT5112 is a single digitally programmable potentiometer (DPPTM) designed as a electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The CAT5112 contains a 32-tap series resistor array connected between two terminals RH and RL. An up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RWB. The CAT5112 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically recalled when The digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. DPPs bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit. FUNCTIONAL DIAGRAM VCC RH RH U/D INC > Control and Memory + - + - RWB R WB CS Power On Recall RL RL Electronic Potentiometer Implementation VSS (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 2002, Rev. F 1 CAT5112 PIN CONFIGURATION PIN FUNCTIONS PDIP/SOIC Package INC 1 8 VCC U/D RH GND 2 3 7 CS RL 4 6 5 RWB Pin Name TSSOP Package CS VCC INC U/D 1 2 3 4 RL 8 7 6 5 RWB GND RH MSOP Package INC U/D RH 1 2 3 8 7 6 GND 4 5 VCC CS RL RWB Function INC Increment Control U/D Up/Down Control RH Potentiometer High Terminal GND Ground RWB Buffered Wiper Terminal RL Potentiometer Low Terminal CS Chip Select VCC Supply Voltage PIN DESCRIPTIONS INC INC: Increment Control Input of the CAT5112 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. The INC input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D input. DEVICE OPERATION D: Up/Down Control Input U/D The CAT5112 operates like a digitally controlled potentiometer with RH and RL equivalent to the high and low terminals and RWB equivalent to the mechanical potentiometer's wiper. There are 32 available tap positions including the resistor end points, RH and RL. There are 31 resistor elements connected in series between the RH and R L terminals. The wiper terminal is connected to one of the 32 taps and controlled by three inputs, INC, U/D and CS. These inputs control a five-bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any highto-low transition on INC will cause the wiper to move one increment toward the RH terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the RL terminal. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the RL terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. With CS set LOW the CAT5112 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC wil increment or decrement the wiper (depending on the state of the U/D input and fivebit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5112 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. RWB: Wiper Potentiometer Terminal (Buffered) RWB is the buffered wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. RL: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the RH terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. R L and R H are electrically interchangeable. With INC set low, the CAT5112 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. CS CS: Chip Select The chip select input is used to activate the control input Doc. No. 2002, Rev. F 2 CAT5112 OPERATING MODES RH INC CS U/D Operation High to Low Low High Wiper toward H High to Low Low Low Wiper toward L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby -0.5V to +7V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V -0.5V to VCC +0.5V RWB CW CL Symbol Parameter Test Method VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up Data Retention Endurance MIL-STD-883, Test Method 3015 JEDEC Standard 17 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 1003 Min Operating Voltage Range Supply Current (Increment) ICC2 Supply Current (Write) ISB1 (2) Supply Current (Standby) Potentiometer Equivalent Circuit Typ Max 2000 100 100 1,000,000 DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified Power Supply Symbol Parameter Conditions Min VCC ICC1 RL * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS TDR NEND Rwi Operating Ambient Temperature Commercial (`C' or Blank suffix) 0C to +70C Industrial (`I' suffix) -40C to +85C Junction Temperature +150C Storage Temperature -65C to +150C Lead Soldering (10 sec max) +300C ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC to GND Inputs CS to GND INC to GND U/D to GND RH to GND RL to GND RWB to GND CH Units Volts mA Years Stores Typ Max Units VCC = 6V, f = 1MHz, IW=0 VCC = 6V, f = 250kHz, IW=0 Programming, VCC = 6V VCC = 3V 2.5 -- -- -- -- -- -- -- -- -- 6.0 200 100 1 500 V A mA A CS=VCC-0.3V -- 75 150 A Min Typ Max Units U/D, INC=VCC-0.3V or GND Logic Inputs Symbol Parameter Conditions IIH IIL VIH1 VIL1 Input Leakage Current Input Leakage Current TTL High Level Input Voltage TTL Low Level Input Voltage VIN = VCC VIN = 0V 4.5V VCC 5.5V -- -- 2 0 -- -- -- -- 10 -10 VCC 0.8 A A V V VIH2 CMOS High Level Input Voltage 2.5V VCC 6V VCC x 0.7 -- VCC + 0.3 V VIL2 CMOS Low Level Input Voltage -0.3 -- VCC x 0.2 V NOTES: (1) (2) (3) (4) This parameter is tested initially and after a design or process change that affects the parameter. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V IW=source or sink These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2002, Rev. F CAT5112 Potentiometer Parameters Symbol RPOT Parameter Conditions Min Typ Potentiometer Resistance -10 Device 10 -50 Device 50 -00 Device 100 Pot Resistance Tolerance Max Units k 15 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 1 % INL Integral Linearity Error IW 2A 0.5 1 LSB DNL Differential Linearity Error IW 2A 0.25 0.5 LSB ROUT Buffer Output Resistance .05VCC VWB .95VCC, VCC=5V 1 IOUT Buffer Output Current .05VCC VWB .95VCC, VCC=5V 3 mA TCRPOT TC of Pot Resistance 300 TCRATIO Ratiometric TC TBD ppm/C Isolation Resistance TBD 8/8/25 pF 1.7 MHz RISO CRH/CRL/CRW Potentiometer Capacitances fc VWB(SWING) Doc. No. 2002, Rev. F Frequency Response Passive Attenuator, 10k Output Voltage Range IOUT100A, VCC=5V 4 0.01VCC ppm/C .99VCC CAT5112 AC CONDITIONS OF TEST VCC Range 2.5V VCC 6V Input Pulse Levels 0.2VCC to 0.7VCC Input Rise and Fall Times 10ns Input Reference Levels 0.5VCC AC OPERATING CHARACTERISTICS: VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified Symbol Parameter Min Typ(1) Max Units tCI tDI tID tIL tIH tIC tCPH tCPH tIW tCYC tR, tF(2) tPU(2) tWR CS to INC Setup U/D to INC Setup U/D to INC Hold INC LOW Period INC HIGH Period INC Inactive to CS Inactive CS Deselect Time (NO STORE) CS Deselect Time (STORE) INC to VOUT Change INC Cycle Time INC Input Rise and Fall Time Power-up to Wiper Stable Store Cycle 100 50 100 250 250 1 100 10 -- 1 -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- 5 -- -- -- -- -- -- -- -- 5 -- 500 1 10 ns ns ns ns ns s ns ms s s s msec ms A. C. TIMING CS (store) tCYC tCI tIL tIC tIH tCPH 90% INC 90% 10% tDI tID tF U/D tR MI (3) tIW RW (1) Typical values are for TA=25C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. 5 Doc. No. 2002, Rev. F CAT5112 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 5112 Product Number 5112: Buffered 5114: Unbuffered Suffix S -10 I Package P: PDIP S: SOIC U: TSSOP R: MSOP Resistance -10: 10kohms -50: 50kohms -00: 100kohms TE13 Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) Notes: (1) The device used in the above example is a CAT5112 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Doc. No. 2002, Rev. F Publication #: Revison: Issue date: Type: 6 2002 F 4/18/02 Final CAT5113 100-Tap Digitally Programmable Potentiometer (DPPTM) FEATURES APPLICATIONS 100-position linear taper potentiometer Automated product calibration Non-volatile NVRAM wiper storage Remote control adjustments Low power CMOS technology Offset, gain and zero control Single supply operation: 2.5V-6.0V Tamper-proof calibrations Increment Up/Down serial interface Contrast, brightness and volume controls Resistance values: 10k , 50k and 100k Motor controls and feedback systems Available in PDIP, SOIC, TSSOP and MSOP packages Programmable analog functions DESCRIPTION The CAT5113 is a single digitally programmable potentiometer (DPPTM) designed as a electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. new system values without effecting the stored setting. Wiper-control of the CAT5113 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The CAT5113 contains a 100-tap series resistor array connected between two terminals RH and RL. An up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RW. The wiper setting, stored in nonvolatile memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be adjusted to test The digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. DPPs bring variability and programmability to a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM VH /R H U/D INC CS Vcc (Supply Voltage) 30 29 R H / VH UP/DOWN (U/D) INCREMENT (INC) Control and Memory R H / VH 31 7-BIT UP/DOWN COUNTER 7-BIT NONVOLATILE MEMORY ONE 28 OF ONE HUNDRED DECODER TRANSFER GATES RESISTOR ARRAY VW / R W R W / VW 2 DEVICE SELECT (CS) R L / VL POR Vcc VSS STORE AND RECALL CONTROL CIRCUITRY 1 0 R L / VL R W / VW GND GENERAL GENERAL (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice VL / R L DETAILED 1 ELECTRONIC POTENTIOMETER IMPLEMENTATION Doc. No. 2009, Rev. J CAT5113 PIN CONFIGURATION PIN FUNCTIONS DIP/SOIC Package Pin Name TSSOP Package CS INC 1 8 VCC U/D RH 2 3 7 6 CS RL VCC GND 4 5 RW U/D INC 1 2 3 4 8 7 6 5 RL RW GND RH MSOP Package INC U/D RH GND 1 2 3 4 8 7 6 5 VCC CS RL RW Function INC Increment Control U/D Up/Down Control RH Potentiometer High Terminal GND Ground RW Potentiometer Wiper Terminal RL Potentiometer Low Terminal CS Chip Select VCC Supply Voltage PIN DESCRIPTIONS INC INC: Increment Control Input of the CAT5113 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. The INC input moves the wiper in the up or down direction determined by the condition of the U/D input. U/D D: Up/Down Control Input DEVICE OPERATION The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any highto-low transition on INC will cause the wiper to move one increment toward the RH terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the RL terminal. The CAT5113 operates like a digitally controlled potentiometer with RH and RL equivalent to the high and low terminals and RW equivalent to the mechanical potentiometer's wiper. There are 100 available tap positions including the resistor end points, RH and RL. There are 99 resistor elements connected in series between the RH and RL terminals. The wiper terminal is connected to one of the 100 taps and controlled by three inputs, INC, U/D and CS. These inputs control a sevenbit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the RL terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. With CS set LOW the CAT5113 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC wil increment or decrement the wiper (depending on the state of the U/D input and seven-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5113 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. RW: Wiper Potentiometer Terminal RW is the wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. Voltage applied to the RW terminal cannot exceed the supply voltage, VCC or go below ground, GND. RL: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the RH terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. R L and R H are electrically interchangeable. With INC set low, the CAT5113 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. CS CS: Chip Select The chip select input is used to activate the control input Doc. No. 2009, Rev. J 2 OPERATION MODES RH INC CS U/D Operation High to Low Low High Wiper toward H High to Low Low Low Wiper toward L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby Supply Voltage VCC to GND ...................................... -0.5V to +7V Inputs CS to GND ............................. -0.5V to VCC +0.5V INC to GND ............................-0.5V to VCC +0.5V U/D to GND ............................-0.5V to VCC +0.5V H to GND ................................-0.5V to VCC +0.5V L to GND ................................-0.5V to VCC +0.5V W to GND ............................... -0.5V to VCC +0.5V RWB CW CL Symbol Parameter Test Method VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up Data Retention Endurance MIL-STD-883, Test Method 3015 JEDEC Standard 17 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 1003 Min ICC2 Supply Current (Write) ISB1 (2) Supply Current (Standby) Potentiometer Equivalent Circuit VCC = 6V, f = 1MHz, IW=0 VCC = 6V, f = 250kHz, IW=0 Programming, VCC = 6V VCC = 3V CS=VCC-0.3V U/D, INC=VCC-0.3V or GND Typ Max 2000 100 100 1,000,000 DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified Power Supply Symbol Parameter Conditions Min Operating Voltage Range Supply Current (Increment) RL * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS VCC ICC1 Rwi Operating Ambient Temperature Commercial (`C' or Blank suffix) ...... 0C to +70C Industrial (`I' suffix) ...................... - 40C to +85C Junction Temperature ..................................... +150C Storage Temperature ....................... -65C to +150C Lead Soldering (10 sec max) .......................... +300C ABSOLUTE MAXIMUM RATINGS TDR NEND CH Units Volts mA Years Stores Typ Max 2.5 -- -- -- -- -- -- -- -- -- 6.0 100 50 1 500 Units mA A -- -- 1 A Min Typ Max Units -- -- -- -- 10 -10 VCC 0.8 A A V V V A Logic Inputs Symbol Parameter Conditions IIH IIL VIH1 VIL1 Input Leakage Current Input Leakage Current TTL High Level Input Voltage TTL Low Level Input Voltage VIN = VCC VIN = 0V 4.5V VCC 5.5V -- -- 2 0 VIH2 CMOS High Level Input Voltage 2.5V VCC 6V VCC x 0.7 -- VCC + 0.3 V VIL2 CMOS Low Level Input Voltage -0.3 -- VCC x 0.2 V NOTES: (1) (2) (3) (4) This parameter is tested initially and after a design or process change that affects the parameter. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V IW=source or sink These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2009, Rev. J CAT5113 Potentiometer Parameters Symbol RPOT Parameter Conditions Min Typ Potentiometer Resistance -10 Device 10 -50 Device 50 -00 Device 100 Pot Resistance Tolerance Max Units k 15 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 1% % INL Integral Linearity Error IW 2A 0.5 1 LSB DNL Differential Linearity Error IW 2A 0.25 0.5 LSB RWi Wiper Resistance VCC = 5V, IW = 1mA 400 1 k 1 mA VCC = 2.5V, IW = 1mA IW Wiper Current TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC RISO Isolation Resistance VN Noise CH/CL/CW fc Doc. No. 2009, Rev. J 20 100kHz / 1kHz Potentiometer Capacitances Frequency Response ppm/oC 300 Passive Attenuator, 10k 4 ppm/oC TBD 8/24 nV/ Hz 8/8/25 pF 1.7 MHz AC CONDITIONS OF TEST VCC Range 2.5V VCC 6V Input Pulse Levels 0.2VCC to 0.7VCC Input Rise and Fall Times 10ns Input Reference Levels 0.5VCC AC OPERATING CHARACTERISTICS: VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified Symbol Parameter Min Typ(1) Max Units tCI tDI tID tIL tIH tIC tCPH tCPH tIW tCYC tR, tF(2) tPU(2) tWR CS to INC Setup U/D to INC Setup U/D to INC Hold INC LOW Period INC HIGH Period INC Inactive to CS Inactive CS Deselect Time (NO STORE) CS Deselect Time (STORE) INC to VOUT Change INC Cycle Time INC Input Rise and Fall Time Power-up to Wiper Stable Store Cycle 100 50 100 250 250 1 100 10 -- 1 -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- 5 -- -- -- -- -- -- -- -- 5 -- 500 1 10 ns ns ns ns ns s ns ms s s s msec ms A. C. TIMING CS (store) tCYC tCI tIL tIC tIH tCPH 90% INC 90% 10% tDI tID tF U/D tR MI (3) tIW RW (1) Typical values are for TA=25C and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. 5 Doc. No. 2009, Rev. J CAT5113 APPLICATIONS INFORMATION Potentiometer Configurations (a) resistive divider (b) variable resistance (c) two-port Applications V1 (-) 3 2 A1 + 1 R3 - +5V +5V +5V DPP 9 U/ +5V R4 R1 R2 10 R2 - + 4 8 A3 2 1 7 U/ VO 8 RA 11 4 RB CAT5114/5113 V2 (+) 6 5 - + A2 R4 R3 +2.5V 7 { { R1 6 5 3 } } pRPOT 7 4 8 3 (1-p)RPOT 555 R2 5 6 2 1 C .01 F .01 F, .003 F Programmable Instrumentation Amplifier Programmable Sq. Wave Oscillator (555) IC3A 1/4 74HC132 7 OSC +5V 10k 0.01 F 20k +200mV U/D 1.00V = VREF ICIB +5V 2 Sensor 3 499k CAT5112/5111 IC2 - + 4 11 -5V 499k 1V + 50mV VSENSR Sensor Auto Referencing Circuit Doc. No. 2009, Rev. J + 5 - CS CS 6 499k VCORR 499k + INC - 6 1 VOUT = 1V + 1mV ICIA 100mV = VSHIFT APPLICATIONS INFORMATION 100k +5V 8 2 U/ CAT5114/5113 1 VOUT 7 V0 (REG) 4 2952 R1 11k VIN (UNREG) 6.8 F 1.23V FB SD GND 6 3 8 7 3 - +5V 7 10k 6 + 4 2 - 7 3 + 4 A1 6 VO A2 IS R3 10k 5 Control and Memory POR 1M 5 2 1 330 3 +5V R2 820 +5V 2 (1-p)R } } .1 1 F LT1097 6 +2.5V CAT5114/5113 4 Programmable Voltage Regulator Programmable I to V convertor R1 100k CAT5112/5111 R1 50k - C2 2 VS .001 +5V +5V +5V 3 Serial Bus 7 - 6 + VS + R1 +2.5V VO 4 R1 100k +5V 2 - 3 + 41 R 2.5k IS 11 100k R1 100k A1 R2 10k 7 A2 5 - 1 F +5V R3 100k C1 .001 + U/ pR 330 SHUTDOWN 6 +2.5V +2.5V A1=A2=1/4 LMC6064A CAT5114/5113 Programmable Bandpass Filter Programmable Current Source/Sink +5V IC1 393 IC2 74HC132 1 OSC CLO - + 2 R1 VLL 3 R2 - + 7 10k 0.1 F CHI IC3 CAT5114/5113 6 5 R3 +5V VUL +5V +5V 8 2 U/D 1 INC 7 CS 6 10k 4 5 3 - + VO AI IC4 2.5V < VO < 5V VS +2.5V 0 < VS < 2.5V Automatic Gain Control 7 Doc. No. 2009, Rev. J CAT5113 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 5113 Product Number 5111: Buffered 5113: Unbuffered Suffix S I Package P: PDIP S: SOIC U: TSSOP R: MSOP -10 Resistance -10: 10kohms -50: 50kohms -00: 100kohms TE13 Tape & Reel TE13: 2000/Reel Notes: (1) The device used in the above example is a CAT5113 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Doc. No. 2009, Rev. J Publication #: Revison: Issue date: Type: 8 2009 J 04/18/02 Final CAT5114 32-Tap Digitally Programmable Potentiometer (DPPTM) FEATURES APPLICATIONS 32-position linear taper potentiometer Automated product calibration Non-volatile NVRAM wiper storage Remote control adjustments Low power CMOS technology Offset, gain and zero control Single supply operation: 2.5V-6.0V Tamper-proof calibrations Increment Up/Down serial interface Contrast, brightness and volume controls Resistance values: 10k, 50k and 100k Motor controls and feedback systems Available in PDIP, SOIC, TSSOP and MSOP packages Programmable analog functions DESCRIPTION The CAT5114 is a single digitally programmable potentiometer (DPPTM) designed as a electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. new system values without effecting the stored setting. Wiper-control of the CAT5114 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The CAT5114 contains a 32-tap series resistor array connected between two terminals RH and RL. An up/ down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RW. The wiper setting, stored in nonvolatile memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be adjusted to test The digitally programmable potentiometer can be used as a three-terminal resistive divider or as a two-terminal variable resistor. DPPs bring variability and programmability to a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM Vcc (Supply Voltage) U/D INC CS R H / VH 31 5-BIT UP/DOWN COUNTER VH /R H 30 R H / VH UP/DOWN (U/D) INCREMENT (INC) 29 Control and Memory R W / VW POR R L / VL DEVICE SELECT (CS) 5-BIT NONVOLATILE MEMORY ONE 28 OF THIRTY TWO DECODER TRANSFER GATES VW / R W RESISTOR ARRAY 2 Vcc GND VSS STORE AND RECALL CONTROL CIRCUITRY 1 0 R L / VL R W / VW GENERAL GENERAL (c) 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice DETAILED 1 VL / R L ELECTRONIC POTENTIOMETER IMPLEMENTATION Doc. No. 2007, Rev. E CAT5114 PIN CONFIGURATION PIN FUNCTIONS DIP/SOIC Package Pin Name TSSOP Package CS INC 1 8 VCC U/D RH GND 2 7 VCC 3 6 CS RL 4 5 RW U/D INC 1 2 3 4 8 7 6 5 RL RW GND RH MSOP Package INC U/D RH GND 1 2 3 4 8 7 6 5 VCC CS RL RW Function INC Increment Control U/D Up/Down Control RH Potentiometer High Terminal GND Ground RW Potentiometer Wiper Terminal RL Potentiometer Low Terminal CS Chip Select VCC Supply Voltage PIN DESCRIPTIONS INC INC: Increment Control Input of the CAT5114 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. The INC input moves the wiper in the up or down direction determined by the condition of the U/D input. U/D D: Up/Down Control Input DEVICE OPERATION The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any highto-low transition on INC will cause the wiper to move one increment toward the RH terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the RL terminal. The CAT5114 operates like a digitally controlled potentiometer with RH and RL equivalent to the high and low terminals and RW equivalent to the mechanical potentiometer's wiper. There are 32 available tap positions including the resistor end points, RH and RL. There are 31 resistor elements connected in series between the RH and R L terminals. The wiper terminal is connected to one of the 32 taps and controlled by three inputs, INC, U/D and CS. These inputs control a five-bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the RL terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. With CS set LOW the CAT5114 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC wil increment or decrement the wiper (depending on the state of the U/D input and fivebit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5114 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. RW: Wiper Potentiometer Terminal RW is the wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. Voltage applied to the RW terminal cannot exceed the supply voltage, VCC or go below ground, GND. RL: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the RH terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. R L and R H are electrically interchangeable. With INC set low, the CAT5114 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. CS CS: Chip Select The chip select input is used to activate the control input Doc. No. 2007, Rev. E 2 CAT5114 OPERATION MODES RH INC CS U/D Operation High to Low Low High Wiper toward H High to Low Low Low Wiper toward L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby Supply Voltage VCC to GND ...................................... -0.5V to +7V Inputs CS to GND ............................. -0.5V to VCC +0.5V INC to GND ............................-0.5V to VCC +0.5V U/D to GND ............................-0.5V to VCC +0.5V H to GND ................................-0.5V to VCC +0.5V L to GND ................................-0.5V to VCC +0.5V W to GND ............................... -0.5V to VCC +0.5V RW CW CL Symbol Parameter Test Method VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up Data Retention Endurance MIL-STD-883, Test Method 3015 JEDEC Standard 17 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 1003 Min ICC2 Supply Current (Write) ISB1 (2) Supply Current (Standby) Potentiometer Equivalent Circuit Typ Max 2000 100 100 1,000,000 DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified Power Supply Symbol Parameter Conditions Min Operating Voltage Range Supply Current (Increment) RL * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS VCC ICC1 Rwi Operating Ambient Temperature Commercial (`C' or Blank suffix) ...... 0C to +70C Industrial (`I' suffix) ...................... - 40C to +85C Junction Temperature ..................................... +150C Storage Temperature ....................... -65C to +150C Lead Soldering (10 sec max) .......................... +300C ABSOLUTE MAXIMUM RATINGS TDR NEND CH Units Volts mA Years Stores Typ Max Units VCC = 6V, f = 1MHz, IW=0 VCC = 6V, f = 250kHz, IW=0 Programming, VCC = 6V VCC = 3V 2.5 -- -- -- -- -- -- -- -- -- 6.0 100 50 1 500 V A mA A CS=VCC-0.3V -- -- 1 A Min Typ Max Units U/D, INC=VCC-0.3V or GND Logic Inputs Symbol Parameter Conditions IIH IIL VIH1 VIL1 Input Leakage Current Input Leakage Current TTL High Level Input Voltage TTL Low Level Input Voltage VIN = VCC VIN = 0V 4.5V VCC 5.5V -- -- 2 0 -- -- -- -- 10 -10 VCC 0.8 A A V V VIH2 CMOS High Level Input Voltage 2.5V VCC 6V VCC x 0.7 -- VCC + 0.3 V VIL2 CMOS Low Level Input Voltage -0.3 -- VCC x 0.2 V NOTES: (1) (2) (3) (4) This parameter is tested initially and after a design or process change that affects the parameter. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V IW=source or sink These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 2007, Rev. E CAT5114 Potentiometer Parameters Symbol RPOT Parameter Conditions Min Typ Potentiometer Resistance -10 Device 10 -50 Device 50 -00 Device 100 Pot Resistance Tolerance Max Units k 15 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 3.2 % INL Integral Linearity Error IW 2A 0.5 1 LSB DNL Differential Linearity Error IW 2A 0.25 0.5 LSB RWi Wiper Resistance VCC = 5V, IW = 1mA 400 1 k 1 mA VCC = 2.5V, IW = 1mA IW Wiper Current TCRPOT TC of Pot Resistance TCRATIO Ratiometric TC RISO Isolation Resistance VN Noise CH/CL/CW fc Doc. No. 2007, Rev. E 20 100kHz / 1kHz Potentiometer Capacitances Frequency Response ppm/oC 300 Passive Attenuator, 10k 4 ppm/oC TBD 8/24 nV/Hz 8/8/25 pF 1.7 MHz CAT5114 AC CONDITIONS OF TEST VCC Range 2.5V VCC 6V Input Pulse Levels 0.2VCC to 0.7VCC Input Rise and Fall Times 10ns Input Reference Levels 0.5VCC AC OPERATING CHARACTERISTICS: VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified Symbol Parameter Min Typ(1) Max Units tCI tDI tID tIL tIH tIC tCPH tCPH tIW tCYC tR, tF(2) tPU(2) tWR CS to INC Setup U/D to INC Setup U/D to INC Hold INC LOW Period INC HIGH Period INC Inactive to CS Inactive CS Deselect Time (NO STORE) CS Deselect Time (STORE) INC to VOUT Change INC Cycle Time INC Input Rise and Fall Time Power-up to Wiper Stable Store Cycle 100 50 100 250 250 1 100 10 -- 1 -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- 5 -- -- -- -- -- -- -- -- 5 -- 500 1 10 ns ns ns ns ns s ns ms s s s msec ms A. C. TIMING CS (store) tCYC tCI tIL tIC tIH tCPH 90% INC 90% 10% tDI tID tF U/D tR MI (3) tIW RW (1) Typical values are for TA=25oC and nominal supply voltage. (2) This parameter is periodically sampled and not 100% tested. (3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. 5 Doc. No. 2007, Rev. E CAT5114 APPLICATIONS INFORMATION Potentiometer Configurations (a) resistive divider (b) variable resistance (c) two-port Applications 3 V1 (-) 2 A1 + 1 R3 +5V R4 - +5V +5V +5V DPP 9 U/ R1 R2 10 R2 - + 4 8 A3 U/ VO 8 2 1 7 RA 11 4 RB 6 CAT5114/5113 V2 (+) 5 - + A2 R4 R3 +2.5V 7 { { R1 6 5 3 } } pRPOT 7 4 8 3 (1-p)RPOT 555 R2 5 6 2 1 C .01 F .01 F, .003 F Programmable Instrumentation Amplifier Programmable Sq. Wave Oscillator (555) IC3A 1/4 74HC132 7 OSC +5V 10k 0.01 F CS 20k +200mV U/D + 5 1.00V = VREF ICIB - +5V CS 2 Sensor 3 499k CAT5112/5111 IC2 - + 4 11 -5V 499k 1V + 50mV VSENSR Sensor Auto Referencing Circuit Doc. No. 2007, Rev. E 6 499k VCORR 499k + INC - 6 1 VOUT = 1V + 1mV ICIA 100mV = VSHIFT CAT5114 APPLICATIONS INFORMATION 100k +5V 8 2 U/ CAT5114/5113 1 VOUT 7 V0 (REG) 4 2952 R1 11k VIN (UNREG) 6.8 F SHUTDOWN FB SD GND 6 7 3 +5V 2 - 7 3 + 4 10k 6 2 - 7 3 + 4 A1 6 VO A2 IS R3 10k 5 Control and Memory POR 1M 5 8 1 330 3 +5V R2 820 +5V 2 (1-p)R } } .1 1 F LT1097 6 +2.5V CAT5114/5113 4 Programmable Voltage Regulator Programmable I to V convertor R1 100k CAT5112/5111 R1 50k - C2 2 VS .001 +5V +5V +5V 3 Serial Bus 7 - 6 + VS + R1 +2.5V VO 4 R1 100k +5V 2 - 3 + 41 R 2.5k IS 11 100k R1 100k A1 R2 10k 7 A2 5 - R3 100k C1 .001 1 F +5V + U/ pR 330 1.23V 6 +2.5V +2.5V A1=A2=1/4 LMC6064A CAT5114/5113 Programmable Bandpass Filter Programmable Current Source/Sink +5V IC1 393 IC2 74HC132 1 OSC CLO - + 2 R1 VLL 3 R2 - + 7 10k 0.1 F CHI IC3 CAT5114/5113 6 5 R3 +5V VUL +5V +5V 8 2 U/D 1 INC 7 CS 6 10k 4 5 3 - + VO AI IC4 2.5V < VO < 5V VS +2.5V 0 < VS < 2.5V Automatic Gain Control 7 Doc. No. 2007, Rev. E CAT5114 ORDERING INFORMATION Prefix CAT Optional Company ID Device # 5112 Product Number 5112: Buffered 5114: Unbuffered Suffix S I Package P: PDIP S: SOIC U: TSSOP R: MSOP -10 Resistance -10: 10kohms -50: 50kohms -00: 100kohms TE13 Tape & Reel TE13: 2000/Reel Notes: (1) The device used in the above example is a CAT5114 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel) Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP TM AE2 TM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Doc. No. 2007, Rev. E Publication #: Revison: Issue date: Type: 8 2007 E 4/18/02 Final