1Doc. No. 2003, Rev. C
1
2
3
4
5
6
7
14
13
12
11
8
10
9
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
VREFH
NC
VOUT
NC
NC
VREFL
GND
1
2
3
4
5
6
7
14
13
12
11
8
10
9
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
VREFH
NC
VOUT
NC
NC
VREFL
GND
CAT521
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
FEATURES
■ 8-bit DPP configured as a programmable
voltage source in DAC-like applications
■ Buffered wiper output
■Non-volatile NVRAM memory wiper storage
■Output voltage range includes both supply rails
■1 LSB accuracy, high resolution
■Serial Microwire-like interface
■Single supply operation: 2.7V - 5.5V
■Setting read-back without effecting outputs
APPLICATIONS
■Automated product calibration
■Remote control adjustment of equipment
■Offset, gain and zero adjustments in
self-calibrating and adaptive control systems
■Tamper-proof calibrations
■DAC (with memory) substitute
DESCRIPTION
The CAT521 is a 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The programmable DPP has an output voltage range
which includes both supply rails. The wiper is buffered
by a rail to rail op amp. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the
device is powered down and is automatically reinstated
when power is returned. The wiper can be dithered to
test new output values without effecting the stored
FUNCTIONAL DIAGRAM PIN CONFIGURATION
settings and stored settings can be read back without
disturbing the DPP’s output.
The CAT521 is controlled with a simple 3-wire, Microwire-
like serial interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the CAT521 Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of the non-volatile NVRAM memory Erase/Write cycle.
The CAT521 is available in 0°C to 70°C commercial and
-40°C to 85°C industrial operating temperature ranges.
Both 14-pin plastic DIP and surface mount packages
are available.
DIP Package (P) SOIC Package (J)
CAT521
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT521
CAT521
RDY/BSY
PROG PROGRAM
CONTROL
DI
CS
CLK
SERIAL
DATA
OUTPUT
REGISTER
GND
VDD
14
7
5
2
412 OU
T
V
6DO
89
31
+
28kΩ
SERIAL
CONTROL NVRAM
WIPER
CONTROL
REGISTER
AND
VREFH
VREFL
CAT521
2
Doc. No. 2003, Rev. C
Symbol Parameter Conditions Min Typ Max Units
IDD1 Supply Current (Read) Normal Operating — 400 600 µA
IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA
VDD = 3V — 1000 1600 µA
VDD Operating Voltage Range 2.7 — 5.5 V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND ...................................... -0.5V to +7V
Inputs
CLK to GND............................ -0.5V to VDD +0.5V
CS to GND.............................. -0.5V to VDD +0.5V
DI to GND ............................... -0.5V to VDD +0.5V
RDY/BSY to GND................... -0.5V to VDD +0.5V
PROG to GND ........................ -0.5V to VDD +0.5V
VREFH to GND ........................ -0.5V to VDD +0.5V
VREFL to GND......................... -0.5V to VDD +0.5V
Outputs
D0 to GND............................... -0.5V to VDD +0.5V
VOUT 1– 4 to GND................... -0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)........................ -40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(2) Latch-Up 100 mA JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol Parameter Conditions Min Typ Max Units
VOH High Level Output Voltage IOH = -40µAV
DD -0.3 — — V
VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
LOGIC INPUTS
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VDD ——10µA
IIL Input Leakage Current VIN = 0V — — -10 µA
VIH High Level Input Voltage 2 — VDD V
VIL Low Level Input Voltage 0 — 0.8 V
POWER SUPPLY
LOGIC OUTPUTS
CAT521
3Doc. No. 2003, Rev. C
Symbol Parameter Conditions Min Typ Max Units
tCSMIN Minimum CS Low Time 150 — — ns
tCSS CS Setup Time 100 — — ns
tCSH CS Hold Time 0 — — ns
tDIS DI Setup Time 50 — — ns
tDIH DI Hold Time 50 — — ns
tDO1 Output Delay to 1 — — 150 ns
tDO0 Output Delay to 0 — — 150 ns
tHZ Output Delay to High-Z — 400 — ns
tLZ Output Delay to Low-Z — 400 — ns
tBUSY Erase/Write Cycle Time — 4 5 ms
tPS PROG Setup Time 150 — — ns
tPROG Minimum Pulse Width 700 — — ns
tCLKHMinimum CLK High Time 500 — — ns
tCLKLMinimum CLK Low Time 300 — — ns
fCClock Frequency DC — 1 MHz
tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs
CLOAD = 10 pF, VDD = +3V — 6 10 µs
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
CL=100pF,
see note 1
Digital
Analog
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance 28 kΩ
RPOT to RPOT Match — +0.5 +1 %
Pot Resistance Tolerance +15 %
Voltage on VREFH pin 2.7 VDD V
Voltage on VREFL pin OV VDD - 2.7 V
Resolution 0.4 %
INL Integral Linearity Error 0.5 1 LSB
DNL Differential Linearity Error 0.25 0.5 LSB
ROUT Buffer Output Resistance 10 Ω
IOUT Buffer Output Current 3 mA
TCRPOT TC of Pot Resistance 300 ppm/˚C
TCRATIO Ratiometric TC ppm/˚C
RISO Isolation Resistance Ω
VNNoise nV/√Hz
CH/CLPotentiometer Capacitances 8/8 pF
fc Frequency Response Passive Attenuator MHz
CAT521
4
Doc. No. 2003, Rev. C
to1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK
t L
CLK tCSH
tCSS
tCSMIN
tDIS
tDIH
tDO0
tLZ
tDO1 tHZ
RDY/BSY
tPROG
tPS
to1 2 3 4 5
tBUSY
A. C. TIMING DIAGRAM
CAT521
5Doc. No. 2003, Rev. C
PIN DESCRIPTION
Pin Name Function
1V
DD Power supply positive
2 CLK Clock input pin
3 RDY/BSY Ready/Busy output
4 CS Chip select
5 DI Serial data input pin
6 DO Serial data output pin
7 PROG EEPROM Programming Enable
Input
8 GND Power supply ground
9V
REFL Minimum DAC output voltage
10 NC No Connect
11 NC No Connect
12 VOUT DPP output
13 NC No Connect
14 VREFH Maximum DPP 1 output voltage
DEVICE OPERATION
The CAT521 is a single 8-bit configured digitally
programmable potentiometer (DPP™) whose output
can be programmed to any one of 256 individual voltage
steps. Once programmed, the output setting is retained
in non-volatile memory and will not be lost when power
is removed from the chip. Upon power up the DPP
returns to the setting stored in non-volatile memory. The
DPP can be written to and read from without effecting the
output voltage during the read or write cycle. The output
can also be adjusted without altering the stored output
setting, which is useful for testing new output settings
before storing them in memory.
DIGITAL INTERFACE
The CAT521 employs a 3 wire, Microwire-like serial
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT521’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control register will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT521 clock controls both data flow in and out of
the device and non-volatile memory cell programming.
Serial data is shifted into the DI pin and out of the DO pin
on the clock’s rising edge. While it is not necessary for
the clock to be running between data transfers, the clock
must be operating in order to write to non-volatile memory,
even though the data being saved may already be
resident in the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT521 internal power-on reset circuitry loads data
from non-volatile memory to the DPP without using the
external clock.
DPP addressing is as follows:
DPP OUTPUT A0 A1
VOUT 10
CAT521
6
Doc. No. 2003, Rev. C
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control register. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
VREF
VREF, the voltage applied between pins VREFH &VREFL,
sets the DPP’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH &VREFL are connected across the
power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on VREFH and
VREFL as specified in the References section of DC
Electrical Characteristics.
READY/BUSYBUSY
BUSYBUSY
BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT521 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT521, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 521s to share a
single serial data line and simplifies interfacing multiple
521s to a microprocessor.
WRITING TO MEMORY
Programming the CAT521’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP wiper control register via the DI pin.
Data enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP wiper
control register will be ready to receive the next set of
address and data bits. The clock must be kept running
throughout the programming cycle. Internal control
circuitry takes care of generating and ramping up the
programming voltage for data transfer to the non-volatile
memory cells. The CAT521 non-volatile memory cells
will endure over 1,000,000 write cycles and will retain
data for a minimum of 100 years without being refreshed.
READING DATA
Each time data is transferred into the DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory's setting is reloaded
into the DPP wiper control register. Since this value is
Figure 1. Writing to Memory Figure 2. Reading from Memory
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
CURRENT
DPP VALUE
NON-VOLATILE
DPP
OUTPUT
PROG
DO
DI
CS
NEW
DPP VALUE
VOLATILE
NEW
DPP VALUE
NON-VOLATILE
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
RDY/BSY
A0 A11
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DPP VALUE
NON-VOLATILE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
RDY/BSY
CAT521
7Doc. No. 2003, Rev. C
Figure 3. Temporary Change in Output
the same as that which had been there previously no
change in the DPP’s output is noticed. Had the value
held in the control register been different from that stored
in non-volatile memory then
a change would
occur
at the
read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT521 allows temporary changes in the DPP’s
output to be made without disturbing the settings retained
in non-volatile memory. This feature is particularly
useful when testing for a new output setting and allows
for user adjustment of preset or default values without
losing the original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may be
changed as many times as required. The temporary
setting remains in effect long as CS remains high. When
CS returns low the DPP will return to the output value
stored in non-volatile memory.
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
because the CAT521’s internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
Amplified DPP Output
APPLICATION CIRCUITS
Bipolar DPP Output
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DPP VALUE
NON-VOLATILE
NEW
DPP VALUE
VOLATILE
CURRENT
DPP VALUE
NON-VOLATILE
RDY/BSY
MSB LSB
1111 1111 —— (.98 VREF) + .01 VREF= .990 V V = +4.90V
1000 0000 —— (.98 VREF) + .01 VREF= .502 V V = +0.02V
0111 1111 —— (.98 VREF) + .01 VREF= .498 V V = -0.02V
0000 0001 —— (.98 VREF + .01 VREF = .014 V V = -4.86V
0000 0000 —— (.98 VREF) + .01 VREF = .010 V V = -4.90V
REF
IF
V = 5V
REF
255
255 OUT
DPP INPUT DPP OUTPUT ANALOG
R = R
OUTPUT
REF OUT
128
255
127
255 REF OUT
1
255 REF OUT
REF OUT
0
255
VFS = 0.99 V
V = 0.01 V
ZERO
V = ——— (V - V ) + V
DPP CODE
255 FS ZERO ZERO
GND
VDD
CONTROL
& DATA
+
–
OP 07
-15V
+15V
+5V
RR
iF
For R =
IRF
V = 2V -V
OUT IDPP
Vi
VOUT
VOUT = VDPP (RI+RF)-VIRF
RI
VREFH
VREFL
CAT521
CAT521
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
RR
IF
V = (1 + –––) V
OUT DPP
RF
RI
CAT521
8
Doc. No. 2003, Rev. C
APPLICATION CIRCUITS (Cont.)
CAT521
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
15K 10 µF
5.1V
10K
4.02 K
1.00K 10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
OPT 515
LT 1029
I > 2 mA
V+
GND
VDD V = 5.000V
REF
V
REFH
V
REFL
CONTROL
& DATA
CAT521
CAT521
9Doc. No. 2003, Rev. C
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT521JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
521 J
Product
Number Package
P: PDIP
J: SOIC
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
-TE13
Tape & Reel
TE13:
2000/Reel
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #: 2003
Revison: C
Issue date: 3/22/02
Type: Final
1
1
2
3
4
5
6
7
14
13
12
11
8
10
9
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
VREFH1
VREFH2
VOUT1
VOUT2
VREFL2
VREFL1
GND
1
2
3
4
5
6
7
14
13
12
11
8
10
9
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
VREFH1
VREFH2
VOUT1
VOUT2
VREFL2
VREFL1
GND
CAT522
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
FEATURES
■ Two 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
■ Independent reference inputs
■Non-volatile NVRAM memory wiper storage
■Output voltage range includes both supply rails
■2 independently addressable buffered
output wipers
■1 LSB accuracy, high resolution
■Serial Microwire-like interface
■Single supply operation: 2.7V - 5.5V
■Setting read-back without effecting outputs
APPLICATIONS
■Automated product calibration.
■Remote control adjustment of equipment
■Offset, gain and zero adjustments in self-
calibrating and adaptive control systems.
■Tamper-proof calibrations.
■DAC (with memory) substitute.
DESCRIPTION
The CAT522 is a dual, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The CAT522 offers two independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail opamps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically
reinstated when power is returned. Each wiper can be
FUNCTIONAL DIAGRAM PIN CONFIGURATION
dithered to test new output values without effecting the
stored settings and stored settings can be read back
without disturbing the DPP's output.
The CAT522 is controlled with a simple 3-wire, microwire-
like serial interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the CAT522 Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of the non-volatile NVRAM memory Erase/Write cycle.
The CAT522 is available in the 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges. Both 14-pin plastic DIP and surface mount
packages are available.
DIP Package (P) SOIC Package (J)
CAT522
© 2002 by Catalyst Semiconductor, Inc. Doc. No. 2004, Rev. B
Characteristics subject to change without notice
CAT522
CAT522
RDY/BSY
PROG PROGRAM
CONTROL
DI
CS
CLK SERIAL
CONTROL
SERIAL
DATA
OUTPUT
REGISTER
GND
VDD
14
7
5
2
4
V
13
12 OU
T1
OUT2
V
6DO
89
31
+
+
28kΩ
28KΩ
WIPER
CONTROL
REGISTERS
AND
NVRAM
11
10
VREFH1 VREFH2
VREFL1 VREFL2
CAT522
2
Doc. No. 2004, Rev. B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND ...................................... -0.5V to +7V
Inputs
CLK to GND............................ -0.5V to VDD +0.5V
CS to GND.............................. -0.5V to VDD +0.5V
DI to GND ............................... -0.5V to VDD +0.5V
RDY/BSY to GND................... -0.5V to VDD +0.5V
PROG to GND ........................ -0.5V to VDD +0.5V
VREFH to GND ........................ -0.5V to VDD +0.5V
VREFL to GND......................... -0.5V to VDD +0.5V
Outputs
D0 to GND............................... -0.5V to VDD +0.5V
VOUT 1– 4 to GND................... -0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)........................ -40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(2) Latch-Up 100 mA JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol Parameter Conditions Min Typ Max Units
IDD1 Supply Current (Read) Normal Operating — 400 600 µA
IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA
VDD = 3V — 1000 1600 µA
VDD Operating Voltage Range 2.7 — 5.5 V
Symbol Parameter Conditions Min Typ Max Units
VOH High Level Output Voltage IOH = -40µAV
DD -0.3 — — V
VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
LOGIC INPUTS
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VDD ——10µA
IIL Input Leakage Current VIN = 0V — — -10 µA
VIH High Level Input Voltage 2 — VDD V
VIL Low Level Input Voltage 0 — 0.8 V
POWER SUPPLY
LOGIC OUTPUTS
CAT522
3Doc. No. 2004, Rev. B
Symbol Parameter Conditions Min Typ Max Units
tCSMIN Minimum CS Low Time 150 — — ns
tCSS CS Setup Time 100 — — ns
tCSH CS Hold Time 0 — — ns
tDIS DI Setup Time 50 — — ns
tDIH DI Hold Time 50 — — ns
tDO1 Output Delay to 1 — — 150 ns
tDO0 Output Delay to 0 — — 150 ns
tHZ Output Delay to High-Z — 400 — ns
tLZ Output Delay to Low-Z — 400 — ns
tBUSY Erase/Write Cycle Time — 4 5 ms
tPS PROG Setup Time 150 — — ns
tPROG Minimum Pulse Width 700 — — ns
tCLKHMinimum CLK High Time 500 — — ns
tCLKLMinimum CLK Low Time 300 — — ns
fCClock Frequency DC — 1 MHz
tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs
CLOAD = 10 pF, VDD = +3V — 6 10 µs
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
CL=100pF,
see note 1
Digital
Analog
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance 28 kΩ
RPOT to RPOT Match — +0.5 +1 %
Pot Resistance Tolerance +15 %
Voltage on VREFH pin 2.7 VDD V
Voltage on VREFL pin OV VDD - 2.7 V
Resolution 0.4 %
INL Integral Linearity Error 0.5 1 LSB
DNL Differential Linearity Error 0.25 0.5 LSB
ROUT Buffer Output Resistance 10 Ω
IOUT Buffer Output Current 3 mA
TCRPOT TC of Pot Resistance 300 ppm/˚C
TCRATIO Ratiometric TC ppm/˚C
RISO Isolation Resistance Ω
VNNoise nV/√Hz
CH/CLPotentiometer Capacitances 8/8 pF
fc Frequency Response Passive Attenuator MHz
CAT522
4
Doc. No. 2004, Rev. B
to1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK
t L
CLK tCSH
tCSS
tCSMIN
tDIS
tDIH
tDO0
tLZ
tDO1 tHZ
RDY/BSY
tPROG
tPS
to1 2 3 4 5
tBUSY
A. C. TIMING DIAGRAM
CAT522
5Doc. No. 2004, Rev. B
PIN DESCRIPTION
Pin Name Function
1V
DD Power supply positive
2 CLK Clock input pin
3 RDY/BSY Ready/Busy output
4 CS Chip select
5 DI Serial data input pin
6 DO Serial data output pin
7 PROG EEPROM Programming Enable
Input
8 GND Power supply ground
9V
REFL1 Minimum DPP 1 output voltage
10 VREFL2 Minimum DPP 2 output voltage
11 VOUT2 DPP 2 output
12 VOUT1 DPP 1 output
13 VREFH2 Maximum DPP 2 output voltage
14 VREFH1 Maximum DPP 1 output voltage
DEVICE OPERATION
The CAT522 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost when
power is removed from the chip. Upon power up the
DPPs return to the settings stored in non-volatile memory.
Each DPP can be written to and read from independently
without effecting the output voltage during the read or
write cycle. Each output can also be adjusted without
altering the stored output setting, which is useful for
testing new output settings before storing them in
memory.
DIGITAL INTERFACE
The CAT522 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT522’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT522’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT522’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
DPP addressing is as follows:
DPP OUTPUT A0 A1
VOUT1 01
VOUT2 11
CAT522
6
Doc. No. 2004, Rev. B
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
VREF
VREF, the voltage applied between pins VREFH &VREFL,
sets the configured DPP’s Zero to Full Scale output
range where VREFL = Zero and VREFH = Full Scale. VREF
can span the full power supply range or just a fraction of
it. In typical applications VREFH &VREFL are connected
across the power supply rails. When using less than the
full supply voltage be mindful of the limits placed on
VREFL and VREFL as specified in the References section
of DC Electrical Characteristics.
READY/BUSYBUSY
BUSYBUSY
BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT522 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT522, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 522s to share a
single serial data line and simplifies interfacing multiple
522s to a microprocessor.
WRITING TO MEMORY
Programming the CAT522’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP wiper control register via the DI pin.
Data enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP wiper
control register will be ready to receive the next set of
address and data bits. The clock must be kept running
throughout the programming cycle. Internal control
circuitry takes care of generating and ramping up the
programming voltage for data transfer to the non-volatile
cells. The CAT522’s non-volatile memory cells will
endure over 1,000,000 write cycles and will retain data
for a minimum of 100 years without being refreshed.
READING DATA
Each time data is transferred into a DPP control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register. Since this value is the
Figure 1. Writing to Memory Figure 2. Reading from Memory
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
CURRENT
DPP VALUE
NON-VOLATILE
DPP
OUTPUT
PROG
DO
DI
CS
NEW
DPP VALUE
VOLATILE
NEW
DPP VALUE
NON-VOLATILE
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
RDY/BSY
A0 A11
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DPP VALUE
NON-VOLATILE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
RDY/BSY
CAT522
7Doc. No. 2004, Rev. B
Figure 3. Temporary Change in Output
same as that which had been there previously no change
in the DPP’s output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then
a change would
occur
at the read
cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT522 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP wiper settings
may be changed as many times as required and can be
made to any of the two DPPs in any order or sequence.
The temporary setting(s) remain in effect long as CS
remains high. When CS returns low all two DPPs will
return to the output values stored in non-volatile memory.
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
because the CAT522’s internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
Amplified DPP Output
APPLICATION CIRCUITS
Bipolar DPP Output
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DPP VALUE
NON-VOLATILE
NEW
DPP VALUE
VOLATILE
CURRENT
DPP VALUE
NON-VOLATILE
RDY/BSY
MSB LSB
1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V
1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V
0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V
0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V
0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V
REF REF REF
IF
V = 5V
REF
255
255 OUT
DPP INPUT DPP OUTPUT ANALOG
R = R
OUTPUT
REF REF REF OUT
128
255
127
255 REF REF REF OUT
1
255 REF REF REF OUT
REF REF REF OUT
0
255
V = 0.99 V
FS REF
V = 0.01 V
ZERO REF
V = ——— (V - V ) + V
DPP CODE
255 FS ZERO ZERO
CAT522
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
RR
IF
V = (1 + –––) V
OUT DPP
RF
RI
CAT522
GND
VDD V
REFH
V
REFL
CONTROL
& DATA +
–
OP 07
V = ( ) -V
OUT RF
R +
i
-15V
+15V
+5V
RR
iF
Ri
i
RF
VDPP
For R =
iRF
V = 2V -V
OUT iDPP
Vi
VOUT
CAT522
8
Doc. No. 2004, Rev. B
APPLICATION CIRCUITS (Cont.)
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V VREF
R = —————
C 256 1 µA
VREF
*
Fine adjust gives ± 1 LSB change in V
when V = ———
OFFSET
VREF
2
OFFSET
VOFFSET
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V +V
REF
-V
-V
REF
Ro
R = ———————————
C 1 µA
OFFSET
VOFFSET
REF
(+V ) - (V )
R = ———————————
o 1 µA
OFFSETREF
(-V ) + (V )
+
+
CAT522
CAT522
CAT522 LT 1029
I > 2 mA
V+
GND
VDD V = 5.000V
REF
V
REFH
V
REFL
CONTROL
& DATA
CAT522
GND
VDD V
REFH
V
REFL
CONTROL
& DATA +
–
15K 10 µF
5.1V
10K
4.02 K
1.00K 10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
CAT522
9Doc. No. 2004, Rev. B
APPLICATION CIRCUITS (Cont.)
Current Sink with 4 Decades of Resolution
CAT522
CAT522
Current Source with 4 Decades of Resolution
GND V
REFL
VDD V
REFH
+5V
DPP
+
–
CONTROL
& DATA
DPP
+
–
5M 5M 39 1W
39 1W
5M 5M 3.9K
LM385-2.5
-15V
5 µA steps
I = 2 - 255 mA
SOURCE
1 mA steps
+
–
10K 10K
+15V
TIP 29
BS170P
BS170P
51K
Ω
Ω
GND V
REFL
VDD V
REFH
+5V
DPP
+
–
CONTROL
& DATA
DPP
+
–
10K 10K 39 1W
LM385-2.5
5 µA steps
I = 2 - 255 mA
SINK
2N7000
10K 10K
TIP 30
39 1W
5M 5M 3.9K
+
–
-15V
2N7000
+5V
+15V
4.7 µA
1 mA steps
2.2K
Ω
Ω
CAT522
10
Doc. No. 2004, Rev. B
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT522JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
522 J
Product
Number Package
P: PDIP
J: SOIC
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0˚C to 70˚C)
I = Industrial (-40˚C to 85˚C)
-TE13
Tape & Reel
TE13:
2000/Reel
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 2004
Revison: B
Issue date: 03/21/02
Type: Final
1
RDY/BSY
PROG PROGRAM
CONTROL
DI
CS
CLK SERIAL
CONTROL
SERIAL
DATA
OUTPUT
REGISTER
GND
VDD
14
7
5
2
4
V
13
12 OU
T2
OUT1
V
6DO
89
31
+
+
V
REFH
V
REFL
28KΩ
28KΩ
WIPER
CONTROL
REGISTER
AND
NVRAM
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FEATURES
■ Two 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
■ Common reference inputs
■Non-volatile NVRAM memory wiper storage
■Output voltage range includes both supply rails
■2 independently addressable buffered
output wipers
■1 LSB accuracy, high resolution
■Serial microwire-like interface
■Single supply operation: 2.7V - 5.5V
■Setting read-back without effecting outputs
APPLICATIONS
■Automated product calibration.
■Remote control adjustment of equipment
■Offset, gain and zero adjustments in self-
calibrating and adaptive control systems.
■Tamper-proof calibrations.
■DAC (with memory) substitute
DESCRIPTION
The CAT523 is a dual, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for systems
capable of self calibration, and applications where
equipment which is either difficult to access or in a
hazardous environment, requires periodic adjustment.
The two independently programmable DPPs have a
common output voltage range which includes both
supply rails. The wipers are buffered by rail to rail op
amps. Wiper settings, stored in non-volatile NVRAM
memory, are not lost when the device is powered down
and are automatically reinstated when power is
returned. Each wiper can be dithered to test new output
values without effecting the stored settings and stored
settings can be read back without disturbing the
DPP’s output.
Control of the CAT523 is accomplished with a simple 3-
wire, Microwire-like serial interface. A Chip Select pin
allows several CAT523's to share a common serial
interface and communication back to the host controller
is via a single serial data line thanks to the CAT523’s Tri-
Stated Data Output pin. A RDY/BSY output working in
concert with an internal low voltage detector signals
proper operation of non-volatile NVRAM memory Erase/
Write cycle.
The CAT523 is available in the 0°C to 70°C Commercial
and -40°C to + 85°C Industrial operating temperature
ranges and offered in 14-pin plastic DIP and SOIC
mount packages.
FUNCTIONAL DIAGRAM PIN CONFIGURATION
CAT523
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
DIP Package (P) SOIC Package (J)
CAT523
Doc. No. 2005, Rev. B
RDY/BSY
CLK
CS
PROG
DI
DO
VDD 2
3
4
13
12
11
5
6
7
10
9
8
114
GND
VREFH
VOUT1
VOUT2
VREFL
CLK
CS
PROG
DI
DO
VDD 2
3
4
13
12
11
5
6
7
10
9
8
114
GND
VREFH
VOUT1
VOUT2
VREFL
CAT
523
CAT
523
RDY/BSY
NC
NC NC
NC
CAT523
2
Doc. No. 2005, Rev. B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND -0.5V to +7V
Inputs
CLK to GND -0.5V to VDD +0.5V
CS to GND -0.5V to VDD +0.5V
DI to GND -0.5V to VDD +0.5V
RDY/BSY to GND -0.5V to VDD +0.5V
PROG to GND -0.5V to VDD +0.5V
VREFH to GND -0.5V to VDD +0.5V
VREFL to GND -0.5V to VDD +0.5V
Outputs
D0 to GND -0.5V to VDD +0.5V
VOUT 1– 4 to GND -0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) 0°C to +70°C
Industrial (‘I’ suffix) -40°C to +85°C
Junction Temperature +150°C
Storage Temperature -65°C to +150°C
Lead Soldering (10 sec max) +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(2) Latch-Up 100 mA JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol Parameter Conditions Min Typ Max Units
IDD1 Supply Current (Read) Normal Operating — 400 600 µA
IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA
VDD = 3V — 1000 1600 µA
VDD Operating Voltage Range 2.7 — 5.5 V
Symbol Parameter Conditions Min Typ Max Units
VOH High Level Output Voltage IOH = -40µAV
DD -0.3 — — V
VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
LOGIC INPUTS
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VDD ——10µA
IIL Input Leakage Current VIN = 0V — — -10 µA
VIH High Level Input Voltage 2 — VDD V
VIL Low Level Input Voltage 0 — 0.8 V
POWER SUPPLY
LOGIC OUTPUTS
CAT523
3Doc. No. 2005, Rev. B
Symbol Parameter Conditions Min Typ Max Units
tCSMIN Minimum CS Low Time 150 — — ns
tCSS CS Setup Time 100 — — ns
tCSH CS Hold Time 0 — — ns
tDIS DI Setup Time 50 — — ns
tDIH DI Hold Time 50 — — ns
tDO1 Output Delay to 1 — — 150 ns
tDO0 Output Delay to 0 — — 150 ns
tHZ Output Delay to High-Z — 400 — ns
tLZ Output Delay to Low-Z — 400 — ns
tBUSY Erase/Write Cycle Time — 4 5 ms
tPS PROG Setup Time 150 — — ns
tPROG Minimum Pulse Width 700 — — ns
tCLKHMinimum CLK High Time 500 — — ns
tCLKLMinimum CLK Low Time 300 — — ns
fCClock Frequency DC — 1 MHz
tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs
CLOAD = 10 pF, VDD = +3V — 6 10 µs
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
CL=100pF,
see note 1
Digital
Analog
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance 28 kΩ
RPOT to RPOT Match — +0.5 +1 %
Pot Resistance Tolerance +15 %
Voltage on VREFH pin 2.7 VDD V
Voltage on VREFL pin OV VDD - 2.7 V
Resolution 0.4 %
INL Integral Linearity Error 0.5 1 LSB
DNL Differential Linearity Error 0.25 0.5 LSB
ROUT Buffer Output Resistance 10 Ω
IOUT Buffer Output Current 3 mA
TCRPOT TC of Pot Resistance 300 ppm/˚C
TCRATIO Ratiometric TC ppm/˚C
RISO Isolation Resistance Ω
VNNoise nV/√Hz
CH/CLPotentiometer Capacitances 8/8 pF
fc Frequency Response Passive Attenuator MHz
CAT523
4
Doc. No. 2005, Rev. B
A. C. TIMING DIAGRAM
to1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK
t L
CLK tCSH
tCSS
tCSMIN
tDIS
tDIH
tDO0
tLZ
tDO1 tHZ
RDY/BSY
tPROG
tPS
to1 2 3 4 5
tBUSY
CAT523
5Doc. No. 2005, Rev. B
DPP addressing is as follows:
DPP OUTPUT A0 A1
VOUT1 0 0
VOUT2 1 0
PIN DESCRIPTION
Pin Name Function
1V
DD Power supply positive.
2 CLK Clock input pin.Clock input pin.
3 RDY/BSY Ready/Busy Output
4 CS Chip Select
5 DI Serial data input pin.
6 DO Serial data output pin.
7 PROG EEPROM Programming Enable
Input
8 GND Power supply ground.
9V
REFL Minimum DPP output voltage.
10 NC No Connect.
11 NC No Connect.
12 VOUT2 DPP output channel 2.
13 VOUT1 DPP output channel 1.
14 VREFH Maximum DPP output voltage.
DEVICE OPERATION
The CAT523 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPPs return to the settings stored in non-volatile
memory. Each DPP can be written to and read from
independently without effecting the output voltage during
the read or write cycle. Each output can also be
temporarily adjusted without changing the stored output
setting, which is useful for testing new output settings
before storing them in memory.
DIGITAL INTERFACE
The CAT523 employs a 3 wire, Microwire-like, serial
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT523’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT523’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT523’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
CAT523
6
Doc. No. 2005, Rev. B
followed by a two bit DPP address and eight data bits are
clocked into the DPP control register via the DI pin. Data
enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high some-
time after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of ramping the programming voltage for data
transfer to the non-volatile memory cells. The CAT523’s
non-volatile memory cells will endure over 100,000 write
cycles and will retain data for a minimum of 100 years
without being refreshed.
READING DATA
Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register.
VREF
VREF, the voltage applied between pins VREFH andVREFL,
sets the DPP’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH andVREFL are connected across the
power supply rails. When using less than the full supply
voltage VREFH is restricted to voltages between VDD and
VDD/2 and VREFL to voltages between GND and VDD/2.
READY/BUSY/BUSY
/BUSY/BUSY
/BUSY
When saving data to non-volatile memory, the Ready/
Busy output (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT523 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT523, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 523s to share a
single serial data line and simplifies interfacing multiple
523s to a microprocessor.
WRITING TO MEMORY
Programming the CAT523’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
Figure 2. Reading from MemoryFigure 1. Writing to Memory
RDY/BSY
NEW DPP DATA
CURRENT DPP DATA
DPP VALUE DPP VALUE DPP VALUE
DPP
OUTPUT
A0 A11
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DPP VALUE
NON-VOLATILE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
CAT523
7Doc. No. 2005, Rev. B
CAT523
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
V = ( ) -V
OUT RF
R +
i
-15V
+15V
+5V
RR
iF
Ri
i
RF
VDPP
For R =
iRF
V = 2V -V
OUT iDPP
Vi
VOUT
APPLICATION CIRCUITS
Since this value is the same as that which had been there
previously no change in the DPP’s output is noticed.
Had the value held in the control register been different
from that stored in non-volatile memory then
a change
would
occur
at the read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT523 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP wiper settings
may be changed as many times as required and can be
made to any of the two DPPs in any order or sequence.
The temporary setting(s) remain in effect long as CS
remains high. When CS returns low all two DPPs will
return to the output values stored in non-volatile memory.
When it is desired to save a new setting acquired using
Figure 3. Temporary Change in Output
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
because the CAT523’s internal control circuitry discards
the new data from the programming register two clock
cycles after receiving it (after reception is complete) if no
PROG signal is received.
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DP P VALUE
NON-VOLATILE
NEW
DP P VALUE
VOLATILE
CURRENT
DP P VALUE
NON-VOLATILE
Bipolar DPP Output
MSB LSB
1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V
1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V
0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V
0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V
0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V
REF REF REF
IF
V = 5V
REF
255
255 OUT
DPP INPUT DPP OUTPUT ANALOG
R = R
OUTPUT
REF REF REF OUT
128
255
127
255 REF REF REF OUT
1
255 REF REF REF OUT
REF REF REF OUT
0
255
V = 0.99 V
FS REF
V = 0.01 V
ZERO REF
V = ——— (V - V ) + V
DPP CODE
255 FS ZERO ZERO
Amplified DPP Output
CAT523
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
VOUT
-15V
+15V
+5V
RR
iF
V = (1 + –––) V
OUT DPP
RF
RI
CAT523
8
Doc. No. 2005, Rev. B
APPLICATION CIRCUITS (Cont.)
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
RE HF
VDD
RC
127RC
+V
+5V +VREF
-V
-VREF
Ro
R = ———————————
C 1 µA
OFFSET
VOFFSET
REF
(+V ) - (V )
R = ———————————
o 1 µA
OFFSETREF
(-V ) + (V )
+
+
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
CAT523
LT 1029
I > 2 mA
V+
GND
VDD V = 5.000V
REF
V
REFH
V
REFL
CONTROL
& DATA
CAT523
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
15K 10 µF
5.1V
10K
4.02 K
1.00K 10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V VREF
R = —————
C 256 1 µA
VREF
*
Fine adjust gives ± 1 LSB change in V
when V = ———
OFFSET
VREF
2
OFFSET
VOFFSET
CAT523
9Doc. No. 2005, Rev. B
APPLICATION CIRCUITS (Cont.)
Current Sink with 4 Decades of Resolution
Current Source with 4 Decades of Resolution
GND V
REFL
VDD VREFH
+5V
DPP
+
–
CAT523
CONTROL
& DATA
DPP
+
–
10K 10K 39Ω1W
LM385-2.5
5 µA steps
I = 2 - 255 mA
SINK
2N7000
10K 10K
TIP 30
39Ω 1W
5 meg 5 meg 3.9K
+
–
-15V
2N7000
+5V
+15V
4.7 µA
1 mA steps
2.2K
GND V
REFL
VDD V
REFH
+5V
DPP
+
–
CONTROL
& DATA
DPP
+
–
5 meg 5 meg 39 1W
39 1W
5 meg 5 meg 3.9K
LM385-2.5
-15V
5 µA steps
I = 2 - 255 mA
SOURCE
1 mA steps
+
–
10K 10K
+15V
TIP 29
BS170P
BS170P
51K
Ω
Ω
CAT523
CAT523
10
Doc. No. 2005, Rev. B
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT523JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
523 J
Product
Number Package
P: PDIP
J: SOIC
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
-TE13
Tape & Reel
TE13: 2000/Reel
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 2005
Revison: B
Issue date: 3/22/02
Type: Final
1
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FEATURES
■ Four 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
■ Common reference inputs
■Buffered wiper outputs
■Non-volatile NVRAM memory wiper storage
■Output voltage range includes both supply rails
■4 independently addressable buffered
output wipers
■1 LSB accuracy, high resolution
■Serial Microwire-like interface
■Single supply operation: 2.7V - 5.5V
■Setting read-back without effecting outputs
APPLICATIONS
■Automated product calibration
■Remote control adjustment of equipment
■Offset, gain and zero adjustments in
self-calibrating and adaptive control systems
■Tamper-proof calibrations
■DAC (with memory) substitute
DESCRIPTION
The CAT524 is a quad, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The four independently programmable DPPs have an
output range which includes both supply rails. The
wipers are buffered by rail to rail op amps. Wiper
settings, stored in non-volatile NVRAM memory, are not
lost when the device is powered down and are
automatically reinstated when power is returned. Each
wiper can be dithered to test new output values without
effecting the stored settings, and stored settings can be
read back without disturbing the DPP’s output.
The CAT524 is controlled with a simple 3-wire serial,
Microwire-like interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the Tri-Stated CAT524 Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of the non-volatile NVRAM memory Erase/Write cycle.
The CAT524 is available in the 0˚C to 70˚C commercial
and -40˚C to 85˚C industrial operating temperature
ranges. Both 14-pin plastic DIP and SOIC packages are
offered.
FUNCTIONAL DIAGRAM PIN CONFIGURATION
CAT524
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
DIP Package (P) SOIC Package (J)
CAT524
Doc. No. 2006, Rev. B
RDY/BSY
CLK
CS
PROG
DI
DO
VDD 2
3
4
13
12
11
5
6
7
10
9
8
114
GND
VREFH
VOUT1
VOUT2
VOUT3
VOUT4
VREFL
CLK
CS
PROG
DI
DO
VDD 2
3
4
13
12
11
5
6
7
10
9
8
114
GND
VREFH
VOUT1
VOUT2
VOUT3
VOUT4
VREFL
CAT
524
CAT
524
RDY/BSY
RDY/BSY
PROG PROGRAM
CONTROL
DI
CS
CLK SERIAL
CONTROL
SERIAL
DATA
OUTPUT
REGISTER
GND V
REFL
V
REFH
VDD
3114
7
5
2
4
V
13
11
10
6
12 OUT2
V
V
OUT1
V
OUT3
OUT4
DO
+
–
+
–
+
–
+
–
9
8
WIPER
CONTROL
REGISTERS
AND
NVRAM
28kΩ(4)
CAT524
2
Doc. No. 2006, Rev. B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND -0.5V to +7V
Inputs
CLK to GND -0.5V to VDD +0.5V
CS to GND -0.5V to VDD +0.5V
DI to GND -0.5V to VDD +0.5V
RDY/BSY to GND -0.5V to VDD +0.5V
PROG to GND -0.5V to VDD +0.5V
VREFH to GND -0.5V to VDD +0.5V
VREFL to GND -0.5V to VDD +0.5V
Outputs
D0 to GND -0.5V to VDD +0.5V
VOUT 1– 4 to GND -0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) 0°C to +70°C
Industrial (‘I’ suffix) -40°C to +85°C
Junction Temperature +150°C
Storage Temperature -65°C to +150°C
Lead Soldering (10 sec max) +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(2) Latch-Up 100 mA JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol Parameter Conditions Min Typ Max Units
IDD1 Supply Current (Read) Normal Operating — 400 600 µA
IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA
VDD = 3V — 1000 1600 µA
VDD Operating Voltage Range 2.7 — 5.5 V
Symbol Parameter Conditions Min Typ Max Units
VOH High Level Output Voltage IOH = -40µAV
DD -0.3 — — V
VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
LOGIC INPUTS
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VDD ——10µA
IIL Input Leakage Current VIN = 0V — — -10 µA
VIH High Level Input Voltage 2 — VDD V
VIL Low Level Input Voltage 0 — 0.8 V
POWER SUPPLY
LOGIC OUTPUTS
CAT524
3Doc. No. 2006, Rev. B
Symbol Parameter Conditions Min Typ Max Units
tCSMIN Minimum CS Low Time 150 — — ns
tCSS CS Setup Time 100 — — ns
tCSH CS Hold Time 0 — — ns
tDIS DI Setup Time 50 — — ns
tDIH DI Hold Time 50 — — ns
tDO1 Output Delay to 1 — — 150 ns
tDO0 Output Delay to 0 — — 150 ns
tHZ Output Delay to High-Z — 400 — ns
tLZ Output Delay to Low-Z — 400 — ns
tBUSY Erase/Write Cycle Time — 4 5 ms
tPS PROG Setup Time 150 — — ns
tPROG Minimum Pulse Width 700 — — ns
tCLKHMinimum CLK High Time 500 — — ns
tCLKLMinimum CLK Low Time 300 — — ns
fCClock Frequency DC — 1 MHz
tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs
CLOAD = 10 pF, VDD = +3V — 6 10 µs
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
CL=100pF,
see note 1
Digital
Analog
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance 28 kΩ
RPOT to RPOT Match — +0.5 +1 %
Pot Resistance Tolerance +15 %
Voltage on VREFH pin 2.7 VDD V
Voltage on VREFL pin OV VDD - 2.7 V
Resolution 0.4 %
INL Integral Linearity Error 0.5 1 LSB
DNL Differential Linearity Error 0.25 0.5 LSB
ROUT Buffer Output Resistance 10 Ω
IOUT Buffer Output Current 3 mA
TCRPOT TC of Pot Resistance 300 ppm/˚C
TCRATIO Ratiometric TC ppm/˚C
RISO Isolation Resistance Ω
VNNoise nV/√Hz
CH/CLPotentiometer Capacitances 8/8 pF
fc Frequency Response Passive Attenuator MHz
CAT524
4
Doc. No. 2006, Rev. B
A. C. TIMING DIAGRAM
to1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK Rising CLK edge to falling CLK edge
t L
CLK Falling CLK edge to CLK rising edge
tCSH Falling CLK edge for last data bit (DI)
to falling CS edge
tCSS Rising CS edge to next rising CLK edge
tCSMIN Falling CS edge to rising CS edge
tDIS Data valid to first rising CLK
edge after CS = high
tDIH Rising CLK edge to end of data valid
tDO0 Rising CLK edge to D0 = low
tLZ Rising CS edge to D0 becoming high
low impedance (active output)
tDO1 Rising CLK edge to D0 = high
tHZ Falling CS edge to D0 becoming high
impedance (Tri-State)
Rising PROG edge to next rising
CLK edge
Falling CLK edge after PROG=H to
rising RDY/
BSY
edge
t H
CLK
t L
CLK tCSH
tCSS
tCSMIN
tDIS
tDIH
tDO0
tLZ
tDO1 tHZ
TIMING
FROM TO MIN/MAX
Min
Min
Min
Min
Min
Min
Min
Max
(Max)
Max
(Max)
Min
Min
PARAM
NAME
RDY/BSY
tBUSY
Rising PROG edge to falling
PROG edge
tPS
tPROG
tPROG
Max
tPS
to1 2 3 4 5
tBUSY
CAT524
5Doc. No. 2006, Rev. B
PIN DESCRIPTION
Pin Name Function
1V
DD Power supply positive.
2 CLK Clock input pin.Clock input pin.
3 RDY/BSY Ready/Busy Output
4 CS Chip Select
5 DI Serial data input pin.
6 DO Serial data output pin.
7 PROG Non-volatile Memory Programming
Enable Input
8 GND Power supply ground.
9V
REFL Minimum DPP output voltage.
10 VOUT4 DPP output channel 4.
11 VOUT3 DPP output channel 3.
12 VOUT2 DPP output channel 2.
13 VOUT1 DPP output channel 1.
14 VREFH Maximum DPP output voltage.
DEVICE OPERATION
The CAT524 is a quad 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost when
power is removed from the chip. Upon power up the
DPPs return to the settings stored in non-volatile memory.
Each DPP can be written to and read from independently
without effecting the output voltage during the read or
write cycle. Each output can also be temporarily adjusted
without changing the stored output setting, which is
useful for testing new output settings before storing
them in memory.
DIGITAL INTERFACE
The CAT524 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT524’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT524’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT524’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
DPP addressing is as follows:
DPP OUTPUT A0 A1
VOUT1 0 0
VOUT2 1 0
VOUT3 0 1
VOUT4 1 1
CAT524
6
Doc. No. 2006, Rev. B
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP control register via the DI pin. Data
enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high sometime
after the start bit and at least 150 ns prior to the rising
edge of the clock cycle immediately following the D7 bit.
Two clock cycles after the D7 bit the DPP wiper control
register will be ready to receive the next set of address
and data bits. The clock must be kept running throughout
the programming cycle. Internal control circuitry takes
care of ramping the programming voltage for data transfer
to the non-volatile cells. The CAT524 non-volatile
memory cells will endure over 100,000 write cycles and
will retain data for a minimum of 20 years without being
refreshed.
READING DATA
Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register.
VREF
VREF, the voltage applied between pins VREFH andVREFL,
sets the configured DPP’s Zero to Full Scale output
range where VREFL = Zero and VREFH = Full Scale. VREF
can span the full power supply range or just a fraction of
it. In typical applications VREFH andVREFL are connected
across the power supply rails. When using less than the
full supply voltage VREFH is restricted to voltages between
VDD and VDD/2 and VREFL to voltages between GND and
VDD/2.
READY/BUSY/BUSY
/BUSY/BUSY
/BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT524 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT524, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 524s to share a
single serial data line and simplifies interfacing multiple
524s to a microprocessor.
WRITING TO MEMORY
Programming the CAT524’s non-volatile memory is
accomplished through the control signals: Chip Select
Figure 2. Reading from MemoryFigure 1. Writing to Memory
A0 A11
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DPP VALUE
NON-VOLATILE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
CURRENT
NON-VOLATILE
DPP
OUTPUT
PROG
DO
DI
CS
NEW
VOLATILE
NEW
NON-VOLATILE
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
DPP VALUE DPP VALUE
DPP VALUE
CAT524
7Doc. No. 2006, Rev. B
APPLICATION CIRCUITS
Since this value is the same as that which had been there
previously no change in the DPP’s output is noticed.
Had the value held in the control register been different
from that stored in non-volatile memory then
a change
would
occur
at the read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT524 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP wiper settings
may be changed as many times as required and can be
made to any of the four DPPs in any order or sequence.
The temporary setting(s) remain in effect long as CS
remains high. When CS returns low all four DPPs will
return to the output values stored in non-volatile memory.
When it is desired to save a new setting acquired using
Figure 3. Temporary Change in Output
this feature, the new value must be reloaded into the
DPP control register prior to programming. This is
because the CAT524’s internal control circuitry discards
the new data from the programming register two clock
cycles after receiving it (after reception is complete) if no
PROG signal is received.
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DP P VALUE
NON-VOLATILE
NEW
DP P VALUE
VOLATILE
CURRENT
DP P VALUE
NON-VOLATILE
Bipolar DPP Output
MSB LSB
1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V
1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V
0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V
0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V
0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V
REF REF REF
IF
V = 5V
REF
255
255 OUT
DPP INPUT DPP OUTPUT ANALOG
R = R
OUTPUT
REF REF REF OUT
128
255
127
255 REF REF REF OUT
1
255 REF REF REF OUT
REF REF REF OUT
0
255
V = 0.99 V
FS REF
V = 0.01 V
ZERO REF
V = ——— (V - V ) + V
DPP CODE
255 FS ZERO ZERO
Amplified DPP Output
OPT 504
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
VOUT
-15V
+15V
+5V
RR
iF
V = (1 + –––) V
OUT DPP
RF
RI
CAT524
CAT524
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
( ) -V RF
R +
i
-15V
+15V
+5V
RR
iF
Ri
i
RF
VDPP
For R =
iRF
V = 2V -V
OUT iDPP
Vi
VOUT
OUT
V=
CAT524
8
Doc. No. 2006, Rev. B
APPLICATION CIRCUITS (Cont.)
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
OPT 505
LT 1029
I > 2 mA
V+
GND
VDD V = 5.000V
REF
V
REFH
V
REFL
CONTROL
& DATA
CAT514
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
15K 10 µF
5.1V
10K
4.02 K
1.00K 10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
CAT524 CAT524
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V VREF
R = —————
C 256 1 µA
VREF
*
Fine adjust gives ± 1 LSB change in V
when V = ———
OFFSET
VREF
2
OFFSET
VOFFSET
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V +VREF
-V
-VREF
Ro
R = ———————————
C 1 µA
OFFSET
VOFFSET
REF
(+V ) - (V )
R = ———————————
o 1 µA
OFFSETREF
(-V ) + (V )
+
+
CAT524
9Doc. No. 2006, Rev. B
APPLICATION CIRCUITS (Cont.)
Staircase Window Comparator
Overlapping Window Comparator
CAT524
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
10K
+5V WINDOW 2
10K
+5V WINDOW 3
10K
+5V WINDOW 4
10K
+5V WINDOW 5
+
–
+
–
10K
+5V WINDOW 1
GND V
REFL
CS
DI
DO
PROG
CLK
VDD V
REFH
VREF
+5V
1.0 µF LM 339
DPP 1
DPP 2
DPP 3
DPP 4
WINDOW 1
WINDOW 2
WINDOW 3
WINDOW 4
WINDOW 5
VREF
V
OUT1
V
OUT2
V
OUT3
V
OUT4
GND
WINDOW STRUCTURE
VIN
CAT524
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
10K
+5V WINDOW 2
10K
+5V WINDOW 3
10K
+5V WINDOW 4
10K
+5V WINDOW 5
+
–
+
–
10K
+5V WINDOW 1
GND V
REFL
CS
DI
DO
PROG
CLK
VDD V
REFH
VREF
+5V
1.0 F
LM 339
DPP 1
DPP 2
DPP 3
DPP 4
WINDOW 1
WINDOW 2
WINDOW 3
WINDOW 4
WINDOW 5
VREF
V
OUT1
V
OUT2
V
OUT3
V
OUT4
GND
WINDOW STRUCTURE
VIN
CAT524
10
Doc. No. 2006, Rev. B
APPLICATION CIRCUITS (Cont.)
Current Sink with 4 Decades of Resolution
Current Source with 4 Decades of Resolution
GND V
REFL
VDD VREFH
+5V
DPP
+
–
CAT524
CONTROL
& DATA
DPP
+
–
10K 10K 39 Ω1W
LM385-2.5
5 µA steps
I = 2 - 255 mA
SINK
2N7000
10K 10K
TIP 30
39Ω 1W
5M 3.9K
+
–
-15V
2N7000
+5V
+15V
4.7 uF
1 mA steps
2.2K
5M
GND V
REFL
VDD V
REFH
+5V
DPP
+
–
CAT524
CONTROL
& DATA
DPP
+
–
5M 5M
39 1W
39 1W
5M 5M
3.9K
LM385-2.5
-15V
5 µA steps
I = 2 - 255 mA
SOURCE
1 mA steps
+
–
10K 10K
+15V
TIP 29
BS170P
BS170P
51K
Ω
Ω
CAT524
11 Doc. No. 2006, Rev. B
APPLICATION CIRCUITS (Cont.)
Vpp
CS
PROG
DI
DO
CLK
VDD
V
REFH
V
REFL
V
OUT3
V
OUT2
V
OUT1
V
OUT4
GND
14
1
13
12
11
10
9
8
4
7
5
6
2
3
47K
47K
47K
47K
1.0 µF
0.22
µF0.22
µF0.22
µF0.22
µF
14
11
5
16
9
23
3
22
1
7
18
17
21
24
12
OUT 2
15
OUT 1
10
13
4
8
+12V
VCC
TREB CAP
BASS CAP
OUTPUT 1
BYPASS
OUTPUT 2
TREB CAP
BASS CAP
GND
GND
STEREO
ENHANCE
IN 2
VOLUME
BALANCE
TREBLE
BASS
LOUDNESS
V
IN 1
Z
19
2
LM1040
OPT 504
CHIP SELECT.
PROGRAM
DATA IN
DATA OUT
CLOCK
INPUT 2
20V
IN5250B
2.5 µF
INPUT 1
1.0 µF
1N914
1N914
+12V
.005 µF
10K
74C14
0.47 µF
0.47 µF
0.1 µF
4.7K
0.1 µF
0.01 µF
0.39 µF
47 µF
10 µF
10 µF
0.39 µF
0.01 µF
Digital Stereo Control
CAT524
CAT524
12
Doc. No. 2006, Rev. B
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT524JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
524 J
Product
Number Package
P: PDIP
J: SOIC
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
-TE13
Tape & Reel
TE13: 2000/Reel
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 2006
Revison: B
Issue date: 03/22/02
Type: Final
1
SERIAL
DATA
OUTPUT
REGISTER
V L1REF
V H1REF
V
1
18
16
15
8
17
OUT
V
3
V
4
OUT
V
2
OUT
OUT
DO
+
–
+
–
+
–
+
–
PROG
RDY/BSY
PROGRAM
CONTROL
H.V.
CHARGE
PUMP
DATA
CONTROLLER
5
CLK
CS
4
6
7
9
V H2REF
V H3REF
V H4REF
122019
11 12 13 14
V L2REF
V L3REF
V L4REF
NVRAM
28kΩ
(ea)
WIPER
CONTROL
REGISTERS
AND
DI
GND
CLK
CS
DI
DO
VDD
PROG
RDY/BSY
VREF
H1
1
2
3
4
5
6
7
10
9
8
20
19
18
17
14
13
12
11
16
15
VREF
H2
VREF
H4
VREF
H3
VREF
L1
VREF L2
VREF L4
VREF L3
VOUT1
VOUT2
VOUT3
VOUT4
GND
CLK
CS
DI
DO
VDD
PROG
RDY/BSY
VREF
H1
1
2
3
4
5
6
7
10
9
8
20
19
18
17
14
13
12
11
16
15
VREF
H2
VREF
H4
VREF
H3
VREF
L1
VREF L2
VREF L4
VREF L3
VOUT1
VOUT2
VOUT3
VOUT4
CAT525
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
FEATURES
■ Four 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
■ Independent reference inputs
■Buffered wiper outputs
■Non-volatile NVRAM memory wiper storage
■Output voltage range includes both supply rails
■4 independently addressable buffered
output wipers
■1 LSB accuracy, high resolution
■Serial Microwire-like interface
■Single supply operation: 2.7V - 5.5V
■Setting read-back without effecting outputs
APPLICATIONS
■Automated product calibration
■Remote control adjustment of equipment
■Offset, gain and zero adjustments in
self-calibrating and adaptive control systems
■Tamper-proof calibrations
■DAC (with memory) substitute
DESCRIPTION
The CAT525 is a quad 8-bit digitally programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax machines
and cellular telephones on automated high volume
production lines and systems capable of self calibration,
it is also well suited for applications were equipment
requiring periodic adjustment is either difficult to access
or located in a hazardous environment.
The CAT525 offers four independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail op amps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically reinstated
when power is returned. Each wiper can be dithered to PIN CONFIGURATION
test new output values without effecting the stored
settings and stored settings can be read back without
disturbing the DPP’s output.
Control of the CAT525 is accomplished with a simple 3-
wire, Microwire-like serial interface. A Chip Select pin
allows several CAT525's to share a common serial
interface and communications back to the host controller
is via a single serial data line thanks to the CAT525’s Tri-
Stated Data Output pin. A RDY/BSY output working in
concert with an internal low voltage detector signals
proper operation of non-volatile NVRAM Memory Erase/
Write cycle.
The CAT525 is available in the 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges and offered in 20-pin plastic DIP and surface
mount packages.
DIP Package (P) SOIC Package (J)
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT525
CAT525
Doc. No. 2001, Rev. B
FUNCTIONAL DIAGRAM
CAT525
CAT525
2
Doc. No. 2001, Rev. B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
VDD to GND ...................................... -0.5V to +7V
Inputs
CLK to GND............................ -0.5V to VDD +0.5V
CS to GND.............................. -0.5V to VDD +0.5V
DI to GND ............................... -0.5V to VDD +0.5V
RDY/BSY to GND................... -0.5V to VDD +0.5V
PROG to GND ........................ -0.5V to VDD +0.5V
VREFH to GND ........................ -0.5V to VDD +0.5V
VREFL to GND......................... -0.5V to VDD +0.5V
Outputs
D0 to GND............................... -0.5V to VDD +0.5V
VOUT 1– 4 to GND................... -0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)........................ -40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter Min Max Units Test Method
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(2) Latch-Up 100 mA JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
Symbol Parameter Conditions Min Typ Max Units
IDD1 Supply Current (Read) Normal Operating — 400 600 µA
IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA
VDD = 3V — 1000 1600 µA
VDD Operating Voltage Range 2.7 — 5.5 V
Symbol Parameter Conditions Min Typ Max Units
VOH High Level Output Voltage IOH = -40µAV
DD -0.3 — — V
VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V
IOL = 0.4 mA, VDD = +3V — — 0.4 V
LOGIC INPUTS
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VDD ——10µA
IIL Input Leakage Current VIN = 0V — — -10 µA
VIH High Level Input Voltage 2 — VDD V
VIL Low Level Input Voltage 0 — 0.8 V
POWER SUPPLY
LOGIC OUTPUTS
CAT525
3Doc. No. 2001, Rev. B
Symbol Parameter Conditions Min Typ Max Units
tCSMIN Minimum CS Low Time 150 — — ns
tCSS CS Setup Time 100 — — ns
tCSH CS Hold Time 0 — — ns
tDIS DI Setup Time 50 — — ns
tDIH DI Hold Time 50 — — ns
tDO1 Output Delay to 1 — — 150 ns
tDO0 Output Delay to 0 — — 150 ns
tHZ Output Delay to High-Z — 400 — ns
tLZ Output Delay to Low-Z — 400 — ns
tBUSY Erase/Write Cycle Time — 4 5 ms
tPS PROG Setup Time 150 — — ns
tPROG Minimum Pulse Width 700 — — ns
tCLKHMinimum CLK High Time 500 — — ns
tCLKLMinimum CLK Low Time 300 — — ns
fCClock Frequency DC — 1 MHz
tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V — 3 10 µs
CLOAD = 10 pF, VDD = +3V — 6 10 µs
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
CL=100pF,
see note 1
Digital
Analog
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance 28 kΩ
RPOT to RPOT Match — +0.5 +1 %
Pot Resistance Tolerance +15 %
Voltage on VREFH pin 2.7 VDD V
Voltage on VREFL pin OV VDD - 2.7 V
Resolution 0.4 %
INL Integral Linearity Error 0.5 1 LSB
DNL Differential Linearity Error 0.25 0.5 LSB
ROUT Buffer Output Resistance 10 Ω
IOUT Buffer Output Current 3 mA
TCRPOT TC of Pot Resistance 300 ppm/˚C
TCRATIO Ratiometric TC ppm/˚C
RISO Isolation Resistance Ω
VNNoise nV/√Hz
CH/CLPotentiometer Capacitances 8/8 pF
fc Frequency Response Passive Attenuator MHz
CAT525
4
Doc. No. 2001, Rev. B
A. C. TIMING DIAGRAM
to1 2 3 4 5
CLK
CS
DI
DO
PROG
t H
CLK Rising CLK edge to falling CLK edge
t L
CLK Falling CLK edge to CLK rising edge
tCSH Falling CLK edge for last data bit (DI)
to falling CS edge
tCSS Rising CS edge to next rising CLK edge
tCSMIN Falling CS edge to rising CS edge
tDIS Data valid to first rising CLK
edge after CS = high
tDIH Rising CLK edge to end of data valid
tDO0 Rising CLK edge to D0 = low
tLZ Rising CS edge to D0 becoming high
low impedance (active output)
tDO1 Rising CLK edge to D0 = high
tHZ Falling CS edge to D0 becoming high
impedance (Tri-State)
Rising PROG edge to next rising
CLK edge
Falling CLK edge after PROG=H to
rising RDY/
BSY
edge
t H
CLK
t L
CLK tCSH
tCSS
tCSMIN
tDIS
tDIH
tDO0
tLZ
tDO1 tHZ
TIMING
FROM TO MIN/MAX
Min
Min
Min
Min
Min
Min
Min
Max
(Max)
Max
(Max)
Min
Min
PARAM
NAME
RDY/BSY
tBUSY
Rising PROG edge to falling
PROG edge
tPS
tPROG
tPROG
Max
tPS
to1 2 3 4 5
tBUSY
CAT525
5Doc. No. 2001, Rev. B
PIN DESCRIPTION
Pin Name Function
1V
REFH2 Maximum DPP 2 output voltage
2V
REFH1 Maximum DPP 1 output voltage
3V
DD Power supply positive
4 CLK Clock input pin
5 RDY/BSY Ready/Busy output
6 CS Chip select
7 DI Serial data input pin
8 DO Serial data output pin
9 PROG Non-volatile Memory Programming
Enable Input
10 GND Power supply ground
11 VREFL1 Minimum DPP 1 output voltage
12 VREFL2 Minimum DPP 2 output voltage
13 VREFL3 Minimum DPP 3 output voltage
14 VREFL4 Minimum DPP 4 output voltage
15 VOUT4 DPP 4 output
16 VOUT3 DPP 3 output
17 VOUT2 DPP 2 output
18 VOUT1 DPP 1 output
19 VREFH4 Maximum DPP 4 output voltage
20 VREFH3 Maximum DPP 3 output voltage
DEVICE OPERATION
The CAT525 is a quad 8-bit configured digitally
programmable potentiometer (DPP/CDPP) whose
outputs can be programmed to any one of 256 individual
voltage steps. Once programmed, these output settings
are retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPPs return to the settings stored in non-volatile
memory. Each confitured DPP can be written to and
read from independently without effecting the output
voltage during the read or write cycle. Each output can
also be adjusted without altering the stored output
setting, which is useful for testing new output settings
before storing them in memory.
DIGITAL INTERFACE
The CAT525 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT525’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP wiper control registers
will remain in effect until CS goes low. Bringing CS to a
logic low returns all DPP outputs to the settings stored in
non-volatile memory and switches DO to its high
impedance Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT525’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT525’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
CDPP/DPP addressing is as follows:
DPP OUTPUT A0 A1
VOUT1 00
VOUT2 10
VOUT3 01
VOUT4 11
CAT525
6
Doc. No. 2001, Rev. B
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
VREF
VREF, the voltage applied between pins VREFH &VREFL,
sets the configured DPP’s Zero to Full Scale output
range where VREFL = Zero and VREFH = Full Scale. VREF
can span the full power supply range or just a fraction of
it. In typical applications VREFH &VREFL are connected
across the power supply rails. When using less than the
full supply voltage be mindfull of the limits placed on
VREFH and VREFL as specified in the References section
of DC Electrical Characteristics.
READY/BUSYBUSY
BUSYBUSY
BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the erase/write cycle. Upon receiving a command to
store data (PROG goes high) RDY/BSY goes low and
remains low until the programming cycle is complete.
During this time the CAT525 will ignore any data
appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring VDD. If VDD is below the minimum value
required for EEPROM programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT525, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 525s to share a
single serial data line and simplifies interfacing multiple
525s to a microprocessor.
WRITING TO MEMORY
Programming the CAT525’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP wiper control register via the DI pin.
Data enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP control
register will be ready to receive the next set of address
and data bits. The clock must be kept running throughout
the programming cycle. Internal control circuitry takes
care of generating and ramping up the programming
voltage for data transfer to the non-volatile memory
cells. The CAT525’s non-volatile memory cells will
endure over 100,000 write cycles and will retain data for
a minimum of 20 years without being refreshed.
READING DATA
Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register. Since this value is the
Figure 1. Writing to Memory Figure 2. Reading from Memory
A0 A11
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12
o
CURRENT
DPP VALUE
NON-VOLATILE
D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
RDY/BSY
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
CURRENT
DPP VALUE
NON-VOLATILE
DPP
OUTPUT
PROG
DO
DI
CS
NEW
DPP VALUE
VOLATILE
NEW
DPP VALUE
NON-VOLATILE
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
RDY/BSY
CAT525
7Doc. No. 2001, Rev. B
Figure 3. Temporary Change in Output
same as that which had been there previously no change
in the DPP’s output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then
a change would
occur
at the read
cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
The CAT525 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may be
changed as many times as required and can be made to
any of the four DPPs in any order or sequence. The
temporary setting(s) remain in effect long as CS remains
high. When CS returns low all four DPPs will return to the
output values stored in non-volatile memory.
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP control register prior to programming. This is
because the CAT525’s internal control circuitry discards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
Amplified DPP Output
APPLICATION CIRCUITS
Bipolar DPP Output
CAT525
GND
VDD V
REFH
V
REFL
CONTROL
& DATA +
–
OP 07
V = ( ) -V
OUT RF
R +
I
-15V
+15V
+5V
RR
IF
RI
I
RF
VDPP
For R =
IRF
V = 2V -V
OUT IDPP
Vi
VOUT
VDPP
A lifi d DAC O
CAT525
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
OP 07
V
OUT
-15V
+15V
+5V
RR
IF
V = (1 + –––) V
OUT DPP
RF
RI
MSB LSB
1111 1111 —— (.98 V ) + .01 V = .990 V V = +4.90V
1000 0000 —— (.98 V ) + .01 V = .502 V V = +0.02V
0111 1111 —— (.98 V ) + .01 V = .498 V V = -0.02V
0000 0001 —— (.98 V ) + .01 V = .014 V V = -4.86V
0000 0000 —— (.98 V ) + .01 V = .010 V V = -4.90V
REF REF
IF
V = 5V
REF
255
255 OUT
DPP INPUT DPP OUTPUT ANALOG
R = R
OUTPUT
REF REF OUT
128
255
127
255 REF REF OUT
1
255 REF REF OUT
REF REF OUT
0
255
V = 0.99 V
FS
V = 0.01 V
ZERO REF
V = ——— (V - V ) + V
DPP CODE
255 FS ZERO ZERO
REF
REF
REF
REF
REF
REF
D0 D1 D2 D3 D4 D5 D6 D7
A0 A1 D0 D1 D2 D3 D4 D5 D6 D71
NEW DPP DATA
CURRENT DPP DATA
DO
DI
CS
PROG
DPP
OUTPUT
t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
o
CURRENT
DPP VALUE
NON-VOLATILE
NEW
DPP VALUE
VOLATILE
CURRENT
DPP VALUE
NON-VOLATILE
RDY/BSY
CAT525
8
Doc. No. 2001, Rev. B
APPLICATION CIRCUITS (Cont.)
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
CAT525
LT 1029
I > 2 mA
V+
GND
VDD V = 5.000V
REF
V
REFH
V
REFL
CONTROL
& DATA
CAT525
GND
VDD V
REFH
V
REFL
CONTROL
& DATA
+
–
15K 10 µF
5.1V
10K
4.02 K
1.00K 10 µF
35V
LM 324
1N5231B
MPT3055EL
28 - 32V
OUTPUT
0 - 25V
@ 1A
Digitally Trimmed Voltage Reference Digitally Controlled Voltage Reference
CAT525
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V VREF
R = —————
C 256 1 µA
VREF
*
Fine adjust gives ± 1 LSB change in V
when V = ———
OFFSET
VREF
2
OFFSET
VOFFSET
+
–
FINE ADJUST
DPP
COARSE ADJUST
DPP
GND V
REFL
V
REFH
VDD
RC
127RC
+V
+5V +V
REF
-V
-V
REF
Ro
R = ———————————
C 1 µA
OFFSET
VOFFSET
REF
(+V ) - (V )
R = ———————————
o 1 µA
OFFSETREF
(-V ) + (V )
+
+
CAT525
9Doc. No. 2001, Rev. B
APPLICATION CIRCUITS (Cont.)
Staircase Window Comparator
Overlapping Window Comparator
CAT525
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
10K
+5V WINDOW 2
10K
+5V WINDOW 3
10K
+5V WINDOW 4
10K
+5V WINDOW 5
+
–
+
–
10K
+5V WINDOW 1
GND V
REFL
CS
DI
DO
PROG
CLK
VPP
VDD V
REFH
V
REF
+5V
1.0 µF
LM 339
DPP 1
DPP 2
DPP 3
DPP 4
WINDOW 1
WINDOW 2
WINDOW 3
WINDOW 4
WINDOW 5
VREF
V 1
OUT
V 2
OUT
V 3
OUT
V 4
OUT
GND
WINDOW STRUCTURE
CAT525
V
IN
+
–
+
–
+
–
10K
+5V WINDOW 2
10K
+5V WINDOW 3
+
–
+
–
10K
+5V WINDOW 1
GND V
REFL
CS
DI
DO
PROG
CLK
VPP
VDD V
REFH
V
REF
+5V
1.0 µF
LM 339
DPP 1
DPP 2
DPP 3
DPP 4
WINDOW 1
WINDOW 2
V 1
OUT
V 2
OUT
V 3
OUT
V 4
OUT
GND
WINDOW STRUCTURE
V
IN
+
–
WINDOW 3
V H
REF
CAT525
10
Doc. No. 2001, Rev. B
GND V
REFL
VDD V
REFH
+5V
DPP1
+
–
CAT525
CONTROL
& DATA
DPP2
+
–
5M 5M 39 1W
39 1W
5M 5M 3.9K
LM385-2.5
-15V
5 µA steps
I = 2 - 255 mA
SOURCE
1 mA steps
+
–
10K 10K
+15V
TIP 29
BS170P
BS170P
51K
Ω
Ω
APPLICATION CIRCUITS (Cont.)
Current Sink with 4 Decades of Resolution
Current Source with 4 Decades of Resolution
CAT525
CAT525
GND V
REFL
VDD V
REF
+5V
DPP1
+
–
CONTROL
& DATA
DPP2
+
–
10K 10K 39 1W
LM385-2.5
5 µA steps
I = 2 - 255 mA
SINK
2N7000
10K 10K
TIP 30
39 1W
5M 5M 3.9K
+
–
-15V
2N7000
+5V
+15V
4.7 µA
1 mA steps
2.2K
Ω
Ω
CAT525
11 Doc. No. 2001, Rev. B
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT525JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
525 J
Product
Number Package
P: PDIP
J: SOIC
CAT
Optional
Company ID
I
Temperature Range
Blank = Commercial (0˚C to 70˚C)
I = Industrial (-40˚C to 85˚C)
-TE13
Tape & Reel
TE13: 2000/Reel
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 2001
Revison: B
Issue Date: 3/22/02
Type: Final
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
CAT5111
100-Tap Digitally Programmable Potentiometer (DPP™) with Buffered Wiper
FEATURES
■100-position linear taper potentiometer
■Non-volatile NVRAM wiper storage;
buffered wiper
■Low power CMOS technology
■Single supply operation: 2.5V-6.0V
■Increment up/down serial interface
■Resistance values: 10kΩ, 50kΩ and 100kΩ
■Available in PDIP, SOIC, TSSOP and MSOP packages
APPLICATIONS
■Automated product calibration
■Remote control adjustments
■Offset, gain and zero control
■Tamper-proof calibrations
■Contrast, brightness and volume controls
■Motor controls and feedback systems
■Programmable analog functions
power is returned. The wiper can be adjusted to test new
system values without effecting the stored
setting. Wiper-control of the CAT5111 is
accomplished with three input control pins, CS, U/D,
and INC. The INC input increments the wiper in the
direction which is determined by the logic state of
the U/D input. The CS input is used to select the
device and also store the wiper position prior to
power down.
The digitally programmable potentiometer can be
used as a three-terminal resistive divider or as a
two-terminal variable resistor. DPPs bring variability and
programmability to a broad range of applications
and are used primarily to control, regulate or adjust a
characteristic or parameter of an analog circuit.
FUNCTIONAL DIAGRAM
DESCRIPTION
The CAT5111 is a single digitally programmable
potentiometer (DPP™) designed as a electronic
replacement for mechanical potentiometers and trim
pots. Ideal for automated adjustments on high volume
production lines, they are also well suited for
applications where equipment requiring periodic
adjustment is either difficult to access or located in a
hazardous or remote environment.
The CAT5111 contains a 100-tap series resistor array
connected between two terminals RH and RL. An up/
down counter and decoder that are controlled by three
input pins, determines which tap is connected to the
wiper, RWB. The CAT5111 wiper is buffered by an op
amp that operates rail to rail. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the device
is powered down and is automatically recalled when
Electronic Potentiometer
Implementation
RH
+
–
RWB
RL
CS
INC
U/D
Control
and
Memory
V
CC
R
R
R
WB
H
L
Power On Recall
GND
+
-
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice Doc. No. 2008, Rev. I1
CAT5111
2
Doc. No. 2008, Rev. I
of the CAT5111 and is active low. When in a high
state, activity on the INC and U/D inputs will not
affect or change the position of the wiper.
DEVICE OPERATION
The CAT5111 operates like a digitally controlled
potentiometer with RH and RL equivalent to the high
and low terminals and RWB equivalent to the mechanical
potentiometer's wiper. There are 100 available tap
positions including the resistor end points, RH and RL.
There are 99 resistor elements connected in series
between the RH and RL terminals. The wiper terminal is
connected to one of the 100 taps and controlled by three
inputs, INC, U/D and CS. These inputs control a seven-
bit up/down counter whose output is decoded to select
the wiper position. The selected wiper position can be
stored in nonvolatile memory using the INC and
CS inputs.
With CS set LOW the CAT5111 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC wil increment or decrement the
wiper (depending on the state of the U/D input and
seven-bit counter). The wiper, when at either fixed
terminal, acts like its mechanical equivalent and does
not move beyond the last position. The value of the
counter is stored in nonvolatile memory whenever CS
transitions HIGH while the INC input is also HIGH. When
the CAT5111 is powered-down, the last stored wiper
counter position is maintained in the nonvolatile memory.
When power is restored, the contents of the memory are
recalled and the counter is set to the value stored.
With INC set low, the CAT5111 may be de-selected
and powered down without storing the current wiper
position in nonvolatile memory. This allows the
system to always power up to a preset value stored
in nonvolatile memory.
PIN DESCRIPTIONS
INCINC
INCINC
INC: Increment Control Input
The INC input (on the falling edge) moves the wiper in the
up or down direction determined by the condition of the
U/D input.
U/DD
DD
D: Up/Down Control Input
The U/D input controls the direction of the wiper
movement. When in a high state and CS is low, any high-
to-low transition on INC will cause the wiper to move one
increment toward the RH terminal. When in a low state
and CS is low, any high-to-low transition on INC will
cause the wiper to move one increment towards the
RL terminal.
RH: High End Potentiometer Terminal
RH is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
greater than the RL terminal. Voltage applied to the RH
terminal cannot exceed the supply voltage, VCC or go
below ground, GND.
RWB: Wiper Potentiometer Terminal (Buffered)
RWB is the buffered wiper terminal of the potentiometer. Its
position on the resistor array is controlled by the control
inputs, INC, U/D and CS.
RL: Low End Potentiometer Terminal
RL is the low end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
less than the RH terminal. Voltage applied to the RL
terminal cannot exceed the supply voltage, VCC or go
below ground, GND. RL and RH are electrically
interchangeable.
CSCS
CSCS
CS: Chip Select
The chip select input is used to activate the control input
PIN FUNCTIONS
Pin Name Function
INC Increment Control
U/DUp/Down Control
RHPotentiometer High Terminal
GND Ground
RWB Buffered Wiper Terminal
RLPotentiometer Low Terminal
CS Chip Select
VCC Supply Voltage
PIN CONFIGURATION
PDIP/SOIC Package TSSOP Package
MSOP Package
INC
VCC
CS RL
RWB
U/D RH
GND
1
2
3
4
8
7
6
5
CS
INC VCC
RL
RWB
U/D
RH
GND
1
2
3
4
8
7
6
5
V
CC
RL
RWB
GND
RH
INC
U/DCS
1
2
3
4
8
7
6
5
CAT5111
3Doc. No. 2008, Rev. I
OPERATING MODES
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC to GND –0.5V to +7V
Inputs
CS to GND –0.5V to VCC +0.5V
INC to GND –0.5V to VCC +0.5V
U/D to GND –0.5V to VCC +0.5V
RH to GND –0.5V to VCC +0.5V
RL to GND –0.5V to VCC +0.5V
RWB to GND –0.5V to VCC +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) 0°C to +70°C
Industrial (‘I’ suffix) – 40°C to +85°C
Junction Temperature +150°C
Storage Temperature –65°C to +150°C
Lead Soldering (10 sec max) +300°C
* Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Absolute Maximum Ratings
are limited values applied individually while other parameters are
within specified operating conditions, and functional operation at any
of these conditions is NOT implied. Device performance and reliability
may be impaired by exposure to absolute rating conditions for extended
periods of time.
NOTES: (1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V
(3) IW=source or sink
(4) These parameters are periodically sampled and are not 100% tested.
RL
CL
CH
RH
CW
RWB
Rwi
Potentiometer
Equivalent Circuit
Power Supply
Symbol Parameter Conditions Min Typ Max Units
VCC Operating Voltage Range 2.5 —6.0 V
ICC1 Supply Current (Increment) VCC = 6V, f = 1MHz, IW=0 ——200 µA
VCC = 6V, f = 250kHz, IW=0 ——100
ICC2 Supply Current (Write) Programming, VCC = 6V ——1mA
VCC = 3V ——500 µA
ISB1 (2) Supply Current (Standby) CS=VCC-0.3V —75 150 µA
U/D, INC=VCC-0.3V or GND
DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VCC ——10 µA
IIL Input Leakage Current VIN = 0V ——–10 µA
VIH1 TTL High Level Input Voltage 4.5V ≤ VCC ≤ 5.5V 2 —VCC V
VIL1 TTL Low Level Input Voltage 0 —0.8 V
VIH2 CMOS High Level Input Voltage 2.5V ≤ VCC ≤ 6V VCC x 0.7 —VCC + 0.3 V
VIL2 CMOS Low Level Input Voltage -0.3 —VCC x 0.2 V
Logic Inputs
INC CS U/D Operation
High to Low Low High Wiper toward RH
High to Low Low Low Wiper toward RL
High Low to High X Store Wiper Position
Low Low to High X No Store, Return to Standby
X High X Standby
RELIABILITY CHARACTERISTICS
Symbol Parameter Test Method Min Typ Max Units
VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA
TDR Data Retention MIL-STD-883, Test Method 1008 100 Years
NEND Endurance MIL-STD-883, Test Method 1003 1,000,000 Stores
CAT5111
4
Doc. No. 2008, Rev. I
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance -10 Device 10
-50 Device 50 kΩ
-00 Device 100
Pot Resistance Tolerance ±15 %
VRH Voltage on RH pin 0 VCC V
VRL Voltage on RL pin 0 VCC V
Resolution 1 %
INL Integral Linearity Error IW ≤ 2µA 0.5 1 LSB
DNL Differential Linearity Error IW ≤ 2µA 0.25 0.5 LSB
ROUT Buffer Output Resistance .05VCC ≤ VWB ≤ .95VCC, VCC=5V 1 Ω
IOUT Buffer Output Current .05VCC ≤ VWB≤ .95VCC, VCC=5V 3 mA
TCRPOT TC of Pot Resistance 300 ppm/oC
TCRATIO Ratiometric TC TBD ppm/oC
RISO Isolation Resistance TBD Ω
CRH/CRL/CRW Potentiometer Capacitances 8/8/25 pF
fc Frequency Response Passive Attenuator, 10kΩ 1.7 MHz
VWB(SWING) Output Voltage Range IOUT≤100µA, VCC=5V 0.01VCC .99VCC
Potentiometer Parameters
CAT5111
5Doc. No. 2008, Rev. I
VCC Range 2.5V ≤ VCC ≤ 6V
Input Pulse Levels 0.2VCC to 0.7VCC
Input Rise and Fall Times 10ns
Input Reference Levels 0.5VCC
AC CONDITIONS OF TEST
A. C. TIMING
(1) Typical values are for TA=25˚C and nominal supply voltage.
(2) This parameter is periodically sampled and not 100% tested.
(3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
CS
INC
U/D
RWB
t
CI
t
CYC
t
IL
MI(3)
90% 90%
10%
(store)
t
F
t
R
t
IW
tID
tDI
t
IH
t
CPH
t
IC
Symbol Parameter Min Typ(1) Max Units
tCI CS to INC Setup 100 ——ns
tDI U/D to INC Setup 50 ——ns
tID U/D to INC Hold 100 ——ns
tIL INC LOW Period 250 ——ns
tIH INC HIGH Period 250 ——ns
tIC INC Inactive to CS Inactive 1 ——µs
tCPH CS Deselect Time (NO STORE) 100 ——ns
tCPH CS Deselect Time (STORE) 10 ——ms
tIW INC to VOUT Change —15µs
tCYC INC Cycle Time 1 ——µs
tR, tF(2) INC Input Rise and Fall Time —— 500 µs
tPU(2) Power-up to Wiper Stable —— 1 msec
tWR Store Cycle —510ms
AC OPERATING CHARACTERISTICS:
VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified
CAT5111
6
Doc. No. 2008, Rev. I
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT5111 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
5111 S
Product Number Package
P: PDIP
S: SOIC
U: TSSOP
CAT
Optional
Company ID
ITE13
Tape & Reel
TE13: 2000/Reel
-10
Resistance
-10: 10kohms
-50: 50kohms
-00: 100kohms
5111: Buffered
5113: Unbuffered
R: MSOP
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #: 2002
Revison: I
Issue date: 04/17/02
Type: Final
1
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice Doc. No. 2002, Rev. F
CAT5112
32-Tap Digitally Programmable Potentiometer (DPP™) with Buffered Wiper
FEATURES
■32-position linear taper potentiometer
■Non-volatile NVRAM wiper storage;
buffered wiper
■Low power CMOS technology
■Single supply operation: 2.5V-6.0V
■Increment up/down serial interface
■Resistance values: 10kΩ, 50kΩ and 100kΩ
■Available in PDIP, SOIC, TSSOP and MSOP packages
APPLICATIONS
■Automated product calibration
■Remote control adjustments
■Offset, gain and zero control
■Tamper-proof calibrations
■Contrast, brightness and volume controls
■Motor controls and feedback systems
■Programmable analog functions
power is returned. The wiper can be adjusted to test new
system values without effecting the stored
setting. Wiper-control of the CAT5112 is
accomplished with three input control pins, CS, U/D,
and INC. The INC input increments the wiper in the
direction which is determined by the logic state of
the U/D input. The CS input is used to select the
device and also store the wiper position prior to
power down.
The digitally programmable potentiometer can be
used as a three-terminal resistive divider or as a
two-terminal variable resistor. DPPs bring variability and
programmability to a broad range of applications
and are used primarily to control, regulate or adjust a
characteristic or parameter of an analog circuit.
FUNCTIONAL DIAGRAM
DESCRIPTION
The CAT5112 is a single digitally programmable
potentiometer (DPP™) designed as a electronic
replacement for mechanical potentiometers and trim
pots. Ideal for automated adjustments on high volume
production lines, they are also well suited for
applications where equipment requiring periodic
adjustment is either difficult to access or located in a
hazardous or remote environment.
The CAT5112 contains a 32-tap series resistor array
connected between two terminals RH and RL. An up/
down counter and decoder that are controlled by three
input pins, determines which tap is connected to the
wiper, RWB. The CAT5112 wiper is buffered by an op
amp that operates rail to rail. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the de-
vice is powered down and is automatically recalled when
Electronic Potentiometer
Implementation
RH
+
–
RWB
RL
CS
+
–
INC
U/D
Control
and
Memory
VCC
R
R
RWB
H
L
VSS
Power On Recall
>
CAT5112
2
Doc. No. 2002, Rev. F
of the CAT5112 and is active low. When in a high
state, activity on the INC and U/D inputs will not
affect or change the position of the wiper.
DEVICE OPERATION
The CAT5112 operates like a digitally controlled
potentiometer with RH and RL equivalent to the high
and low terminals and RWB equivalent to the mechanical
potentiometer's wiper. There are 32 available tap posi-
tions including the resistor end points, RH and RL. There
are 31 resistor elements connected in series between
the RH and RL terminals. The wiper terminal is
connected to one of the 32 taps and controlled by three
inputs, INC, U/D and CS. These inputs control a five-bit
up/down counter whose output is decoded to select the
wiper position. The selected wiper position can be
stored in nonvolatile memory using the INC and
CS inputs.
With CS set LOW the CAT5112 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC wil increment or decrement the
wiper (depending on the state of the U/D input and five-
bit counter). The wiper, when at either fixed terminal,
acts like its mechanical equivalent and does not move
beyond the last position. The value of the counter is
stored in nonvolatile memory whenever CS transitions
HIGH while the INC input is also HIGH. When the
CAT5112 is powered-down, the last stored wiper counter
position is maintained in the nonvolatile memory. When
power is restored, the contents of the memory are
recalled and the counter is set to the value stored.
With INC set low, the CAT5112 may be de-selected
and powered down without storing the current wiper
position in nonvolatile memory. This allows the
system to always power up to a preset value stored
in nonvolatile memory.
PIN DESCRIPTIONS
INCINC
INCINC
INC: Increment Control Input
The INC input (on the falling edge) moves the wiper in the
up or down direction determined by the condition of the
U/D input.
U/DD
DD
D: Up/Down Control Input
The U/D input controls the direction of the wiper
movement. When in a high state and CS is low, any high-
to-low transition on INC will cause the wiper to move one
increment toward the RH terminal. When in a low state
and CS is low, any high-to-low transition on INC will
cause the wiper to move one increment towards the
RL terminal.
RH: High End Potentiometer Terminal
RH is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
greater than the RL terminal. Voltage applied to the RH
terminal cannot exceed the supply voltage, VCC or go
below ground, GND.
RWB: Wiper Potentiometer Terminal (Buffered)
RWB is the buffered wiper terminal of the potentiometer. Its
position on the resistor array is controlled by the control
inputs, INC, U/D and CS.
RL: Low End Potentiometer Terminal
RL is the low end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
less than the RH terminal. Voltage applied to the RL
terminal cannot exceed the supply voltage, VCC or go
below ground, GND. RL and RH are electrically
interchangeable.
CSCS
CSCS
CS: Chip Select
The chip select input is used to activate the control input
PIN FUNCTIONS
Pin Name Function
INC Increment Control
U/DUp/Down Control
RHPotentiometer High Terminal
GND Ground
RWB Buffered Wiper Terminal
RLPotentiometer Low Terminal
CS Chip Select
VCC Supply Voltage
PIN CONFIGURATION
PDIP/SOIC Package TSSOP Package
MSOP Package
INC
VCC
CS RL
RWB
U/D RH
GND
1
2
3
4
8
7
6
5
CS
INC VCC
RL
RWB
U/D
RH
GND
1
2
3
4
8
7
6
5
V
CC
RL
RWB
GND
RH
INC
U/DCS
1
2
3
4
8
7
6
5
CAT5112
3Doc. No. 2002, Rev. F
Power Supply
Symbol Parameter Conditions Min Typ Max Units
VCC Operating Voltage Range 2.5 —6.0 V
ICC1 Supply Current (Increment) VCC = 6V, f = 1MHz, IW=0 ——200 µA
VCC = 6V, f = 250kHz, IW=0 ——100
ICC2 Supply Current (Write) Programming, VCC = 6V ——1mA
VCC = 3V ——500 µA
ISB1 (2) Supply Current (Standby) CS=VCC-0.3V —75 150 µA
U/D, INC=VCC-0.3V or GND
OPERATING MODES
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC to GND -0.5V to +7V
Inputs
CS to GND -0.5V to VCC +0.5V
INC to GND -0.5V to VCC +0.5V
U/D to GND -0.5V to VCC +0.5V
RH to GND -0.5V to VCC +0.5V
RL to GND -0.5V to VCC +0.5V
RWB to GND -0.5V to VCC +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) 0°C to +70°C
Industrial (‘I’ suffix) -40°C to +85°C
Junction Temperature +150°C
Storage Temperature -65°C to +150°C
Lead Soldering (10 sec max) +300°C
* Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Absolute Maximum Ratings
are limited values applied individually while other parameters are
within specified operating conditions, and functional operation at any
of these conditions is NOT implied. Device performance and reliability
may be impaired by exposure to absolute rating conditions for extended
periods of time.
NOTES: (1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V
(3) IW=source or sink
(4) These parameters are periodically sampled and are not 100% tested.
RL
CL
CH
RH
CW
RWB
Rwi
Potentiometer
Equivalent Circuit
INC CS U/D Operation
High to Low Low High Wiper toward H
High to Low Low Low Wiper toward L
High Low to High X Store Wiper Position
Low Low to High X No Store, Return to Standby
X High X Standby
RELIABILITY CHARACTERISTICS
Symbol Parameter Test Method Min Typ Max Units
VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA
TDR Data Retention MIL-STD-883, Test Method 1008 100 Years
NEND Endurance MIL-STD-883, Test Method 1003 1,000,000 Stores
DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VCC ——10 µA
IIL Input Leakage Current VIN = 0V ——–10 µA
VIH1 TTL High Level Input Voltage 4.5V ≤ VCC ≤ 5.5V 2 —VCC V
VIL1 TTL Low Level Input Voltage 0 —0.8 V
VIH2 CMOS High Level Input Voltage 2.5V ≤ VCC ≤ 6V VCC x 0.7 —VCC + 0.3 V
VIL2 CMOS Low Level Input Voltage -0.3 —VCC x 0.2 V
Logic Inputs
CAT5112
4
Doc. No. 2002, Rev. F
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance -10 Device 10
-50 Device 50 kΩ
-00 Device 100
Pot Resistance Tolerance ±15 %
VRH Voltage on RH pin 0 VCC V
VRL Voltage on RL pin 0 VCC V
Resolution 1 %
INL Integral Linearity Error IW ≤ 2µA 0.5 1 LSB
DNL Differential Linearity Error IW ≤ 2µA 0.25 0.5 LSB
ROUT Buffer Output Resistance .05VCC ≤ VWB≤ .95VCC, VCC=5V 1 Ω
IOUT Buffer Output Current .05VCC ≤ VWB≤ .95VCC, VCC=5V 3 mA
TCRPOT TC of Pot Resistance 300 ppm/˚C
TCRATIO Ratiometric TC TBD ppm/˚C
RISO Isolation Resistance TBD Ω
CRH/CRL/CRW Potentiometer Capacitances 8/8/25 pF
fc Frequency Response Passive Attenuator, 10kΩ 1.7 MHz
VWB(SWING) Output Voltage Range IOUT≤100µA, VCC=5V 0.01VCC .99VCC
Potentiometer Parameters
CAT5112
5Doc. No. 2002, Rev. F
VCC Range 2.5V ≤ VCC ≤ 6V
Input Pulse Levels 0.2VCC to 0.7VCC
Input Rise and Fall Times 10ns
Input Reference Levels 0.5VCC
AC CONDITIONS OF TEST
A. C. TIMING
(1) Typical values are for TA=25˚C and nominal supply voltage.
(2) This parameter is periodically sampled and not 100% tested.
(3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
CS
INC
U/D
RW
t
CI
t
CYC
t
IL
MI(3)
90% 90%
10%
(store)
t
F
t
R
t
IW
tID
tDI
t
IH
t
CPH
t
IC
Symbol Parameter Min Typ(1) Max Units
tCI CS to INC Setup 100 ——ns
tDI U/D to INC Setup 50 ——ns
tID U/D to INC Hold 100 ——ns
tIL INC LOW Period 250 ——ns
tIH INC HIGH Period 250 ——ns
tIC INC Inactive to CS Inactive 1 ——µs
tCPH CS Deselect Time (NO STORE) 100 ——ns
tCPH CS Deselect Time (STORE) 10 ——ms
tIW INC to VOUT Change —15µs
tCYC INC Cycle Time 1 ——µs
tR, tF(2) INC Input Rise and Fall Time ——500 µs
tPU(2) Power-up to Wiper Stable —— 1 msec
tWR Store Cycle —510ms
AC OPERATING CHARACTERISTICS:
VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified
CAT5112
6
Doc. No. 2002, Rev. F
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT5112 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel)
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #: 2002
Revison: F
Issue date: 4/18/02
Type: Final
Prefix Device # Suffix
5112 S
Product Number Package
P: PDIP
S: SOIC
U: TSSOP
CAT
Optional
Company ID
ITE13
Tape & Reel
TE13: 2000/Reel
-10
Resistance
-10: 10kohms
-50: 50kohms
-00: 100kohms
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
5112: Buffered
5114: Unbuffered
R: MSOP
1
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice Doc. No. 2009, Rev. J
CAT5113
100-Tap Digitally Programmable Potentiometer (DPP™)
FEATURES
■100-position linear taper potentiometer
■Non-volatile NVRAM wiper storage
■Low power CMOS technology
■Single supply operation: 2.5V-6.0V
■Increment Up/Down serial interface
■Resistance values: 10kΩ , 50kΩ and 100kΩ
■Available in PDIP, SOIC, TSSOP and MSOP packages
APPLICATIONS
■Automated product calibration
■Remote control adjustments
■Offset, gain and zero control
■Tamper-proof calibrations
■Contrast, brightness and volume controls
■Motor controls and feedback systems
■Programmable analog functions
new system values without effecting the stored
setting. Wiper-control of the CAT5113 is
accomplished with three input control pins, CS, U/D,
and INC. The INC input increments the wiper in the
direction which is determined by the logic state of
the U/D input. The CS input is used to select the
device and also store the wiper position prior to
power down.
The digitally programmable potentiometer can be
used as a three-terminal resistive divider or as a
two-terminal variable resistor. DPPs bring variability and
programmability to a wide variety of applications
including control, parameter adjustments, and
signal processing.
FUNCTIONAL DIAGRAM
DESCRIPTION
The CAT5113 is a single digitally programmable
potentiometer (DPP™) designed as a electronic
replacement for mechanical potentiometers and trim
pots. Ideal for automated adjustments on high volume
production lines, they are also well suited for
applications where equipment requiring periodic
adjustment is either difficult to access or located in a
hazardous or remote environment.
The CAT5113 contains a 100-tap series resistor array
connected between two terminals RH and RL. An up/
down counter and decoder that are controlled by three
input pins, determines which tap is connected to the
wiper, RW. The wiper setting, stored in nonvolatile
memory, is not lost when the device is powered
down and is automatically reinstated when power
is returned. The wiper can be adjusted to test
GENERAL DETAILED ELECTRONIC POTENTIOMETER
IMPLEMENTATION
(INC)
(U/D)
(CS)
Control
and
Memory
INCREMENT
UP/DOWN
DEVICE SELECT
Vcc
(Supply Voltage)
GENERAL
RH
V
W
L
R
R
H
V
V
W
L/
/
/
POR
GND
ONE
OF
ONE HUNDRED
DECODER
31
30
29
28
2
1
0
TRANSFER
GATES RESISTOR
ARRAY
R
H
L
R
H
V
V
L
/
/
V
W
R
W
/
7-BIT
NONVOLATILE
MEMORY
STORE AND
RECALL
CONTROL
CIRCUITRY
U/D
INC
CS
Vcc
V
SS
7-BIT
UP/DOWN
COUNTER
RH
VW
L
R
R
H
V
V
W
L
/
/
/
CAT5113
2
Doc. No. 2009, Rev. J
of the CAT5113 and is active low. When in a high
state, activity on the INC and U/D inputs will not
affect or change the position of the wiper.
DEVICE OPERATION
The CAT5113 operates like a digitally controlled
potentiometer with RH and RL equivalent to the high
and low terminals and RW equivalent to the mechanical
potentiometer's wiper. There are 100 available tap
positions including the resistor end points, RH and RL.
There are 99 resistor elements connected in series
between the RH and RL terminals. The wiper terminal is
connected to one of the 100 taps and controlled by three
inputs, INC, U/D and CS. These inputs control a seven-
bit up/down counter whose output is decoded to select
the wiper position. The selected wiper position can be
stored in nonvolatile memory using the INC and
CS inputs.
With CS set LOW the CAT5113 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC wil increment or decrement the
wiper (depending on the state of the U/D input and
seven-bit counter). The wiper, when at either fixed
terminal, acts like its mechanical equivalent and does
not move beyond the last position. The value of the
counter is stored in nonvolatile memory whenever CS
transitions HIGH while the INC input is also HIGH. When
the CAT5113 is powered-down, the last stored wiper
counter position is maintained in the nonvolatile memory.
When power is restored, the contents of the memory are
recalled and the counter is set to the value stored.
With INC set low, the CAT5113 may be de-selected
and powered down without storing the current wiper
position in nonvolatile memory. This allows the
system to always power up to a preset value stored
in nonvolatile memory.
PIN DESCRIPTIONS
INCINC
INCINC
INC: Increment Control Input
The INC input moves the wiper in the up or down direction
determined by the condition of the U/D input.
U/DD
DD
D: Up/Down Control Input
The U/D input controls the direction of the wiper
movement. When in a high state and CS is low, any high-
to-low transition on INC will cause the wiper to move one
increment toward the RH terminal. When in a low state
and CS is low, any high-to-low transition on INC will
cause the wiper to move one increment towards the
RL terminal.
RH: High End Potentiometer Terminal
RH is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
greater than the RL terminal. Voltage applied to the RH
terminal cannot exceed the supply voltage, VCC or go
below ground, GND.
RW: Wiper Potentiometer Terminal
RW is the wiper terminal of the potentiometer. Its position
on the resistor array is controlled by the control inputs, INC,
U/D and CS. Voltage applied to the RW terminal cannot
exceed the supply voltage, VCC or go below ground, GND.
RL: Low End Potentiometer Terminal
RL is the low end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
less than the RH terminal. Voltage applied to the RL
terminal cannot exceed the supply voltage, VCC or go
below ground, GND. RL and RH are electrically
interchangeable.
CSCS
CSCS
CS: Chip Select
The chip select input is used to activate the control input
PIN FUNCTIONS
Pin Name Function
INC Increment Control
U/DUp/Down Control
RHPotentiometer High Terminal
GND Ground
RWPotentiometer Wiper Terminal
RLPotentiometer Low Terminal
CS Chip Select
VCC Supply Voltage
PIN CONFIGURATION
DIP/SOIC Package TSSOP Package
MSOP Package
CS
INC V
CC
U/D
GND
RHRL
RW
1
2
3
4
8
7
6
5
INC
VCC
CS
U/D
GND
R
W
R
H
R
L
1
2
3
4
8
7
6
5
V
CC
R
R
GND
R
INC
U/DCS
W
L
H
1
2
3
4
8
7
6
5
3Doc. No. 2009, Rev. J
OPERATION MODES
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC to GND ......................................–0.5V to +7V
Inputs
CS to GND .............................–0.5V to VCC +0.5V
INC to GND ............................–0.5V to VCC +0.5V
U/D to GND ............................–0.5V to VCC +0.5V
H to GND ................................–0.5V to VCC +0.5V
L to GND ................................–0.5V to VCC +0.5V
W to GND ...............................–0.5V to VCC +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)...................... – 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Absolute Maximum Ratings
are limited values applied individually while other parameters are
within specified operating conditions, and functional operation at any
of these conditions is NOT implied. Device performance and reliability
may be impaired by exposure to absolute rating conditions for extended
periods of time.
NOTES: (1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V
(3) IW=source or sink
(4) These parameters are periodically sampled and are not 100% tested.
RL
CL
CH
RH
CW
RWB
Rwi
Potentiometer
Equivalent Circuit
INC CS U/D Operation
High to Low Low High Wiper toward H
High to Low Low Low Wiper toward L
High Low to High X Store Wiper Position
Low Low to High X No Store, Return to Standby
X High X Standby
RELIABILITY CHARACTERISTICS
Symbol Parameter Test Method Min Typ Max Units
VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA
TDR Data Retention MIL-STD-883, Test Method 1008 100 Years
NEND Endurance MIL-STD-883, Test Method 1003 1,000,000 Stores
Power Supply
Symbol Parameter Conditions Min Typ Max Units
VCC Operating Voltage Range 2.5 —6.0 V
ICC1 Supply Current (Increment) VCC = 6V, f = 1MHz, IW=0 ——100 µA
VCC = 6V, f = 250kHz, IW=0 ——50
ICC2 Supply Current (Write) Programming, VCC = 6V ——1mA
VCC = 3V ——500 µA
ISB1 (2) Supply Current (Standby) CS=VCC-0.3V ——1µA
U/D, INC=VCC-0.3V or GND
DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VCC ——10 µA
IIL Input Leakage Current VIN = 0V ——–10 µA
VIH1 TTL High Level Input Voltage 4.5V ≤ VCC ≤ 5.5V 2 —VCC V
VIL1 TTL Low Level Input Voltage 0 —0.8 V
VIH2 CMOS High Level Input Voltage 2.5V ≤ VCC ≤ 6V VCC x 0.7 —VCC + 0.3 V
VIL2 CMOS Low Level Input Voltage -0.3 —VCC x 0.2 V
Logic Inputs
CAT5113
4
Doc. No. 2009, Rev. J
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance -10 Device 10
-50 Device 50 kΩ
-00 Device 100
Pot Resistance Tolerance ±15 %
VRH Voltage on RH pin 0 VCC V
VRL Voltage on RL pin 0 VCC V
Resolution 1% %
INL Integral Linearity Error IW ≤ 2µA 0.5 1 LSB
DNL Differential Linearity Error IW ≤ 2µA 0.25 0.5 LSB
RWi Wiper Resistance VCC = 5V, IW = 1mA 400 Ω
VCC = 2.5V, IW = 1mA 1 kΩ
IWWiper Current 1 mA
TCRPOT TC of Pot Resistance 300 ppm/oC
TCRATIO Ratiometric TC 20 ppm/oC
RISO Isolation Resistance TBD Ω
VNNoise 100kHz / 1kHz 8/24 nV/ Hz
CH/CL/CWPotentiometer Capacitances 8/8/25 pF
fc Frequency Response Passive Attenuator, 10kΩ 1.7 MHz
Potentiometer Parameters
5Doc. No. 2009, Rev. J
VCC Range 2.5V ≤ VCC ≤ 6V
Input Pulse Levels 0.2VCC to 0.7VCC
Input Rise and Fall Times 10ns
Input Reference Levels 0.5VCC
AC CONDITIONS OF TEST
A. C. TIMING
(1) Typical values are for TA=25˚C and nominal supply voltage.
(2) This parameter is periodically sampled and not 100% tested.
(3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
CS
INC
U/D
RW
tCI
tCYC
tIL
MI(3)
90% 90%
10%
(store)
tFtR
tIW
tID
tDI
tIH tCPH
tIC
Symbol Parameter Min Typ(1) Max Units
tCI CS to INC Setup 100 ——ns
tDI U/D to INC Setup 50 ——ns
tID U/D to INC Hold 100 ——ns
tIL INC LOW Period 250 ——ns
tIH INC HIGH Period 250 ——ns
tIC INC Inactive to CS Inactive 1 ——µs
tCPH CS Deselect Time (NO STORE) 100 ——ns
tCPH CS Deselect Time (STORE) 10 ——ms
tIW INC to VOUT Change —15µs
tCYC INC Cycle Time 1 ——µs
tR, tF(2) INC Input Rise and Fall Time —— 500 µs
tPU(2) Power-up to Wiper Stable —— 1 msec
tWR Store Cycle —510ms
AC OPERATING CHARACTERISTICS:
VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified
CAT5113
6
Doc. No. 2009, Rev. J
Potentiometer Configurations
(a) resistive divider (b) variable resistance (c) two-port
+
–
+
–
+
–
V1
(-)
V2
(+)
R1R2
R2
R3
R3R4
VO
A3
R4+2.5V
+5V
10
1
A1
A2
2
3
4
5
6
7
8
9
11
+5V
U/
DPP
CAT5114/5113
{
{
555
+5V
.01 F
8
3
5
4
6
21
}
}
57
RA
RB
R1
R2
+5V
8
4
2
1
7
pRPOT
(1-p)RPOT
U/
C
.01 F,
.003 F
3
6
Applications
Programmable Instrumentation Amplifier Programmable Sq. Wave Oscillator (555)
+
–
+
–
+
–
Sensor
VCORR
1.00V = VREF
CAT5112/5111
IC2
U/D
INC
CS
10k
0.01 F
OSC
CS
IC3A
1/4 74HC132
+5V +200mV
499k 499k
499k
1V + 50mV
VSENSR
+5V
4
11 1
2
3
-5V
VOUT = 1V + 1mV
ICIA
100mV = VSHIFT
499k
20k ICIB
6
5
7
APPLICATIONS INFORMATION
Sensor Auto Referencing Circuit
7Doc. No. 2009, Rev. J
+
–
+5V
VO
+2.5V
1F
C1
.001
A1
C2
4
7
2
3
R2
10k
CAT5114/5113
R3
100k
R1
50k
.001 6
VS
+5V
+
–
+
–
+
–
+5V
CHI
CLO
IC3
CAT5114/5113
+5V
U/D
INC
CS
2
1
6
5
3
VS+2.5V
0 < VS < 2.5V
OSC
IC2
74HC132
+5V
IC1
393
2
3
VLL R1
R2R3
VUL
2.5V < VO < 5V
VO
AI
IC4
6
5
+5V
1
7
10k 0.1 F
10k
8
4
7
Control
and
Memory
POR
CAT5114/5113
4
6
5
3
R3
10k
R2
820
11k
R1 6.8 F
V0 (REG)
GND
SD
VIN (UNREG)
SHUTDOWN
1F
+5V
8
2
1
7
2952
FB 1.23V
VOUT
100k
U/
.1
Programmable Voltage Regulator
APPLICATIONS INFORMATION
+
–
+
–
2
1
7
8
4
+5V
+5V +5V
}
}
pR (1-p)R
22 7
7
4
4
33
+2.5V
A1
66
A2
1M330330
IS
U/
10k
6
53
CAT5114/5113
VO
LT1097
Programmable I to V convertor
+
–
+
–
+
–
Serial
Bus
+5V +5V
CAT5112/5111
+2.5V
R1
100k
R1
100k
R1
100k
VS
A2
75
6
+5V
41
11
+2.5V
IS
R
2.5k
R1
100k
2
3
A1=A2=1/4 LMC6064A
Programmable Bandpass Filter Programmable Current Source/Sink
Automatic Gain Control
CAT5113
8
Doc. No. 2009, Rev. J
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT5113 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel)
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 2009
Revison: J
Issue date: 04/18/02
Type: Final
Prefix Device # Suffix
5113 S
Product Number Package
P: PDIP
S: SOIC
U: TSSOP
CAT
Optional
Company ID
ITE13
Tape & Reel
TE13: 2000/Reel
-10
Resistance
-10: 10kohms
-50: 50kohms
-00: 100kohms
5111: Buffered
5113: Unbuffered
R: MSOP
1
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice Doc. No. 2007, Rev. E
CAT5114
32-Tap Digitally Programmable Potentiometer (DPP™)
FEATURES
■32-position linear taper potentiometer
■Non-volatile NVRAM wiper storage
■Low power CMOS technology
■Single supply operation: 2.5V-6.0V
■Increment Up/Down serial interface
■Resistance values: 10kΩ, 50kΩ and 100kΩ
■Available in PDIP, SOIC, TSSOP and MSOP packages
APPLICATIONS
■Automated product calibration
■Remote control adjustments
■Offset, gain and zero control
■Tamper-proof calibrations
■Contrast, brightness and volume controls
■Motor controls and feedback systems
■Programmable analog functions
new system values without effecting the stored
setting. Wiper-control of the CAT5114 is
accomplished with three input control pins, CS, U/D,
and INC. The INC input increments the wiper in the
direction which is determined by the logic state of
the U/D input. The CS input is used to select the
device and also store the wiper position prior to
power down.
The digitally programmable potentiometer can be
used as a three-terminal resistive divider or as a
two-terminal variable resistor. DPPs bring variability and
programmability to a wide variety of applications
including control, parameter adjustments, and
signal processing.
FUNCTIONAL DIAGRAM
DESCRIPTION
The CAT5114 is a single digitally programmable
potentiometer (DPP™) designed as a electronic
replacement for mechanical potentiometers and trim
pots. Ideal for automated adjustments on high volume
production lines, they are also well suited for
applications where equipment requiring periodic
adjustment is either difficult to access or located in a
hazardous or remote environment.
The CAT5114 contains a 32-tap series resistor array
connected between two terminals RH and RL. An up/
down counter and decoder that are controlled by three
input pins, determines which tap is connected to the
wiper, RW. The wiper setting, stored in nonvolatile
memory, is not lost when the device is powered
down and is automatically reinstated when power
is returned. The wiper can be adjusted to test
GENERAL DETAILED ELECTRONIC POTENTIOMETER
IMPLEMENTATION
R
H
V
W
L
R
R
H
V
V
W
L
/
/
/
ONE
OF
THIRTY TWO
DECODER
31
30
29
28
2
1
0
TRANSFER
GATES RESISTOR
ARRAY
R
H
L
R
H
V
V
L
/
/
V
W
R
W
/
5-BIT
NONVOLATILE
MEMORY
STORE AND
RECALL
CONTROL
CIRCUITRY
U/D
INC
CS
Vcc
V
SS
5-BIT
UP/DOWN
COUNTER
(INC)
(U/D)
(CS)
Control
and
Memory
INCREMENT
UP/DOWN
DEVICE SELECT
Vcc (Supply Voltage)
GENERAL
RH
V
W
L
R
R
H
V
V
W
L/
/
/
POR
GND
CAT5114
2
Doc. No. 2007, Rev. E
of the CAT5114 and is active low. When in a high
state, activity on the INC and U/D inputs will not
affect or change the position of the wiper.
DEVICE OPERATION
The CAT5114 operates like a digitally controlled
potentiometer with RH and RL equivalent to the high
and low terminals and RW equivalent to the mechanical
potentiometer's wiper. There are 32 available tap posi-
tions including the resistor end points, RH and RL. There
are 31 resistor elements connected in series between
the RH and RL terminals. The wiper terminal is
connected to one of the 32 taps and controlled by three
inputs, INC, U/D and CS. These inputs control a five-bit
up/down counter whose output is decoded to select the
wiper position. The selected wiper position can be
stored in nonvolatile memory using the INC and
CS inputs.
With CS set LOW the CAT5114 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC wil increment or decrement the
wiper (depending on the state of the U/D input and five-
bit counter). The wiper, when at either fixed terminal,
acts like its mechanical equivalent and does not move
beyond the last position. The value of the counter is
stored in nonvolatile memory whenever CS transitions
HIGH while the INC input is also HIGH. When the
CAT5114 is powered-down, the last stored wiper counter
position is maintained in the nonvolatile memory. When
power is restored, the contents of the memory are
recalled and the counter is set to the value stored.
With INC set low, the CAT5114 may be de-selected
and powered down without storing the current wiper
position in nonvolatile memory. This allows the
system to always power up to a preset value stored
in nonvolatile memory.
PIN DESCRIPTIONS
INCINC
INCINC
INC: Increment Control Input
The INC input moves the wiper in the up or down direction
determined by the condition of the U/D input.
U/DD
DD
D: Up/Down Control Input
The U/D input controls the direction of the wiper
movement. When in a high state and CS is low, any high-
to-low transition on INC will cause the wiper to move one
increment toward the RH terminal. When in a low state
and CS is low, any high-to-low transition on INC will
cause the wiper to move one increment towards the
RL terminal.
RH: High End Potentiometer Terminal
RH is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
greater than the RL terminal. Voltage applied to the RH
terminal cannot exceed the supply voltage, VCC or go
below ground, GND.
RW: Wiper Potentiometer Terminal
RW is the wiper terminal of the potentiometer. Its position
on the resistor array is controlled by the control inputs, INC,
U/D and CS. Voltage applied to the RW terminal cannot
exceed the supply voltage, VCC or go below ground, GND.
RL: Low End Potentiometer Terminal
RL is the low end terminal of the potentiometer. It is not
required that this terminal be connected to a potential
less than the RH terminal. Voltage applied to the RL
terminal cannot exceed the supply voltage, VCC or go
below ground, GND. RL and RH are electrically
interchangeable.
CSCS
CSCS
CS: Chip Select
The chip select input is used to activate the control input
PIN FUNCTIONS
Pin Name Function
INC Increment Control
U/DUp/Down Control
RHPotentiometer High Terminal
GND Ground
RWPotentiometer Wiper Terminal
RLPotentiometer Low Terminal
CS Chip Select
VCC Supply Voltage
PIN CONFIGURATION
DIP/SOIC Package TSSOP Package
MSOP Package
CS
INC V
CC
U/D
GND
RHRL
RW
1
2
3
4
8
7
6
5
INC
VCC
CS
U/D
GND
R
W
R
H
R
L
1
2
3
4
8
7
6
5
V
CC
R
R
GND
R
INC
U/DCS
W
L
H
1
2
3
4
8
7
6
5
CAT5114
3Doc. No. 2007, Rev. E
RELIABILITY CHARACTERISTICS
Symbol Parameter Test Method Min Typ Max Units
VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA
TDR Data Retention MIL-STD-883, Test Method 1008 100 Years
NEND Endurance MIL-STD-883, Test Method 1003 1,000,000 Stores
Power Supply
Symbol Parameter Conditions Min Typ Max Units
VCC Operating Voltage Range 2.5 —6.0 V
ICC1 Supply Current (Increment) VCC = 6V, f = 1MHz, IW=0 ——100 µA
VCC = 6V, f = 250kHz, IW=0 ——50
ICC2 Supply Current (Write) Programming, VCC = 6V ——1mA
VCC = 3V ——500 µA
ISB1 (2) Supply Current (Standby) CS=VCC-0.3V ——1µA
U/D, INC=VCC-0.3V or GND
OPERATION MODES
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC to GND ......................................–0.5V to +7V
Inputs
CS to GND .............................–0.5V to VCC +0.5V
INC to GND ............................–0.5V to VCC +0.5V
U/D to GND ............................–0.5V to VCC +0.5V
H to GND ................................–0.5V to VCC +0.5V
L to GND ................................–0.5V to VCC +0.5V
W to GND ...............................–0.5V to VCC +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)...................... – 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Absolute Maximum Ratings
are limited values applied individually while other parameters are
within specified operating conditions, and functional operation at any
of these conditions is NOT implied. Device performance and reliability
may be impaired by exposure to absolute rating conditions for extended
periods of time.
NOTES: (1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V
(3) IW=source or sink
(4) These parameters are periodically sampled and are not 100% tested.
R
L
C
L
C
H
R
H
C
W
R
W
R
wi
Potentiometer
Equivalent Circuit
DC Electrical Characteristics: VCC = +2.5V to +6.0V unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VCC ——10 µA
IIL Input Leakage Current VIN = 0V ——–10 µA
VIH1 TTL High Level Input Voltage 4.5V ≤ VCC ≤ 5.5V 2 —VCC V
VIL1 TTL Low Level Input Voltage 0 —0.8 V
VIH2 CMOS High Level Input Voltage 2.5V ≤ VCC ≤ 6V VCC x 0.7 —VCC + 0.3 V
VIL2 CMOS Low Level Input Voltage -0.3 —VCC x 0.2 V
Logic Inputs
INC CS U/D Operation
High to Low Low High Wiper toward H
High to Low Low Low Wiper toward L
High Low to High X Store Wiper Position
Low Low to High X No Store, Return to Standby
X High X Standby
CAT5114
4
Doc. No. 2007, Rev. E
Symbol Parameter Conditions Min Typ Max Units
RPOT Potentiometer Resistance -10 Device 10
-50 Device 50 kΩ
-00 Device 100
Pot Resistance Tolerance ±15 %
VRH Voltage on RH pin 0 VCC V
VRL Voltage on RL pin 0 VCC V
Resolution 3.2 %
INL Integral Linearity Error IW ≤ 2µA 0.5 1 LSB
DNL Differential Linearity Error IW ≤ 2µA 0.25 0.5 LSB
RWi Wiper Resistance VCC = 5V, IW = 1mA 400 Ω
VCC = 2.5V, IW = 1mA 1 kΩ
IWWiper Current 1 mA
TCRPOT TC of Pot Resistance 300 ppm/oC
TCRATIO Ratiometric TC 20 ppm/oC
RISO Isolation Resistance TBD Ω
VNNoise 100kHz / 1kHz 8/24 nV/√Hz
CH/CL/CWPotentiometer Capacitances 8/8/25 pF
fc Frequency Response Passive Attenuator, 10kΩ 1.7 MHz
Potentiometer Parameters
CAT5114
5Doc. No. 2007, Rev. E
VCC Range 2.5V ≤ VCC ≤ 6V
Input Pulse Levels 0.2VCC to 0.7VCC
Input Rise and Fall Times 10ns
Input Reference Levels 0.5VCC
AC CONDITIONS OF TEST
A. C. TIMING
(1) Typical values are for TA=25oC and nominal supply voltage.
(2) This parameter is periodically sampled and not 100% tested.
(3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
CS
INC
U/D
RW
t
CI
t
CYC
t
IL
MI(3)
90% 90%
10%
(store)
t
F
t
R
t
IW
tID
tDI
t
IH
t
CPH
t
IC
Symbol Parameter Min Typ(1) Max Units
tCI CS to INC Setup 100 ——ns
tDI U/D to INC Setup 50 ——ns
tID U/D to INC Hold 100 ——ns
tIL INC LOW Period 250 ——ns
tIH INC HIGH Period 250 ——ns
tIC INC Inactive to CS Inactive 1 ——µs
tCPH CS Deselect Time (NO STORE) 100 ——ns
tCPH CS Deselect Time (STORE) 10 ——ms
tIW INC to VOUT Change —15µs
tCYC INC Cycle Time 1 ——µs
tR, tF(2) INC Input Rise and Fall Time ——500 µs
tPU(2) Power-up to Wiper Stable ——1 msec
tWR Store Cycle —510ms
AC OPERATING CHARACTERISTICS:
VCC = +2.5V to +6.0V, VH = VCC, VL = 0V, unless otherwise specified
CAT5114
6
Doc. No. 2007, Rev. E
Potentiometer Configurations
(a) resistive divider (b) variable resistance (c) two-port
+
–
+
–
+
–
V1
(-)
V2
(+)
R1R2
R2
R3
R3R4
VO
A3
R4+2.5V
+5V
10
1
A1
A2
2
3
4
5
6
7
8
9
11
+5V
U/
DPP
CAT5114/5113
{
{
555
+5V
.01 F
8
3
5
4
6
21
}
}
57
RA
RB
R1
R2
+5V
8
4
2
1
7
pRPOT
(1-p)RPOT
U/
C
.01 F,
.003 F
3
6
Applications
Programmable Instrumentation Amplifier Programmable Sq. Wave Oscillator (555)
+
–
+
–
+
–
Sensor
VCORR
1.00V = VREF
CAT5112/5111
IC2
U/D
INC
CS
10k
0.01 F
OSC
CS
IC3A
1/4 74HC132
+5V +200mV
499k 499k
499k
1V + 50mV
VSENSR
+5V
4
11 1
2
3
-5V
VOUT = 1V + 1mV
ICIA
100mV = VSHIFT
499k
20k ICIB
6
5
7
APPLICATIONS INFORMATION
Sensor Auto Referencing Circuit
CAT5114
7Doc. No. 2007, Rev. E
+
–
+5V
VO
+2.5V
1F
C1
.001
A1
C2
4
7
2
3
R2
10k
CAT5114/5113
R3
100k
R1
50k
.001 6
VS
+5V
+
–
+
–
+
–
+5V
CHI
CLO
IC3
CAT5114/5113
+5V
U/D
INC
CS
2
1
6
5
3
VS+2.5V
0 < VS < 2.5V
OSC
IC2
74HC132
+5V
IC1
393
2
3
VLL R1
R2R3
VUL
2.5V < VO < 5V
VO
AI
IC4
6
5
+5V
1
7
10k 0.1 F
10k
8
4
7
Control
and
Memory
POR
CAT5114/5113
4
6
5
3
R3
10k
R2
820
11k
R1 6.8 F
V0 (REG)
GND
SD
VIN (UNREG)
SHUTDOWN
1F
+5V
8
2
1
7
2952
FB 1.23V
VOUT
100k
U/
.1
Programmable Voltage Regulator
APPLICATIONS INFORMATION
+
–
+
–
2
1
7
8
4
+5V
+5V +5V
}
}
pR (1-p)R
22 7
7
4
4
33
+2.5V
A1
66
A2
1M330330
IS
U/
10k
6
53
CAT5114/5113
VO
LT1097
Programmable I to V convertor
+
–
+
–
+
–
Serial
Bus
+5V +5V
CAT5112/5111
+2.5V
R1
100k
R1
100k
R1
100k
VS
A2
75
6
+5V
41
11
+2.5V
IS
R
2.5k
R1
100k
2
3
A1=A2=1/4 LMC6064A
Programmable Bandpass Filter Programmable Current Source/Sink
Automatic Gain Control
CAT5114
8
Doc. No. 2007, Rev. E
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT5114 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel)
Prefix Device # Suffix
5112 S
Product Number Package
P: PDIP
S: SOIC
U: TSSOP
CAT
Optional
Company ID
ITE13
Tape & Reel
TE13: 2000/Reel
-10
Resistance
-10: 10kohms
-50: 50kohms
-00: 100kohms
5112: Buffered
5114: Unbuffered
R: MSOP
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
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Phone: 408.542.1000
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Publication #: 2007
Revison: E
Issue date: 4/18/02
Type: Final
