DTC114TE
NPN Digital Transistor
Features
• Built-in bias resistors enable the configuration of an inverter circuit
without connecting external input resistors (see equivalent circuit)
• The bias resistors consist of thin-film resistors with complete
isolation to allow negative biasing of the input. They also have the
advantage of almost completely eliminating parasitic effects
• Only the on/off conditions need to be set for operation, making
device design easy
Absolute Maximum Ratings
Parameter Symbol Value Unit
Collector-Base Voltage VCBO 50 V
Collector-Emitter Voltage VCEO 50 V
Emitter-Base voltage VEBO 5 V
Collector Current-Continuous IC 100 mA
Collector Dissipation PC 150 mW
Junction Temperature TJ 150 ℃
Storage Temperature Range TSTG -55~150 ℃
Electrical Characteristics
Sym Parameter Min Typ Max Unit
V(BR)CBO Collector-Base Breakdown Voltage
(IC=50uA, IE=0) 50 --- --- V
V(BR)CEO Collector-Emitter Breakdown Voltage
(IC=1mA, IB=0) 50 --- --- V
V(BR)EBO Emitter-Base Breakdown Voltage
(IE=50uA, IC=0) 5 --- --- V
ICBO Collector Cut-off Current
(VCB=50V, IE=0) --- --- 0.5 uA
IEBO Emitter Cut-off Current
(VEB=4V, IC=0)
hFE DC Current Gain
(VCE=5V, IC=1mA) 100 300 600 ---
VCE(sat) Collector-Emitter Saturation Voltage
(IC=10mA, IB=1mA) --- --- 0.3 V
R1 Input Resistor 7 10 13 KΩ
fT Transition Frequency
(VCE=10V, IC=-5mA, f=100MHz) --- 250 --- MHz
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MCC
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Revision: 1 2005/06/29
--- --- 0.5 uA
SOT-523
INCHES MM
DIM MIN MAX MIN MAX NOTE
A .059 .067 1.50 1.70
B .030 .033 0.75 0.85
C .057 .069 1.45 1.75
D .020 Nominal 0.50Nominal
E .035 .043 0.90 1.10
G .000 .004 .000 .100
H .028 .031 .70 0.80
J .004 .008 .100 .200
K .010 .014 .25 .35
A
C
B
D
E
G
H
J
DIMENSIONS
K
3
1
2
1. Base
2. Emitter
3. Collector
www.mccsemi.com
Revision: 1 2005/06/29
DTC114TEMCC