A3942KLGTR-T - Allegro Microsystems

Description

The A3942 is a highly-integrated gate driver IC that can drive

up to four N-Channel MOSFETs in a high-side configuration.

The device is designed to withstand the harsh environmental

conditions and high reliability standards of automotive

applications.

Serial Peripheral Interface (SPI) compatibility makes the device

easily integrated into existing applications. The MOSFETs in

such applications are typically used to drive gasoline or diesel

engine management actuators, transmission actuators, body

control actuators and other general-purpose automotive or

industrial loads. In particular, the A3942 is suited for driving

glow plugs, valves, solenoids, and other inductive loads in

engine management and transmission systems.

The device is available in a 38-lead thin (1.20 mm maximum

overall height) TSSOP package with six pins that are fused

internally to provide enhanced thermal dissipation (package

LG). It is lead (Pb) free with 100% matte tin leadframe

plating.

3942-DS, Rev. 5

Features and Benefits

▪ Drives four N-channel high-side MOSFETS

▪ Charge pump for 100% duty cycle operation

▪ Serial and discrete inputs

▪ SPI port for control and fault diagnostics

▪ 4.5 to 60 V input voltage range

▪ Sleep function for minimum power drain

▪ Thin profile 38-lead TSSOP with internally fused leads for

enhanced thermal dissipation

▪ Lead (Pb) free

▪ Device protection features:

▫ Short-to-ground detection (latched)

▫ Short-to-battery protection (latched)

▫ Open load detection (latched)

▫ VDD undervoltage lockout

▫ VCP undervoltage lockout

▫ Thermal monitor

Quad High-Side Gate Driver

for Automotive Applications

Package: 38 pin TSSOP (suffix LG)

Typical Application

A3942

Approximate Scale 1:1

FAULTZ

BAT

A3942

SDO

System

Control

Logic

SDI

CSZ

SCLK

RESETZ

ENB

IN1

IN2

IN3

IN4

GND GND GND GND GND GND

CP1 CP2 CP3 CP4

IREF

VREG

VBB

VDD

VCP

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings*

Characteristic Symbol Notes Rating Units

VBB, CP1, CP3 Pins Voltage –0.3 to 60 V

Dx (Drain Detect) Pins Voltage VDx

VBB – 6 V

to VBB + 0.5 V V

Sx (Output Source) Pins Voltage VSx –10 to 60 V

VCP, CP2, CP4, Gx Pins Voltage –0.3 to 74 V

All Other Pins –0.3 to 7 V

Operating Ambient Temperature TARange K –40 to 125 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

ESD Rating, Human Body Model AEC-Q100-002, all pins 2500 V

ESD Rating, Charged Device Model AEC-Q100-011, all pins 1050 V

*With respect to ground. Exceeding maximum ratings may cause permanent damage. Correct operation is not guaranteed when absolute

maximum conditions are applied.

Selection Guide

Part Number Packing

A3942KLGTR-T 4000 pieces per reel

Thermal Characteristics

Characteristic Symbol Test Conditions* Rating Units

Package Thermal Resistance, Junction

to Ambient RθJA

4-layer PCB based on JEDEC standard, with no

thermal vias 47 ºC/W

*For additional information, refer to the Allegro website.

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

CBB2

IN4

IN3

IN2

IN1

RESETZ

ENB

CSZ

SCLK

SDI

SDO

Control

Logic

Fault

Monitor

FAULTZ

VCP

CP4

CP3

CP2

CP1

Charge

Pump

UVLO

High

Side

Driver

CCP

VBB

GND

One of Four

High-Side Drivers

Open

Load

Detect

Monitor

Reference

Current

VDD

RDx

UVLO

CREG

VREG

Internal

Regulator

Thermal

Warning

IREF

CBB1

CDD

C12

C34

Voltage to VBB pin

and to Qx MOSFETs

must come from

the same supply

CREF

60.4 kΩ

GND GND GND GND GND

RGx

Functional Block Diagram

Name Suitable Characteristics Representative Device

C12, C34 0.33 μF or 0.47 μF, 25 V, X7R ceramic

CBB1 47 μF, 63 V, electrolytic EGXE630ELL470MJC5S

CBB2 0.22 μF, 100 V, X7R ceramic

CCP 1 μF, 16V, X7R ceramic

CDD 0.47 μF, 16 V, X7R ceramic

CREF 47 pF, 16 V, X7R ceramic

CREG 0.22 μF, 16 V, X7R ceramic

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Supplies and Regulators

Operating Voltage VBB 4.5 – 60 V

Quiescent Current IBB(Q)

Charge pump on,

outputs disabled

VBB = 60 V – – 10 mA

VBB = 36 V – – 8 mA

Sleep mode VBB = 36 V – – 15 μA

VBB = 36 V, TJ = 25°C – – 1 μA

Logic Supply (voltage supplied to

logic circuits) VDD 3 – 5.5 V

Logic Supply Current IDD

VDD = 5.5 V, serial port switching – – 3 mA

VDD = 5.5 V, device quiescent or in sleep mode – – 0.5 mA

Logic Supply UVLO Threshold VDD(UV)

VDD falling, FAULTZ pin held active (low) for

1.5 V ≤ VDD ≤ VDDUV

2.6 – 2.9 V

Logic Supply UVLO Hysteresis VDD(hys) 100 150 200 mV

Charge Pump Switching Frequency fCP – 100 – kHz

Charge Pump Output Voltage VCP

Measured relative to

VBB pin

VBB = 12 V, ICP = 10 mA 10 – 13 V

VBB = 6.0 V, ICP = 5 mA 10 – 13 V

VBB = 4.5 V, ICP = 5 mA 7 – 11 V

Charge Pump UVLO VCP(UV) Relative to VBB pin, VCP falling 5.1 – 5.8 V

Internal Regulator Voltage VREG CREG = 0.22 μF –4–V

Regulator Voltage UVLO VREG(UV) VREG falling 3 – 3.8 V

Regulator Voltage UVLO Hysteresis VREG(hys) 100 – 400 mV

Control Circuits

Current Reference Source Voltage VREF 1.14 1.2 1.26 V

Master Reset Pulse tRESET RESETZ pin pulsed low 0.3 – 5 μs

Sleep Command tSLEEP RESETZ pin held low 20 – – μs

Wake-Up Delay tWAKE RESETZ pin held high; CCP = 1 μF ––2ms

Logic I/O

Logic Input Voltage, High VIH

0.7 ×

VDD

–V

DD V

Logic Input Voltage, Low VIL 0–

0.3 ×

VDD

ELECTRICAL CHARACTERISTICS Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF, RREF = 60.4 kΩ, and

VBB within limits, unless otherwise noted

Continued on the next page...

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Logic Input Hysteresis Vhys

0.1 ×

VDD

––V

Logic Input Current1

II(HI)

CSZ pin

VI = VDD = 5.5 V

––10μA

SDI and SCLK Pins – – 5 μA

All other pins – – 100 μA

II(LO)

CSZ pin

VI = 0 V

– – –100 μA

SDI and SCLK Pins – – –5 μA

All other pins – – –10 μA

Logic Output Voltage, SDO Pin

(CMOS push-pull circuit)

VOUT(HI) IOUT = –1 mA VDD

– 0.5 –V

DD V

VOUT(LO) IOUT = 1 mA – – 0.4 V

FAULTZ Pin Active (Low) Voltage VFAULTZ(LO) IFAULTZ = 1 mA, VDD = 1.5 V, VBB = 4.5 V – – 0.4 V

FAULTZ Pin Inactive (High) Current IFAULTZ(HI) VFAULTZ = 5 V – – 10 μA

Drivers

Gate Voltage, High VG(HI)

Measured relative to Sx pin, capacitive load–fully

charged

VCP

– 1 –V

CP V

Gate Voltage, Low VG(LO)

Measured relative to Sx pin, capacitive load–fully

discharged – – 0.1 V

Peak Gate Current1,2

IG(HI)

RG = 0 Ω, 1 V ≤ VGS ≤

4 V, VSx = VBB

VBB = 4.5 V, VCP = 9 V –10 – – mA

VBB ≥ 9 V, VCP = 13 V –15 – – mA

IG(LO)

RG = 0 Ω, VGS = 1 V, VSx = 0 V 10 – – mA

RG = 0 Ω, 2 V ≤ VGS ≤ 4 V, VSx = 0 V 25 – – mA

Propagation Delay tp(on) From 90% VINx to VGx – VSx = 200 mV – 0.6 – μs

tp(off) From 10% VINx to VCP – VGx = 200 mV – 0.6 – μs

Gate-to-Source Resistance RGS RESETZ pin held low; VGSZ = 10 V 300 500 800 kΩ

Gate-to-Source Zener Diode Voltage VGS(Z) IG = 2 mA 15 – 18 V

Drain Leakage Current IDlkg

RESETZ pin held low, VBB = VDx = 60 V – – 10 μA

RESETZ pin held low,

VBB = VDx = 36 V

TJ = 150°C – – 5 μA

TJ = 25°C – – 1 μA

ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF,

RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted

Continued on the next page...

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Driver Fault Detection

Drain Fault Detect Current IDx

VBB = 60 V 75 100 125 μA

VBB = 36 V 85 100 120 μA

Drain Fault Detect Voltage3VDx

VBB ≥ 9 V VBB

– 3 –VBB

+ 0.2 V

VBB = 6 V 5 – VBB

+ 0.2 V

VBB = 4.5 V 4 – VBB

+ 0.2 V

Open Load Detect Source Current1IOL VSx = 1.35 V; 4.5 V ≤ VBB ≤ 36 V –48 – –82 μA

Open Load Detect Voltage VOL 1.4 1.5 1.6 V

Open Load VSx Clamp VCLAMP

Active (when an open load fault is active),

VBB ≤ 36 V ––5V

ICLAMP Current limit in short-to-battery; VSx =VBB = 36 V – – 200 μA

Turn-On Blank Time

tON(00)

tON(00) is the default, TJ = 150°C

2.5 – 3.4 μs

tON(01) 3.7 – 5.9 μs

tON(10) 5.6 – 11.2 μs

tON(11) 8.9 – 22.3 μs

Turn-Off Blank Time tOFF –t

ON –μs

Short-to-Ground Fault Detect Filter

Delay tSTG From VSx < VDx to 90% VFAULTZ – 1 1.2 μs

STB Comparator Offset Voltage VOS(STB) – – 60 mV

STG Comparator Offset Voltage VOS(STG) – – 45 mV

Temperature Monitor

Thermal Warning Threshold4TWARN Temperature rising 155 165 175 °C

Thermal Warning Hysteresis TWARN(hys) –15–°C

1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.

2For IG(HI)

, VCP relative to VBB.

3Minimum values of VDx are specified only to avoid short-to-battery nuisance faults. For more information, refer to the Open Load Fault Level topic in

the Applications Information section.

4Minimum and maximum not tested; guaranteed by design.

ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF,

RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Transfer Frequency f – – 8 MHz

Setup Lead Time tlead 375 – – ns

Setup Lag Time tlag 50 – – ns

Setup Time Before Read tsu 15 – – ns

Access Time Before Write taCSDO = 100 pF – – 340 ns

Chip Selection Inactive Time tCSZN 2––μs

Delay Before Output Disabled tdis CSDO = 0 pF – – 100 ns

Serial Clock Period TSCLK 125 – – ns

Serial Clock Pulse Width, High tw(HI) 50 – – ns

Serial Clock Pulse Width, Low tw(LO) 50 – – ns

Serial Clock Hold Time th(SCLK) 300 – – ns

Serial Data In Hold Time th(SDI) 20 – – ns

Serial Data Out Hold Time th(SDO) CSDO = 0 pF 0 – – ns

Serial Data Out Time Before Valid

State tvs

CSDO = 100 pF, VDD = 3 V – – 120 ns

CSDO = 100 pF, VDD = 4.75 V – – 80 ns

SERIAL PERIPHERAL INTERFACE (SPI) TIMING CHARACTERISTICS Valid at –40°C ≤ TJ ≤ 150°C and VBB and VDD within

limits, unless otherwise noted

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VBB

8 V

Open

Load

Delay

Gx Off

Gx On Gx

Off

Gx Off

Logic

FAULTZ

System and

Load Faults

Sport OSC

Serial

Port

Mask

Clear

Read

VBB

Short to

Ground

Short to

Battery

Write

Vclamp

SCLK

CSZ

SDI

SDO

lead

HI-Z

D7 D6

w(HI)

w(LO)

SCLK

h(SDI)

h(SCLK)

lag

dis

CSZN

D0 DON’T

CARE

h(SDO)

Serial Peripheral Interface (SPI) Timing Diagram

Fault System Block Diagram

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

INx

Gate begins

to charge

Timer is running for

turn-on blank time

Set blank time to expire

after V

nears V

GSx

Timer is running for

turn-off blank time

p(off)

p(on)

= V

Set blank time to expire

after V

nears 0 V

Input SettingsTiming Chart

Fault Logic Table

Circled data cells indicate default settings, X indicates “don’t care”, Z indicates high impedance state

Causes Effects

Mode of Operation

RESETZ

ENB

VDD UVLO

VCP UVLO

Channel-Specific

Thermal Warning

FAULTZ

VCP

VREG

Open Load

Short-to-Battery

Short-to-Ground

Off-State Faults Masked

1000000X01011Gates actively pulled low

1100000X01INx11Normal operation

1100000X10INx11FAULTZ issued but A3942 fully operational

1100XX0101INx11Normal operation, OL and STB masked

1X00001XX0011STG cannot be masked

1X000100X0011STB

1X001000X0011OL

1 X 0 1 X X X X X 0 0 UV 1 VCP UVLO disables outputs only

1 X 1 0 X X X X X 0 0 1 1 VDD UVLO disables outputs only

0XXXXXXXX0Z0 0Sleep mode

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Serial Port Bit Definition All bits active high, except WriteZ

D7 D6 D5 D4 D3 D2 D1 D0

Input Address MSB Address LSB Input Read

Enable

Mask

Off-State Faults (*) Clear Faults STG Blank

Time MSB

STG Blank

Time LSB

Gate

On/Off

Output Fault Address MSB Address LSB WriteZ Charge Pump

UVLO

Thermal

Warning

Open Load

Fault (*) STB Fault (*) STG Fault

Serial Port Registers Description

There are two 8-bit registers served by the serial port,

the Input register and the Output Fault register. The

structure of the registers is shown in the table at the

bottom of this page. The function of each bit in the

registers is described in this section.

Input Register

D0 Gate On/Off Bit This bit is used to control the gate

drive output. It is logically ORed with the signal on

the discrete input pin, INx, corresponding to each of

the four channels, according to the following table:

ORed Settings Result on

Gx Pin

Bit D0 Pin INx

0 0 Off

01On

10On

11On

D1, D2 Short-to-Ground (STG) Turn-On Blank Time

MSB and LSB Bits The blank time, ton(xx), delay

allows switching transients to settle before the A3942

STG function checks for a short. For each individual

channel, the combination of these bits sets the wait

time for the VDS monitor, according to the following

table:

D2 D1 tON Selected

00 t

ON(00)*

01 t

ON(01)

10 t

ON(10)

11 t

ON(11)

*default state at device power-on

D3 Clear Faults Bit This bit is used to clear a latched

fault. After the fault is cleared, the gate output can

again follow the input logic to determine if the fault is

still present. Faults are cleared on a channel specific

basis.

D4 Mask Off-State Faults Bit [See asterisks (*) in

the table below.] When the application requires that

Short-to-Battery (STB) and Open Load (OL) faults be

checked primarily before output is enabled for the first

time, this bit can be used to allow STB and Open Load

faults to be ignored during normal operation (Short-to-

Ground faults can not be masked). This bit is applied

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

on a channel-specific basis, according to the following

table:

D4 Setting Handling of

Off-State Faults

0 Registered

1 Ignored

D5 Read Enable Bit This bit enables or disables read-

ing on the serial inputs, according to the following

table:

D5 Setting Handling of

Serial Input

0 Ignored

1 Registered

D6, D7 Address MSB and LSB Bits (Input and Out-

put Fault registers) For channel-specific bits, these

bits are used to specify which channel is indicated.

The channel-specific bits are:

Input D0, D1, D2, D3, D4

Output D0, D1, D2

These bits determine the channel, according to the fol-

lowing table:

D7 D6 Channel Selected

00 1

01 2

10 3

11 4

Output FAULT Register

D0 Short-to-Ground (STG) Fault Bit The voltage

from drain to source for each MOSFET is monitored.

An internal current source sinks IDx from the Dx pins

to set the VDS threshold for each channel, the level at

which an STG fault condition is evaluated.

The A3942 enables monitoring for an STG fault after

the MOSFET is turned on and the turn-on blank time,

tON , expires. (The MOSFET is turned on via the Input

for the channel of the MOSFET, and tON is set by

Input register D1 and D2 bits). If the MOSFET gate-

to-source voltage exceeds the VDS threshold, then

an STG fault will be registered for that channel, the

MOSFET gate will be discharged, and the FAULTZ

pin will be set low (active).

An STG fault is latched until cleared (using the Input

can continue to operate normally.

D1 Short to Battery (STB) Fault Bit When a chan-

nel turns off, STB fault detection is blanked for tOFF.

Subsequently, if the Sx pin voltage exceeds the VDS

threshold voltage for that channel, an STB fault is

latched. The output for that channel is disabled until

the fault is either cleared (via the Input register D3 bit)

or the off-state fault diagnostics are masked (via the

Input register D4 bit).

Because the output is disabled, there is no active

pull-down during an STB event. Note that, in general,

when the voltage on SX is high enough to trip the STB

comparator, it also trips the OL comparator, and both

the STB and the OL faults are latched.

D2 Open Load (OL) Fault Bit When a channel turns

off, the OL fault is blanked for tOFF. A small bias

current, IOL , is sourced to the Sx pin of the channel.

There it divides between RSx and the load. If the load

is open, the Sx voltage will rise above the OL fault

detection threshold. In that case, the output is disabled

until the fault is cleared (via the Input register D3 bit)

or the off-state fault diagnostics are masked (via the

Input register D4 bit).

D3 Thermal Warning Bit A die temperature monitor

is integrated on the A3942 chip. If the die temperature

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

approaches the maximum allowable level, a thermal

warning signal will be triggered.

Note that this fault sets the FAULTZ pin low (active),

but does not disable the outputs or operation of the

chip.

D4 Charge Pump UVLO Bit The charge pump must

maintain a voltage guard band above VBB , in order

to charge the gates when commanded to turn on the

MOSFETs. If an undervoltage (UVLO) condition is

detected on the charge pump, the FAULTZ pin will be

set low (active), and all outputs will be disabled.

D5 WriteZ (Not Write) Bit In a written byte, D5 = 0.

D6, D7 Address Bits See description, above.

Pin Descriptions

In this section, the functions of the individual termi-

nals of the A3942 are described.

VBB Supply Voltage (Power) The A3942 is fully

operational over the specified range of VBB. The exter-

nal MOSFETs must be supplied by the same voltage

source as the A3942. A bypass capacitor should be

placed as close as practicable to the A3942.

VDD Supply Voltage (Logic) Logic voltage must be

supplied to the A3942. The wide allowable range of

input voltages allows both 3.3 V and 5 V supplies. A

bypass capacitor should be placed as close as practi-

cable to the A3942.

VCP Charge Pump The integrated charge pump is

used to generate a supply above VBB to drive the gates

of the external power MOSFETs. This tripler keeps the

part functional over a wide range of VBB.

CP1 through CP4 Charge Pump Capacitor Con-

nections These are the connections for the two exter-

nal capacitors that level-shift the charge up to VCP

VREG Internal Linear Voltage Regulator This pro-

vides a connection for an external capacitor that sets

the regulation value for voltage supplied to internal

logic circuits.

IN1 through IN4 Discrete Inputs For each output

channel, the gate pin, Gx, sources voltage when the

corresponding INx pin is set high. Gx sinks voltage to

ground when the corresponding INx pin is set low. The

INx setting is logically ORed with the Gate On/Off bit

(Input register bit D0) for the respective output.

D1 through D4 Output Drains For each output chan-

nel, the voltage on the corresponding Dx pin is used

to evaluate STB and STG fault conditions. The A3942

compares the Dx voltage level to the VDS threshold of

the MOSFET to determine if a fault condition exists.

The trip voltage level is set by selecting an appropriate

value for the resistor, RDx, connected to the corre-

sponding current sink. Because both the Dx pins and

RDx are high impedance, each RDx must be placed

as close to the corresponding A3942 Dx pin as practi-

cable.

G1 through G4 Output Gates These pins drive the

gates of the high-side external MOSFETs. They source

voltage from VCP and sink to GND. The correspond-

ing external gate resistors, RGx, should be ≥ 2 kΩ

for consistent switching times between A3942s when

applicable (see IG(HI) and IG(LO) in the Electrical Char-

acteristics table).

If negative voltages are applied, Gx is clamped to

GND by internal diodes. Back-to-back Zener diodes

are internally connected between Gx and Sx.

Sx Output Sources These are used to measure the

source terminal of the external MOSFET. The pins

may be tied directly to the MOSFET. Although the Sx

pins can survive large negative transients, it is recom-

mended to connect a clamp diode between the Sx pin

and ground to limit any negative transients at the Sx

pin when a load is switched off. This helps to avoid

false fault detection caused by transient noise coupling

into adjacent channels which may not be switching

and therefore have no fault blanking during the tran-

sient. This is especially recommended when there is

significant wiring between the load and the Sx pin

even if the load incorporates a recirculation diode.

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

RESETZ Master Reset and Sleep Mode Pulsing this

pin low clears all latched faults in the channel-specific

fault registers. It also clears the serial port registers

(they return to their default values). When RESETZ is

held low long enough (t > tSLEEP) the A3942 goes to

sleep, as described in the Sleep topic in the Functional

Description section.

ENB Enable Set low to actively pull low all outputs.

FAULTZ Fault Active low open drain output. Signals a

fault. Allows parallel connection with FAULTZ sig-

nals from other devices when required.

SCLK SPI Clock See Serial Port Operation topic in

Functional Description section.

CSZ SPI Chip Select input.

SDO SPI Data Output connection.

SDI SPI Data Input connection.

IREF Current Reference Defines the current used

as a reference to set gate drive currents, diagnostic

currents and internal timers. A resistor, RREF, con-

nected between the IREF pin and the adjacent GND

pin is selected to set the reference current to 20μA.

The IREF pin is a voltage source at a voltage, VREF,

of typically 1.2V. The resistor required is therefore

60.4kOhm, which is the standard resistor value that

provides a typical current closest to the 20μA target.

Any variation in RREF will affect the internal settings

as described in the section below on RREF selection.

Being a high impedance node, the IREF pin is suscep-

tible to external sources of noise and transients and

should be decoupled with a capacitor across RREF

between the IREF pin and the adjacent GND pin. The

capacitor value should be less than 100pF to avoid

any delay when power is first applied to the A3942

or when coming out of sleep mode. When control-

ling large load currents a larger capacitor may be

required to suppress any transient noise. At power-on

or when coming out of sleep mode this capacitor will

be charged at typically 240μA until it reaches VREF.

The time taken to charge the capacitor will be approxi-

mately:

tCHARGE = 5 × C

where tCHARGE is in μs and C is the capacitor value

in nF. At least twice this time should be allowed, after

power-on or after coming out of sleep mode, before

the A3942 is used to switch any loads.

GND Ground All GND pins are internally fused to

the metal die pad to which the chip is soldered. This

allows for high thermal conductance through the GND

pins. Connecting to these pins to a PCB ground plane

improves thermal performance.

Functional Description

Power On When power is applied to either VDD or

VBB, the Output Fault register is initially loaded with

default values, all zeros (0). However, as individual

internal circuits are initially powered on, they may

latch spurious faults in the fault registers for each

channel. Therefore, before operating the A3942 all

fault registers must be cleared by pulsing the RESETZ

pin.

Sleep Mode This mode disables various internal cir-

cuits including the charge pump, VREG, and the logic

circuits. The serial port also is disabled. All Input and

Output Fault register bits are cleared.

To leave sleep mode, pull RESETZ high and then

allow a delay for the charge pump to stabilize. Before

sending commands, clear any spurious faults as

described in the Power On topic.

Faults Faults are categorized either as system faults or

load faults. All faults are ORed to the FAULTZ pin.

System faults are VREG UVLO, CP UVLO, VDD

UVLO, and Thermal Warning. They are not latched in

the channel-specific self-protection circuit fault reg-

isters, however, the flags in the Output Fault register

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

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1.508.853.5000; www.allegromicro.com

bits D3, D4, and D5, are latched. If the fault condition

is resolved, these flags are latched until they are read,

at which time they are cleared.

Load faults are OL, STB, and STG. They are latched

into the channel-specific self-protection circuit fault

registers, and shifted into Output Fault register bits

D0, D1, and D2 when called. Thus, load faults may be

masked or cleared on a channel-specific basis.

Serial Port Operation

The serial port is compatible with the full duplex

Serial Peripheral Interface (SPI) conventions. The

inputs to the SPI port are logically ORed with the

discrete input pins, INx, settings. This allows indepen-

dent operation using only the discrete inputs, only the

serial inputs, or both. Timing is clocked by an on-

board 4 MHz oscillator.

When a Chip Select event occurs, the Output Fault

and the byte is then shifted out through the SDO pin.

Simultaneously, bits at the SDI pin are shifted into the

shift register (full duplex). At the end of a Chip Select

event, the shift register contents are latched into the

Input register.

Alternative Configurations Multiple A3942s can be

configured together.

• Standalone Connection In this configuration, the

master simultaneously shifts eight bits in through

the SDI pin and shifts eight bits out of the SDO pin.

First, the CSZ pin is set low. Then, the Output Fault

the Output Fault Register topic below). Eight clock

cycles are used to perform the shifts.

• Parallel Connection Because each slave has a CSZ

pin, operation is identical to the Standalone configu-

ration. When CSZ is inactive, SDI is “don’t care” and

SDO is high impedance.

• Daisy Chain Connection The master shifts n bytes

(eight bits each) during n × 8 clock cycles. Regard-

less of the position of an individual A3942 slave

in the daisy chain, the slaves shift the output byte

during the first eight clock cycles after CSZ goes

low. When CSZ goes high, the eight bits in the Shift

Serial Port Disabling Disable the serial port by set-

ting the CSZ pin high while in sleep mode. This loads

the Input register with default values, all zeroes (0).

Serial Port Error Handling Input data is discarded if

the number of bits in an input stream are not a mul-

tiple of eight. Furthermore, unless the number of clock

cycles is a multiple of eight while CSZ is active, any

bits shifted in from the SDI pin are discarded.

Input Register Operation After a valid byte is

latched into the Input register from the shift register,

bit D5 is evaluated to determine if the byte is to be

read. An inactive (0) bit value causes all other bits to

be ignored.

If bit D5 is active (1) the other bits are read and

decoded. Bits D6 and D7 are used to determine which

output channel is updated. Bits D0 through D4 set

the channel-specific operation, including clearing and

masking of faults.

Output Fault Register Operation This register is

loaded with fault data to be shifted out through the

SDO pin. No handshaking is required.

The Output Fault register contains data on active

faults. Four internal channel-specific fault registers

contain any latched fault data for each respective

channel. The following describes how the A3942

determines which channel-specific fault register to

transfer into the Output Fault register.

• No Faults If there are no current faults, the Output

Fault register is loaded with all zeros:

0 0 0 0 0 0 0 0

Quad High-Side Gate Driver

for Automotive Applications

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• Single Fault If there is only one fault detected, the

Output Fault register is filled to indicate that fault.

For a load fault, the Address bits are set to indicate

the affected channel; for example, a short-to-battery

on channel 3 would be written:

1 0 0 0 0 0 1 0

On the other hand, for system faults, the Address bits

are irrelevant, and a CP UVLO fault would be loaded

as:

0 0 0 1 0 0 0 0

with the Address bits defaulting to 0 0.

• Multiple System Faults If there are multiple system

faults, the Output Fault register is loaded with the

setting for each system fault (the Address bits re-

main irrelevant, as in the case of a single fault). For

example, when CP UVLO and Thermal Warning

faults both have occurred, the Output Fault register is

loaded with:

0 0 0 1 1 0 0 0

• Multiple System Faults and Single Channel Load

Fault If one or more system faults and one or more

load faults from a single channel have occurred, all

faults are loaded into the Output Fault register, with

the channel of the load faults indicated in the Address

bits. For example, a CP UVLO system fault and an

STG load fault on Channel 2 would be written as:

0 1 0 1 0 0 0 1

• Multiple Channel Load Faults When load faults

occur on more than one channel, the data cannot be

signalled in a single SDO byte. However, the data

can still be retrieved. The A3942 polls each channel-

specific fault register, in ascending order by channel

number.

Each output is delimited by the appropriate CSZ

event. For example, assume an OL on channel 2 and

an STG on Channel 4. The first CSZ event writes:

0 1 0 0 0 1 0 0

and the second CSZ writes:

1 1 0 0 0 0 0 1

In summary, all faults are retrieved by issuing con-

secutive CSZ events until the channel number stops

increasing.

• If there are no faults, this byte will be shifted out

each time:

0 0 0 0 0 0 0 0

• If there are only system faults, this byte will be

shifted out each time:

0 0 [1|0] [1|0] [1|0] 0 0 0

• If there are system faults and only one load fault, one

byte contains all of the fault data.

• If there are load faults on more than one channel,

these bytes would be shifted out in succession, and

any existing system faults will be indicated. For ex-

ample, if there were no system faults and load faults

on channels 2, 3, and 4, the following series of bytes

would be shifted out:

0 1 0 0 0 [1|0] [1|0] [1|0]

1 0 0 0 0 [1|0] [1|0] [1|0]

1 1 0 0 0 [1|0] [1|0] [1|0]

0 1 0 0 0 [1|0] [1|0] [1|0]

. . .

Applications

Unused Outputs When any of the four output chan-

nels are not used, the related pins should be connected

as follows:

Unused Channel Pin Connection

INx GND

Sx GND

Dx VBB

Gx Floating

RREF Selection The tolerance on RREF can be

as high as ±4%. Depending on how a specific part

Quad High-Side Gate Driver

for Automotive Applications

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115 Northeast Cutoff

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changes over temperature changes and lifetime, the

±4% range generally covers nominal 1% resistors.

The parameters which are affected by changes in

RREF are listed in the following table:

Parameter Change as RREF Tolerance

Increases Decreases

IREF –+

tRESET +–

tSLEEP +–

tWAKE +–

IG(HI) and IG(LO) –+

IOL –+

tON and tOFF +–

Setting Fault Circuit Trip Levels The load faults,

Short-to-Battery (STB), Short-to-Ground (STG), and

Open Load (OL), are all latched. The thresholds for

STG and OL faults can be set by the value for the RDx

resistor.

Open Load Fault Level When the gate is commanded

off, a commanded current, IOL , is sourced to Sx to

detect if the load is still in the circuit. VOL is compared

IOL × [RL // RGS]

to evaluate an OL fault.

If the load has been removed, VSx exceeds VOL and

a fault is registered. VSx would drift to VBB when an

open load exists and thereby inadvertantly trip a nui-

sance STB fault. To prevent this, the Sx pin is clamped

to VCLAMP

The operating limits specified in the Electrical Char-

acteristics table allow the fault circuitry to distinguish

all faults within the operating range of VBB. If, how-

ever, the specified limits on VDx are too restrictive at

low VBB levels, the only repercussion is a nuisance

STB fault, and this only occurs when an OL condi-

tion exists. The limit on VDx can be ignored either if

the off-state faults are masked or if it is acceptable to

latch the nuisance fault and clear it when the OL fault

is cleared.

Because VOS << VOL , a fault is registered if

IOL × RL // RGS > VOL .

Hence, the trip level, RL(trip) is:

RL(trip)

–1

VOL

IOL

RGS

⎜

⎝

⎛

⎜

⎝

⎛

–

The OL circuit and its tolerances are designed to

ensure that external loads above 50 kΩ are identified

as open load and that loads below 10 kΩ are identified

as valid. Note that these numbers are valid in steady

state. As a result, blanking times must be set appropri-

ately for a given load.

Under normal conditions, when the external MOSFET

is off, and the load is in circuit,

IOL × RL < VOL.

Short-to-Battery Fault Level The STB comparator

compares the load voltage

IOL × RL // RGS]

to the voltage set by RDx,

VBB –ID × RD .

The comparator is active only when the gate is com-

manded off.

During an STB condition, IOL = 0 because the current

source has run out of headroom. A fault is registered

when

VL > VBB –ID × RD ± VOS.

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

That is, the load voltage is within ∆V = ID × RD volts

of VBB.

Using VDS = VBB – VL and rearranging, we find that

VDS < ID × RD ± VOS .

Therefore,

RD = (VDS(trip) ±VOS) / ID ,

which is also the case for STG faults, described below.

Note that an STB condition generally latches the OL

flag as well.

Under normal conditions RL << RGS and IOL flows

through the load, given

IOL × (RD + RL ) < VBB –ID × RD ± VOS .

Because IOL × (RD + RL ) ≈ 0 when the external

MOSFET is off, no fault is registered.

Short-to-Ground Fault Level The effect of the STG

comparator is to compare the external MOSFET VDS

(VL) to the set trip voltage VBB –ID × RD .

The comparator is active only when the gate is com-

manded on. Also, the sourced current IOL is deacti-

vated.

If VDS is too large, an STG fault is registered when

VL < VBB –ID × RD ± VOS ,

or, because the external MOSFET VDS = VBB – VL ,

VDS > ID × RD ± VOS .

Therefore, the STG trip level in the on state is the

same as the STB level in the off state:

RD = (VDS(trip) ±VOS) / ID .

Converse to the preceding, in normal operation

VL > VBB –ID × RD ± VOS

VDS < ID × RD ± VOS .

Power Limits

Power dissipation, PD, is limited by thermal con-

straints. The maximum junction temperature, TJ(max),

and the thermal resistance, RθJA , are given in this

datasheet. The maximum allowed power is then found

for a given ambient, TA , from this equation:

TJ = PD × RθJA + TA , or

D = (TJ – TA ) / RθJA .

The three main contributions to power dissipation are:

• quiescent supply, PBB(Q)

• driver outputs, PDRV , and

• logic level supply, PDD .

These three terms appear in the following equation:

PD = PBB(Q) + PDRV + PDD .

The quiescent supply current leads to a baseline power

loss:

PBB(Q) = VBB × IBB(Q) .

In general, the losses in a driver can be quantified as

follows. Given that the driver current leaves Gx to

charge a gate, and assuming that the external circuit

is approximately lossless, then the same charge is

sunk back into Gx. Therefore, all driver current can be

treated as going to heat the chip.

Total current into VBB includes the quiescent current,

IBB(Q) , plus additional current, ∆IBB, to energize the

gates. The latter is three times the average gate cur-

rent:

∆IBB = 3 × IGx(av) .

The average load current is calculated using the gate

charge, QG , from the external MOSFET datasheet and

the switching frequency:

IGx(av) = fsw × QG .

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

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If all four outputs are supplying this current,

∆IBB = 4 (3 × IGx) = 12 × fSW × QG,

and

PDRV = VBB × ∆IBB = 12 × fSW × QG × VBB .

Finally, loss in the logic circuits is

PDD = VDD × IDD.

Example:

Find the junction temperature with one IRFZ44ES

MOSFET at each output, being switched at 5 kHz, and

given VBB = 14 V and VDD = 5.5 V.

Answer: The IRFZ44ES datasheet gives QG(max)

= 60 nC (note that this parameter depends on circuit

design constraints, such as VDS). The Electrical Char-

acteristics table gives the following maximum values

for the A3942: IBB(Q) = 10 mA, VDD = 5.5 V, and IDD

= 3 mA.

First, calculate total power loss:

PD = VBB IBB(Q) + 12 fswQGVBB+VDDIDD

= 14 V × 11 mA

+ 4 × 3 × 5 kHz ×60 nC × 14 V

+ 5.5 V × 3 mA

= 221 mW .

Then, the junction temperature can be found for a

given ambient temperature; TA = 125°C is assumed

here. Thermal resistance depends significantly on the

board design; RθJA = 100 °C/W is assumed here. Sub-

stituting these values:

TJ = PD × RθJA + TA

= 221 mW × 100 °C/W + 125°C

= 147°C .

LAYOUT AND COMPONENTS

General good practices should be followed. In addi-

tion, the following are recommended:

• Locate bypass capacitors (VBB, VDD, VREG, and

IREF) as close to the A3942 as practicable.

• Traces to bypass capacitors should be as wide as

practicable; minimize the number of vias.

• Use both bulk storage capacitors (for example, elec-

trolytic) and low impedance bypass capacitors (for

example, ceramic) on all supply pins. See the Func-

tional Block Diagram for recommended values.

• Input and output lines should not be in close proxim-

ity. If they do overlap, it should be at right angles.

• Use ample copper in the ground and power paths.

Use planes or fills where possible.

• The A3942 ground and VBB supply should be star-

connected to the power ground and supply.

• The trace connecting the RDx resistors to the A3942

Dx pins should be as short as possible.

• The trace leaving the other side of the RDx resistors

can be long because it has a low impedance path to

ground; however, it must run independently to the re-

spective external MOSFET in order to make a Kelvin

connection.

• All support capacitors are to be referenced to the

A3942 ground plane or ground fill. Minimize loop

area of traces.

• These traces should be as wide as practicable: VBB,

VDD, VREG, VCP, and Gx. Secondarily, it is also

preferred that the traces to the charge pump caps be

as wide as practicable. In both cases, the number of

vias should be minimized.

• Minimize the distance connecting to ground pins in

order to minimize ground loops.

Finally, a note about thermals. Because the A3942

ground pins are internally fused to the die mounting

pad, they are the main path for heat dissipation. In

applications producing high junction temperatures,

care must be given to designing the thermal path. For

example, multiple thermal vias should be run from

ground pins down to the ground plane. If space allows,

wide traces from ground pins to exposed copper fills

on the top layer efficiently release heat through con-

vection cooling.

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Terminal List

No. Name Pin Description

1 SDO Serial Data Out

2 SDI Serial Data In

3 SCLK Serial Clock

4 CSZ Chip Select – NOT

5 FAULTZ Fault – NOT (Open Drain)

6 RESETZ Reset – NOT (Discrete)

7 ENB Enable (Discrete)

8 VDD Logic Supply

9 IREF Current Reference Pin

10 GND

11 IN2 Discrete Input Channel 2

12 IN1 Discrete Input Channel 1

13 D2 Channel 2: Drain

14 D1 Channel 1: Drain

15 GND

16 S1 Channel 1: Source

17 G1 Channel 1: Gate

18 G2 Channel 2: Gate

19 S2 Channel 2: Source

20 S3 Channel 3: Source

21 G3 Channel 3: Gate

22 G4 Channel 4: Gate

23 S4 Channel 4: Source

24 GND

25 D3 Channel 3: Drain

26 D4 Channel 4: Drain

27 IN3 Discrete Input Channel 3

28 IN4 Discrete Input Channel 4

29 VREG Internal Regulator

30 VBB Power Supply

31 GND

32 VCP Reservoir Capacitor Terminal

33 CP1 Charge Pump Capacitor Terminal

34 CP3 Charge Pump Capacitor Terminal

35 CP2 Charge Pump Capacitor Terminal

36 CP4 Charge Pump Capacitor Terminal

37 GND

38 GND

Quad High-Side Gate Driver

for Automotive Applications

A3942

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

1.20 MAX

4º

6.00

1.60

SEATING

PLANE

0.50

C0.10

38X C

0.30

0.10 ±0.05

0.22 ±0.05

4.40 ±0.10 6.40 ±0.20

9.70 ±0.10

0.15 +0.06

–0.05

GAUGE PLANE

SEATING PLANE

ATerminal #1 mark area

All dimensions nominal, not for tooling use

(reference JEDEC MO-153 BD-1)

Dimensions in millimeters

Pins 10, 15, 24, 31, 37, and 38 fused internally

BReference pad layout (reference IPC SOP50P640X110-38M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

PCB Layout Reference View

0.50

0.25

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

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LG Package, 38-Pin TSSOP