HN27C4096ACP Series
262144-word × 16-bit CMOS One Time Programmable ROM
ADE-203-240B (Z)
Rev. 2.0
Jun. 22, 1995
Description
The Hitachi HN27C4096ACP is a 4-Mbit one time programmable ROM, featuring high speed and low power
dissipation. Fabricated on advanced fine process and high speed circuitry technique, the HN27C4096ACP
makes high speed access time possible. Therefore, it is suitable for 16-bit microcomputer systems using high
speed microcomputer such as the 80286 and 68020. The HN27C4096ACP offers high speed programming
using page programming mode. This device is packaged in a 44-pin plastic leaded chip carrier (PLCC).
Therefore, this device cannot be rewritten.
Features
• High speed
Access time: 120 ns/150 ns (max)
• Low power dissipation
Standby mode: 5 µW (typ)
Active mode: 35 mW/MHz (typ)
• Fast high reliability page programming, fast high-reliability programming and option programming
Programming voltage: +12.5 V D.C.
Program time: 3.5 sec (min) (Theoretical in Page programming)
• Inputs and outputs TTL compatible during both read and program modes
• Pin arrangement: 44-pin PLCC JEDEC standard
• Device identifier mode: Manufacturer code and device code
• Fully compatible with the HN27C4096CP Series
Ordering Information
Type No. Access Time Package
HN27C4096ACP-12
HN27C4096ACP-15 120 ns
150 ns 44-pin PLCC (CP-44)
HN27C4096ACP Series
2
Pin Arrangement
I/O12
I/O11
I/O10
I/O9
I/O8
V
NC
I/O7
I/O6
I/O5
I/O4
A13
A12
A11
A10
A9
V
NC
A8
A7
A6
A5
SS SS
I/O13
I/O14
I/O15
CE
V
NC
V
A17
A16
A15
A14
PP
CC
I/O3
I/O2
I/O1
I/O0
OE
NC
A0
A1
A2
A3
A4
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6 5 4 3 2 1 44 43 42 41 40
2827262524232221201918
(Top View)
HN27C4096ACP Series
Pin Description
Pin Name Function
A0 – A17 Address
I/O0 – I/O15 Input/output
CE Chip enable
OE Output enable
VCC Power supply
VPP Programming power supply
VSS Ground
HN27C4096ACP Series
3
Block Diagram
A7
A17
I/O0
I/O15
X-Decoder 2048 × 2048
Memory Matrix
Input
Data
Control
Y-Gating
Y-Decoder
A0 A6
H : High Threshold Inverter
H
CE
OE
VCC
VPP
VSS
H
................
............
HN27C4096ACP Series
4
Mode Selection
Mode Pin CE (3) OE (22) A9 (35) VPP (2) VCC (44) I/O (4 – 11, 14 – 21)
Read VIL VIL XV
SS – VCC VCC Dout
Output disable VIL VIH XV
SS – VCC VCC High-Z
Standby VIH XXV
SS – VCC VCC High-Z
Page program Page program set VIH VH*2 XV
PP VCC High-Z
Page data latch VIL VH*2 XV
PP VCC Din
Page program VIL VIH XV
PP VCC High-Z
Page program verify VIH VIL XV
PP VCC Dout
Page program reset VIH VIH XV
CC VCC High-Z
Word program Program VIL VIH XV
PP VCC Din
Program verify VIH VIL XV
PP VCC Dout
Optional verify VIL VIL XV
PP VCC Dout
Program inhibit VIH VIH XV
PP VCC High-Z
Identifier VIL VIL VH*2 VSS – VCC VCC Code
Notes: 1. X: Don’t care.
2. VH: 12.0 V ± 0.5 V
Absolute Maximum Ratings
Parameter Symbol Value Unit Notes
All input and output voltages Vin, Vout –0.6*2 to +7.0 V 1, 2
Voltage on pin A9 and OE VID –0.6*2 to +13.0 V 2
VPP voltage VPP –0.6 to +13.5 V 1
VCC voltage VCC –0.6 to +7.0 V 1
Operating temperature range Topr 0 to +70 °C
Storage temperature range Tstg –55 to +125 °C3
Storage temperature under bias Tbias –20 to +80 °C
Notes: 1. Relative to VSS.
2. Vin, Vout, VID min = –2.0 V for pulse width ≤ 20 ns.
3. Storage temperature range of device before programming.
HN27C4096ACP Series
5
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test Conditions
Input capacitance Cin — — 12 pF Vin = 0 V
Output capacitance Cout — — 20 pF Vout = 0 V
Read Operation
DC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 5.5 V
Output leakage current ILO ——2 µA Vout = 5.5 V/0.45 V
VPP current IPP1 —1 20µAV
PP = 5.5 V
Standby VCC current ISB1 ——1 mACE = VIH
ISB2 —1 20µACE = VCC ±0.3 V
Operating VCC current ICC1 — — 30 mA Iout = 0 mA, f = 1 MHz
ICC2 — — 90 mA Iout = 0 mA, f = 8.4 MHz
Input voltage VIL –0.3*1 — 0.8 V
VIH 2.2 — VCC + 1*2 V
Output voltage VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns.
VIL min = –2.0 V for pulse width ≤ 20 ns.
2. VIH max = Vcc +1.5 V for pulse width ≤ 20 ns.
If VIH is over the specified maximum value, read operation cannot be guaranteed.
HN27C4096ACP Series
6
AC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 10 ns
• Output load: 1 TTL Gate + 100 pF
• Reference levels for measuring timing: 0.8 V, 2.0 V
HN27C4096ACP
-12 -15
Parameter Symbol Min Max Min Max Unit Test Conditions
Address to output delay tACC — 120 — 150 ns CE = OE = VIL
CE to output delay tCE — 120 — 150 ns OE = VIL
OE to output delay tOE — 60 — 70 ns CE = VIL
OE high to output float*1 tDF 0 40 0 50 ns CE = VIL
Address to output hold tOH 5—5—nsCE = OE = VIL
Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
Read Timing Waveform
Address
CE
OE
Data Out Data Out Valid
tACC
tCE
tOE tOH
tDF
Standby mode Active mode Standby mode
HN27C4096ACP Series
7
Fast High-Reliability Page Programming
This device can be applied the high performance page programming algorithm shown in the following
flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device
nor deterioration in reliability of programmed data.
Page Program Set
Apply 12 V to OE pin after applying 12.5 V to VPP to set a page program mode.
The device operates in a page program mode until reset.
Page Program Reset
Set VPP to VCC level or less to reset a page program mode.
HN27C4096ACP Series
8
START
SET PAGE PROG LATCH MODE
VPP = 12.5 ± 0.3 V, VCC = 6.25 ± 0.25 V
= 12.0 ± 0.5 V
OE
Address = 0
n = 0
Latch
Address + 1 Address
→
Latch
Address + 1 Address
→
Address + 1 Address
→
Latch
Latch
n + 1 n
→
SET PAGE PROG./VERIFY MODE
VPP = 12.5 ± 0.3 V, VCC = 6.25 ± 0.25 V
Address + 1 Address
→
NOGO
GO
YES
NOGO
NO NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
VCC = 5.0 ± 0.5 V, VPP = VCC
GO
Program tPW = 50 µs ± 5%
YES
Fast High-Reliability Page Programming Flowchart
HN27C4096ACP Series
9
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 6.5 V/0.45 V
Output voltage during
verify VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Operating VCC current ICC ——50mA
Input voltage VIL –0.1*5 — 0.8 V
VIH 2.2 — VCC + 0.5*6 V
VH11.5 12.0 12.5 V
VPP supply current IPP ——70mACE = VIL
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while VPP =
12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width ≤ 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
HN27C4096ACP Series
10
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 20 ns
• Reference levels for measuring timing: Inputs: 0.8 V, 2.0 V,
Outputs: 0.8 V, 2.0 V
Parameter Symbol Min Typ Max Unit Test Conditions
Address setup time tAS 2——µs
OE setup time tOES 2——µs
Data setup time tDS 2 — —µs
Address hold time tAH 0— —µs
Data hold time tDH 2— —µs
OE high to output float delay tDF*1 0 — 130 ns
VPP setup time tVPS 2— —µs
V
CC setup time tVCS 2— —µs
CE programming pulse width tPW 47.5 50.0 52.5 µs
CE setup time tCES 2— —µs
Data valid from OE tOE 0 — 150 ns
CE pulse width during data latch tLW 1— —µs
OE = VH setup time tOHS 2— —µs
OE = VH hold time tOHH 2— —µs
V
PP hold time*2 tVRS 1— —µs
Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
2. Page program mode will be reset when VPP is set to VCC or less.
HN27C4096ACP Series
11
Fast High-Reliability Page Programming Timing Waveform
Program data latch Page program Program verify
Data out valid
Data in
stable
Page program mode
ttt
t
tLW
VRS
OES
PW
CES
tOHH
t
VCS
t
VPS
t
OHS
t
DS
t
DH
t
OE
t
DF
t
AS
t
AH
t
AH
t
AS
A2 – A17
A0, A1
Data
V
V
CE
OE
V
V + 1.25
V
PP VPP
CC
CC
CC
CC
VIL
VH
VIH
HN27C4096ACP Series
12
Fast High-Reliability Progamming
This device can be applied the fast high-reliability programming algorithm shown in the following flowchart.
This algorithm allows to obtain faster programming time without any voltage stress to the device nor
deterioration in reliability of programmed data.
NOGO
START
Address = 0
n = 0
n + 1 n
SET PROG./VERIFY MODE
VPP = 12.5 ± 0.3 V, VCC = 6.25 ± 0.25 V
Address + 1 Address GO
YES
NOGO
NO NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
VCC = 5.0 ± 0.5 V, VPP = VCC
GO
Program tPW = 50 µs ± 5%
YES
Fast High-Reliability Programming Flowchart
HN27C4096ACP Series
13
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 6.5 V/0.45 V
VPP supply current IPP ——40mACE = VIL
Operating VCC current ICC ——50mA
Input voltage VIL –0.1*5 — 0.8 V
VIH 2.2 — VCC + 0.5*6 V
Output voltage VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while VPP =
12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width ≤ 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 20 ns
• Reference levels for measuring timing: Inputs: 0.8 V, 2.0 V,
Outputs: 0.8 V, 2.0 V
Parameter Symbol Min Typ Max Unit Test Conditions
Address setup time tAS 2 ——µs
OE setup time tOES 2 ——µs
Data setup time tDS 2 ——µs
Address hold time tAH 0 ——µs
Data hold time tDH 2 ——µs
OE to output float delay tDF*1 0 — 130 ns
VPP setup time tVPS 2 ——µs
V
CC setup time tVCS 2 ——µs
CE programming pulse width tPW 47.5 50.0 52.5 µs
Data valid from OE tOE 0 — 150 ns
Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
HN27C4096ACP Series
14
Fast High-Reliability Programming Timing Waveform
Program Program Verify
Address
Data Data In Stable Data Out Valid
tAS
tDS
tVPS
tVCS
tDH tDF
tAH
tPW tOES tOE
VPP VCC
VPP
VCC VCC
V +1.25
CC
CE
tDS
OE
Optional Page Programming
This device can be applied the optional page programming algorithm shown in the following flowchart. This
algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration
in reliability of programmed data.
This programming algorithm is the combination of page programming and word verify. It can avoid the
increase of programming verify time when a programmer with slow machine cycle is used, and shorten the
total programming time.
Regarding the timing specifications for page programming and word verify, please refer to the specifications
for fast high-relaibility page programming and fast high-reliability programming.
HN27C4096ACP Series
15
START
SET PAGE PROG. LATCH MODE
V
PP
= 12.5 ± 0.3 V, V
CC
= 6.25 ± 0.25 V
= 12.0 ± 0.5 V
OE
Address = 0
Latch
Address + 1 Address
Latch
Address + 1 Address
Address + 1 Address
Latch
Latch
n + 1 n
SET PAGE PROG./MODE
V
PP
= 12.5 ± 0.3 V, V
CC
= 6.25 ± 0.25 V
Address + 1 Address
NOGO
GO
YES
NOGO
NO
NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
V
CC
= 5.0 ± 0.5 V, V
PP
= V
CC
GO
Program t
PW
= 50 µs ± 5%
SET WORD PROG./VERIFY MODE
V
PP
= 12.5 ± 0.3 V, V
CC
= 6.25 ± 0.25 V
PAGE PROG. RESET
V
PP
= V
CC
= 6.25 ± 0.25 V
Address = 0
n = 0
Address + 1 Address Program t
PW
= 50 µs ± 5%
VERIFY
YES
LAST
address?
GO
NOGO
YES
NO
Optional Page Programming Flowchart
HN27C4096ACP Series
16
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 6.5 V/0.45 V
Output voltage during verify VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Operating VCC current ICC — — 50 mA
Inputt voltage VIL –0.1*5 — 0.8 V
VIH 2.2 — VCC + 0.5*6 V
VH11.5 12.0 12.5 V
VPP supply current IPP — — 70 mA CE = VIL
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while VPP =
12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width ≤ 20 ns.
6. If VIH is over the specified maximum value, programming opration cannot be guaranteed.
HN27C4096ACP Series
17
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 20 ns
• Reference levels for measuring timing: Inputs: 0.8 V, 2.0 V,
Outputs: 0.8 V, 2.0 V
Parameter Symbol Min Typ Max Unit Test Conditions
Address setup time tAS 2––µs
OE setup time tOES 2––µs
Data setup time tDS 2––µs
Addres hold time tAH 0––µs
Data hold time tDH 2––µs
OE high to output float delay tDF*1 0 – 130 ns
VPP setup time tVPS 2––µs
V
CC setup time tVCS 2––µs
CE programming pulse width tPW 47.5 50.0 52.5 µs
CE setup time tCES 2––µs
Data valid from OE tOE 0 – 150 ns
CE pulse width during data latch tLW 1––µs
OE = VH setup time tOHS 2––µs
OE = VH hold time tOHH 2––µs
Page programming reset time*2 tVLW 1––µs
V
PP hold time*2 tVRS 1––µs
Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
2. Page program mode will be reset when VPP is set to VCC or less.
HN27C4096ACP Series
18
Optional Page Programming Timing Waveform
Program data latch Page program
Program verify
Page program mode
t
t
tLW OES
PW
tOHH
t
VCS
t
VPS
t
DS
t
DH
t
OE
t
DS
t
AS
t
AH
t
AH
t
AS
A2 – A17
A0, A1
Data
V
V
CE
OE
V
V + 1.25
V
PP VPP
CC
CC
CC
CC
VIL
VH
VIH
t
AH
Word program mode
Program
t
DH
t
VPS
t
DF
t
VRS
t
VLW
tCES tCES
tPW
t
OHS
Data in
stable
Data
out
valid Data in stable
Mode Description
Device Identifier Mode
The device identifier mode allows the reading out of binary codes that identify manufacturer and type of
device, from outputs of OTPROM. By this mode, the device will be automatically matched its own
corresponding programming algorithm, using programming equipment.
HN27C4096ACP Series
19
HN27C4096ACP Identifier Code
Identifier A0
(24) I/O8 – I/O15
(11) – (4) I/O7
(14) I/O6
(15) I/O5
(16) I/O4
(17) I/O3
(18) I/O2
(19) I/O1
(20) I/O0
(21) Hex Data
Manufacturer code VIL X 0000011107
Device code VIH X 10100010A2
Notes: 1. VCC = 5.0 V ± 10%.
2, A9 = 12.0 V ± 0.5 V.
3. A1 – A8, A10 – A17, CE, OE = VIL.
4. X: Don’t care.
Recommended Screening Conditions
Before mounting, please make the screening (baking without bias) shown in the right.
Program and
verify
by programmer
Baking at
125 to 150°C
for 24 to 48 hrs
Ensuring
read-out
Mounting
Recommended
Screening Conditions
HN27C4096ACP Series
20
Package Dimensions
HN27C4096ACP Series (CP-44) Unit: mm
1.27
0.43 ± 0.10
17.53 ± 0.12
16.58
39 29
717
28
18
40
44
1
6
15.50 ± 0.50
15.50 ± 0.50
4.40 ± 0.20
2.55 ± 0.15
17.53 ± 0.12
0.74
0.10
