InvenSense Inc.
1197 Borregas Ave, Sunnyvale, CA 9 40 89 U. S.A.
Tel: +1 (408) 988-7339 Fax : +1 (408 ) 988-8104
Website: ww w. in v ensens e.c om
Document Number: RM-MPU-6000A-00
R evis i on: 4. 0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 1 of 47
MPU-6000 and MPU-6050
Register Map and Descriptions
Revision 4.0
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 2 of 47
CONTENTS
1 REVISION HISTORY ............................................................................................................................. 4
2 PURPOS E AND SCOPE ....................................................................................................................... 5
3 REGISTER MAP ................................................................................................................................... 6
4 REGISTER DESCRIPTIONS ................................................................................................................. 9
4.1 REGISTERS 13 TO 16 – SELF TEST REGISTERS ................................................................................ 9
4.2 REGISTER 25 – SAMPLE RATE DIVIDER ...........................................................................................11
4.3 REGISTER 26 – CONFIGURATION ....................................................................................................13
4.4 REGISTER 27 – GYROSCOPE CONFIGURATION.................................................................................14
4.5 REGISTER 28 – ACCELEROMETER CONFIGURATION..........................................................................15
4.6 REGISTER 31 – MOTION DETECTION THRESHOLD ............................................................................16
4.7 REGISTER 35 – FIFO ENABLE .......................................................................................................16
4.8 REGISTER 36 – I2C MASTER CONTROL ...........................................................................................17
4.9 REGISTERS 37 TO 39 – I2C SLAVE 0 CONTROL ................................................................................20
4.10 REGISTERS 40 TO 42 – I2C SLAVE 1 CONTROL ................................................................................23
4.11 REGISTERS 43 TO 45 – I2C SLAVE 2 CONTROL ................................................................................23
4.12 REGISTERS 46 TO 48 – I2C SLAVE 3 CONTROL ................................................................................23
4.13 REGISTERS 49 TO 53 – I2C SLAVE 4 CONTROL ................................................................................24
4.14 REGISTER 54 – I2C MASTER STATUS ..............................................................................................26
4.15 REGISTER 55 – INT PIN / BYPASS ENABLE CONFIGURATION .............................................................27
4.16 REGISTER 56 – INTERRUPT ENABLE ...............................................................................................28
4.17 REGISTER 58 – INTERRUPT STATUS ...............................................................................................29
4.18 REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS ..............................................................30
4.19 REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT ..................................................................31
4.20 REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS .....................................................................32
4.21 REGISTERS 73 TO 96 – EXTERNAL SENSOR DATA ............................................................................33
4.22 REGISTER 99 – I2C SLAVE 0 DATA OUT ..........................................................................................35
4.23 REGISTER 100 – I2C SLAVE 1 DATA OUT ........................................................................................35
4.24 REGISTER 101 – I2C SLAVE 2 DATA OUT ........................................................................................36
4.25 REGISTER 102 – I2C SLAVE 3 DATA OUT ........................................................................................36
4.26 REGISTER 103 – I2C MASTER DELAY CONTROL ...............................................................................37
4.27 REGISTER 104 – SIGNAL PATH RESET ............................................................................................38
4.28 REGISTER 105 – MOTION DETECTION CONTROL ..............................................................................39
4.29 REGISTER 106 – USER CONTROL...................................................................................................39
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 3 of 47
4.30 REGISTER 107 – POWER MANAGEMENT 1 .......................................................................................41
4.31 REGISTER 108 – POWER MANAGEMENT 2 .......................................................................................43
4.32 REGISTER 114 AND 115 – FIFO COUNT REGISTERS ........................................................................44
4.33 REGISTER 116 – FIFO READ WRITE ..............................................................................................45
4.34 REGISTER 117 – WHO AM I ...........................................................................................................46
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 4 of 47
1 Revision History
Revision
Date
Revision
Description
11/29/2010 1.0 Initial Release
04/20/2011 1.1 Updated register m ap and descripti ons to r eflect enhanced register f unc tionality .
05/19/2011 2.0
Updates for Rev C sili c on:
Edi ts for readabilit y ( secti on 2.1)
Edi ts for changes in functionali ty ( sect ion 3, 4.4, 4. 6, 4.7, 4.8, 4.21, 4.22, 4.23,
4.37)
10/07/2011 3.0 Updates for Rev D sili c on:
Updated accelerometer sensitivity specifications (sections 4.6, 4.8, 4.10, 4.23)
10/24/2011 3.1 Edits for clarity
11/14/2011 3.2
Updated reset value for register 107 (sect ion 3)
Updated register 27 with gyro self-t est bits (secti on 4.4)
Provided gyr o self-test instructions and regi ster bits (section 4.4)
Provided acc el self-test i nstr uc tions (section 4.5)
3/9/2012 4.0
Updated register m ap to include Self -Test registers (sec ti on 3)
Added descri pti on of Self-Test register s (section 4. 1)
Revi sed temper ature r egister secti on ( sect ion 4. 19)
Correcti ons i n regi ster s 107 and 108 (section 4. 30)
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 5 of 47
2 Purpose and Scope
This document provides preliminary information regarding the register map and descriptions for the Motion
Processing Units™ MPU-6000™ and M P U-6050™ , collec tively c alled the MPU-60X0™ or MPU™.
The MPU devices provide the world’s first integrated 6-axis motion processor solution that eliminates the
package-level g y r oscope and acc eler om eter cross-ax is mi salignment associ ated wit h di screte soluti ons. The
devices combine a 3-axis gyroscope and a 3-axis accelerometer on the same silicon die together with an
onboard Di git al Motion Processor™ ( DMP™) capabl e of processi ng com plex 9-ax i s sensor f usion algorit hms
using the field-proven and proprietary MotionFusion™ engine.
The MPU-6000 and MPU-6050’s integrated 9-axis MotionFusion algori thms access ext ernal m agnetomet ers
or other sensor s through an auxili ary master I2C bus, allowing the devices to gather a full set of sensor data
without intervention from the system processor. The devices are offered in the same 4x4x0.9 mm QFN
footprint and pinout as the current MPU-3000™ family of integrated 3-axis gyroscopes, providing a simple
upgrade path and facilitating plac em ent on alr eady space constr ained circuit boards.
For precision tracking of both fast and slow motions, the MPU-60X0 features a user-programmable
gyroscope full-scale range of ±250, ±500, ±1000, and ±2000°/sec (dps). The parts also have a user-
programmable ac c elero meter full-scal e r ange of ±2g, ±4g, ±8g, and ±16g.
The MPU-6000 f amily i s compri sed of t wo part s, the MPU-6000 and MPU-6050. These parts are identical to
each other with two exceptions. The MPU-6050 supports I2C communications at up to 400kHz and has a
VLOGI C pin that defines its interf ace volt age l ev els; the MPU-6000 supports SPI at up to 20M Hz i n additi on
to I2C, and has a single supply pin, VDD, which is both the device’s logic reference supply and the analog
supply for the part.
For more detailed information for the MPU-60X0 devices, please refer to the “MPU-6000 and MPU-6050
Product Specification”.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 6 of 47
3 Register Map
The register map for the MPU-60X0 is li sted below.
Addr
(Hex) Addr
(Dec.) Register Name Serial
I/F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0D 13 SELF_TEST_X R/W XA_TEST[4-2] XG_TEST[4-0]
0E 14 SELF_TEST_Y R/W YA_TEST[4-2] YG_TEST[4-0]
0F 15 SELF_TEST_Z R/W ZA_TEST[4-2] ZG_TEST[4-0]
10 16 SELF_TEST_A R/W RESERVED XA_TEST[1-0] YA_TEST[1-0] ZA_TEST[1-0]
19 25 SMPLRT_DIV R/W SMPLRT_DIV[7:0]
1A 26 CONFIG R/W - - EXT_SYNC_SET[2:0] DLPF_CFG[2:0]
1B 27 GYRO_CONFIG R/W - - - FS_SEL [1:0] - - -
1C 28 ACCEL_CONFIG R/W XA_ST YA_ST ZA_ST AFS_SEL[1:0]
1F 31 MOT_THR R/W MOT_THR[7:0]
23 35 FIFO_EN R/W TEMP
_FIFO_EN
XG
_FIFO_EN
YG
_FIFO_EN
ZG
_FIFO_EN
ACCEL
_FIFO_EN
SLV2
_FIFO_EN
SLV1
_FIFO_EN
SLV0
_FIFO_EN
24 36 I2C_MST_CTRL R/W
MULT
_MST_EN
WAIT
_FOR_ES
SLV_3
_FIFO_EN
I2C_MST
_P_NSR I2C_MST_CLK[3:0]
25 37 I2C_SLV0_ADDR R/W I2C_SLV0
_RW
I2C_SLV0_ADDR[6:0]
26 38 I2C_SLV0_REG R/W I2C_SLV0_REG[7:0]
27 39 I2C_SLV0_CTRL R/W
I2C_SLV0
_EN
I2C_SLV0
_BYTE_SW
I2C_SLV0
_REG_DIS
I2C_SLV0
_GRP I2C_SLV0_LEN[3:0]
28 40 I2C_SLV1_ADDR R/W I2C_SLV1
_RW
I2C_SLV1_ADDR[6:0]
29 41 I2C_SLV1_REG R/W I2C_SLV1_REG[7:0]
2A 42 I2C_SLV1_CTRL R/W
I2C_SLV1
_EN
I2C_SLV1
_BYTE_SW
I2C_SLV1
_REG_DIS
I2C_SLV1
_GRP
I2C_SLV1_LEN[3:0]
2B 43 I2C_SLV2_ADDR R/W I2C_SLV2
_RW
I2C_SLV2_ADDR[6:0]
2C 44 I2C_SLV2_REG R/W I2C_SLV2_REG[7:0]
2D 45 I2C_SLV2_CTRL R/W
I2C_SLV2
_EN
I2C_SLV2
_BYTE_SW
I2C_SLV2
_REG_DIS
I2C_SLV2
_GRP I2C_SLV2_LEN[3:0]
2E 46 I2C_SLV3_ADDR R/W I2C_SLV3
_RW
I2C_SLV3_ADDR[6:0]
2F 47 I2C_SLV3_REG R/W I2C_SLV3_REG[7:0]
30 48 I2C_SLV3_CTRL R/W I2C_SLV3
_EN
I2C_SLV3
_BYTE_SW
I2C_SLV3
_REG_DIS
I2C_SLV3
_GRP
I2C_SLV3_LEN[3:0]
31 49 I2C_SLV4_ADDR R/W I2C_SLV4
_RW I2C_SLV4_ADDR[6:0]
32 50 I2C_SLV4_REG R/W I2C_SLV4_REG[7:0]
33 51 I2C_SLV4_DO R/W I2C_SLV4_DO[7:0]
34 52 I2C_SLV4_CTRL R/W I2C_SLV4
_EN I2C_SLV4
_INT_EN I2C_SLV4
_REG_DIS I2C_MST_DLY[4:0]
35 53 I2C_SLV4_DI R I2C_SLV4_DI[7:0]
36 54 I2C_MST_STATUS R PASS_
THROUGH I2C_SLV4
_DONE I2C_LOST
_ARB I2C_SLV4
_NACK I2C_SLV3
_NACK I2C_SLV2
_NACK I2C_SLV1
_NACK I2C_SLV0
_NACK
37 55 INT_PIN_CFG R/W INT_LEVEL INT_OPEN LATCH
_INT_EN INT_RD
_CLEAR FSYNC_
INT_LEVEL FSYNC
_INT_EN
I2C
_BYPASS
_EN -
38 56 INT_ENABLE R/W - MOT_EN - FIFO
_OFLOW
_EN
I2C_MST
_INT_EN - - DATA
_RDY_EN
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 7 of 47
Addr
(Hex) Addr
(Dec.) Register Name Serial
I/F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
3A 58 INT_STATUS R - MOT_INT - FIFO
_OFLOW
_INT
I2C_MST
_INT - - DATA
_RDY_INT
3B 59 ACCEL_XOUT_H R ACCEL_XOUT[15:8]
3C 60 ACCEL_XOUT_L R ACCEL_XOUT[7:0]
3D 61 ACCEL_YOUT_H R ACCEL_YOUT[15:8]
3E 62 ACCEL_YOUT_L R ACCEL_YOUT[7:0]
3F 63 ACCEL_ZOUT_H R ACCEL_ZOUT[15:8]
40 64 ACCEL_ZOUT_L R ACCEL_ZOUT[7:0]
41 65 TEMP_OUT_H R TEMP_OUT[15:8]
42 66 TEMP_OUT_L R TEMP_OUT[7:0]
43 67 GYRO_XOUT_H R GYRO_XOUT[15:8]
44 68 GYRO_XOUT_L R GYRO_XOUT[7:0]
45 69 GYRO_YOUT_H R GYRO_YOUT[15:8]
46 70 GYRO_YOUT_L R GYRO_YOUT[7:0]
47 71 GYRO_ZOUT_H R GYRO_ZOUT[15:8]
48 72 GYRO_ZOUT_L R GYRO_ZOUT[7:0]
49 73 EXT_SENS_DATA_00 R EXT_SENS_DATA_00[7:0]
4A 74 EXT_SENS_DATA_01 R EXT_SENS_DATA_01[7:0]
4B 75 EXT_SENS_DATA_02 R EXT_SENS_DATA_02[7:0]
4C 76 EXT_SENS_DATA_03 R EXT_SENS_DATA_03[7:0]
4D 77 EXT_SENS_DATA_04 R EXT_SENS_DATA_04[7:0]
4E 78 EXT_SENS_DATA_05 R EXT_SENS_DATA_05[7:0]
4F 79 EXT_SENS_DATA_06 R EXT_SENS_DATA_06[7:0]
50 80 EXT_SENS_DATA_07 R EXT_SENS_DATA_07[7:0]
51 81 EXT_SENS_DATA_08 R EXT_SENS_DATA_08[7:0]
52 82 EXT_SENS_DATA_09 R EXT_SENS_DATA_09[7:0]
53 83 EXT_SENS_DATA_10 R EXT_SENS_DATA_10[7:0]
54 84 EXT_SENS_DATA_11 R EXT_SENS_DATA_11[7:0]
55 85 EXT_SENS_DATA_12 R EXT_SENS_DATA_12[7:0]
56 86 EXT_SENS_DATA_13 R EXT_SENS_DATA_13[7:0]
57 87 EXT_SENS_DATA_14 R EXT_SENS_DATA_14[7:0]
58 88 EXT_SENS_DATA_15 R EXT_SENS_DATA_15[7:0]
59 89 EXT_SENS_DATA_16 R EXT_SENS_DATA_16[7:0]
5A 90 EXT_SENS_DATA_17 R EXT_SENS_DATA_17[7:0]
5B 91 EXT_SENS_DATA_18 R EXT_SENS_DATA_18[7:0]
5C 92 EXT_SENS_DATA_19 R EXT_SENS_DATA_19[7:0]
5D 93 EXT_SENS_DATA_20 R EXT_SENS_DATA_20[7:0]
5E 94 EXT_SENS_DATA_21 R EXT_SENS_DATA_21[7:0]
5F 95 EXT_SENS_DATA_22 R EXT_SENS_DATA_22[7:0]
60 96 EXT_SENS_DATA_23 R EXT_SENS_DATA_23[7:0]
63 99 I2C_SLV0_DO R/W I2C_SLV0_DO[7:0]
64 100 I2C_SLV1_DO R/W I2C_SLV1_DO[7:0]
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 8 of 47
Addr
(Hex) Addr
(Dec.) Register Name Serial
I/F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
65 101 I2C_SLV2_DO R/W I2C_SLV2_DO[7:0]
66 102 I2C_SLV3_DO R/W I2C_SLV3_DO[7:0]
67 103 I2C_MST_DELAY_CT
RL R/W DELAY_ES
_SHADOW - - I2C_SLV4
_DLY_EN I2C_SLV3
_DLY_EN I2C_SLV2
_DLY_EN I2C_SLV1
_DLY_EN I2C_SLV0
_DLY_EN
68 104 SIGNAL_PATH_RES
ET R/W - - - - - GYRO
_RESET ACCEL
_RESET TEMP
_RESET
69 105 MOT_DETECT_CTRL R/W - - ACCEL_ON_DELAY[1:0] - -
6A 106 USER_CTRL R/W - FIFO_EN I2C_MST
_EN I2C_IF
_DIS - FIFO
_RESET I2C_MST
_RESET SIG_COND
_RESET
6B 107 PWR_MGMT_1 R/W DEVICE
_RESET SLEEP CYCLE - TEMP_DIS CLKSEL[2:0]
6C 108 PWR_MGMT_2 R/W LP_WAKE_CTRL[1:0] STBY_XA STBY_YA STBY_ZA STBY_XG STBY_YG STBY_ZG
72 114 FIFO_COUNTH R/W FIFO_COUNT[15:8]
73 115 FIFO_COUNTL R/W FIFO_COUNT[7:0]
74 116 FIFO_R_W R/W FIFO_DATA[7:0]
75 117 WHO_AM_I R - WHO_AM_I[6:1] -
Note:
Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal
register value.
In the detailed register tables that follow, register names are in capital letters, while register values are in
capital letters and italicized. For example, the ACCEL_XOUT_H register (Register 59) contains the 8 most
significant bits, ACCEL_XOUT[15:8], of t he 16-bit X -Axis accelerometer measurement, ACCEL_XOUT.
The reset value is 0x00 f or all r egister s other than the regi ster s bel ow.
• Register 107: 0x40.
• Register 117: 0x68.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 9 of 47
4 Register Descriptions
This sect ion describes the function and cont ents of each register withi n the MPU-60X0.
Note:
The device will come up in sleep mode upon power-up.
4.1 Reg isters 13 to 16 – Self Test Registers
SELF_TEST_X, SELF_TEST_Y, SELF_TEST_Z, and SELF_TEST_A
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0D 13 XA_TEST[4-2] XG_TEST[4-0]
0E 14 YA_TEST[4-2] YG_TEST[4-0]
0F 15 ZA_TEST[4-2] ZG_TEST[4-0]
10 16 RESERVED XA_TEST[1-0] YA_TEST[1-0] ZA_TEST[1-0]
These registers are used for gyroscope and accelerom eter self-t est s that permit t he user to t est the
mechanical and electrical portions of the gyroscope and the accelerometer. The following sections
describe the self -test process.
Description:
1. Gyroscope Hardware Self-Test: Relative Met hod
Gyroscope self-test permits users to test the mechanical and electrical portions of the gyroscope.
Code for operating self-test is included within the MotionApps™ software provided by InvenSense.
Please refer to the next section (Obtaining the Gyroscope Factory Trim (FT) Value) if not using
MotionApps sof tware.
When self-test is activated, the on-board electronics will actuate the appropriate sensor. This
actuation will move the sensor’s proof masses over a distance equivalent to a pre-defined Coriolis
force. This proof mass displacement results in a change in the sensor output, which is reflected in
the out put signal. The out put signal is used to observe the self-test response.
The self-test r esponse (STR) is defined as follows:
=
- -
This self t est-r esponse is used to determine whether the part has passed or f ail ed self-test by fi nding
the change from factory trim of the self -test respon se a s follows:
- (%)=( )
where,
= ,
This change from factory trim of the self -test respon se must be wit hin t he lim its provided in t he M P U-
6000/MPU-6050 Product Specific ation docum ent f or the part to pass self-test. Otherwise, t he part is
deem ed to have failed self-test.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 10 of 47
Obt aining the Gy r oscope F actor y Trim (FT) V alue
If Inv enSense MotionApps soft ware i s not used, t he procedure detailed bel ow should be followed to
obtain the Factory trim value of the self test response (FT) mentioned above. For the specific
regi ster s mentioned below, pl ease ref er to registers 13-15.
The Factory trim v alue of the self test response (FT ) i s calculated as shown below. FT[Xg], FT[Yg],
and FT[Zg] refer to the factory trim (FT) values for the gyroscope X, Y, and Z axes, respectively.
XG_TES T is the decimal ver si on of XG_TE ST[4-0], YG_TEST is the dec imal v er si on of YG_TEST[4-
0], and ZG_TEST is the decimal version of ZG_TEST[4-0].
When performing self t est for the gyroscope, th e full-scale rang e should be set to ±250dps.
FT [Xg] = 25 131 1.046(_) if XG_TEST ≠ 0
FT [Xg]= 0 if XG_TEST = 0
FT [Yg]= 25 131 1.046(_) if YG_TEST ≠ 0
FT [Yg]= 0 if YG_TEST = 0
FT [Zg] = 25 131 1.046(_) if ZG_TEST ≠ 0
FT [Zg]= 0 if ZG_TEST = 0
2. Accel erometer Hard ware Sel f-Test: Relative Method
Accelerometer self-test permits users to test the mechanical and electrical portions of the
accelerometer. Code for operating self-test is included within the MotionApps software provided by
InvenSense. Please refer to the next section (titled Obtaining the Accelerometer Factory Trim (FT)
Value) if not usi ng M otionApps software.
When self-test is activated, the on-board electronics will actuate the appropriate sensor. This
actuation simulates an external force. The actuated sensor, in turn, will produce a corresponding
output si gnal. The output signal is used to observe the self-test respon se.
The self-test r esponse (STR) is defined as foll ows:
= -
-
This self t est-r esponse is used to determine whether the part has passed or f ail ed self -test by fi nding
the change from factory trim of the self -test respon se a s follows:
- (%)=( )
where,
= ,
This change from factory trim of the self-test response must be withi n the limit s provided in the MP U-
6000/MPU-6050 Product Specifi cation document for the part t o pass self -test. Ot herwi se, t he part is
deem ed to have failed self-test.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 11 of 47
Obtaining the Accelero meter Factory Trim (FT) Value
If Inv enSense MotionApps soft ware i s not used, t he procedure detailed bel ow should be f oll owed to
obtain the Factory trim value of the self test response (FT) mentioned above. For the specific
regi ster s mentioned below, pl ease ref er to registers 13-16.
The Factory trim v alue of the self test response (FT ) i s calculated as shown below. FT[Xa], FT[ Ya],
and FT [Za] r efer to t he f actory trim (FT) values for the acc elerom eter X, Y, and Z axes, r espect ively.
In the equations below, the factory trim values for the accel should be in decimal format, and they
are determined by concatenating the upper accelerometer self test bits (bits 4-2) with the lower
accelerometer self t est bits (bits 1-0).
When performing accelerometer self t est , the full-scale rang e should be set to ±8g.
FT[Xa] = 4096 0.34 .
.
(_
) if XA_TEST ≠ 0.
FT[Xa] = 0 if XA_TEST = 0.
FT[Ya] = 4096 0.34 .
.
(_
) if YA_TEST ≠ 0.
FT[Ya] = 0 if YA_TEST = 0.
FT[Za] = 4096 0.34 .
.
(_
) if ZA_TEST ≠ 0.
FT[Za] = 0 if ZA_TEST = 0.
XA_TEST 5-bit unsigned value. FT[Xa] is determined by using this value as explained
above.
Parameters:
XG_TEST 5-bit unsigned value. FT[Xg] is determined by using this v alue as explained
above.
YA_TEST 5-bit unsigned value. FT[Ya] is determined by using this value as explained
above.
YG_TEST 5-bit unsigned value. FT[Yg] is determined by using this value as explained
above.
ZA_TEST 5-bit unsigned value. FT[Za] is determined by using this value as explained
above.
ZG_TEST 5-bit unsigned value. FT[Zg] is determined by using this value as explained
above.
4.2 Reg ister 25 – Sampl e Rat e Divider
SMPRT_DIV
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
19 25 SMPLRT_DIV[7:0]
Description:
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 12 of 47
Thi s register specif ies the divider from the gyroscope output rat e used to generat e the Sam pl e R at e
for the MPU-60X0.
The sensor register output, FIFO output, DMP sampling and Motion detection are all based on the
Sample Rate.
The Sam ple Rate is generated by div iding t he gyroscope output rat e by SMPLRT_DIV:
Sample Rate = Gyroscope Out put Rate / (1 + SMPLRT_DIV)
where Gyroscope Output Rate = 8kHz when the DLPF is disabled (DLPF_CFG = 0 or 7), and 1kHz
when the DLPF is enabled (see Regi ster 26) .
Note:
For a diagram of the gyroscope and accelerometer signal paths, see Section 8 of the MPU-
6000/MPU-6050 Product Specificati on doc um ent.
The accelerom eter output rate is 1kHz. T his means that for a Sam ple Rate great er than 1kHz,
the same accelerometer sample may be output to the FIFO, DMP, and sensor registers more than
once.
SMPLRT_DIV 8-bit unsigned value. The Sample Rate is determined by dividing the
gyroscope output rat e by this value.
Parameters:
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4.3 Reg ister 26 – Configuration
CONFIG
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1A 26 - - EXT_SYNC_SET[2:0] DLPF_CFG[2:0]
This register configures the external Frame Synchronization (FSYNC) pin sampling and the Digital
Low Pass Filter (DLPF) setting for both the gyroscopes and accel er om eters.
Description:
An ext er nal si gnal connec ted to the FSYNC pin can be sampled by configuring EXT_SYNC_SET.
Signal changes to the FSYNC pin are latched so that short strobes may be captured. The latched
FSYNC signal will be sampled at the Sampling Rate, as defined in register 25. After sampling, the
latch will r eset to the current FSYNC si gnal state.
The sampled value will be reported in place of the least significant bit in a sensor data register
determined by the value o f EXT_SYNC_SET according to the fo llow ing table.
EXT_SYNC_SET FSYNC Bit Location
0 Input disabled
1 TEMP_OUT_L[0]
2 GYRO_XOUT_L[0]
3 GYRO_YOUT_L[0]
4 GYRO_ZOUT_L[0]
5 ACCEL_XOUT_L[0]
6 ACCEL_YOUT_L[0]
7 ACCEL_ZOUT_L[0]
The DLPF is configured by DLPF_CFG. The accelerometer and gyroscope are filtered according to
the value o f DLPF_CFG as shown in t he table bel ow.
DLPF_CFG Accelerometer
(Fs = 1kHz) Gyroscope
Bandwidth
(Hz) Delay
(ms) Bandwidth
(Hz) Delay
(ms) Fs (kHz)
0 260 0 256 0.98 8
1 184 2.0 188 1.9 1
2 94 3.0 98 2.8 1
3 44 4.9 42 4.8 1
4 21 8.5 20 8.3 1
5 10 13.8 10 13.4 1
6 5 19.0 5 18.6 1
7 RESERVED RESERVED 8
Bi t 7 and bit 6 are reserved.
EXT_SYNC_SET 3-bit unsigned value . Configur es the FSYNC pin sampling.
Parameters:
DLPF_CFG 3-bit unsigned value. Configures t he DLPF setting.
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4.4 Reg ister 27 – Gyroscope Configuration
GYRO_CONFIG
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1B 27 XG_ST YG_ST ZG_ST FS_SEL[1:0] - - -
This register is used to tri gger gy r oscope self-test and configure t he gyroscopes’ full scal e r ange.
Description:
Gyroscope self-test permits users to test the mechanical and electrical portions of the
gyroscope. The self-test for each gyroscope axis can be activated by controlling the XG_ST,
YG_ST, and ZG_ST bit s of thi s regi ster. Self-test for each axi s m ay be perform ed independentl y
or all at t he same time.
When self-test is activated, the on-board electronics will actuate the appropriate sensor. This
actuation will move the sensor’s proof masses over a distance equivalent to a pre-defined
Coriolis force. This proof mass displacement results in a change in the sensor output, which is
reflected in the output signal. The out put signal is used to observe the self-test response.
The self-test r esponse is defi ned as follows:
Self-test response = Sensor output with self-test enabled – Sensor output without self-
test enabled
The self-test limits for each gyroscope axis is prov ided in the electrical characteristics tables of
the MPU-6000/MPU-6050 Product Specification document. When the value of the self-test
response is within the min/max limits of the product specification, the part has passed self test.
W hen the self-t est response ex ceeds the mi n/max values specif ied in the doc um ent, the part is
deem ed to have failed self-test.
FS_SEL select s the full scale r ange of the gyroscope outputs according to the following tabl e.
FS_SEL Full Scale Range
0 ± 250 °/s
1 ± 500 °/s
2 ± 1000 °/s
3 ± 2000 °/s
Bi ts 2 through 0 ar e r eserved.
XG_ST Setting this bit causes the X axis gyroscope to perform self test.
Parameters:
YG_ST Setting this bit causes the Y axis gyroscope to perform self test.
ZG_ST Setting this bit causes the Z ax is gyroscope to perform self test.
FS_SEL 2-bit unsigned value. Selects the full scale range of gyroscopes.
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4.5 Reg ister 28 – Accelerometer Configuration
ACCEL_CONFIG
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1C 28 XA_ST YA_ST ZA_ST AFS_SEL[1:0] -
This register is used to trigger accelerometer self test and configure the accelerometer full scale
range. This register also configur es the Digit al High P ass Fil ter (DHPF).
Description:
Accelerometer self-test permits users to test the mechanical and electrical portions of the
accel eromet er. The self -test f or each accelerometer axis can be activ ated by controlling the XA_ST,
YA_ST, and ZA_ST bits of this register. Self-test for each axis may be performed independently or
all at the same time.
When self-test is activated, the on-board electronics will actuate the appropriate sensor. This
actuation simulates an external force. The actuated sensor, in turn, will produce a corresponding
output si gnal. The output signal is used to observe the self-test respon se.
The self-test response is defi ned as follows:
Self-test response = Sensor output with self-test enabled – Sensor output without self-test
enabled
The self-test limits for each accelerometer axis is provided in the electrical characteristics tables of
the MP U-6000/MPU-6050 Product Specifi cati on document. W hen the v alue of t he self-test response
is within t he m in/max lim its of the produc t specif ication, the part has passed sel f test. When the sel f-
test response exceeds the min/max values specified in the document, the part is deemed to have
failed self -test.
AFS_SEL selects the full scale range of the ac c eler ometer outputs accor ding to the foll owing table.
AFS_SEL
Full Scale Range
0 ± 2g
1 ± 4g
2 ± 8g
3 ± 16g
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XA_ST When set t o 1, t he X- Axis accelerom eter performs self test.
Parameters:
YA_ST When set t o 1, t he Y- Axi s acceler om eter perf orms self test.
ZA_ST When set to 1, the Z- Axis acceleromet er perf orms self test.
AFS_SEL 2-bit unsigned value. Select s the full scale range of accelerometers.
4.6 Register 31 – Motion Detection Threshold
MOT_THR
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1F 31 MOT_THR[7:0]
This register configures the detection threshold for Motion interrupt generation. The mg per LSB
inc rem ent for MOT_THR can be found in the Electrical Specifications table of the MPU-6000/MPU-
6050 Product Specificati on doc um ent.
Description:
Moti on is detect ed when the absolute v alue of any of the accel eromet er m easurement s exceeds thi s
Motion detection threshold.
The Motion interrupt will indicate the axis and polarity of detected motion in MOT_DETECT
_STA TUS (Register 97).
For more details on the Motion detection interrupt, see Section 8.3 of the MPU-6000/MPU-6050
Product Specificati on doc um ent as wel l as Registers 5 6 and 58 of this document.
MOT_THR 8-bit unsigned value. Specifies the Motion detection threshold.
Parameters:
4.7 Reg ister 35 – FIFO Enable
FIFO_EN
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
23 35 TEMP_
FIFO_EN XG_
FIFO_EN YG_
FIFO_EN ZG_
FIFO_EN ACCEL
_FIFO_EN SLV2
_FIFO_EN SLV1
_FIFO_EN SLV0
_FIFO_EN
This register determines which sensor measurements are loaded i nto t he FIFO buffer.
Description:
Data stored inside the sensor data registers (Registers 59 to 96) will be loaded into the FIFO buffer if
a sensor’s respec tive FIFO_E N bit is set to 1 in thi s register.
W hen a sensor’s FIFO_EN bit is enabled in t hi s register, data f rom the sensor data registers will be
loaded i nt o the FIFO buff er. The sensor s are sam pl ed at t he Sample Rate as defi ned i n Register 25.
For further inf ormation r egar ding sensor data registers, please refer to Regi ster s 59 to 96
MPU-6000/MPU-6050 Register Map and
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W hen an external Slave’s corr esponding FI FO_EN bit (SLVx_FIFO_EN, where x= 0, 1, or 2) i s set to
1, the data stored in its corresponding data registers (EXT_SENS_DATA registers, Registers 73 to
96) will be written into the FIFO buffer at the Sample Rate. EXT_SENS_DATA register association
with I2C Slaves is determined by the I2C_SLVx_CTRL registers (where x=0, 1, or 2; Registers 39,
42, and 45). For information regarding EXT_SENS_DATA registers, please refer to Registers 73 to
96.
Note that the corresponding FIFO_EN bit (SLV3_FIFO_EN) is found in I2C_MST_CTRL (Register
36). Also note that Slave 4 behaves in a different manner compared to Slaves 0-3. Please refer to
Register s 49 to 53 for f urther information regarding Slav e 4 usage.
TEMP_FIFO_EN W hen set t o 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers
65 and 66) to be wri tt en into the FIFO buffer.
Parameters:
XG_ FIFO_EN When set to 1, this bit enables GYRO_XOUT_H and GYRO_XOUT_L
(Regi ster s 67 and 68) t o be wri tten into the FIF O buffer.
YG_ FIFO_EN When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L
(Regi ster s 69 and 70) t o be wri tten into the FIF O buffer.
ZG_ FIFO_EN When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L
(Regi ster s 71 and 72) t o be wri tten into the FIF O buffer.
ACCEL_ FIFO_EN W hen set to 1, this bi t enables ACCEL_XOUT_H, A CCEL_XOUT_L,
ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, and
ACCEL_Z OUT_L (Regi ster s 59 to 64) to be writt en into the FIFO buffer .
SLV2_ FIFO_EN When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to
96) associ ated with Sl av e 2 to be writt en into the FIFO buffer.
SLV1_ FIFO_EN When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to
96) associ ated with Sl av e 1 to be writt en into the FIFO buffer.
SLV0_ FIFO_EN When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to
96) associ ated with Sl av e 0 to be writt en into the FIFO buffer.
Note
: F or further information regarding the associ ati on of EXT_S E NS _DATA r egister s to par ticular
slave devices, please refer to Registers 73 to 96.
4.8 Reg ister 36 – I2C Mast er Con t rol
I2C_MST_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
24 36 MULT
_MST_EN WAIT
_FOR_ES SLV_3
_FIFO_EN I2C_MST
_P_NSR I2C_MST_CLK[3:0]
This register c onfigures the auxiliary I 2C bus for si ngle-master or mu lti-master c ontrol. In addition, the
register is used to delay the Data Ready interrupt, and also enables the writing of Slave 3 data into
the FIFO buff er. The regi ster also configur es the auxiliary I2C Master ’s transiti on from one sl av e read
to t he nex t, as well as the MPU-60X0’s 8MHz internal clock .
Description:
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
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Multi-master capability allows multiple I2C masters to operate on the same bus. In circuits where
multi-master capability is required, set MULT_MST_EN to 1. This will increase current drawn by
approximately 30µA.
In circuits where multi-master capability is required, the state of the I2C bus must always be
monitored by each separate I2C Master. Before an I2C Master can assume arbitration of the bus, it
m ust first confirm t hat no other I 2C Master has arbit ration of t he bus. W hen MULT_MST_EN i s set t o
1, the MPU-60X0’s bus arbitrati on detection logi c is turned on, enabl ing it to detect when the bus is
available.
When the WAIT_FOR_ES bit is set to 1, the Data Ready interrupt will be delayed until External
Sensor data f rom the Slave Dev i ces are loaded i nt o the EXT_SENS_DA TA registers. This is used to
ensure that both the internal sensor data (i.e. from gyro and accel) and external sensor data have
been loaded to their r espect ive data registers (i.e. the data is synced) when the Data Ready i nterrupt
is tri gger ed.
When the Slav e 3 FIF O enabl e bit (SLV_3_FIFO_EN) is set to 1, Sl av e 3 sensor m easurem ent dat a
will be loaded into the FIFO buffer each time. EXT_S ENS_DATA register associat ion wit h I 2C Slaves
is determi ned by I2C_S LV 3_CTRL (Register 48).
For further information regarding EXT_SENS_DATA registers, pl ease refer to Register s 73 to 96.
The cor r espondi ng FIFO _E N bits for Slave 0, Slave 1, and Slav e 2 can be found in Register 35.
The I2C_MST_P_NSR bit configures the I2C Master’s transition from one slave read to the next
slav e read. If the bit equal s 0, there will be a r estart betwee n reads. If the bit equal s 1, there wil l be a
stop followed by a start of the f ollowing read. When a writ e transact ion follows a read transaction, the
stop foll owed by a start of t he successive write will be always used.
MPU-6000/MPU-6050 Register Map and
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I2C_MST_CLK is a 4 bi t unsigned v alue which c onfigures a div i der on the M PU-60X0 int ernal 8MHz
cl oc k. It sets the I2C master clock speed according to the following t able:
I2C_MST_CLK I2C Master Clock
Speed 8MHz Clock
Divider
0 348 kH z 23
1 333 kH z 24
2 320 kH z 25
3 308 kH z 26
4 296 kH z 27
5 286 kH z 28
6 276 kH z 29
7 267 kH z 30
8 258 kH z 31
9 500 kH z 16
10 471 kHz 17
11 444 kHz 18
12 421 kHz 19
13 400 kHz 20
14
381 kH z 21
15 364 kHz 22
MUL_MST_EN When set to 1, this bit enables multi-master c apability .
Parameters:
WAIT_FOR_ES When set to 1, this bit delays the Data Ready interrupt until External Sensor
data from the Slave devices have been loaded into the EXT_SENS_DATA
registers.
SLV3_FIFO_EN When set to 1, this bit enables EXT_SENS_DATA registers associated with
Sla ve 3 to be wri tt en into the FIFO. The cor r espondi ng bit s for Sl av es 0-2 can
be found i n Register 35.
I2C_MST_P_NSR Controls the I2C Master’s transition from one slave read to the next slave
read.
When this bit equal s 0, there is a restart between reads.
When t his bi t equal s 1, there i s a stop and star t m arki ng the begi nni ng of the
next read.
When a wr ite follows a r ead, a stop and start is always enf or c ed.
I2C_MST_CLK 4 bit unsigned value. Confi gur es the I2C master c lock speed divider.
Note
: F or further information regarding the associ ati on of EXT_S E NS _DATA r egister s to par ticular
slave devices, please refer to Registers 73 to 96.
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4.9 Reg isters 37 to 39 – I2C Slave 0 Control
I2C_SLV0_ADDR, I2C_S LV0_REG, and I2C_S LV0_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
25 37 I2C_SLV0
_RW I2C_SLV0_ADDR[6:0]
26 38 I2C_SLV0_REG[7:0]
27 39 I2C_SLV0
_EN
I2C_SLV0
_BYTE
_SW
I2C_SLV0_
REG_DIS I2C_SLV
0_GRP I2C_SLV0_LEN[3:0]
These regi ster s configure the data transfer sequence for Slave 0. Slaves 1, 2, and 3 also behave in a
simil ar manner to Sl av e 0. Howev er , Slav e 4’s character isti cs diff er greatl y from those of Sl aves 0-3.
For further inf ormation r egar ding Sl ave 4, please refer to registers 49 to 53.
Description:
I2C slave data transactions between the MPU-60X0 and Slave 0 are set as either read or write
operations by the I2C_SLV0_RW bit. When thi s bit is 1, the t r ansfer is a read operation. When the bit
is 0, the transf er i s a write operat ion.
I2C_SLV0_ADDR i s used t o specify the I 2C sl av e address of Sl av e 0.
Data transf er sta rt s at an internal register within Slav e 0 . T h is address of t hi s register is specifi ed by
I2C_SLV0_REG.
The number of bytes transferred is specified by I2C_SLV0_LEN. When more than 1 byte is
transferred (I2C_SLV0_LEN > 1), data is read from (written to) sequential addresses starting from
I2C_SLV0_REG.
In read m ode, the result of the read i s pl aced in t he l owest av ail able EXT_S ENS_DATA regi ster. F or
further information regarding the allocation of read results, please refer to the EXT_SENS_DATA
regi ster descript ion (Register s 73 – 96).
In write mode, the c ontent s of I2C_SLV0_DO (Regi ster 99) will be written to the slave devic e.
I2C_SLV0_EN enabl es Slav e 0 for I2C data transaction. A data t ransacti on i s perf ormed only if more
than zero bytes are to be transferred (I2C_SLV0_LEN > 0) between an enabled slave device
(I2C_SLV0_EN = 1).
I2C_SLV0_BYTE_SW configur es byte swapping of wo rd pairs. W hen byte swappi ng is enabled, the
high and low bytes of a word pair are swapped. Please refer to I2C_SLV0_GRP for the pairing
conv ention of the word pairs. When this bit is clear ed to 0, bytes transf erred to and f rom Sl av e 0 will
be written to EXT_SENS _DA TA r egister s i n the order they wer e transferred.
When I2C_SLV0_REG_DIS i s set to 1, t he transacti on wil l read or write data only. W hen cl eared to
0, t he transact ion will wri te a register address pri or to reading or wri ti ng dat a. T his bit should equal 0
when specifying the register address within the Slave device to/from which the ensuing data
transact ion will take pl ac e.
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I2C_SLV0_GRP specif ies the groupi ng order of word pai rs received from register s. When cleared t o
0, bytes from r egister addr esses 0 and 1, 2 and 3, et c (ev en, then odd regi ster addr es se s) are paired
to form a word. W hen set to 1, bytes from register addresses are paired 1 and 2, 3 and 4, etc. (odd,
then even register addr esses) are paired t o form a word.
I2C data transactions are performed at the Sample Rate, as defined in Register 25. The user is
responsible for ensuring that I2C data transactions to and from each enabled Slave can be
completed within a single per iod of the Sample Rat e.
The I2C slave access rate can be reduced relative to the Sam ple Rate. This reduced access rate is
determ ined by I2C_MST_DLY (Regi ster 52) . W hether a slav e’s access rate is reduced relative t o the
Sample Rate is determined by I2C_MST_DELAY_CTRL (Regi ster 103) .
The processing order for the slaves is fixed. The sequence followed for processing the slaves is
Sl av e 0, Slav e 1, Slav e 2, Slave 3 and Slave 4. If a particular Slave is disabl ed it will be skipped.
Each slave can either be accessed at the sam pl e rat e or at a reduced sampl e rat e. In a case where
some slaves are accessed at the Sample Rate and some slaves are accessed at the reduced rate,
the sequence of acc essing the slaves (Slave 0 to Slave 4) is still followed. However , t he r educ ed r ate
slaves will be skipped if their access rate dictates that they should not be accessed during that
particular cycle. For further inform ation regarding the reduced access rate, please ref er to Register
52. Whether a slave is accessed at the Sample Rate or at the reduced rate is determined by the
Delay E nable bits in Register 103.
I2C_SLV0_RW When set to 1, this bit configures the dat a transfer as a read operat ion.
Parameters:
When cleared to 0, this bi t configures the dat a transfer as a write oper ati on.
I2C_SLV0_ADDR 7-bit I2C address of Sl av e 0.
I2C_SLV0_REG 8-bit address of the Slave 0 register to/from which data transfer starts.
I2C_SLV0_EN When set t o 1, t his bi t enables Slav e 0 for data tr ansfer operat ions.
When cleared to 0, this bi t disables Sl av e 0 from data transfer oper ations.
I2C_SLV0_BYTE_SW When set to 1, this bit enables byte swapping. When byte swapping is
enabled, the hi gh and low bytes of a word pair are swapped. P lease ref er to
I2C_SLV0_GRP for the pairing conv ention of the word pairs.
When cleared to 0, bytes transferred to and from Slave 0 will be written to
EXT_SENS _DA TA register s i n the order they wer e transferred.
I2C_SLV0_REG_DIS When set to 1, the transaction will read or wri te data only.
When cleared to 0, the transaction will write a register address prior to
readi ng or wri ting data.
I2C_SLV0_GRP 1-bit value specifying the grouping order of word pairs received from
registers. When cleared to 0, bytes from register addresses 0 and 1, 2 and
3, etc (even, then odd register addresses) are pai red to f orm a word. When
set to 1, bytes from register addresses are paired 1 and 2, 3 and 4, etc.
(odd, then even register addr esses) are paired t o form a word.
I2C_SLV0_LEN 4-bit unsi gned v al ue. Specifies the number of bytes transferred to and from
Sl av e 0.
Clearing this bit to 0 is equivalent to disabling the register by writing 0 to
I2C_SLV0_EN.
MPU-6000/MPU-6050 Register Map and
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Docum ent Num b er : RM-MPU-6000A-00
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Byte Sw app in g Example
The following example demonstrates byte swapping for I2C_SLV0_BYTE_SW = 1,
I2C_SLV0_GRP = 0 , I2C_SLV0_REG = 0x 01, and I2C_SLV0_LEN = 0x4:
1. T he fi rst byte, read f rom Slave 0 register 0x01, will be stored at EXT_SE NS_DATA_00. Because
I2C_SLV0_GRP = 0, bytes from even, then odd register addresses will be paired together as
word pairs. Since the read operation started from an odd register address instead of an even
address, only one byte is read.
2. The second and third bytes will be swapped, since I2C_SLV0_BYTE_SW = 1 and
I2C_SLV0_REG[0] = 1. The data read from 0x02 will be stored at EXT_SENS_DATA_02, and
the dat a r ead from 0x03 will be stored at E XT_S E NS _DATA _01.
3. The last by te, read fr om addr ess 0x04, will be stored at EXT_S E NS _DA TA_03. Bec ause ther e is
only one by te rem aining in the read operation, byte swapping will not occur.
Slave 0 is accessed at the Sample Rate, while Slave 1 is accessed at half the Sample Rate. The
other slav es are disabled. In the fi rst cy cl e, both Slav e 0 and Sl av e 1 will be accessed. Howev er, in
the second cycle, only Slav e 0 will be accessed. I n the thi rd cycl e, both Slave 0 and Slave 1 will be
accessed. In the fourth cycle, only Sl av e 0 will be ac c essed. This patter n c ontinues.
Slave Access Example
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4.10 Registers 40 t o 42 – I2C Slave 1 Control
I2C_SLV1_ADDR, I2C_S LV1_REG, and I2C_S LV1_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
28 40 I2C_SLV1
_RW I2C_SLV1_ADDR[6:0]
29 41 I2C_SLV1_REG[7:0]
2A 42 I2C_SLV1
_EN
I2C_SLV1
_BYTE
_SW
I2C_SLV1_
REG_DIS I2C_SLV
1_GRP I2C_SLV1_LEN[3:0]
These regi sters descri be t he data transf er sequence for Slav e 1. Their functi ons c orrespond to t hose
described for the Slav e 0 regi ster s (Registers 37 to 39).
Description:
4.11 Registers 43 t o 45 – I2C Slave 2 Control
I2C_SLV2_ADDR, I2C_S LV2_REG, and I2C_S LV2_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
2B 43 I2C_SLV2
_RW I2C_SLV2_ADDR[6:0]
2C 44 I2C_SLV2_REG[7:0]
2D 45 I2C_SLV2
_EN
I2C_SLV2
_BYTE
_SW
I2C_SLV2_
REG_DIS I2C_SLV
2_GRP I2C_SLV2_LEN[3:0]
These regi sters descri be t he data transf er sequence for Slave 2. Their functions corr espond to those
described for the Slav e 0 regi ster s (Registers 37 to 39).
Description:
4.12 Registers 46 t o 48 – I2C Slave 3 Control
I2C_SLV3_ADDR, I2C_S LV3_REG, and I2C_S LV3_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
2E 46 I2C_SLV3
_RW I2C_SLV3_ADDR[6:0]
2F 47 I2C_SLV3_REG[7:0]
30 48 I2C_SLV3
_EN
I2C_SLV3
_BYTE
_SW
I2C_SLV3_
REG_DIS I2C_SLV
3_GRP I2C_SLV3_LEN[3:0]
These regi sters descri be t he data transf er sequence for Slave 3. Their functions corr espond to those
described for the Slav e 0 regi ster s (Registers 37 to 39).
Description:
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
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4.13 Reg isters 49 to 53 – I2C Slave 4 Control
I2C_SLV4_ADDR, I2C_S LV4_REG, I2C_SLV4_DO, I2C_SLV4_CTRL, and I2C_SLV4_DI
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
31 49 I2C_SLV4
_RW I2C_SLV4_ADDR[6:0]
32 50 I2C_SLV4_REG[7:0]
33 51 I2C_SLV4_DO[7:0]
34 52 I2C_SLV4_
EN I2C_SLV4
_INT_EN I2C_SLV4
_REG_DIS I2C_MST_DLY[4:0]
35 53 I2C_SLV4_DI[7:0]
These regi sters descri be t he data transf er sequence f or Slave 4. The char acteri stics of Slave 4 diff er
greatly from those of Sl av es 0-3. For further inform ation regarding the characteristics of Slaves 0-3,
please refer to Registers 37 to 48.
Description:
I2C slave data transactions between the MPU-60X0 and Slave 4 are set as either read or write
operations by the I2C_SLV4_RW bit. When this bit is 1, the transfer is a read operati on. When the bit
is 0, the transf er i s a write operat ion.
I2C_SLV4_ADDR i s used t o specify the I 2C sl av e address of Sl av e 4.
Data transfer starts at an internal register within Slave 4. This register address is specified by
I2C_SLV4_REG.
In read m ode, the result of the r ead wi ll be avail able i n I2C_SLV4_DI. In wri te m ode, the cont ents of
I2C_SLV4_DO will be written into the slave devic e.
A data transaction is perf orm ed only if the I2C_SLV4_EN bit i s set to 1. The data transaction should
be enabled once its parameters are configured in the _ADDR and _REG registers. For write, the
_DO register is also required. I2C_SLV4_EN will be clear ed after the transaction is performed once.
An interrupt is triggered at the completion of a Slave 4 data transaction if the interrupt is enabled .
The stat us of this int er r upt can be observed in Register 54.
When I2C_SLV4_REG_DIS is set to 1, the transaction will read or write data instead of writing a
register address. This bit should equal 0 when specifying the register address within the Slave
devi c e to/from which t he ensui ng data transacti on will take place.
I2C_MST_DLY configures the reduced access rate of I2C slaves relativ e to the Sample Rate. When
a slave’s access rat e is decreased relative to the Sam ple Rate, the slav e is accessed every
1 / (1 + I2C_MST_DLY) sa mpl es
This base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and DLPF_CFG
(regi ster 26). Whet her a slav e’s access rate i s reduced rel ative t o the Sampl e Rate is determi ned by
I2C_MS T_DELAY _CTRL (r egister 103) .
For further inf ormation r egar ding the Sample Rate, please ref er to register 25.
Slave 4 transactions are performed after Slave 0, 1, 2 and 3 transactions have been completed.
Thus the maximum rate for Slave 4 transactions is determined by the Sample Rate as defined in
Register 25.
MPU-6000/MPU-6050 Register Map and
Descriptions
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Revision: 4.0
Release Date: 03/09/2012
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I2C_SLV4_RW When set to 1, this bit configures the dat a transfer as a read operat ion.
When clear ed to 0, this bit configures the data transfer as a writ e oper ation.
Parameters:
I2C_SLV4_ADDR 7-bit I2C address f or Sl av e 4.
I2C_SLV4_REG 8-bit addr ess of the Slav e 4 r egister to/from which dat a transfer starts.
I2C_SLV4_DO T his register stor es the data to be written into the Slave 4.
If I2C_SLV4_RW is set 1 (set to read), this register has no effect.
I2C_SLV4_EN When set t o 1, t his bi t enables Slav e 4 for data tr ansfer operat ions.
When clear ed to 0, this bit disables Slav e 4 from data transfer oper ati ons.
I2C_SLV4_INT_EN When set to 1, this bi t enables the generation of an interrupt si gnal upon
completion of a Slave 4 transaction.
When clear ed to 0, this bit disables the generat ion of an inter r upt signal
upon completion of a Slave 4 transaction.
The interrupt status can be observed in Regi ster 54.
I2C_SLV4_REG_DIS When set to 1, the transaction will read or wri te data.
When clear ed to 0, the transaction will read or write a register addr es s.
I2C_MST_DLY Configures the decr eased acces s rat e of sl av e devi c es relative to the
Sample Rate.
I2C_SLV4_DI T his register stor es the data read from Sl av e 4.
This fi eld is populated after a read tr ansact ion.
MPU-6000/MPU-6050 Register Map and
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4.14 Reg ister 54 – I2C Master St atus
I2C_MST_STATUS
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
36 54 PASS_
THROUGH I2C_SLV4
_DONE I2C_LOST
_ARB I2C_SLV4
_NACK I2C_SLV3
_NACK I2C_SLV2
_NACK I2C_SLV1
_NACK I2C_SLV0
_NACK
This register shows the status of the interrupt generating signals in the I2C Master within the MPU-
60X0. This regi ster also comm unicates the stat us of the FSYNC interrupt to t he host pr oc essor.
Description:
Reading thi s register will clear all the status bits i n the register .
PASS_THROUGH This bit reflects the status of the FSYNC interrupt from an external device
into the MPU-60X0. This is used as a way to pass an external interrupt
through t he MPU-60X0 to the host appli cation processor. When set to 1, thi s
bit will cause an interrupt if FSYNC_INT_EN is asserted in INT_PIN_CFG
(Regi ster 55) .
Parameters:
I2C_SLV4_DONE Automatically sets to 1 when a Slave 4 transaction has completed. This
tri ggers an interrupt if the I2C_MST_INT_EN bit i n the I NT_ENA BLE regi ster
(Register 56) is asserted and if the SLV_4_DONE_INT bit i s asserted in the
I2C_SLV 4_CTRL register (Register 52).
I2C_LOST_ARB T his bit aut omati cally sets to 1 when the I2C Master has lost arbi tr ation of the
auxiliary I2C bus (an error condition). This triggers an interrupt if the
I2C_MST_INT_EN bit i n the INT_E NA B LE register (Register 56) is asserted.
I2C_SLV4_NACK This bit automatically sets to 1 when the I2C Master receives a NACK in a
transaction with Slave 4. This triggers an interrupt if the I2C_MST_INT_EN
bit in the INT_ENAB LE register (Register 56) is asserted.
I2C_SLV3_NACK This bit automatically sets to 1 when the I2C Master receives a NACK in a
transaction with Slave 3. This triggers an interrupt if the I2C_MST_INT_EN
bit in the INT_ENAB LE register (Register 56) is asserted.
I2C_SLV2_NACK This bit automatically sets to 1 when the I2C Master receives a NACK in a
transaction with Slave 2. This triggers an interrupt if the I2C_MST_INT_EN
bit in the INT_ENAB LE register (Register 56) is asserted.
I2C_SLV1_NACK This bit automatically sets to 1 when the I2C Master receives a NACK in a
transaction with Slave 1. This triggers an interrupt if the I2C_MST_INT_EN
bit in the INT_ENAB LE register (Register 56) is asserted.
I2C_SLV0_NACK This bit automatically sets to 1 when the I2C Master receives a NACK in a
transaction with Slave 0. This triggers an interrupt if the I2C_MST_INT_EN
bit in the INT_ENAB LE register (Register 56) is asserted.
MPU-6000/MPU-6050 Register Map and
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4.15 Reg ister 55 – I NT Pin / Bypass Enable Con f igurat ion
INT_PIN_CFG
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
37 55 INT_LEVEL INT_OPEN LATCH
_INT_EN INT_RD
_CLEAR FSYNC_
INT_LEVEL FSYNC_
INT_EN
I2C
_BYPASS
_EN -
This register configures the behavior of the interrupt signals at the INT pins. This register is also
used to enable the FSYNC Pin to be used as an interrupt to the host application processor, as well
as to enable Bypass Mode on t he I2C M aster . This bit also enabl es the c lock output.
Description:
FSYNC_INT_EN enables the FSYNC pin to be used as an interrupt to the host application
processor. A transition to the active level specified in FSYNC_INT_LEVEL will trigger an interrupt.
The status of this interrupt is read from the PASS_THROUGH bit i n the I2C Master Status Register
(Regi ster 54) .
When I2C_BYPASS_EN is equal t o 1 and I2C_MST_EN (Register 106 bit[5]) is equal to 0, the host
application processor will be able to directly access the auxiliary I2C bus of the MPU-60X0. When
this bit is equal to 0, the host appli c ation processor will not be able to directly ac c ess the auxiliar y I2C
bus of the MPU-60X0 regardless of the state of I2C_MST_EN.
For f urther information regarding Bypass Mode, please refer to Section 7.11 and 7.13 of the MPU-
6000/MPU-6050 Product Specificati on doc um ent.
INT_LEVEL When this bit is equal to 0, the logic lev el for the INT pin is active high.
Parameters:
When this bit is equal to 1, the logic lev el for the INT pin is activ e low.
INT_OPEN When this bit is equal to 0, the INT pin is configur ed as push-pull.
When this bit is equal to 1, the INT pin is configur ed as open drain.
LATCH_INT_EN When this bit is equal to 0, the INT pin emits a 50us long pul se.
When this bit is equal to 1, the INT pin is hel d high until t he interrupt is
cleared.
INT_RD_CLEAR When this bit is equal to 0, interrupt status bits are cleared only by reading
INT _S TATUS (Register 58)
When this bit is equal to 1, int er r upt status bits are cleared on any read
operation.
FSYNC_INT_LEVEL When this bit is equal to 0, the logic level for the FSYNC pin (when used as
an interrupt t o the host proc essor) i s act ive high.
When thi s bi t is equal to 1, the logic lev el f or t he FSY NC pin ( when used as
an interrupt t o the host proc essor) i s act ive low.
FSYNC_INT_EN When equal to 0, this bit disabl es the FSYNC pin from causing an inter r upt t o
the host proc es sor.
When equal to 1, this bit enables the FSYNC pin to be used as an i nterrupt to
the host proc es sor.
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I2C_BYPASS_EN When thi s bi t is equal to 1 and I2C_MST_EN (Regi ster 106 bit[5]) is equal to
0, t he host application processor wi ll be able to directly access the aux iliary
I2C bus of the MPU-60X0.
When this bit i s equal to 0, the host applicati on pr oc essor will not be able to
dir ec tly access the auxiliary I2C bus of t he MPU-60X0 regardless of the state
of I2C_MST_EN (Register 106 bit[5]).
4.16 Reg ister 56 – Int errup t Enabl e
INT_ENABLE
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
38 56 MOT_EN FIFO
_OFLOW
_EN
I2C_MST
_INT_EN - - DATA
_RDY_EN
This register enables interr upt generati on by i nterrupt sources.
Description:
For information regarding the interrupt status for each interrupt generation source, please refer to
Register 58. Further information regarding I2C Master int errupt generation can be found i n Register
54.
Bits 2 and 1 are reserved.
MOT_EN When set t o 1, t his bi t enables Motion detection to generate an interrupt .
Parameters:
FIFO_OFLOW_EN When set to 1, this bit enables a FIFO buffer overflow to generate an
interrupt.
I2C_MST_INT_EN When set to 1, this bit enables any of the I2C Master interrupt sources to
generate an int er r upt.
DATA_RDY_EN When set to 1, this bit enables the Data Ready interrupt, which occurs each
time a wri te operation to all of the sensor registers has been completed.
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4.17 Reg ister 58 – Int errup t Status
INT_STATUS
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
3A 58 - MOT_INT - FIFO
_OFLOW
_INT
I2C_MST
_INT - - DATA
_RDY_INT
This register shows the interrupt status of each interrupt generation source. Each bit will clear after
the register is read.
Description:
For information regarding the corr espondi ng interrupt enable bit s, please ref er to Register 56.
For a list o f I2C Master interrupts, please refer to Register 54.
Bits 2 and 1 are reserved.
MOT_INT This bit automatically sets to 1 when a Motion Detection interrupt has been
generated.
Parameters:
The bit cl ear s to 0 aft er the register has been read.
FIFO_OFLOW_INT This bit automatically sets to 1 when a FIFO buffer overflow interrupt has
been generated.
The bit cl ear s to 0 aft er the register has been read.
I2C_MST_INT This bit automatically sets to 1 when an I2C Master interrupt has been
generated. For a list of I 2C Master int er r upts, please refer to Register 54.
The bit cl ear s to 0 aft er the register has been read.
DATA_RDY_INT T his bit aut om atically sets to 1 when a Data Ready inte rrupt is generated.
The bit cl ear s to 0 aft er the register has been read.
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4.18 Reg isters 59 to 64 – Acceleromet er M easurement s
ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, and
ACCEL_ZOUT_L
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
3B 59 ACCEL_XOUT[15:8]
3C 60 ACCEL_XOUT[7:0]
3D 61 ACCEL_YOUT[15:8]
3E 62 ACCEL_YOUT[7:0]
3F 63 ACCEL_ZOUT[15:8]
40 64 ACCEL_ZOUT[7:0]
These regi ster s store the most recent accelero meter measurements.
Description:
Accelerometer measurements are written to these registers at the Sample Rate as defined in
Register 25.
The accelerometer measurement registers, along with the temperature measurement registers,
gyroscope measurement registers, and external sensor data registers, are composed of two sets of
registers: an inter nal r egister set and a user-facing r ead regi ster set.
The data within the accelerometer sensors’ internal register set is always updated at the Sample
Rate. Meanwhile, the user-facing read register set duplicates the internal register set’s data values
whenev er the serial interface is idle. This guarantees that a burst read of sensor registers will read
measurements from the same sampling instant. Note that if burst reads are not used, the user is
responsible for ensuring a set of single byte reads correspond to a single sampling instant by
checking t he Data Ready interrupt.
Each 16-bit accelerometer measurement has a full scale defined in ACCEL_FS (Register 28). For
each full scal e setti ng, the accelerometers’ sensitivity per LSB in ACCEL_xOUT is shown i n the table
below.
AFS_SEL Full Scale Range LSB Sensitivity
0 ±2g 16384 LSB/g
1 ±4g 8192 LSB/ g
2 ±8g 4096 LSB/ g
3 ±16g 2048 LSB/g
ACCEL_XOUT 16-bit 2’s complement value.
Parameters:
Stores the most recent X ax is accelerometer measurement.
ACCEL_YOUT 16-bit 2’s com plement value.
Stores the most recent Y axis accel er om eter measurement.
ACCEL_ZOUT 16-bit 2’s complement value.
Stores the most recent Z axis accelerometer measurement.
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4.19 Registers 65 and 66 – Temperature Measurement
TEMP_OUT_H and TEMP_OUT_L
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
41 65 TEMP_OUT[15:8]
42 66 TEMP_OUT[7:0]
These regi ster s store the most recent temperature sensor measurement.
Description:
Temper ature m easurement s are wri tten t o these regi sters at the S am ple Rate as defi ned i n Register
25.
These temperature measurement registers, along with the accelerometer measurement registers,
gyroscope measurement registers, and external sensor data registers, are composed of two sets of
regi ster s: an int er nal r egister set and a user-facing r ead regi ster set.
The dat a wi thi n the temperature sensor’s i nternal regi ster set i s always updated at t he S am p le Rate.
Meanwhile, the user-facing read register set duplicates the internal register set’s data values
whenev er the serial interface is idle. This guarantees that a burst read of sensor registers will read
measurements from the same sampling instant. Note that if burst reads are not used, the user is
responsible for ensuring a set of single byte reads correspond to a single sampling instant by
checking t he Data Ready interrupt.
The scal e f actor and off set f or the tem perat ure sensor are f ound in the Electr ical Specif icati ons table
(Section 6.4 o f the MPU-6000/MPU-6050 P r oduc t Specification document ).
The t em per ature in degrees C for a giv en regi ster v alue may be com puted as:
Temper ature in degrees C = (TE MP_O UT Register Value as a signed quant ity ) /340 + 36.53
Pl ease note that the math in the above equation is in decimal.
TEMP_OUT 16-bit signed value.
Parameters:
Stor es the m ost r ec ent temperature sensor measurement.
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4.20 Reg isters 67 to 72 – Gyroscop e M easurements
GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H, GYRO_YOUT_L, GYRO_ZOUT_H, and
GYRO_ZOUT_L
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
43 67 GYRO_XOUT[15:8]
44 68 GYRO_XOUT[7:0]
45 69 GYRO_YOUT[15:8]
46 70 GYRO_YOUT[7:0]
47 71 GYRO_ZOUT[15:8]
48 72 GYRO_ZOUT[7:0]
These regi ster s store the most recent gyroscope measurements.
Description:
Gyroscope measurements are written to these registers at the Sample Rate as defined in Register
25.
These gyroscope measurement registers, along with the accelerometer measurement registers,
temperature measurement regis ters, and external sensor data registers, are com posed of two sets of
regi ster s: an int er nal r egister set and a user-facing r ead regi ster set.
The data within the gyroscope sensors’ internal register set is always updated at the Sample Rate.
Meanwhile, the user-facing read register set duplicates the internal register set’s data values
whenev er the serial interface is idle. This guarantees that a burst read of sensor registers will read
measurements from the same sampling instant. Note that if burst reads are not used, the user is
responsible for ensuring a set of single byte reads correspond to a single sampling instant by
checking t he Data Ready interrupt.
Each 16-bit gyroscope measurem ent has a f ull scale defined in FS_SEL (Regi ster 27). F or each full
scale sett ing, the gyr oscopes’ sen si tivity per LSB i n GYRO_xOUT is sh own in the t able below:
FS_SEL Full Scale Range LSB Sensitivity
0 ± 250 °/s 131 LSB/°/s
1 ± 500 °/s 65. 5 LSB / ° /s
2 ± 1000 °/s 32.8 LS B/ ° /s
3 ± 2000 °/s 16.4 LS B/ ° /s
GYRO_XOUT 16-bit 2’s compl em ent value.
Parameters:
Stor es the m ost r ec ent X ax is gyroscope measurem ent.
GYRO_YOUT 16-bit 2’s com plement value.
Stor es the m ost r ec ent Y axis gyroscope measurem ent.
GYRO_ZOUT 16-bit 2’s complement value.
Stor es the m ost r ec ent Z axi s gyroscope measurement.
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4.21 Reg isters 73 to 96 – E xt ernal Sensor Data
EXT _S E NS _DATA_00 through EXT _SENS_DATA_23
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
49 73 EXT_SENS_DATA_00[7:0]
4A 74 EXT_SENS_DATA_01[7:0]
4B 75 EXT_SENS_DATA_02[7:0]
4C 76 EXT_SENS_DATA_03[7:0]
4D 77 EXT_SENS_DATA_04[7:0]
4E 78 EXT_SENS_DATA_05[7:0]
4F 79 EXT_SENS_DATA_06[7:0]
50 80 EXT_SENS_DATA_07[7:0]
51 81 EXT_SENS_DATA_08[7:0]
52 82 EXT_SENS_DATA_09[7:0]
53 83 EXT_SENS_DATA_10[7:0]
54 84 EXT_SENS_DATA_11[7:0]
55 85 EXT_SENS_DATA_12[7:0]
56 86 EXT_SENS_DATA_13[7:0]
57 87 EXT_SENS_DATA_14[7:0]
58 88 EXT_SENS_DATA_15[7:0]
59 89 EXT_SENS_DATA_16[7:0]
5A 90 EXT_SENS_DATA_17[7:0]
5B 91 EXT_SENS_DATA_18[7:0]
5C 92 EXT_SENS_DATA_19[7:0]
5D 93 EXT_SENS_DATA_20[7:0]
5E 94 EXT_SENS_DATA_21[7:0]
5F 95 EXT_SENS_DATA_22[7:0]
60 96 EXT_SENS_DATA_23[7:0]
These registers stor e data read from ext ernal sensor s by the Slave 0, 1, 2, and 3 on the auxili ar y I2C
interface. Data read by Slave 4 is stored i n I2C_SLV 4_DI (Regi ster 53) .
Description:
Ext ernal sensor data is wri tten to these registers at the Sample Rate as defi ned i n Regi st er 25. This
access rat e c an be r educ ed by usi ng the Slave Delay Enable registers (Register 103).
External sensor data registers, along with the gyroscope measurement registers, accelerometer
measurement registers, and temperature measurement registers, are composed of two sets of
regi ster s: an int er nal r egister set and a user-facing r ead regi ster set.
The data within the external sensors’ internal register set is always updated at the Sample Rate (or
the reduced access rate) whenev er the serial interface is idle. This guarantees that a burst read of
sensor regi sters will read m easurement s from the same sampling instant. Note that if burst reads are
not used, the user is responsible for ensuring a set of single byte reads correspond to a single
sampling i nstant by checking t he Data Ready interrupt.
Data is placed in these external sensor data registers according to I2C_SLV0_CTRL,
I2C_SLV1_CTRL, I2C_SLV2_CTRL, and I2C_SLV3_CTRL (Registers 39, 42, 45, and 48). When
m ore than zero byt es are read (I2C_SLVx_LEN > 0) f rom an enabl ed slav e (I2C_SLVx_EN = 1), the
slav e i s read at the Sample Rat e (as defi ned in Register 25) or delayed rat e (if specifi ed i n Regi ster
52 and 103). During each S ampl e cy cle, slav e reads are performed in order of Slave number. If all
slaves are enabled wit h m or e than zero by tes to be read, the order will be Sl av e 0, followed by Slave
1, Slave 2, and Slav e 3.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 34 of 47
Each enabled slave will have EXT_SENS_DA TA registers associat ed with it by num ber of bytes read
(I2C_SLVx_LEN) in order of slave number, starting from EXT_SENS_DATA_00. Note that this
m eans enabl ing or di sabling a slav e m ay change the higher numbered slaves’ associat ed registers.
Furthermore, if fewer total bytes are being read from the external sensors as a result of such a
change, then the data remaining in the registers which no longer have an associated slave device
(i .e. hi gh num ber ed r egisters) will remain i n these prev iousl y allocated registers unless reset.
If the sum of the read lengths of all SLVx transactions exceed the number of available
EXT_SENS_DATA registers , the excess bytes will be dropped. There are 24 EXT_SENS_DATA
regi sters and hence the t otal read l engths between all the slav es cannot be great er t han 24 or some
bytes wil l be lost.
Note
: Slave 4’s behavior is distinct from that of Slaves 0-3. For further information regarding the
characteristics of Slav e 4, please refer to Regi ster s 49 to 53.
Suppose that Slav e 0 is enabled with 4 bytes to be re ad (I2C_SLV0_EN = 1 and I2C_SLV0_LEN =
4) while Slave 1 is enabled with 2 bytes to be read, (I2C_SLV1_EN=1 and I2C_SLV1_LEN = 2). In
such a situation, EXT_SENS_DATA _00 through _03 will be associated with Slave 0, while
EXT_SENS _DA TA _04 and 05 will be associat ed with Slave 1.
Example:
If Slav e 2 is enabled as well , registers start ing f rom EXT_SENS_DA TA_06 will be all ocat ed to Sl av e
2.
If Slave 2 is disabled while Slave 3 is enabled in this same situation, then registers starting from
EXT_SENS _DA TA_06 will be allocat ed to Slav e 3 instead.
If a slave is disabled at any time, the space initially allocated to t he slave i n the EXT_SENS_DATA
register, will remain associated with that slave. This is to avoid dynamic adjustment of the register
allocation.
Register Allocation for Dynamic Disable vs. Normal Disable
The allocation of the EXT_SENS_DATA registers is recomputed only when (1) all slaves are
disabled, or (2) the I2C_MST_RST bit is set (Register 106).
This above is also true if one of t he sl av es gets NACKed and stops functi oning.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 35 of 47
4.22 Register 99 – I2C Slave 0 Data Out
I2C_SLV0_DO
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
63 99 I2C_SLV0_DO[7:0]
This register holds the output data written into Sl av e 0 whe n S lave 0 is set to write mode.
Description:
For further inf ormation r egar ding Sl ave 0 control, please r efer t o Register s 37 to 39.
I2C_SLV0_DO 8 bi t unsigned value that i s written int o Sl ave 0 when Slave 0 is set to write
mode.
Parameters:
4.23 Register 100 – I2C Slave 1 Data Out
I2C_SLV1_DO
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
64 100 I2C_SLV1_DO[7:0]
This register holds the output data writ ten into Sl av e 1 when Sl av e 1 is set to wri te mode.
Description:
For further inf ormation r egar ding Sl ave 1 control, please r efer t o Register s 40 to 42.
I2C_SLV1_DO 8 bit unsigned v alue t hat is written into Slave 1 when Sl av e 1 is set to write
mode.
Parameters:
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 36 of 47
4.24 Register 101 – I2C Slave 2 Data Out
I2C_SLV2_DO
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
65 101 I2C_SLV2_DO[7:0]
This register holds the output data writ ten into Sl av e 2 when Sl av e 2 is set to wri te mode.
Description:
For further inf ormation r egar ding Sl ave 2 control, please r efer t o Register s 43 to 45.
I2C_SLV2_DO 8 bit unsigned v alue t hat is written into Slave 2 when Sl av e 2 is set to write
mode.
Parameters:
4.25 Register 102 – I2C Slave 3 Data Out
I2C_SLV3_DO
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
66 102 I2C_SLV3_DO[7:0]
This register holds the output data writ ten into Sl av e 3 when Sl av e 3 is set to wri te mode.
Description:
For further inf ormation r egar ding Sl ave 3 control, please r efer t o Register s 46 to 48.
I2C_SLV3_DO 8 bi t unsigned v al ue that is written int o Sl ave 3 when Slave 3 is set to write
mode.
Parameters:
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 37 of 47
4.26 Register 103 – I2C Master Delay Con t rol
I2C_MST_DELAY_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
67 103 DELAY
_ES
_SHADOW - - I2C_SLV4
_DLY_EN I2C_SLV3
_DLY_EN I2C_SLV2
_DLY_EN I2C_SLV1
_DLY_EN I2C_SLV0
_DLY_EN
This register is used to specify the timing of external sensor data shadowing. The register is also
used to decrease the access rate of sl av e dev ices relat ive to the Sample Rate.
Description:
When DELAY_ES_SHADOW i s set to 1, shadowing of external sensor data i s del ayed until al l data
has been received.
When I2C_SLV4_DLY_EN, I2C_SLV3_DLY_EN, I2C_SLV2_DLY_EN, I2C_SLV1_DLY_EN, and
I2C_SLV0_DLY_EN ar e enabled, the rat e of acc ess f or the c or r espondi ng sl ave dev ices i s reduced.
When a slave’s access rat e is decreased rel ativ e to the Sample Rate, the slave is accessed every
1 / (1 + I2C_MST_DLY) samples.
This base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and DLPF_CFG
(register 26).
For further information regarding I2C_MST_DLY, please refer to register 52.
For further information regarding the Sample Rate, please ref er to register 25.
Bi ts 6 and 5 are reserved.
DELAY_ES_SHADOW When set, delays shadowing of external sensor data until all data
has been received.
Parameters:
I2C_SLV4_DLY_EN When enabled, slave 4 will only be ac c essed at a decreased rate.
I2C_SLV3_DLY_EN When enabled, slave 3 will only be acc essed at a decreased rate.
I2C_SLV2_DLY_EN When enabled, sl av e 2 will only be ac c essed at a decreased rate.
I2C_SLV1_DLY_EN When enabled, sl av e 1 will only be ac c essed at a decreased rat e.
I2C_SLV0_DLY_EN When enabled, sl av e 0 will only be ac c essed at a decreased rat e.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 38 of 47
4.27 Reg ister 104 – Signal Path Reset
SIGNAL_PATH_RESET
Type: Write Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
68 104 - - - - - GYRO
_RESET ACCEL
_RESET TEMP
_RESET
This register is used to reset the analog and digital signal paths of the gyroscope, accelerometer,
and temperature sensors.
Description:
The reset will revert the signal path analog to digital converters and filters to their power up
configurations.
Note:
Bi ts 7 to 3 are reserved.
This regi ster does not clear the sensor r egisters.
GYRO_RESET When set to 1, this bit resets the gy r oscope analog and digital si gnal paths.
Parameters:
ACCEL_RESET When set to 1, this bit resets the accelerometer analog and digital signal
paths.
TEMP_RESET When set to 1, this bit resets the t em per ature sensor anal og and digit al si gnal
paths.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 39 of 47
4.28 Reg ister 105 – Motion Detection Control
MOT_DETECT_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
69 105 - - ACCEL_ON_DELAY[1:0] - -
This register is used to add delay to the ac c elerom eter power on time. It is al so used t o c onfi gur e the
Motion det ection dec r em ent rate.
Description:
The accelerometer data path provides samples to the sensor registers and Motion detection
detection modules. The signal path contains filters which must be flushed on wake-up with new
samples before the detection modules begin operations. The default wake-up delay, of 4m s can be
lengt hened by up to 3ms. This additional delay is specifi ed i n ACCEL_ON_DELAY in units of 1 LSB
= 1 ms. The user may select any value above zero unless instructed otherwise by InvenSense.
Please refer to Section 8 of the MPU-6000/MPU-6050 Product Specification document for further
information regarding the detection m odules.
Bi ts 7 and 6 are reserved.
ACCEL_ON_DELAY 2-bit unsigned value. Specifies the additional power-on delay applied to
accelerometer data path m odules.
Parameters:
Unit of 1 LSB = 1 ms.
4.29 Reg ister 106 – User Cont rol
USER_CTRL
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
6A 106 - FIFO_EN I2C_MST
_EN I2C_IF
_DIS - FIFO
_RESET I2C_MST
_RESET SIG_COND
_RESET
This register allows the user to enable and disable the FIFO buffer, I2C Master Mode, and primary
I2C interface. The FIFO buffer, I2C Master, sensor signal paths and sensor registers can also be
reset using t his regi ster .
Description:
When I2C_MST_EN is set to 1, I2C Master Mode is enabled. In this mode, the MPU-60X0 acts as
the I2C Master to the external sensor slav e devices on the aux iliary I2C bus. W hen t his bit i s clear ed
to 0, the auxiliary I2C bus lines (AUX_DA and AUX_CL) are logically driven by the primary I2C bus
(SDA and SCL). This is a precondition to enabling Bypass Mode. For further information regarding
Bypass Mode, please refer to Register 55.
MPU-6000: The prim ary SPI i nterface will be enabled in plac e of the disabled primary I2C interf ac e
when I2C_IF_DIS is set to 1.
MPU-6050: Always write 0 to I2C_IF_DIS.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 40 of 47
When t he reset bi ts (FIFO_RE SET, I2C_MST_RE SET, and SIG_COND_RE SET ) are set to 1, these
reset bi ts will trigger a reset and then clear to 0.
Bi ts 7 and 3 are reserved.
FIFO_EN When set to 1, t his bi t enables FIFO operations.
Parameters:
When this bit is cleared to 0, the FIFO buffer is disabled. The FIFO buffer
cannot be written to or read from while disabled.
The FIFO buffer’s state does not change unless the MPU-60X0 is power
cycled.
I2C_MST_EN When set to 1, thi s bit enables I2C Master Mode.
When this bit is cleared to 0, the auxiliary I2C bus lines (AUX_DA and
AUX_CL) are l ogically driven by the prim ar y I2C bus (SDA and SCL).
I2C_IF_DIS MPU-6000:
When set to 1, this bit disables the primary I2C interface and
enables the SPI interface instead.
MPU-6050
FIFO_RESET This bit resets the FIFO buff er when set to 1 while FIFO_EN equals 0. This
bit automatic ally clears to 0 after the reset has been triggered.
: Al wa y s wr ite this bit as zero.
I2C_MST_RESET This bit resets the I2C Master when set to 1 while I2C_MST_EN equals 0.
This bit autom atically cl ear s to 0 after the r eset has been tri gger ed.
SIG_COND_RESET When set to 1, this bit resets the signal paths for all sensors (gyroscopes,
accelerometers, and temperature sensor). This operation will also clear the
sensor registers. This bit automatically clears to 0 after the reset has been
triggered.
When resetting only the signal path (and not the sensor registers), please
use Register 104, S IGNA L_P ATH_RE S ET.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 41 of 47
4.30 Reg ister 107 – Power Management 1
PWR_MGMT_1
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
6B 107 DEVICE
_RESET SLEEP CYCLE - TEMP_DIS CLKSEL[2:0]
Thi s register allows the user t o confi gure t he power mode and cloc k source. I t al so provi des a bit for
resetting t he entire devic e, and a bit for disabl ing the tem per ature sensor.
Description:
By sett ing SLEEP to 1, the MPU-60X0 can be put int o low power sl eep mode. When CYCLE is se t to
1 while SLEEP is disabled, the MPU-60X0 will be put into Cycle Mode. In Cycle Mode, the device
cycles between sleep mode and waking up to take a singl e sample of data from accelerometer at a
rate determined by LP_WAKE_CTRL (register 108). To configure the wake frequency, use
LP_WAKE_CTRL within the Power Management 2 register (Register 108).
An internal 8MHz oscillator, gyroscope based clock, or external sources can be selected as the
MPU-60X0 clock source. W hen t he internal 8 MHz oscill ator or an ext ernal source i s chosen a s t he
cl oc k source, the MPU-60X0 can operate in low power modes wit h the gyroscopes disabled.
Upon power up, the MPU-60X0 clock source defaults to the internal oscillator. Howev er, it is highl y
recommended that the device be configured to use one of the gyroscopes (or an external clock
source) as the cl ock refer ence f or im proved stability. The cl ock source can be select ed acc ording to
the following table.
CLKSEL Clock Source
0 Int er n al 8 MH z oscill ator
1 PLL wit h X axis gyros cope reference
2 PLL wit h Y axis gyros cope reference
3 PLL wit h Z axis g yroscop e r ef erence
4 PLL with external 32.768kHz reference
5 PLL with external 19.2MHz reference
6 Reserved
7 Stops the c loc k and keeps the ti mi ng g enerat or
in reset
For further information regarding the MPU-60X0 clock source, please refer to the MPU-6000/MPU-
6050 Product Specificati on doc um ent.
Bi t 4 is reserv ed.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 42 of 47
DEVICE_RESET When set t o 1, this bit r esets al l internal r egister s to their default values.
Parameters:
The bit automati c ally cl ear s to 0 once the r eset is done.
The def ault values for each regi ster can be found in S ection 3.
SLEEP When set t o 1, this bit puts the MPU-60X0 into sleep mode.
CYCLE When this bit is set to 1 and SLEEP is disabled, the MPU-60X0 will cycle
between sleep mode and waking up to take a single sample of data from
active sensors at a rate determined by LP_WAKE_CTRL (register 108).
TEMP_DIS When set t o 1, this bit disables the t em per ature sensor.
CLKSEL 3-bit unsigned value. Specifi es the cl oc k source of the device.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 43 of 47
4.31 Reg ister 108 – Power Management 2
PWR_MGMT_2
Type: Read/Writ e
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
6C 108 LP_WAKE_CTRL[1:0] STBY_XA STBY_YA STBY_ZA STBY_XG STBY_YG STBY_ZG
This register allows the user to configure the frequency of wake-ups in Accelerometer Only Low
Power Mode. This register also allows the user to put individual axes of the accelerometer and
gyroscope i nto standby mode.
Description:
The MP U-60X0 can be put into Accelerometer Only Low P ower Mode using t he foll owing steps:
(i) Set CYCLE bit t o 1
(ii) Set SLEEP bi t to 0
(iii) Set TEMP_DIS bit to 1
(iv) Set STBY_XG, STBY_YG, STBY_ZG bits t o 1
All of t he abov e bits can be found in Power M anagement 1 register (Register 107) .
In this mode, the device will power off all devices except for the primary I2C interface, waking only
the accelerometer at fixed interv als to take a single measurement. The frequency of wake-ups can
be configured with LP_WAKE_CTRL as shown below.
LP_WAKE_CTRL Wake-up Frequency
0 1.25 Hz
1 5 Hz
2 20 Hz
3 40 Hz
For fur ther information regar ding the MPU-6050’s power modes, please refer to Register 107.
The user can put individual accelerometer and gyroscopes axes into standby mode by using this
regi st er. If the device is using a gyroscope ax is as the clock source and t his ax is is put i nto standby
m ode, t he cl oc k source wil l automati c ally be changed to the int er nal 8M Hz oscillator .
LP_WAKE_CTRL 2-bit unsigned value.
Parameters:
Specif ies the f requency of wake-ups during Accel erometer Only Low Power
Mode.
STBY_XA When set to 1, this bi t put s the X axis accelerometer into standby mode.
STBY_YA When set to 1, this bi t put s the Y axis accelerometer into standby mode.
STBY_ZA When set to 1, this bi t put s the Z axis accelerom eter into standby mode.
STBY_XG When set to 1, t his bit put s the X axis gyroscope into standby mode.
STBY_YG When set to 1, t his bi t put s the Y axis gyroscope int o standby mode.
STBY_ZG When set to 1, t his bi t put s the Z axis gyroscope into standby mode.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 44 of 47
4.32 Reg ister 114 and 115 – FIFO Count Registers
FIFO_COUNT_H and FIFO_COUN T_L
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
72 114 FIFO_COUNT[15:8]
73 115 FIFO_COUNT[7:0]
These regi ster s keep t r ac k of the number of samples currentl y i n the FIFO buffer.
Description:
These registers shadow the FIFO Count value. Both registers are loaded with the current sample
count when FI FO_COUNT _H ( Register 72) is read.
Note: Reading only FIFO_COUNT_L will not update the registers to the current sample count.
FIFO_COUNT_H must be ac c essed fi r st to update the content s of both these registers.
FIFO_COUNT should always be read in high-low order in order to guarantee that the most current
FIFO Count v alue is read.
FIFO_COUNT 16-bit unsigned value. Indicates the number of bytes stored in the FIFO
buff er. This number is in turn the number of bytes that can be read fr om the
FIFO buffer and it is dir ectly proporti onal to the num ber of sam ples available
giv en the set of sensor dat a bound t o be stored i n the FIFO (r egister 35 and
36).
Parameters:
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 45 of 47
4.33 Reg ister 116 – FIFO Read Write
FIFO_R_W
Type: Read/Write
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
74 116 FIFO_DATA[7:0]
This register is used to read and write data from the FIFO buffer.
Description:
Data i s wri tten to the FIFO i n order of register num ber (from lowest to hi ghest). If all the FIFO enable
flags (see below) are enabled and all External Sensor Data registers (Registers 73 to 96) are
associat ed with a S lav e dev ice, the cont ents of register s 59 through 96 wil l be wri tten i n order at the
Sample Rate.
The content s of t he sensor data registers (Regi st ers 59 to 96) are writt en int o t he FIFO buff er when
their corresponding FIFO enable flags are set to 1 in FIFO_EN (Register 35). An additional flag f or
the sensor data registers associated with I2C Slave 3 can be found in I2C_MS T_CTRL (Regi ster 36).
If the FI FO buffer has ov erflowed, t he status bit FIFO_OFLOW_INT is autom atically set to 1. This bit
is located i n INT_STATUS (Register 58). W hen the F IFO buff er has ov erflowed, the ol dest data will
be lost and new data will be writ ten to the FIFO.
If the FI FO buffer is empty, r eading thi s register will r eturn the last byt e that was previously read from
the FIFO until new data is available. The user should check FIFO_COUNT to ensure that the FIFO
buffer is not read when em pty.
FIFO_DATA 8-bit data transferred to and from the FIFO buffer.
Parameters:
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 46 of 47
4.34 Reg ister 117 – W ho Am I
WHO_AM_I
Type: Read Only
Register
(Hex) Register
(Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
75 117 - WHO_AM_I[6:1] -
Thi s register is used to verify the ident ity of the device. The contents of WHO_AM_I are the upper 6
bit s of the MPU-60X0’s 7-bit I2C address. T he least signifi cant bit of the MPU-60X0’s I2C address is
determ ined by the value of the AD0 pin. The value of t he AD0 pi n is not r eflected in this register.
Description:
The def ault value of the register is 0x 68.
Bits 0 and 7 are reser ved. (Hard coded t o 0)
WHO_AM_I Contains the 6-bit I2C address of the MPU-60X0.
Parameters:
The Power-On-Res et va lue o f Bit6: Bi t1 is 110 100.
MPU-6000/MPU-6050 Register Map and
Descriptions
Docum ent Num b er : RM-MPU-6000A-00
Revision: 4.0
Release Date: 03/09/2012
CONFIDENTIAL & PROPRIETARY 47 of 47
T his inform at i on f ur n is h ed by I n ven Sense i s b eli ev ed to b e acc urate an d reliabl e. Howev er , n o r es p ons ibil ity is ass u m ed b y InvenSense
for its us e, or for any infring ements of p atents or other rights of thir d parties that may result fr om its us e. Spec ific at ions are su bject to
change without notice. InvenSense reserves the right to make changes to this product, including its circuits and s oftware, in order to
impr ov e it s d es ig n and/ or per f or m anc e, wit hout prior n otic e. Inv enS ens e makes n o warr anti es, n eith er expressed nor implied, regarding
th e inform at i on and specif icati ons contain ed i n th is doc u m ent. Inv en Sens e ass u mes n o resp onsibili ty f or an y c l aims or d am ag es arising
f rom inf orm ati on c ontain ed i n t his d ocu ment, or f rom th e us e of pr od ucts and s ervic es det ail ed th er ein. T his i ncl ud es , but is n ot li mit ed
t o, cl aims or dam ag es bas ed on th e inf ri n g em en t of p aten t s , c op yr ig h ts , mas k work an d/ or oth er int ellec tu al property rights .
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by
implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information
previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors
sh ould n ot b e used or s ol d in th e d evel op ment, st or age, prod uct ion or utili zati on of any c on vent i onal or mass -des truc ti ve weap ons or for
any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime
pr even t ion eq uip men t.
InvenSense® is a registered trademark of InvenSense, Inc. MPUTM, MPU-6000TM, MPU-6050TM, MPU-60X0TM, Digital Motion
Processor™, DMP ™, Motion Processing Unit™, M oti onFus i on™, an d M oti onApps ™ are trademarks of InvenSense, Inc.
©2011 InvenSense, Inc. All rights rese rved.
