a AN-555 APPLICATION NOTE One Technology Way * P.O. Box 9106 * Norwood, MA 02062-9106 * 781/329-4700 * World Wide Web Site: http://www.analog.com Using the AD9709, AD9763, AD9765, AD9767 Dual DAC Evaluation Board By Steve Reine and Dawn Ostenberg GENERAL DESCRIPTION The AD9709, AD9763, AD9765 and AD9767 are highspeed, high-performance dual DACs (8-, 10-, 12-, 14bits) designed for I/Q transmit applications and for applications where board space is at a premium. The evaluation board allows the user to take full advantage of the various modes in which the AD976x can operate. This includes operation as dual DACs with their own individual digital inputs, as well as interleaved DACs where data is alternately written from digital input Port 1 to either of the two DACs. Information on how to operate the evaluation board is included in this application note. However, for more detailed performance information, the reader should consult the individual data sheets for the AD9709, AD9763, AD9765, and AD9767. The 8-, 10-, 12-, and 14-bit DACs in this family are all pinfor-pin-compatible and are MSB justified. Therefore, the same evaluation board can be used to evaluate all four parts. EVALUATION SETUP To evaluate the performance of the AD976x dual DAC family, a small set of measurement and signal generation equipment is needed. Figure 1 shows a typical test setup. Power supplies capable of driving from 3 V to 5 V are needed for both analog and digital circuitry on the evaluation board. A signal generator and digital word generator are needed to provide the data and clock inputs. On the output, an oscilloscope or spectrum analyzer may be needed, depending on the type of performance being analyzed. WORD GENERATOR DIGITAL DATA BUS CLOCK SOURCE ACOM DCOM DIGITAL VDD (3V TO 5V) Figure 1. Typical Test Setup to Evaluate Performance of AD976x Dual DAC Using Evaluation Board POWER CONNECTIONS The AD9709, AD9763, AD9765, AD9767 dual DACs all have separate digital and analog power and ground pins. Analog and digital power and ground have their own banana-style connectors on the dual DAC evaluation board. The best performance when using the evaluation board is achieved when analog and digital power and ground are connected to separate power supplies. Figure 2 shows the power supply, grounding, and decoupling connections for the evaluation board and for the DAC itself. Note that for best noise rejection on the power supplies, the high value bulk capacitors are placed at the external power connectors, while the smaller value capacitors, needed for high frequency rejection, are located close to the DAC. L2 DVDD BEAD AVDDIN C9 10mF 25V BAN-JACK TP37 TP38 TP39 TP43 DGND BAN-JACK AVDD BEAD C10 10mF 25V TP40 BAN-JACK DVDD C1 0.001mF TP41 TP44 AVDD C2 0.01mF C3 0.1mF DVDD1 DCOM1 DCOM2 DVDD2 AD9709 AD9763 AD9765 AD9767 AVDD C13 0.1mF C12 0.01mF C11 0.001mF ACOM DUAL DAC Figure 2. Analog and Digital Power Connections on Dual DAC Evaluation Board REV. 0 SPECTRUM ANALYZER TP11 L1 BAN-JACK OSCILLOSCOPE DUAL DAC EVALUATION BOARD AVDD DVDD ANALOG VDD (3V TO 5V) TP10 DVDDIN DATA OUT DATA IN CLK TP42 AGND AN-555 Analog and digital supplies can be run at either 3 V or 5 V, and do not have to run from the same supply voltage. Regardless of supply voltage, the digital input data can be safely run from 3 V or 5 V logic levels, as long as the proper resistor packs are placed in the digital input data path (see Digital Inputs section). CLOCK INPUTS SMA connectors S1 to S4 are intended to be used as clock and control lines for the AD976x, and are 50 terminated. The selection of JP9 also allows the user to select a clock generated on the same digital data bus as the input data. Jumpers JP1 to JP7, JP9, and JP16 control the clock inputs for the various clock modes in which the dual DACs can operate. It is recommended that the clock source be a square wave with minimal overshoot and undershoot. Overshoot and undershoot beyond the supply rails can inject noise onto the clock, which may result in jitter and reduced DAC performance. The dual DACs can operate with a sine wave clock, but dynamic performance will be degraded. Figure 4 shows the clock input section and jumper options for the dual DAC evaluation board. DIGITAL INPUTS The digital inputs on the dual DAC evaluation board are designed to accept inputs from any generic word generator. However, when running the DAC at high sample rates, the quality of the digital data can have an impact on the performance of the DAC. As an example, if the edges of the digital information are slow, or the edges of the various bits are skewed from each other in time, specifications such as SNR and SINAD may be degraded. The digital input path on the evaluation board includes both pull-up and pull-down plug-in resistor packs. The pull down resistors allow the user to apply digital logic at 5 V levels when the DAC digital supply is operating at 3 V, and the pull-ups allow 3 V logic levels when the DAC is run from a 5 V digital supply. The digital input signal path is shown in Figure 3. MODES OF OPERATION The AD976x dual DAC family is designed to operate either as two completely separate DACs in dual DAC mode, or with a single digital input port in which the input data is alternately sent to either of the two DACs (interleaving mode). DVDD NOT SUPPLIED WITH EVALUATION BOARD 22V DIGITAL DATA INPUT DATA INPUT ON AD9763/AD9765/AD9767 NOT SUPPLIED WITH EVALUATION BOARD NOT SUPPLIED WITH EVALUATION BOARD DGND Figure 3. Input Structure of Digital Input Signal Path on Dual DAC Evaluation Board JP9 DCLKIN1 TP29 DCLKIN2 DVDD JP6 H L JP16 WRT1IN S1 IQWRT JP2 TP30 DVDD JP1 JP5 CLK1IN S2 IQCLK I D PRE J K U1 CLK Q CLR C 1 TP31 CLK2IN S3 RESET I TP32 74HC112 JP7 JP4 C DGND;8 DVDD;16 DVDD H L JP3 WRT2IN S4 IQSEL WRT1/IQWRT I R1 50V R2 50V R3 50V C R4 50V CLK1/IQCLK CLK2/IQRESET WRT2/IQSEL AD9709/AD9763/AD9765/AD9767 Figure 4. Jumper Options for Clock Input Section on Dual DAC Evaluation Board -2- REV. 0 AN-555 detailed information on the functions of these inputs, as well as the DAC input and output timing, see the AD9709, AD9763, AD9765, and AD9767 data sheets. DUAL DAC MODE Jumper J8 controls the logic level of the MODE pin on the AD976x dual DAC. With this jumper in the D position, the mode pin is pulled to a high logic level and the AD976x is in dual DAC mode. Operation with a single clock can be achieved by selecting JP16 or JP9 for the clock source and inserting JP5 in the C position, and removing JP3. JP4 can be used to control IQRESET, but for most evaluations can simply be tied low (Position I). The simplest method for operating the dual DAC evaluation board in the dual DAC mode is to select a common clock for WRT1, WRT2, CLK1, and CLK2. An external clock generator can be selected by inserting JP16, or a clock from the word generator can be selected by inserting JP9. By inserting JP3, JP4, and JP5 all in the C position, the selected clock can be applied to all four clock inputs. In interleaving mode, digital data present at input Port 1 is written into the Port 1 or Port 2 input buffers internal to the DAC on the rising edge of IQWRT. The port into which data is written depends on the state of IQSEL at the time of the IQWRT rising edge. If IQSEL is high when the rising edge occurs, data will be written to input Port 1. If IQSEL is low at that time, data will be written to input Port 2. Different combinations of JP3, JP4, and JP5 allow multiple options if the user desires to drive the WRT and CLK inputs from separate clocks. In the dual mode, jumpers JP1 and JP2 should be removed. The state of Jumpers JP6 and JP7 does not matter in this mode. U1 on the evaluation board provides an alternating IQSEL signal by toggling on every falling edge of IQWRT. To enable this function, insert JP1 and JP2 and remove JP3. JP6 and JP7 are used to synchronize the input data stream with the IQSEL pin. To perform this synchronization, power up the evaluation board with the IQWRT and input data clocks disabled and at logic low. If the first word in the digital data stream is meant for Channel 1, preset U1 by inserting JP7 in the H position, temporarily insert JP6 in the L position, then permanently in the H position. If the first word in the data stream in intended for Channel 2, reset U1 by inserting JP6 in the H position, insert JP7 temporarily in the L position, then permanently in the H position. Table I illustrates the jumper positions required to operate in the dual DAC mode of operation. Table I. Jumper Options for Dual DAC Mode Jumper Position Description JP1, JP2, JP6, JP7 Removed These are only used in interleaved mode. JP3, JP4, JP5 C With these in the B position, the evaluation board can be run with one common clock. JP8 D Enables Dual DAC Mode. JP9 Optional Selects clock from word generator. Remove JP9 if clock source is from S1/JP16. JP16 Optional Table II illustrates the jumper positions required to operate in the dual DAC mode of operation. Table II. Jumper Options for Interleaved Mode Selects clock from connector S1. Remove JP16 if clock source is from JP9/JP16/ DCLK1, DCLK2. INTERLEAVING MODE With jumper JP8 in the I position, the MODE pin on the AD976x is pulled to a logic low level and the DAC is in interleaving mode. In this mode, a single stream of digital data drives Port 1 on the DAC. This stream of data contains alternating bits from two data channels. By using the correct clock and control signals, data in the two channels will be separated and sent to the correct DAC outputs. This is typical of an I/Q application. Position Description JP1, JP2 Inserted JP3 Remove JP4 I JP5 C These enable U1 to generate the alternating logic signal for IQSEL. If the IQSEL logic is to be generated by U1, this is not needed. Use to allow S3 control of IQRESET pin. Allows IQWRT and IQCLK to be driven by a common clock. These are used to preset the IQSEL pin before the data clock is enabled. See text for description of use. Enables Interleaved Mode. Selects clock from word generator. Remove JP9 if clock source is from S1/JP16. Selects clock from Connector S1. Remove JP16 if clock source is from JP9/DCLK1, DCLK2. JP6, JP7 In interleaving mode, the definitions for the four clock inputs change. WRT1, WRT2, CLK1, and CLK2 become IQWRT, IQCLK, IQRESET, and IQSEL, respectively. For REV. 0 Jumper -3- JP8 JP9 I Optional JP16 Optional AN-555 CLOCK TIMING/PERFORMANCE To ensure that specified setup-and-hold times are met, the digital data inputs should change state on the falling edge of the clock. However, due to timing skews and delays inherent in some circuits, this does not always happen. If the timing of the data transition and the rising edge of the clock violates the setup-and-hold times, SNR performance will be seriously degraded. Figure 5 shows the valid window during the clock cycle in which the digital input data can transition with no degradation in SNR performance. DATA CLOCK CHANNEL 2 CHANNEL 1 tS tH DATA CLOCK Figure 5. Valid Window for Data Transition During Clock Cycle Figure 6. Verifying Clock/Data Timing on Evaluation Board, Proper Use of Scope Probes Correct timing can be verified by generating a word pattern that repeatedly toggles the LSBs between Logic 1 and Logic 0. The user will also need a digital oscilloscope with persistence capability. To measure the input data hold time, perform the same operation, but start with the data transition occurring at the midpoint of the clock transition. SNR at this point will be completely degraded. Increase the digital input delay until the SNR is optimized. At this point, again measure the time difference between the data transition and the midpoint of the rising edge. This is the measured data hold time. Place one probe from the scope on the clock input of the DAC. The sensitivity of this measurement is in the tenths of nanoseconds, so the probe should be placed as close as possible to the DAC itself. In addition, the scope should be set to trigger from this channel. Place a second probe from the oscilloscope on the LSB input of the DAC, again as close as possible to the DAC itself. The barrels of both probes should be grounded to the evaluation board, as close to the measurement point as possible. A convenient way of doing this is to wrap a piece of bus wire around the barrel and then solder the other end of the bus wire to the PCB. Figure 6 illustrates a typical oscilloscope display for this test, as well as the proper way to use the scope probes. REFERENCE OPERATION The AD9709, AD9763, AD9765, AD9767 contain a single 1.2 V reference that is shared by both of the DACs on the chip. This reference drives two control amplifiers that independently control the full-scale output currents in each of the two DACs. Using the 1.2 V reference and the control amplifier, reference currents are produced for each DAC in an external resistor attached to FSADJ1 (DAC1) and to FSADJ2 (DAC2). The relationship between the external resistor current and the full-scale output current is: For the most accurate results, identical high input impedance, low input capacitance probes should be used. If possible, they should also be calibrated. IOUTFS = 32 x Reference Current The data setup time can be measured by placing a variable delay between the clock generator and the clock input of the word generator. This is most often done by using a pulse generator. By adjusting the delay of the digital data, place the data transition point on the falling edge of the clock. At this point, SNR should be optimized. Increase the amount of delay for the digital data, moving the transition point closer to the rising edge. As the data transition gets close to the rising edge, SNR will begin to degrade. At this point, on the oscilloscope, measure the time difference between the data transition and the midpoint of the rising edge. This is the measured data setup time. Using the internal reference, this can also be expressed as: IOUTFS = 38.4 / REXT On the evaluation board, R9 and R10 are the two external resistors that define the full-scale current. An external reference can also be used simply by driving the REFIO pin on the dual DAC (TP36) with an external reference. The input impedance of the REFIO pin is very high, minimizing any loading of the external reference. However, because some references behave poorly when driving capacitive loads, the bypass capacitor on -4- REV. 0 AN-555 enabled. In this mode, a single RSET resistor is connected to FSADJ1 and the resistor on FSADJ2 can be removed. REFIO (C14) may need to be removed under these conditions. Figures 7 and 8 show the internal and external reference configurations for the AD9709, AD9763, AD9765, and AD9767. Note: Only parts with date code of 9930 or later have the Master/Slave GAINCTRL function. For parts prior to this date code, Pin 42 must be connected to AGND, and the part will operate in the two resistor, independent gain control mode. When using an external reference in this way, the fullscale output current for each DAC can be defined by; IOUTFS = 32 x VREF/REXT OUTPUT CONFIGURATION The AD9709, AD9763, AD9765, AD9767 have been designed to achieve optimum performance with the outputs used differentially. A transformer on the evaluation board (Mini-Circuits T1-1T) allows the conversion of the differential outputs to a single-ended signal. The bandwidth of this transformer allows low distortion operation from 350 kHz to well past the Nyquist bandwidth of the DAC when operating at its highest sampling rate. Note that in the internal reference configuration, any additional load on the reference should be buffered with an external amplifier. This external amplifier is not included on the evaluation board. For more detailed information on the operation of the reference section of the DACs, see page 9 of the data sheet. OPTIONAL EXTERNAL REFERENCE BUFFER GAINCTRL +1.2V REF AVDD REFIO ADDITIONAL EXTERNAL LOAD 0.1mF IREF Figure 9 shows a typical DAC output configuration. Both outputs drive a 50 resistor as well as a transformer. The grounded centertap on the primary of the transformer causes the output of the DAC to swing around ground, allowing for wider p-p swing while still remaining within the output voltage compliance range of the DAC. On the evaluation board, these resistors are R5, R6, R7, and R8. This provides a full-scale differential output voltage of 0.67 V p-p when operating with IOUTFS = 20 mA and the transformer terminated with 50 . DUAL DAC REFERENCE SECTION CURRENT SOURCE ARRAY FSADJ 2kV ACOM Figure 7. Internal Reference Configuration AVDD If the secondary of the transformer is terminated with 50 , the DAC will then be capable of driving 0.5 dBm into this load at full-scale out. CURRENT SOURCE ARRAY C4, C5, C6, and C15 (10 pF) on the evaluation board, working together with the 50 output resistors, form a low-pass filter which gives some amount of image rejection at higher output frequencies. In applications where an amplifier is used in place of the transformer, it is important that the capacitor values be chosen to limit the output slew rate of the DAC. If the output of the amplifier becomes slew rate limited, severe distortion can result. GAINCTRL AVDD +1.2V REF REFIO EXTERNAL REFERENCE FSADJ IREF 2kV DUAL DAC REFERENCE SECTION ACOM Figure 8. External Reference Configuration MASTER/SLAVE RESISTOR MODE, GAINCTRL The AD9709, AD9763, AD9765, AD9767 all allow the gain of each channel to be independently set by connecting one RSET resistor to FSADJ1 and another RSET resistor to FSADJ2. To add flexibility and reduce system cost, a single RSET resistor can be used to set the gain of both channels simultaneously. IOUT AD9709 AD9763 AD9765 AD9767 When GAINCTRL is low (i.e., connected to AGND), the independent channel gain control mode using two resistors is enabled. In this mode, individual RSET resistors should be connected to FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., connected to AVDD), the master/ slave channel gain control mode using one resistor is REV. 0 50V IOUT 10pF 50V 50V 10pF Figure 9. Typical DAC Output Configuration -5- AN-555 TROUBLESHOOTING The dual DAC evaluation board has been designed to allow optimum performance from the AD9709, AD9763, AD9765, AD9767. However, many factors can contribute to suboptimal performance. The following is a list of potential problems and their likely sources. Problem--Unusually high amount of noise on the output. With an oscilloscope, verify the relative timing between the data transition and the clock input as described in the Clock Timing Performance section. Check to make sure that the clock for the data source is synchronized with the clock input to the DAC. Problem--No signal or reduced signal on the output. Is power applied correctly? Use an oscilloscope to verify that the input data pins are switching and that the clock is present on the input. Make sure that the output transformer is in place. Do the data input logic levels match the DVDD being applied (3 V or 5 V)? Does the clock pass through the input threshold, roughly one-half of DVDD? If the internal reference is being used, make sure that 1.2 V is present at FSADJ1, FSADJ2 and REFIO. Make sure that R9 and R10 are in place next to these test points. Problem--Can not match noise specifications from data sheet. Is a low jitter clock being used? When generating a single tone, does the spectrum analyzer show skirting around the tone at the noise floor? This is a symptom of clock jitter. Problem--Can not match distortion spec. Is the output signal from the DAC seeing 50 ? Is the voltage on the output of the DAC within the compliance range of 1 V? Is the DAC output overdriving the spectrum analyzer input? Try increasing the spectrum analyzer input attenuation to see if the distortion products drop. If they do, the analyzer is being overdriven. Problem--Signal and images appear at the DAC output at twice or half the expected frequency. The DAC is in the incorrect mode (Dual DAC or Interleaving). Make sure that the mode select jumper in the top right corner of the eval board is set to the correct position. This jumper must be in one position or the other and cannot be allowed to float. -6- REV. 0 AN-555 POWER DECOUPLING AND INPUT CLOCKS B1 RED TP10 DVDDIN BAN-JACK RED TP11 B3 L1 DVDD BEAD 1 BAN-JACK BEAD BAN-JACK C9 10mF BLK TP37 2 25V B2 L2 AVDDIN BLK TP38 BLK TP39 TP43 BLK AVDD 1 C10 10mF BLK TP40 2 25V B4 BAN-JACK DGND BLK TP41 TP44 BLK BLK TP42 AGND JP9 2 1 DCLKIN1 3 DCLKIN2 A B /2 CLOCK DIVIDER JP6 WHT TP29 JP16 WRT1IN S1 IQWRT 2 1 DVDD 3 A B JP2 4 DGND;3,4,5 PRE WHT TP30 3 JP5 CLK1IN S2 IQCLK 2 1 I DGND;3,4,5 WHT TP31 JP1 3 A B C WHT TP32 C DVDD JP3 DGND;3,4,5 1 2 R1 50V 1 2 R2 50V 1 2 R3 50V 1 2 A B 1 2 3 3 A B I 15 JP7 2 1 WRT2IN S4 IQSEL 6 DGND;8 DVDD;16 3 A B I DGND;3,4,5 K CLR Q TSSOP112 2 1 U1 5 Q CLK 2 DVDD JP4 CLK2IN S3 RESET 1 J WRT1 C CLK1 R4 50V CLK2 WRT2 WHT TP33 SLEEP SLEEP DVDD 10 11 PRE 9 J U1 Q CLK 7 12 K Q CLR 1 13 TSSOP112 RP16 R1 R9 RP9 2 C8 0.01mF DGND;8 DVDD;16 R1 RP10 R9 R1 R9 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30 INCK1 1 RP15 R1 1 2 3 4 5 6 7 8 9 10 Figure 10. Power Decoupling and Clocks on Dual DAC Evaluation Board REV. 0 -7- R9 RCOM 22 RCOM 22 INP9 INP10 INP11 INP12 INP13 INP14 2 3 4 5 6 7 8 9 10 INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8 1 1 2 14 RCOM 22 RCOM 22 C7 0.1mF INCK2 2 R13 50V INP31 INP32 INP33 INP34 INP35 INP36 1 AN-555 RP3 R1 R9 RCOM 22 2 3 4 5 6 7 8 9 10 1 INP1 2 P1 P1 1 4 P1 P1 3 6 P1 P1 5 8 P1 P1 7 10 P1 P1 9 12 P1 P1 11 14 P1 P1 13 16 P1 P1 15 18 P1 P1 17 20 P1 P1 19 22 P1 P1 21 24 P1 P1 23 26 P1 P1 25 28 P1 P1 30 P1 P1 29 32 P1 P1 34 P1 P1 33 36 P1 P1 35 38 P1 P1 37 40 P1 P1 27 INP2 INP3 INP4 INP5 INP6 INP7 INP8 INP9 INP10 INP11 INP12 INP13 INP14 DVDD RP5, 10V 1 16 14 2 12 10 16 14 12 2 3 4 5 6 7 8 9 10 1 RP11 R1 R9 RCOM 33 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 DVDD DUTP1 DUTP2 DUTP3 DUTP4 DUTP5 DUTP6 11 DUTP7 RP5, 10V 8 DUTP8 9 DUTP9 RP6, 10V 2 DUTP10 15 DUTP11 RP6, 10V 4 RP6, 10V 5 R9 13 6 RP6, 10V 3 R1 RP5, 10V RP6, 10V 1 RP13 RCOM 33 15 4 RP5, 10V 7 R9 RP5, 10V RP5, 10V 5 R1 RP5, 10V RP5, 10V 3 RP1 RCOM 22 DUTP12 13 DUTP13 RP6, 10V 6 DUTP14 11 31 RP6, 10V INCK1 8 DCLKIN1 9 39 RP4 R1 R9 RCOM 22 1 2 P2 P2 1 4 P2 P2 3 6 P2 P2 5 8 P2 P2 7 10 P2 P2 9 12 P2 P2 11 14 P2 P2 13 16 P2 P2 15 18 P2 P2 17 20 P2 P2 19 22 P2 P2 21 24 P2 P2 23 26 P2 P2 25 28 P2 P2 30 P2 P2 29 32 P2 P2 34 P2 P2 33 36 P2 P2 35 38 P2 P2 37 40 P2 P2 27 INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30 INP31 INP32 INP33 INP34 INP35 INP36 DVDD RP7, 10V 1 16 RP7, 10V 3 14 RP7, 10V 5 12 RP7, 10V 7 10 RP8, 10V 1 16 RP8, 10V 3 14 RP8, 10V 5 12 RP2 R1 R9 RCOM 22 2 3 4 5 6 7 8 9 10 RP14 R1 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 DUTP26 DUTP27 DUTP28 11 DUTP29 DUTP30 9 DUTP31 DUTP32 15 DUTP33 RP8, 10V 4 DUTP34 13 DUTP35 RP8, 10V 6 2 3 4 5 6 7 8 9 10 DUTP25 13 RP8, 10V 2 1 DUTP24 RP7, 10V 8 R9 DUTP23 15 RP7, 10V 6 R1 DVDD RP7, 10V 4 RP12 RCOM 33 RP7, 10V 2 R9 RCOM 33 DUTP36 11 31 INCK2 RP8, 10V 8 DCLKIN2 9 DIGITAL INPUT SIGNAL CONDITIONING SPARES RP5, 10V 7 39 10 RP8, 10V 7 10 Figure 11. Digital Input Signal Conditioning -8- REV. 0 AN-555 BL1 TP34 WHT NC = 5 3 4 S6 OUT1 DVDD 1 C1 2 VAL 1 1 C2 2 0.01mF C3 ACOM 2 0.1mF MODE1 1 AVDD 1 DB13P1 (MSB) MODE 48 DUTP2 2 DB12P1 AVDD 47 DUTP3 3 DB11P1 IA1 46 DUTP4 4 DB10P1 IB1 45 DUTP5 5 DB9P1 FSADJ1 44 DUTP6 6 DB8P1 REFIO 43 DUTP8 DUTP9 DUTP10 7 DB7P1 DB6P1 FSADJ2 41 9 DB5P1 IA2 40 IB2 U2 DB3P1 AD9763/ ACOM AD9765/ DB2P1 AD9767 SLEEP 1:1 6 T1 JP8 2 3 BL2 1 R5 50V 2 C4 2 10pF 1 R6 C5 2 10pF 1 2 50V TP45 WHT 1 R9 1.92kV 2 1 C16 22nF 1 2 1 1 2 1 C15 2 DUTP12 12 DUTP13 13 DB1P1 DB0P2 36 DUTP36 DUTP14 14 DB0P1 DB1P2 35 DUTP35 15 DCOM1 DB2P2 34 DUTP34 16 DVDD1 DB3P2 33 DUTP33 WRT1 17 WRT1 DB4P2 32 DUTP32 CLK1 18 CLK1 DB5P2 31 DUTP31 CLK2 19 CLK2 DB6P2 30 DUTP30 38 SLEEP 37 20 WRT2 DB7P2 29 DUTP29 21 DCOM2 DB8P2 28 DUTP28 22 DVDD2 DB9P2 27 DUTP27 DUTP23 23 DB13P2 (MSB) DB10P2 26 DUTP26 DUTP24 24 DB12P2 DB11P2 25 DUTP25 C6 2 10pF 1 1 2 10pF 1 1 R7 50V 2 R8 50V C11 2 VAL 2 R12 VAL 2 NC = 5 BL4 C13 2 0.1mF DUT AND ANALOG OUTPUT SIGNAL CONDITIONING Figure 12. Output Signal Conditioning -9- TP35 WHT 6 T2 1 4 1:1 1 C12 2 0.01mF 0.1mF JP10 R10 1.92kV 3 1 2 2 BL3 AVDD 1 TP46 WHT 1 C14 R14 256V 2 1 39 REFIO TP36 WHT R15 256V C17 22nF DUTP11 REV. 0 AGND;3,4,5 1 A B 11 WRT2 3 GAINCTRL 42 8 10 DB4P1 2 A B DUTP1 DUTP7 JP15 1 AVDD 2 R11 VAL AGND;3,4,5 S11 OUT2 AN-555 Figure 13. Assembly, Top Side Figure 14. Assembly, Bottom Side -10- REV. 0 AN-555 Figure 15. Layer 1, Top Side Figure 16. Layer 2, Ground Plane REV. 0 -11- E3661-2-12/99 (rev. 0) AN-555 PRINTED IN U.S.A. Figure 17. Layer 3, Power Plane Figure 18. Layer 4, Bottom Side -12- REV. 0 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9775-EBZ