This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.1 / Feb. 2006 1
256MBit MOBILE DDR SDRAMs based on 4M x 4Bank x16 I/O
Document Title
256MBit (4Bank x 4M x 16bits) MOBILE DDR SDRAM Memory
Revision History
Note
1)
Now under evaluation by the Hynix Development Division.
Revision No. History Draft Date Remark
0.1 Initial Draft Feb.2006 Preliminary
Rev 0.1 / Feb. 2006 2
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
FEATURES SUMMARY
●Mobile DDR SDRAM MEMORIES
- Double data rate architecture
: two data transfers per clock cycle
●Mobile DDR SDMRAMs INTERFACE
- x16 bus width : HY5MS5B6LF(P)
- Multiplexed Address/ Data
- Pinout compatibility for all densities
●SUPPLY VOLTAGE
- 1.8V device: VDD = 1.7 to 1.95V
●Memory Interface
- LV-CMOS compatible inputs
●MEMORY CELL ARRAY
- 256Mbit (x16 device) = 4M x 4Bank x 16 I/O
●DATA STRODB (Bidirectional)
- x16 device: All Bank(4 Bank) Operation
(with single pulsed RAS)
- All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
●LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR
(Temperature Compensated Self Refresh)
- DS (Drive Strength)
- Deep Power Down Mode
●INPUT CLOCK
- Fully differential clock inputs (CK, CK) operation
●Data MASK
- UDM, LDM : Input mask signal for write data
- DM mask write data-in at the both rising and
falling edges of the data strobe
●MODE RERISTER SET AND EXTENDED MODE
REGISTER SET
- Keep to the JEDEC Standard regulation
(Low Power DDR)
●CAS LATENCY (Programmable)
- Programmable CAS latency 3 / 2 supported
●BURST LENGTH
- Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
●AUTO PRECHARGE
- Option for each burst access
●AUTO REFRESH AND SELF REFRESH MODE
●CLOCK STOP MODE
- Clock stop mode is a feature supported by
Mobile DDR SDRAM devices.
- Keep to the JEDEC Standard regulation
●
INITIALIZING
THE MOBILE DDR SDRAMs
- Occur at device power up or interruption of device
power.
●Mobile DDR SDRAMs
DEEP POWER-DOWN ENTRY AND EXIT
●PACKAGE
- HY5MS5B6LF(P)
: 60-Ball FBGA (8 x 10 x 1.0 mm)
- HY5MS5B6LF (Leaded)
- HY5MS5B6LFP (Lead Free)
Rev 0.1 / Feb. 2006 3
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
DESCRIPTION
The Hynix Mobile DDR SDRAMs is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G
cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5MS5B6ALF(P)-xE Series is 268,435,456-bit CMOS Low Power Double Data Rate Synchronous
DRAM(Mobile DDR), ideally suited for the main memory applications which requires large memory density and high
bandwidth. It is organized as 4banks of 4,194,304x16.
The HYNIX HY5MS5B6ALF(P)-xE Low power Double Data Rate SDRAM(Mobile DDR) uses a double-data-rate architec-
ture to achieve high-speed operation. The address lines are multiplexed with the Data Input/ Output signals on a mul-
tiplexed x16 Input/ Output bus. The double data rate architecture is essentially a 2
n
prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. This interface reduces the pin count and
makes it possible to migrate to other densities without changing the footprint.
The Hynix HY5MS5B6ALF(P)-xE Serises Low power DDR SDRAMs(Mobile DDR) offer fully synchronous operations ref-
erenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising
edges of the CK (The Mobile DDR operates from a differential clock
: the crossing of CK going HIGH and CK going LOW
is referred to as the positive edge of CK
), Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it (
Input data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK
). The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with Interface of Low Power DDR SDRAM(Mobile DDR)
Device.
Read and write accesses to the Low Power DDR SDRAMs(Mobile DDR) are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The Low Power DDR SDRAMs(Mobile DDR) provides for programmable read or write bursts of 2, 4 or 8 locations. An
AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst access.
As with standard SDRAMs, the pipe lined, multibank architecture of Low Power DDR SDRAMs(Mobile DDR) allows for
concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation times.
And the Low Power DDR SDRAMs(Mobile DDR) also provides for special programmable options including Partial Array
Self Refresh of a quarter bank, a half bank or all banks, Temperature Compensated Self Refresh of 45 or 85 degrees
oC. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted
and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule).
Rev 0.1 / Feb. 2006 4
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
The Hynix HY5MS5B6ALF(P)-xE has the special Low Power function of Auto TCSR(Temperature Compensated Self
Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to
automatically adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is a additional operating mode for Low Power DDR SDRAMs(Mobile DDR). This mode can
achieve maximum power reduction by removing power to the memory array within each DDR SDRAMs. By using this
feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up
mother-board power-line layout flexibility.
All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
The devices are available in the following packages:
- FBGA_60Ball : 8mm x 10mm x 1.0 mm
(max)
256M Mobile DDR ORDERING INFORMATION
Notice : Clock Frequency DDR333 / 166MHz Product :
- Contact Hynix Office for product availability.
Part Number Clock Frequency CAS
Latency Organization Interface Package
HY5MS5B6ALF-6 DDR333
166MHz 3
4banks x 4Mb x 16 LVCMOS
LeadHY5MS5B6ALF-H DDR266
133MHz 3
HY5MS5B6ALF-S DDR200
105MHz 3
HY5MS5B6ALFP-6 DDR333
166MHz 3
Lead Free
HY5MS5B6ALFP-H DDR266
133MHz 3
HY5MS5B6ALFP-S DDR200
105MHz 3
Rev 0.1 / Feb. 2006 5
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
FBGA 60Ball ASSIGNMENT
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CKE
A9
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CK
A11
A
B
C
D
E
F
G
H
A6 A7
J
VSS A4
K
VSSQ
DQ14
DQ12
DQ10
DQ8
NC
/CK
A12
A8
A5
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
/WE
/CS
A10
A2
DQ0
DQ2
DQ4
DQ6
LDQS
LDM
/CAS
BA0
A0
A3
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VDD
/RAS
BA1
A1
VDD
123456789
Rev 0.1 / Feb. 2006 6
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
60Ball FBGA FUNCTION DES CRIPTIONS(I)
SYMBOL TYPE DESCRIPTION
CK, CK INPUT
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossings of CK and CK (both directions of crossing).
CKE INPUT
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row AC-
TIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT,
which is achieved asynchronously.
CS INPUT
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM.
CS enables (registered LOW) and disables (registered HIGH) the command decoder.All
commands are masked when CS is registered HIGH. CS provides for external bank selec-
tion on systems with multiple banks. CS is considered part of the command code.
BA0, BA1 INPUT
Bank Address Inputs :
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE.
command is being applied. BA0 and BA1 also determine which mode register is to be load-
ed during a MODE REGISTER SET command (MRS or EMRS).
A0 ~ A12 INPUT
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10/AP
Provide the row address for ACTIVE commands, and the column address and AUTO PRE-
CHARGE bit for READ/WRITE commands, to select one location out of the memory array
in the respective bank. A10 sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank
is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the
op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode
register ( Mode Register or Extended Mode Register ) is loaded during the MODE REGIS-
TER SET command.
RAS, CAS, WE INPUT Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
UDM, LDM INPUT
Input Data Mask:Controls output buffers in read mode and masks input data in write
mode.
Data Mask is an input mask signal for write data. Input data is masked when Data Mask
is sampled.HIGH along with that input data during a WRITE access. Data Mask is sampled
on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ
and DQS loading. LDM corresponds to the data on DQ0-DQ7 ; UDM corresponds to the
data on DQ8-DQ15
LDQS, UDQS I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
Rev 0.1 / Feb. 2006 7
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
60Ball FBGA FUNCTION DES CRIPTIONS (II)
SYMBOL TYPE DESCRIPTION
DQ0 ~ DQ15 I/O Data Input/Output : Multiplexed data input/output pin
VDD SUPPLY Power supply
VSS SUPPLY Ground
VDDQ SUPPLY I/O Power supply
VSSQ SUPPLY I/O Ground
NC - No connection : These pads should be left unconnected
Rev 0.1 / Feb. 2006 8
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Mobile DDR SDRAM
16
Internal Row
Counter
Column
Pre
Decoder
Column Add
Counter
Self refresh
logic & timer
Extended
Mode
Register
Sense AMP & I/O Gate
Output Buffer & Logic
Address
Register Burst
Counter
Mode Register
State Machine Address Buffers
Bank Select
Column Active
Row Active
CAS
Latency
CLK
CKE
CS
RAS
CAS
WE
U/LDM
A0
A1
BA1
BA0
A12
PASR
Row
Pre
Decoder
Refresh
DQ0
DQ15
Row decoders
Row decoders
Row decoders
Row decoders
Column decoders
4Mx16 BANK 0
4Mx16 BANK 1
4Mx16 BANK 2
4Mx16 BANK 3
Memory
Cell
Array
Data Out Control
Burst
Length
CLK
Input Buffer & Logic
DS
Write Data Register
2-bit Prefetch Unit
32
16
32
Data Strobe
Transmitter
Data Strobe
Receiver
DS
LDQS
,
UDQS
Rev 0.1 / Feb. 2006 9
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register Set(MRS) for Mobile DDR SDRAM
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00000 000 CAS Latency BT Burst Length
Burst Type
A3 Burst Type
0Sequential
1Interleave
Burst Length
A2 A1 A0 Burst Length
A3 = 0 A3=1
0 0 0 Reserved Reserved
00 1 2 2
01 0 4 4
01 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
CAS Latency
A6 A5 A4 CAS Latency
0 0 0 R e s e r v e d
0 0 1 R e s e r v e d
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 R e s e r v e d
1 1 0 R e s e r v e d
1 1 1 Reserved
Rev 0.1 / Feb. 2006 10
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
BASIC FUNCTIONAL DESCRIPTION (Continued)
Extended Mode Register Set(EMRS) for Mobile DDR SDRAM
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10000000 DS 00 PASR
DS (Driver Strength)
A6 A5 Driver Strength
00Full
0 1 1/2 Strength
1 0 1/4 Strength
1 1 1/8 Strength
PASR (Partial Array Self Refresh)
A2 A1 A0 Self Refresh Coverage
000All Banks
0 0 1 Half of Total Bank (BA1=0)
0 1 0 Quarter of Total Bank (BA1=BA0=0)
011Reserved
100Reserved
101
One Eighth of Total Bank
(BA1 = BA0 = Row Address MSB=0)
110
One Sixteenth of Total Bank
(BA1 = BA0 = Row Address 2 MSBs=0)
111Reserved
Rev 0.1 / Feb. 2006 11
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
COMMAND TRUTH TABLE
DM TRUTH TABLE
Note:
1. All states and sequences not shown are illegal or reserved.
2. DESLECT and NOP are functionally interchangeable.
3. Autoprecharge is non-persistent. A10 High enables Autoprecharge, while A10 Low disables Autoprecharge
4. Burst Terminate applies to only Read bursts with autoprecharge disabled.
This command is undefined and should not be used for Read with Autoprecharge enabled, and for Write bursts.
5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.
6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged
and BA0-BA1 are don't care.
7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.
8. All address inputs and I/O are ''don't care'' except for CKE. Internal refresh counters control Bank and Row addressing.
9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.
10. BA0 and BA1 value select between MRS and EMRS.
11. Used to mask write data, provided coincident with the corresponding data.
12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
Function CS RAS CAS WE BA A10/AP ADDR Note
DESELECT (NOP) H X X X X X X 2
NO OPERATION (NOP) L H H H X X X 2
ACTIVE (Select Bank and activate Row) L L H H Valid Row Row
READ (Select bank and column and start read burst) L H L H Valid L Col
READ with AP (Read Burst with Autoprecharge) L H L H Valid H Col 3
WRITE (Select bank and column and start write
burst) LH L LValidL Col
WRITE with AP (Write Burst with Autoprecharge) L H L L Valid H Col 3
BURST TERMINATE or enter DEEP POWER DOWN L H H L X X X 4, 5
PRECHARGE (Deactivate Row in selected bank) L L H L Valid L X 6
PRECHARGE ALL (Deactivate rows in all Banks) L L H L X H X 6
AUTO REFRESH or enter SELF REFRESH L L L H X X X 7,8,9
MODE REGISTER SET L L L L Valid Op_Code 10
Function DM DQ Note
Write Enable L Valid 11
Write Inhibit H X 11
Rev 0.1 / Feb. 2006 12
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
CKE TRUTH TABLE
Note:
1. CKEn is the logic state of CKE at clock edge
n
; CKE
n
-1 was the state of CKE at the previous clock edge.
2. Current state is the state of LP DDR immediately prior to clock edge
n
.
3. COMMAND
n
is the command registered at clock edge n, and ACTION
n
is the result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of
the Functional Description.
9. The clock must toggle at least one time during the tXP period.
10. The clock must toggle at least once during the tXSR time.
CKEn-1 CKEnCurrent State COMMAND
n
ACTION
n
Note
L L Power Down X Maintain Power Down
L L Self Refresh X Maintain Self Refresh
L L Deep Power Down X Maintain Deep Power
Down
L H Power Down NOP or DESELECT Exit Power Down 5,6,9
L H Self Refresh NOP or DESELECT Exit Self Refresh 5,7,10
L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5,8
H L All Banks Idle NOP or DESELECT Precharge Power
Down Entry 5
HLBank(s) ActiveNOP or DESELECT
Active Power Down
Entry 5
H L All Banks Idle AUTO REFRESH Self Refresh entry
H L All Banks Idle BURST TERMINATE Enter Deep Power
Down
H H See the other Truth Tables
Rev 0.1 / Feb. 2006 13
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
CURRENT STATE BANK
n
TRUTH TABLE (COMMAND TO BANK
n
)
Note:
1. The table applies when both CKE
n
-1 and CKE
n
are HIGH, and after tXSR or tXP has been met if the previous state was
Self Refresh or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. This command may or may not be bank specific. If all banks are being precharged,
they must be in a valid state for precharging.
5. A command other than NOP should not be issued to the same bank while a READ or WRITE Burst with
auto precharge is enabled.
6. The new Read or Write command could be auto precharge enabled or auto precharge disabled.
Current State Command Action Notes
CS RAS CAS WE Description
Any
H X X X DESELECT (NOP) Continue previous Operation
L H H H NOP Continue previous Operation
Idle
L L H H ACTIVE Select and activate row
L L L H AUTO REFRESH Auto refresh 10
L L L L MODE REGISTER SET Mode register set 10
L L H H PRECHARGE No action if bank is idle
Row Active
L H L H READ Select Column & start read burst
L H L L WRITE Select Column & start write burst
L L H L PRECHARGE Deactivate Row in bank (or banks) 4
Read
(without Auto
recharge)
LH L H READ Truncate Read &
start new Read burst 5,6
LH L L WRITE Truncate Read &
start new Write burst 5,6,13
L L H L PRECHARGE Truncate Read, start Precharge
L H H L BURST TERMINATE Burst terminate 11
Write
(without Auto
precharge)
LH L H READ Truncate Write &
start new Read burst 5,6,12
LH L L WRITE Truncate Write &
start new Write burst 5,6
L L H L PRECHARGE Truncate Write, start Precharge 12
Rev 0.1 / Feb. 2006 14
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
7. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
8. The following states must not be interrupted by a command issued to the same bank.
DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring
during these states. Allowable commands to the other bank are determined by its current state and Truth Table3,
and according to Truth Table 4.
Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the ''row active'' state.
Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends
when tRP has been met. Once tRP has been met, the bank will be in the idle state.
Write with AP Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
to each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met.
Once tRFC is met, the LP DDR will be in an ''all banks idle'' state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once tMRD is met, the LP DDR will be in an ''all banks idle'' state.
Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
10. Not bank-specific; requires that all banks are idle and no bursts are in progress.
11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank.
12. Requires appropriate DM masking.
13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be
used to end the READ prior to asserting a WRITE command.
Rev 0.1 / Feb. 2006 15
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
CURRENT STATE BANK
n
TRUTH TABLE (COMMAND TO BANK
m
)
Current State Command Action Notes
CS RAS CAS WE Description
Any
H X X X DESELECT (NOP) Continue previous Operation
L H H H NOP Continue previous Operation
Idle X X X X ANY Any command allowed to bank m
Row Activating,
Active, or Pre-
charging
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8
L H L L WRITE Start WRITE burst 8
LLHL PRECHARGE Precharge
Read with Auto
Precharge dis-
abled
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8
L H L L WRITE Start WRITE burst 8,10
LLHL PRECHARGE Precharge
Write with Auto
precharge dis-
abled
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8,9
L H L L WRITE Start WRITE burst 8
LLHL PRECHARGE Precharge
Read with Auto
Precharge
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 5,8
L H L L WRITE Start WRITE burst 5,8,10
LLHL PRECHARGE Precharge
Write with Auto
precharge
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 5,8
L H L L WRITE Start WRITE burst 5,8
LLHL PRECHARGE Precharge
Rev 0.1 / Feb. 2006 16
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Note:
1. The table applies when both CKE
n
-1 and CKE
n
are HIGH, and after tXSR or tXP has been met if the previous state was
Self Refresh or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
5. Read with AP enabled and Write with AP enabled: The read with Autoprecharge enabled or Write with Autoprecharge
enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the
precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the
earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the
precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts
with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period,
of the Read with Autoprecharge enabled or Write with Autoprecharge enabled states, ACTIVE, PRECHARGE, READ, and
WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands
to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data
and WRITE data must be avoided).
6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
7. A BURST TERMINATE command cannot be issued to another bank;
it applies to the bank represented by the current state only.
8. READs or WRITEs listed in the Command column include READs and WRITEs with AUTO PRECHARGE enabled and
READs and WRITEs with AUTO PRECHARGE disabled.
9. Requires appropriate DM masking.
10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command
must be issued to end the READ prior to asserting a WRITE command.
Rev 0.1 / Feb. 2006 17
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
ABSOLUTE MAXIMUM RATING
DC OPERATING CONDITION (TA= -25 to 85oC )
Note :
1. All Voltages are referenced to VSS = 0V
2. VDDQ must not exceed the level of VDD
CLOCK INPUTS (TA= -25 to 85oC )
Note :
1. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on CK.
2. The value of VIX is expected to be 0.5*VDDQ and must track variations in the DC level of the same.
Parameter Symbol Rating Unit
Ambient Temperature TA-25 ~ 85 oC
Storage Temperature TSTG -55 ~ 150 oC
Voltage on Any Pin relative to VSS VIN, VOUT -0.3 ~ VDDQ+0.3 V
Voltage on VDD relative to VSS VDD -0.3 ~ 2.7 V
Voltage on VDDQ relative to VSS VDDQ -0.3 ~ 2.7 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD0.7 W
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 1.7 1.8 1.90 V 1
Power Supply Voltage VDDQ 1.7 1.8 1.90 V 1, 2
Parameter Symbol Min Max Unit Note
DC Input Voltage VIN -0.3 VDDQ+0.3 V
DC Input Differential Voltage VID(DC) 0.4*VDDQ VDDQ+0.6 V 1
AC Input Differential Voltage VID(AC) 0.6*VDDQ VDDQ+0.6 V 1
AC Differential Crosspoint Voltage VIX 0.4*VDDQ 0.6*VDDQ V2
CK
CK
VID
tCK
tCL tCH
VREF
VDD
VSS
VIX
VDD
VSS
VIL
VIH
t
Delta
Input signal slew rate = [VIH(AC) - VIL(AC)] / t
Delta
Rev 0.1 / Feb. 2006 18
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Address And Command Inputs (A0~An, BA0, BA1, CKE, CS, RAS, CAS, WE )
Data Inputs (DQ0 - DQ15, UDM, LDM, UDQS, LDQS)
Data Outputs (DQ0 - DQ15, UDQS, LDQS)
DC CHARACTERRISTICS I (TA= -25 to 85oC)
Note :
1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V.
2. DOUT is disabled. VOUT= 0 to 1.9V.
Parameter Symbol Min Max Unit Note
Input High Voltage VIH 0.8*VDDQ VDDQ+0.3 V
Input Low Voltage VIL -0.3 0.2*VDDQ V
Parameter Symbol Min Max Unit Note
DC Input High Voltage VIHD(DC) 0.7*VDDQ VDDQ+0.3 V
DC Input Low Voltage VILD(DC) -0.3 0.3*VDDQ V
AC Input High Voltage VIHD(AC) 0.8*VDDQ VDDQ+0.3 V
AC Input Low Voltage VILD(AC) -0.3 0.2*VDDQ V
Parameter Symbol Min Max Unit Note
DC Output High Voltage
(IOH = -0.1mA) VOH 0.9*VDDQ -V
DC Output High Voltage
(IOL = 0.1mA) VOL -0.1*VDDQ V
Parameter Symbol Min Max Unit Note
Input Leakage Current ILI -1 1 uA 1
Output Leakage Current ILO -1.5 1.5 uA 2
Rev 0.1 / Feb. 2006 19
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
AC OPERATING TEST CONDITION (TA= -25 to 85 oC, VDD = 1.8V, VSS = 0V)
Note 1.
Input / Output Capaci-
tance (TA= 25 oC, f=1MHz)
Note :
1.These values are guaranteed by design and are tested on a sample base only.
2.Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This
is required to match signal propagation times of DQ, DQS and DM in the system.
3.Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD,
VDDQ are applied and all other pins (except the pin under test) floating. DQ's should be in high impedance state. This may be achieved
by pulling CKE to low level.
4.These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.
Parameter Symbol Value Unit Note
AC Input High/Low Level Voltage VIH / VIL 0.9*VDDQ/0.2 V
Input Timing Measurement Reference Level Voltage Vtrip 0.5*VDDQ V
Input Rise/Fall Time tR / tF1ns
Output Timing Measurement Reference Level Voltage Voutref 0.5*VDDQ V
Output Load Capacitance for Access Time Measurement CL pF 1
Parameter Symbol Speed Unit Note
Min Max
Input capacitance, CK, CK CCK 1.5 3.5 pF 1, 3
Input capacitance delta, CK, CK CDCK - 0.25 pF 1, 3
Input capacitance, all other input-only pins CI 1.5 3.0 pF 1, 3
Input capacitance delta, all other input-only pins CDI - 0.5 pF 1, 3
Input/output capacitance, DQ, DM, DM, DQS CIO 2.0 4.5 pF 1,2,3
Input/output capacitance delta, DQ, DM, DQS CDIO - 0.5 pF 1,2,3
Test Load for Full Drive Strength Buffer
(20 pF)
Test Load for Half Drive Strength Buffer
(10 pF)
Output
Z
O
=50Ω
Rev 0.1 / Feb. 2006 20
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Mobile DDR OUTPUT SLEW RATE CHARACTERRISTICS
Note :
1. Measured with a test load of 20pF connected to VSSQ
2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC)
3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process
variation.
Mobile DDR AC OVERSHOOT / UNDERSHOOT SPECIFICATION
Note :
1. This specification is internded for devices with no clamp protection and is guaranteed by design.
Parameter Min Max Unit Note
Pull-up and Pull-Down Slew Rate for Full Strength Driver 0.7 2.5 V/ns 1, 2
Pull-up and Pull-Down Slew Rate for Half Strength Driver 0.3 1.0 V/ns 1, 2
Output Slew Rate Matching ratio (Pull-up to Pull-down) 0.7 1.4 - 3
Parameter Specification
Maximum peak amplitude allowed for overshoot 0.5V
Maximum peak amplitude allowed for undershoot 0.5V
The area between overshoot signal and VDD must be less than or equal to 3V-ns
The area between undershoot signal and GND must be less than or equal to 3V-ns
2.5V
2.0V
1.5V
1.0V
0.5V
0.0V
-0.5V
Overshoot
Undershoot
VDD
VSS
Max. Amplitude = 0.5V Max. Area = 3V-ns
Time (ns)
Voltage (V)
Rev 0.1 / Feb. 2006 21
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
DC CHARACTERISTICS II (TA= -25 to 85oC) (Sheet 1 of 2)
Parameter Sym-
bol Test Condition
Max
Unit Note
DDR
333 DDR
266 DDR
200
Operating one bank
active-precharge cur-
rent
IDD0
tRC = tRC
(min
)
tCK = tCK
(min)
CKE is HIGH
CS is HIGH between valid commands
address inputs are SWITCHING
data bus inputs are STABLE
60 55 50 mA 1
Precharge power-
down standby current IDD2P
all banks idle,
CKE is LOW
CS is HIGH, tCK = tCK
(min)
address and control inputs are SWITCHING
data bus inputs are STABLE
0.3 mA
Precharge power-
down standby
current with clock
stop
IDD2PS
all banks idle,
CKE is LOW
CS is HIGH, CK = LOW, CK = HIGH
address and control inputs are SWITCHING
data bus inputs are STABLE
0.3 mA
Precharge non pow-
er-down standby cur-
rent
IDD2N
all banks idle,
CKE is HIGH
CS is HIGH, tCK = tCK
(min)
address and control inputs are SWITCHING
data bus inputs are STABLE
10
mA
Precharge non
power-down standby
current with clock
stop
IDD2NS
all banks idle,
CKE is HIGH
CS is HIGH, CK = LOW, CK = HIGH
address and control inputs are SWITCHING
data bus inputs are STABLE
1.0
Active power-down
standby current IDD3P
one bank active,
CKE is LOW
CS is HIGH, tCK = tCK
(min)
address and control inputs are SWITCHING
data bus inputs are STABLE
3.0
mA
Active power-down
standby current with
clock stop
IDD3PS
one bank active,
CKE is LOW
CS is HIGH, CK = LOW, CK = HIGH
address and control inputs are SWITCHING
data bus inputs are STABLE
1.0
Rev 0.1 / Feb. 2006 22
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
DC CHARACTERISTICS II (TA= -25 to 85oC) (Sheet 2 of 2)
Parameter Sym-
bol Test Condition
Max
Unit Note
DDR
333 DDR
266 DDR
200
Active non power-
down standby current IDD3N
one bank active
CKE is HIGH
CS is HIGH, tCK = tCK
(min)
address and control inputs are SWITCHING
data bus inputs are STABLE
15
mA
Active non power-
down standby current
with clock stop
IDD3NS
one bank active
CKE is HIGH
CS is HIGH, CK = LOW, CK = HIGH
address and control inputs are SWITCHING
data bus inputs are STABLE
10
Operating burst read
current IDD4R
one bank active
BL=4
CL=3
tCK = tCK
(min
)
continuous read bursts
IOUT=0mA
address inputs are SWITCHING
50% data change each burst transfer
80 70 60
mA 1
Operating burst write
current IDD4W
one bank active
BL=4
tCK=tCK
(min)
continuous write bursts
address inputs are SWITCHING
50% data change each burst transfer
90 80 70
Auto Refresh Current IDD5
tRC=tRFC
(min)
tCK=tCK
(min)
burst refresh
CKE is HIGH
address and control inputs are SWITCHING
data bus inputs are STABLE
85 80 70 mA
Self Refresh Current IDD6
CKE is LOW
CK=LOW, CK=HIGH, tCK=tCK
(min)
Extended Mode Register set to all 0's
address and control inputs are STABLE
data bus inputs are STABLE
See Next Page mA 2
Standby Current in
Deep Power Down
Mode
IDD8 See p.42 ~ 44
Rev 0.1 / Feb. 2006 23
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Note : IDD values are for full operating range of voltage and temperature.
1. IDD specifications are tested after the device is properly intialized
2. Input slew rate is 1V/ns
3. Definitions for IDD:
LOW is defined as VIN ≤ 0.1 * VDDQ
HIGH is defined as VIN ≥ 0.9 * VDDQ
STABLE is defined as inputs stable at a HIGH or LOW level
SWITCHING is defined as
- address and command: inputs changing between HIGH and LOW once per two clock cycles
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle
DM and DQS are STABLE
DC CHARACTERISTICS III - IDD6 (Max)
Temp.
( oC) Memory Array Unit
4 Banks 2 Banks 1 Bank
45 200 140 100 uA
85 400 280 200 uA
Rev 0.1 / Feb. 2006 24
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 1 of 2)
Now under evaluation by the Hynix Development Division.
Parameter Symbol DDR333 DDR266 DDR200 Unit Note
Min Max Min Max Min Max
DQ Output Access Time (from CK, CK)tAC 2.0 5.5 2.0 6.5 2.0 7.0 ns
DQS Output Access Time (from CK, CK)tDQSCK 2.0 5.5 2.0 6.5 2.0 7.0 ns
Clock High-level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock Low-level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock Half Period tDQSCK
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-ns 1,2
System Clock
Cycle Time
CAS Laten-
cy=3 tCK3 6.0 - 7.5 - 10 - ns 3
DQ and DM Input Setup Time tDS 0.7 0.9 1.2 ns 4,5,6
DQ and DM Input Hold Time tDH 0.7 0.9 1.2 ns 4,5,6
DQ and DM Input Pulse Width tDIPW 2.1 - 1.8 - 2.4 - ns 7
Address and Control Input Setup Time tIS 1.3 1.5 1.7 ns 6,8,9
Address and Control Input Hold Time tIH 1.3 1.5 1.7 ns 6,8,9
Address and Control Input Pulse Width tIPW 2.7 - 3.0 - 3.4 - ns 7
DQ & DQS Low-impedance time from CK,
CK tLZ 1.0 - 1.0 - 1.0 - ns 10
DQ & DQS High-impedance time from CK,
CK tHZ 5.5 6.5 7.0 ns 10
DQS - DQ Skew tDQSQ 0.5 0.6 0.7 ns 11
DQ / DQS output hold time from DQS tQH tHP -
tQHS
tHP -
tQHS
tHP -
tQHS ns 2
Data Hold Skew Factor tQHS 0.65 0.75 1.0 ns 2
Write Command to 1st DQS Latching
Transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS Input High-Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS Input Low-Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Rev 0.1 / Feb. 2006 25
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 2 of 2)
Now under evaluation by the Hynix Development Division.
Parameter Symbol DDR266 DDR200 DDR200 Unit Note
Min Max Min Max Min Max
DQS Falling Edge to CK Setup Time tDSS 0.2-0.2-0.2-tCK
DQS Falling Edge Hold Time From CK tDSH 0.2-0.2-0.2-tCK
MODE REGISTER SET Command Period tMRD 2-2-2-tCK
Write Preamble Setup Time tWPRES 0-0-0-ns12
Write Postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 13
Write Preamble tWPRE 0.25 - 0.25 - 0.25 - tCK
Read Preamble CAS Latency=3 tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 14
Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
ACTIVE to PRECHARGE Command Period tRAS 42 70,00
045 70,00
050 70,00
0ns
ACTIVE to ACTIVE Command Period tRC 60 - 75 - 80 - ns
AUTO REFRESH to ACTIVE/AUTO REFRESH
Command Period tREFC 80 - 80 - 80 - ns
ACTIVE to READ or WRITE Delay tRCD
18 - 22.5 - 30 - ns 15
30 - 30 - 30 - ns 16
PRECHARGE Command Period tRP
18 - 22.5 - 30 - ns 15
30 - 30 - 30 - ns 16
ACTIVE Bank
A
to ACTIVE Bank
B
Delay tRRD 12 - 15 - 15 - ns
WRITE Recovery Time tWR 15 - 15 - 15 - ns
Auto Precharge Write Recovery + Precharge
Time tDAL (tWR/tCK) + (tRP/tCK)17
Internal Write to Read Command Delay tWTR 2-1-1-tCK
Self Refresh Exit to next valid Command Delay tXSR 200 - 200 - 200 - ns
Exit Power Down to next valid Command Delay tXP 25 - 25 - 25 - ns
CKE
min
. Pulse Width (High and Low Pulse
Width) tCKE 2-2-2-tCK
Average Periodic Refresh Interval tREFI 7.8 - 7.8 - 7.8 - us 18
Refresh Period tREF -64-64-64ms
Rev 0.1 / Feb. 2006 26
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Note :
1. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH)
2. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).
tQHS accounts for
1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the
worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
3. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes.
4. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to
VIL(AC) for falling input signals.
5. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
6. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
7. These parameters guarantee device timing but they are not necessarily tested on each device.
8. The transition time for address and command inputs is measured between VIH and VIL.
9. A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
11. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from HIGH to LOW at this time, depending on tDQSS.
13. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
14. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the
system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
15. Speed bin (CL-tRCD-tRP) = 3-3-3 (DDR266 only), 3-5-5 (DDR333 only)
16. Speed bin (CL-tRCD-tRP) = 3-4-4 (DDR266 only), 3-5-5 (DDR333 only)
17. tDAL = (tWR/tCK) + (tRP/tCK) : for each of the terms above, if not already an integer, round to the next higher integer.
18. A maximum of eight Refresh commands can be posted to any given Low-Power DDR SDRAM, meaning that the maximum absolute
interval between any Refresh command and the next Refresh command is 8*tREFI.
Rev 0.1 / Feb. 2006 27
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Mobile DDR SDRAM OPERATION
State Diagram
IDLE
ALL BANK
PCG.
AUTO
REFRESH
SELF
REFRESH
PCG.
POWER
DOWN
(E)MRS
SET
WRITE READ
Precharge
ALL
ACTIVE
POWER
DOWN
ROW
ACTIVE
MRS,
EMRS REFS
CKEL
REFA
CKEH
ACT
CKEL
CKEH
WRITE
WRITE READ
REFSX
COMMAND Input
AUTOMATIC
Sequence
DEEP
POWER
DOWN
POWER
ON
PCG.
ALL
BANKS
Power
applied
DPDS
DPDSX
BURST
STOP
WRITEA
READ
READA
BST
READ A
WRITE A
WRITEA READA
READ
PRE
PRE PRE
ACT :
Active
BST :
Burst
CKEL :
Enter Power-
Down
CKEH :
Exit Power-Down
DPDS :
Enter Deep
Power-Down
DPDSX :
Exit Deep Power-
DownEMRS
EMRS :
Ext. Mode Reg.
Set
MRS :
Mode Register Set
PRE :
Precharge
PREALL :
Precharge All
Banks
REFA :
Auto Refresh
REFS :
Enter Self Refresh
REFSX :
Exit Self Refresh
READ :
Read w/o Auto
Precharge
READA :
Read with Auto
Precharge
WRITE :
Write w/o Auto
Precharge
WRITEA :
Write with Auto
Precharge
Rev 0.1 / Feb. 2006 28
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
DESELECT
The DESELECT function (CS = High) prevents new commands from being executed by the Mobile DDR SDRAM. The
LPDDR SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to perform a NOP to a Mobile DDR SDRAM that is selected (CS = Low,
RAS = CAS = WE = High). This prevents unwanted commands from being registered during idle or wait states. Oper-
ations already in progress are not affected. (see to next figure)
ACTIVE
The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of
the BA0,BA1 inputs selects the bank, and the address provided on A0-A12(or the highest address bit) selects the row.
(see to next figure)
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank
must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be acti-
vated.
The row remains active until a PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) com-
mand is issued to the bank.
A PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command must be issued before
opening a different row in the same bank.
CS
A0~A9,
A11, A12
WE
CAS
RAS
Don't Care
/CLK
CLK
CKE
High-Z
BA0,1
CS
A0~A9,
A11, A12
WE
Bank Address
CAS
RAS
Row Address
Don't Care
/CL
K
CLK
CKE
High-Z
RA
BA
BA0,1
NOP command ACTIVATING A SPECIFIC
ROW IN A SPECIFIC BANK
Rev 0.1 / Feb. 2006 29
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Once a row is Open(with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the
tRCD specification. tRCD (
MIN
) should be divided by the clock period and rounded up to the next whole number to
determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row
has been closed(precharge). The minimum time interval between successive ACTIVE commands to the same bank is
defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in
a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to differ-
ent banks is defined by tRRD.
Don't Care
Once a row is Open(with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the
tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to
determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered.
/
CLK
CLK
NOP NOPNOPNOP
tRCD
Command
A
ddress
Write A
With A/P
Bank
B
ACT
NOP
Bank A
ACT
Bank A
Col
Bank
B
Row
Bank A
Row
Bank
A
ACT
Bank
A
Row
tRRD
tRC
Rev 0.1 / Feb. 2006 30
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
READ / WRITE COMMAND
The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and
address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used. If autoprecharge is selected, the row being
accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open
for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.
The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble
and the last data-out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon com-
pletion of a burst, assuming no new READ commands have been initiated, the I/O's will go high-Z.
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank
and address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used.If autoprecharge is selected, the row being
accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open
for subsequent access. Input data appearing on the data bus, is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be
written to the memory; if the DM signal is registered high, the corresponding data-inputs will be ignored, and a write
will not be executed to that byte/column location. The memory controller drives the DQS during write operations. The
initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write
postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z
and any additional input data will be ignored.
READ / WRITE COMMAND
CS
A0 ~ A8
WE
CAS
RAS
Don't Care
/CL
K
CLK
CKE
High-Z
CA
BA
BA0,1
Enable
Auto
Precharge
Disable
Auto
Precharge
Read Command
Operation Write Command
Operation
A10
CS
A0 ~ A8
WE
CAS
RAS
/CLK
CLK
CKE
High-Z
CA
BA
BA0,1
A10
Rev 0.1 / Feb. 2006 31
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
READ
The basic Read timing parameters for DQs are shown next Figure(Basic Read Timing Parameter).
; they apply to all Read operations. During Read bursts, DQS is driven by the Mobile DDR SDRAM along with the out-
put data. The initial Low state of the DQS is known as the read preamble; the Low state coincident with last data-out
element is known as the read postamble.
Basic Read Timing Parameter
Do
n
Do
n+1
Do
n+2
Do
n+3
/CLK
CLK
tCK tCK tCH tCL
tRPRE
tDQSCK
tDQSQ
max
tAC
tLZ tQH
tDQSCK
tQH
tQH
tHZ
tQH
tRPRE
tDQSCK
tLZ
tDQSCK
tRPST
tAC
tDQSQ max
Do
n
Do
n+1
Do
n+2
Do
n+3
DQS
DQ
DQS
DQ
Don't Care
1) Do
n
: Data Out from column n
2) All DQ are vaild tAC after the CK edge
All are vaild tDQSQ after the DQS edge, regardless of tAC
Rev 0.1 / Feb. 2006 32
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out elements are
edge aligned to successive edges of DQS. This is shown in naxt fig. with a CAS latency of 2 and 3.Upon completion of
a read burst, assuming no other READ command has been initiated, the DQs will go to High-Z.
Read Burst Showing CAS Latency
/CLK
CLK
Do
n
Do
n
READ NOP NOP NOP NOP NOP
BA, Col
n
CL =3
CL =2
Don't Care
1) Do
n
: Data out from column n
2) BA, Col
n
= Bank A, Column n
3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following
Do
n
4) Shown with nominal tAC, tDQSCK and tDQSQ
Command
A
ddress
DQS
DQ
DQS
DQ
Rev 0.1 / Feb. 2006 33
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
READ to READ
Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the
new burst follows either the last element of a completed burst or the last desired element of a longer burst that is
being truncated. The new READ command should be issued X cycles after the first READ command, where X equals
the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture).
Consective Read Bursts
A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are
shown in Figure. Full-speed random read accesses within a page or pages can be performed as shown in Fig.
/CLK
CLK
Do
n
Do
b
Do
n
READ NOP READ NOP NOP NOP
BA, Col
n
CL =3
CL =2
Don't Care
1) Do
n
(or
b
): Data out from column n
2) BA, Col
n (b)
= Bank A, Column n (b)
3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following
Do
n (b)
4) Shown with nominal tAC, tDQSCK and tDQSQ
Command
A
ddress
DQS
DQ
DQS
DQ
BA, Col
b
Do
b
Rev 0.1 / Feb. 2006 34
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Non-Consective Read Bursts
Randum Read Bursts
/CLK
CLK
Do
n
Do
n
READ NOP NOP READ NOP NOP
BA, Col
n
CL =3
CL =2
Don't Care
1) Do
n
(or
b
): Data out from column n
2) BA, Col
n (b)
= Bank A, Column n (b)
3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following
Do
n (b)
4) Shown with nominal tAC, tDQSCK and tDQSQ
Command
A
ddress
DQS
DQ
DQS
DQ
BA, Col
b
Do
b
/CLK
CLK
Do
n
Do
x'
Do
n
READ READ READ READ NOP NOP
BA, Col
n
CL =3
CL =2
Don't Care
1) Do
n,
etc: Data out from column n, etc
n', x', etc : Data Out elements, accoding to the programmd burst order
2) BA, Col
n
= Bank A, Column n
3) Burst Length = 2, 4, 8 or 16 in cases shown (if burst of 4, 8, or 16, the burst is interrupted)
4) Read are to active row in any banks
Command
A
ddress
DQS
DQ
DQS
DQ
BA, Col
b
Do
b
BA, Col
x
BA, Col
g
Do
n'
Do
x
Do
x'
Do
b'
Do
g
Do
g'
Do
n'
Do
x
Do
b
Do
b'
Rev 0.1 / Feb. 2006 35
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
READ BURST TERMINATE
Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is
equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ com-
mand where X equals the desired data-out element pairs.
Terminating a Read Burst
/CLK
CLK
READ BURST NOP NOP NOP NOP
BA, Col
n
CL =3
CL =2
Don't Care
1) Do
n
: Data out from column n
2) BA, Col
n
= Bank A, Column n
3) Cases shown are bursts of 4, 8, or 16 terminated after 2 data elements
4) Shown with nominal tAC, tDQSCK and tDQSQ
Command
A
ddress
DQS
DQ
DQS
DQ
Rev 0.1 / Feb. 2006 36
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
READ to WRITE
Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If trun-
cation is necessary, the BURST TERMINATE command must be used, as shown in next fig. for the case of nominal
tDQSS.
Read to Write
/CLK
CLK
Do
n
Do
n
READ BST NOP WRITE NOP
BA, Col
n
CL =3
CL =2
Don't Care
1) DO
n
= Data Out from column n; DI b = Data In to column b
2) Burst length = 4, 8 or 16 in the cases shown; if the burst length is 2, the BST command can be
ommitted
3) Shown with nominal tAC, tDQSCK and tDQSQ
Command
Address
DQS
DQ
DQS
DQ
BA, Col
b
NOP
DM
READ BST NOP NOP NOP
BA, Col
n
Command
Address BA, Col
b
WRITE
tDQSS
Rev 0.1 / Feb. 2006 37
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
READ to PRECHARGE
A Read burst may be followed by or truncated with a PRECHARGE command to the same bank (provided Auto Pre-
charge was not activated). The PRECHARGE command should be issued X cycles after the READ command, where X
equal the number of desired data-out element pairs.
Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Note that part of the row precharge time is hidden during the access of the last data-out elements.In the case of a
Read being executed to completion, a PRECHARGE command issued at the optimum time (as described above) pro-
vides the same operation that would result from Read burst with Auto Precharge enabled.
The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at
the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to
truncate bursts.
READ to PRECHARGE
/CLK
CLK
Do
n
Do
n
READ NOP PRE NOP NOP ACT
BA, Col
n
CL =3
CL =2
Don't Care
1) DO
n
= Data Out from column n
2) Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8 or 16
3) Shown with nominal tAC, tDQSCK and tDQSQ
4) Precharge may be applied at (BL / 2) tCK after the READ command.
5) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable
banks.
6) The ACTIVE command may be applied if tRC has been met.
Command
A
ddress
DQS
DQ
DQS
DQ
Bank
A, All
BA,
Row
tRP
Rev 0.1 / Feb. 2006 38
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Write
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
Basic Write timing parameters for DQs are shown in Figure; they apply to all Write operations.
Basic Write Timing Parameters
During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the
WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of
DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS
following the last data-in element is called the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a rel-
atively wide range - from 75% to 125% of a clock cycle. Next fig. shows the two extremes of tDQSS for a burst of 4.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain high-Z and any
aditional input data will be ignored.
/CLK
CLK
tCK tCH tCL
D
IN
D
IN
DQS
DQS
DQ,
DM
DQ,
DM
tDQSS tDQSH
tDSH tDSH
tWPST
tWPRES
tDS tDH
tWPRE
tDS tDH
tWPRES tWPRE
tDQSS tDQSH
tWPST
tDSS tDSS
tDQSL
Don't Care
1) D
IN
: Data in for column n
2) 3 subsequent elements of Data in are applied in the programmed order following D
IN
3) tDQSS : eatch rising edge of DQS must fall within the +/-25(percentage) Window of the
corresponding positive clock edge
Rev 0.1 / Feb. 2006 39
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Write Burst (min. and max. tDQSS)
/CLK
CLK
WRITE NOP NOP NOP NOP
BA, Col
b
tDQSS
min
Don't Care
1) DO
n
= Data Out from column n; DI b = Data In to column b
2) Burst length = 4, 8 or 16 in the cases shown; if the burst length is 2, the BST command can be
ommitted
3) Shown with nominal tAC, tDQSCK and tDQSQ
Command
Address
DQS
DQ
DQS
DQ
NOP
DM
DM
tDQSS
max
Rev 0.1 / Feb. 2006 40
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
WRITE to WRITE
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case,
a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of
the clock following the previous WRITE command.The first data-in element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The
new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of
desired data-in element pairs.
Concatenated Write Bursts
/CLK
CLK
WRITE NOP WRITE NOP NOP
BA, Col
b
tDQSS
min
Don't Care
1) DI
b
(
n
) = Data In to column b (column n)
2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements
of Data In are applied in the programmed order following DI n.
3) Non-interrupted bursts of 4 are shown.
4) Each WRITE command may be to any active bank
Command
Address
DQS
DQ
DQS
DQ
NOP
DM
DM
BA, Col
n
Di
b
Di
n
Di
b
Di
n
tDQSS
max
Rev 0.1 / Feb. 2006 41
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Non-Concatenated Write Bursts
Random Write Cycles
/CLK
CLK
WRITE NOP NOP NOP NOP
BA, Col
b
Don't Care
1) DI
b
(
n
) = Data In to column b (or column n).
2) 3 subsequent elements of Data In are applied in the programmed order following DI
b
. 3 subsequent elements
of Data In are applied in the programmed order following DI
n
.
3) Non-interrupted bursts of 4 are shown.
4) Each WRITE command may be to any active bank and may be to the same or different devices.
Command
Address
DQS
DQ
NOP
DM
tDQSS
max
CLK
CLK
WRITE WRITE WRITE WRITE NOP
BA, Col
b
Don't Care
1) DI b etc. = Data In to column b, etc.
; b', etc. = the next Data In following DI b, etc. according to the programmed burst order
2) Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4, 8 or 16, burst would be truncated.
3) Each WRITE command may be to any active bank and may be to the same or different devices.
Command
A
ddress
WRITE
BA, Col
n
BA, Col
x
BA, Col
a
BA, Col
g
DQS
DM
tDQSS
max
DQ Di
b
Di
b'
Di
x
Di
x'
Di
n
Di
n'
Di
a
Di
a'
Rev 0.1 / Feb. 2006 42
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
WRITE to READ
Data for any Write burst may be followed by a subsequent READ command. To follow a Write without truncating the
write burst, tWTR should be met as shown in Figure.
Data for any Write burst may be truncated by a subsequent READ command as shown in Figure. Note that the only
data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in
must be masked with DM.
/
CL
K
CLK
WRITE NOP NOP NOP NOP
BA, Col
b
Don't Care
1) DI
b
= Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b.
2) A non-interrupted burst of 4 is shown.
3) tWTR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
Command
Address
DQS
DQ
READ
DM
tDQSS
max
BA, Col
n
tWTR CL=3
NOP
Di
b
Rev 0.1 / Feb. 2006 43
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Interrupting Write to Read
/
CL
K
CLK
WRITE NOP NOP READ NOP
BA, Col
b
Don't Care
1) DI
b
= Data In to column b. DO
n
= Data Out from column n.
2) An interrupted burst of 4 is shown, 2 data elements are written. 3 subsequent elements of Data In are applied in the programmed order
following DI b.
3) tWTR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
Command
Address
DQS
DQ
NOP
DM
tDQSS
max
tWTR CL=3
NOP
Di
b
BA, Col
n
Do
n
Rev 0.1 / Feb. 2006 44
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto
Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in
Fig.
Non-Interrupting Write to Precharge
/CLK
CLK
WRITE NOP NOP NOP PRE
BA, Col
b
Don't Care
1) DI b (n) = Data In to column b (column n)
2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements
of Data In are applied in the programmed order following DI n.
3) Non-interrupted bursts of 4 are shown.
4) Each WRITE command may be to any active bank
Command
Address
DQS
DQ
NOP
DM
tDQSS
max
BA
a
(or
All
)
tWR
Di
b
Rev 0.1 / Feb. 2006 45
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.
Note that only data-in pairs that are registered prior to the tWR period are written to the internal array, and any subse-
quent data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met.
Interrupting Write to Precharge
/CLK
CLK
WRITE NOP NOP NOP NOP
BA, Col
b
Don't Care
1) DI b = Data In to column b .
2) An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written.
3) tWR is referenced from the positive clock edge after the last desired Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) *1 = can be Don't Care for programmed burst length of 4
6) *2 = for programmed burst length of 4, DQS becomes Don't Care at this point
Command
Address
DQS
DQ
PRE
DM
tDQSS
max
tWR
Di
b
*
2
*
1
*
1
*
1
*
1
BA
a
(or
All
)
Rev 0.1 / Feb. 2006 46
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled). The most recently
registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation sec-
tion of this datasheet. Note the BURST TERMINATE command is not bank specific. This command should not be used
to terminate write bursts.
BURST TERMINATE COMMAND
CS
A0 ~ A9
A11, A12
WE
CAS
RAS
Don't Care
/CLK
CLK
CKE
High-Z
BA0, 1
Rev 0.1 / Feb. 2006 47
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.
Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is
completed.
If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged,
A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE
command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the
process of precharging.
PRECHARGE command
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but with-
out requiring an explicit command.
This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write
command. This precharges the bank/row after the Read or Write burst is complete.
Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is
desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.
The user must not issue another command to the same bank until the precharge time (tRP) is completed.
Don't Care
CS
A0~A9
A11, A12
WE
CAS
RAS
/CLK
CLK
CKE
High-Z
BA
BA0,1
A10
Bank Address
A10 defines the precharge
mode when a precharge
command, a read command
or a write command is
issued.
If A10 = High when a
precharge command is
issued, all banks are
precharged.
If A10 = Low when a
precharge command is
issued, only the bank that is
selected by BA1/BA0 is
precharged.
If A10 = High when read or
write command, auto-
precharge function is
enabled.
While A10 = Low, auto-
precharge function is
disabled.
Rev 0.1 / Feb. 2006 48
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
AUTO REFRESH AND SELF REFRESH
Mobile DDR devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two
ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:
- AUTO REFRESH.
This command is used during normal operation of the Mobile DDR. It is non persistent, so must be issued each time a
refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile DDR requires
AUTO REFRESH commands at an average periodic interval of tREFI.
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile DDR, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*tREFI.
-SELF REFRESH.
This state retains data in the Mobile DDR, even if the rest of the system is powered down (even without external clock-
ing). Note refresh interval timing while in Self Refresh mode is scheduled internally in the Mobile DDR and may vary
and may not meet tREFI time.
''Don't Care'' except CKE, which must remain low. An internal refresh cycle is scheduled on Self Refresh entry. The pro-
cedure for exiting Self Refresh mode requires a series of commands. First clock must be stable before CKE going high.
NOP commands should be issued for the duration of the refresh exit time (tXSR), because time is required for the com-
pletion of any internal refresh in progress.
The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is
raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recom-
mended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self
Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section.
The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM
operates refresh cycle asynchronously.
The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile DDR
can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode regis-
ters. The Mobile DDR can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature
Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of
PASR(Partial Array Self Refresh). The Mobile DDR can reduce the self refresh current(IDD6) by using these two modes.
Rev 0.1 / Feb. 2006 49
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
CS
A0 ~ A9
A11, A12
WE
CAS
RAS
/CLK
CLK
CKE High-Z
BA0, 1
CS
A0 ~ A9
A11, A12
WE
CAS
RAS
Don't Care
/CLK
CLK
CKE
BA0, 1
High-Low
Auto-Refresh Command Self-Refresh Command
Rev 0.1 / Feb. 2006 50
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
/CLK
CLK
Enter
Self Ref.
Mode
PRE NOP ARF NOP NOP NOP ARF NOP ACT
Pre
All
CKE
Command
Address
A10(AP)
DQ
Ba_A
Row_
n
Row_
n
High-Z
Exit
Self Ref.
Mode Command
(Au to R e f .
Recommand) Cont't Care
tRP tRFC tXSR tRFC
/CLK
CLK
PRE NOP ARF NOP ARF NOP NOP NOP ACT
Pre
All
Command
Address
A10(AP)
DQ
Ba_A
Row_
n
Row_
n
High-Z
tRP tRFC tRFC
NOP
Auto-Refresh Cycles Back-to-Back
Self-Refresh Entry and Exit
Rev 0.1 / Feb. 2006 51
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
MODE REGISTER SET
The mode registers are loaded via the address bits.
BA0 and BA1 are used to select between the Mode Register and the Extended Mode Register. See the Mode Register
description in the register definition section. The MODE REGISTER SET command can only be issued when all banks
are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met.
MODE REGISTER SET COMMAND
Note:
BA0=BA1=Low loads the Mode Register, whereas BA0=Low and BA1=High loads the Extended Mode Register.
Code = Mode Register / Extended Mode Register selection
(BA0, BA1) and op-code (A0 - An)
tMRD DEFINITION
MRS NOP Valid
Code Valid
tMRD
/
CLK
CLK
Command
Address
Don't Care
CS
A0 ~ A9
A11, A12
WE
CAS
RAS
Don't Care
/CL
K
CLK
CKE
BA0, 1
Code
Code
High-Z
Rev 0.1 / Feb. 2006 52
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
POWER DOWN
Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in
progress. If power down occurs when all banks are idle, it is Precharge Power Down.
If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot
stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is
exited by setting CKE high while issuing a Device Deselect or NOP command.
A valid command can be issued after tXP. For Clock stop during power down mode, please refer to the Clock Stop sub-
section in Operation section of this datasheet. (Page 53)
POWER-DOWN COMMAND
NOTE:
This case shows CKE low coincident with NO OPERATION.
Alternately POWER DOWN entry can be achieved with CKE low coincident with Device DESELECT.
CS
A0 ~ A9
A11, A12
(An)
WE
CAS
RAS
Don't Care
/CL
K
CLK
CKE
BA0, 1
CKE_Low
Rev 0.1 / Feb. 2006 53
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
DEEP POWER-DOWN
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the
LPDDR are stopped and all memory data is lost in this mode.
All the information in the Mode Register and the Extended Mode Register is lost. Next Figure,
DEEP POWER-DOWN
COMMAND
shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus
prior to entering the DPD mode. While in this state, CKE must be held in a constant low state.
To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least
200 us. After 200 us a complete re-initialization routing is required following steps 4 through 11 as defined for the ini-
tialization sequence. (Page 60, 61)
DEEP POWER-DOWN COMMAND
CS
A0 ~ A9
A11, A12
WE
CAS
RAS
Don't Care
/CLK
CLK
CKE
BA0, 1
CKE_Low
Rev 0.1 / Feb. 2006 54
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Mobile DDR SDRAM Deep Power-Down Entry and Exit
Before entering deep power down the DRAM must be in an all banks idle state with no activity on the data bus. Upon
entering deep power down all data will be lost. While in deep power down CKE must be held in a constant low state.
Upon exiting deep power down NOP command must be maintained for 200us. After 200us a complete initialization
routine is required following steps 4 through 11 as defined for the initialization sequence.
Steps follow (See Page46, 47)
Figure 5. Mobile DDR SDRAM Deep Power-Down Entry and Exit
Note
1. Clock must be stable before exiting deep power down mode. That is, the clock must be cycling within specifications by Ta0.
2. Device must be in the all banks idle state prior to entering Deep Power Down mode.
3. 200us is required before any command can be applied upon exiting DPD.
4. DPD = Deep Power Down command.
5. Upon exiting Deep Power Down a precharge all command must be issued followed by two auto refresh commands and a load
mode register sequence.
DON'T CARE
NOP DPD
4
NOP VALID
5
VALID
T
0
T
1
Ta0
1
Ta
1
Tb
1
tCK
tIH
tIS
tCH tCL
tIS tIH
tIS tIH tIS
tRP
2
Deep Power Down Mode Exit Deep Power Down Mode
T=200us
3
CK
CK
CKE
COM
ADD
DQS
DQ
DM
tIS
Rev 0.1 / Feb. 2006 55
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
FUNCTION OF Mobile DDR SDRAM
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Power must be applied to VDD and
VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial pause of 200 usec
is required. And a precharge all command will be issued to the Mobile DDR. Then, 8 or more Auto refresh cycles will
be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to pro-
gram the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will
be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Mobile SDRAM is
ready for normal opeartion. To ensure device functionality, there is a predefined sequence that must occur at device
power up or if there is any interruption of device power. Steps follow (See Page60, 61)
Figure 1. Initialization Waveform Sequence
VDD
VDDQ
/CLK
CLK
CKE
CMD
DM
ADDR
A10
BA0,
BA1
DQ,
DQS
T=200usec tRP tMRD
tRFC tMRD
VDD/VDDQ
Powered up
CLOCK stable Auto
Refresh
NOP ARFPRE MRSARF ACTMRS
CODE RACODE
CODE RA
CODE
BA0=L
BA1=L BA
BA0=L
BA1=H
tRFC
Load
Mode
Register
tCH tCL
tCK
ALL
BANKS
tIS tIH
tIS tIH
tIS tIH
tIS tIH
DON'T CARE
High-Z
Precharge
All Auto
Refresh
Load
Extended
Mode
Register
Rev 0.1 / Feb. 2006 56
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
CAS LATENCY DEFINITION
CAS latency definition of Mobile DDR SDRAM must be must be loaded when all banks are idle, and the controller must
wait the specified time before initiating the subsequent operation.
CAS latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ
command was registered (See Figure 2)
Figure 2. CAS LATENCY DEFINITION
NOTE
1. DQ transitioning after DQS transition define tDQSQ window.
2. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
3. tAC is the DQ output window relative to CK, and is the long term component of DQ skew.
Read NOP NOP NOP NOP
T
0
T
1
T
3
T
4
T
5
T
2
T
2n
T
3n
T
4n
T
5n
T
16
NOP NOP
T
2
T
2n
T
3
T
3n
T
4
T
4n
T
5
T
5n
All DQ values,
collectively
2
CL = 3
tLZ
min
tRPRE
tAC
min
tLZ
min
tDQSCK
min
tDQSCK
min
tRPST
DQS,
or LDQS/UDQS
1
CMD
CK
CK
Rev 0.1 / Feb. 2006 57
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Clock Stop Mode
Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption
during idle periods of the device.
Conditions: the Mobile DDR SDRAM supports clock stop in case:
● The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of required clock pulses per access
command depends on the device's AC timing parameters and the clock frequency;
● The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met;
● CKE is held HIGH.
When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be
entered with CK held LOW and CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command
have to be issued for at least one clock cycle before the next access command may be applied. Additional clock pulses
might be required depending on the system characteristics.
Figure1 illustrates the clock stop mode:
● Initially the device is in clock stop mode;
● The clock is restarted with the rising edge of T0 and a NOP on the command inputs;
● With T
1
a valid access command is latched; this command is followed by NOP commands in order to allow for clock
stop as soon as this access command has completed;
● T
n
is the last clock pulse required by the access command latched with T
1.
● The timing condition of this access command is met with the completion of T
n
; therefore Tn is the last clock pulse
required by this command and the clock is then stopped.
Figure 3. Clock Stop Mode
CK
ADD
CMD NOP NOP NOPNOP
Valide
Clock
Stopped
Exit Clock
Stop Mode
Valid
Command
Enter Clock
Stop Mode Don't Care
(High-Z)
CK
CM
D
T
0
T
1
T
2
T
n
CKE
DQ,
DQS
Timing Condition
Rev 0.1 / Feb. 2006 58
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Mode Register
The mode register contains the specific mode of operation of the Mobile DDR SDRAM. This register includes the selec-
tion of a burst length( 2, 4, 8, 16), a cas latency(2, 3 or 4), a burst type. The mode register set must be done before
any activate command after the power up sequence. Any contents of the mode register be altered by re-programming
the mode register through the execution of mode register set command.
Figure 4. Mode Register Set
BURST LENGTH
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as
shown in Page10. The burst length determines the maximum number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4, 8 or 16 locations are available for both the sequential and the
interleaved burst types.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved.
CAS LATENCY
The CAS latency is the delay between the registration of a READ command and the availability of the first piece of out-
put data. The latency should be set to 3 clocks. If a READ command is registered at a clock edge
n
and the latency is
3 clocks, the first data element will be valid at
n
+ 2tCK + tAC. If a READ command is registered at a clock edge
n
and
the latency is 2 clocks, the first data element will be valid at
n
+ tCK + tAC.
Data mask1,2)
Mobile DDR SDRAM uses a DQ write mask enable signal (DM) which masks write data.
Data masking is only available in the write cycle for Mobile DDR SDRAM. Data masking is available during write, but
data masking during read is not available.
DM command masks burst write data with reference to data strobe signal and it is not related with read data. DM com-
mand can be initiated at both the rising edge and the falling edge of the DQS. DM latency for write operation is zero.
For x16 data I/O, DDR SDRAM is equipped with LDM and UDM which control lower byte (DQ0~DQ7) and upper byte
(DQ8~DQ15) respectively.
Note 1) : Mobile SDR can mask both read and write data, but the read mask is not supported by Mobile DDR.
2) : Differences in Functions and Specifications (next table)
Item Mobile DDR Mobile SDR
Data mask Write mask only Write mask/Read mask
CLK
CLK
Precharge
All Bank
Mode
Register
Set
CMD
tCK
Command
(any)
0 1 234 56 78 910
tRP 2 CLK
min
Rev 0.1 / Feb. 2006 59
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Data Masking (Wite cycle : BL=4)
WRIT WRIT
DM
CMD
CK
CK
D0 D1
MK
D3 D0 D1 D3
MK
Hi-
Z
DQS
DQ
Data
Masking
Data
Masking
tDQSS
tDQSL
tDS tDH
tDQSH
Hi-
Z
Rev 0.1 / Feb. 2006 60
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Extended Mode Register
The Extended Mode Register contains the specific features of self refresh opeartion of the Mobile DDR SDRAM.
The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=1 and BA0=0) and
will retain the stored information until it is reprogrammed, the device is put in Deep Power-Down mode, or the device
loses power. The Extended Mode Register should be loaded when all Banks are idle and no bursts are in progress, and
subsequent operation should only be initiated after tMRD. Violating these requirements will result in unspecified opera-
tion.
The Extended Mode Register is written by asserting low on CS, RAS, CAS, WE and high on BA0. The state of address
pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode regis-
ter. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the con-
troller must wait the specified time before initiating any subsequent operation. Violating either of these requirements
will result in unspecified operation.
This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended
mode register set must be done before any activate command after the power up sequence. Any contents of the mode
register be altered by re-programming the mode register through the execution of extended mode register set com-
mand.
PARTIAL ARRAY SELF-REFRESH (PASR)
With PASR, the self refresh may be restricted to a variable portion of the total array. The whole array (default), 1/2
array, or 1/4 array could be selected.
DRIVE STRENGTH (DS)
The drive strength could be set to full or half via address bits A5 and A6. The half drive strength is intended for lighter
loads or point-to-point environments.
Rev 0.1 / Feb. 2006 61
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Mobile DDR SDRAM Deep Power-Down Entry and Exit
Before entering deep power down the DRAM must be in an all banks idle state with no activity on the data bus. Upon
entering deep power down all data will be lost. While in deep power down CKE must be held in a constant low state.
Upon exiting deep power down NOP command must be maintained for 200us. After 200us a complete initialization
routine is required following steps 4 through 11 as defined for the initialization sequence.
Steps follow (See Page102, 103)
Figure 5. Mobile DDR SDRAM Deep Power-Down Entry and Exit
Note
1. Clock must be stable before exiting deep power down mode. That is, the clock must be cycling within specifications by Ta0.
2. Device must be in the all banks idle state prior to entering Deep Power Down mode.
3. 200us is required before any command can be applied upon exiting DPD.
4. DPD = Deep Power Down command.
5. Upon exiting Deep Power Down a precharge all command must be issued followed by two auto refresh commands and a load
mode register sequence.
DON'T CARE
NOP DPD
4
NOP VALID
5
VALID
T
0
T
1
Ta0
1
Ta
1
Tb
1
tCK
tIH
tIS
tCH tCL
tIS tIH
tIS tIH tIS
tRP
2
Deep Power Down Mode Exit Deep Power Down Mode
T=200us
3
CK
CK
CKE
COM
ADD
DQS
DQ
DM
tIS
Rev 0.1 / Feb. 2006 62
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Mobile DDR SDRAM Initialization and Entry and Exit Deep Power Down
Initializing the Mobile DDR SDRAM
To ensure device functionality, there is a predefined sequence that must occur at device power up or if there is any
interruption of device power.
- Steps follow:
●Step1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up
simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ
are from the same power source. Also assert and hold CLOCK ENABLE (CKE) to a LVCMOS logic high level.
●Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply
stable clock.
●Step 3: There must be at least 200us of valid clocks before any command may be given to the DRAM.
During this time NOP or DESELECT commands must be issued on the command bus.
●Step 4: Issue a PRECHARGE ALL command.
●Step 5: Provide NOPs or DESELECT commands for at least tRP time.
●Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.
Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.
Note as part of the initialization sequence there must be two auto refresh commands issued.
The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.
●Step 7: Using the LMR command, load the base mode register. Set the desired operating modes.
●Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
●Step 9: Using the LMR command, program the extended mode register for the desired operating modes.
Note the order of the base and extended mode register programming is not important.
●Step 10: Provide NOP or DESELCT commands for at least tMRD time.
●Step 11: The DRAM has been properly initialized and is ready for any valid command.
Rev 0.1 / Feb. 2006 63
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
Figure 6.The Steps of Initializing (Mobile DDR SDRAM)
1
2
3
4
5
6
VDD and VDDQ Ramp,
CKE must be LVCMOS High
Apply Stable CLOCKs
Assert NOP or Deselect for t
RP
time
Configure Base Mode Register
Asser NOP or Deselect for t
MRD
time
Configure Extended Mode Reg ister
Assert NOP or Deselect for t
MRD
time
Issue two AUTO Refresh command
each followed by NOP or Deselect
commend for t
RFC
7
8
9
10
11
Wate at lest 200us with NOP
or Deselect on Command Bus
Precharge All
DRAM is ready for any valid
command
Rev 0.1 / Feb. 2006 64
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
PACKAGE INFORMATION
60 Ball 0.8mm pitch FBGA
Unit
[mm]
0.80
BOTTOM
VIEW
0.340 +/-
0.05
0.80 Typ.
0.40
0.80
Typ.
1.00 max
3.20
1.60
0.450 +/-
0.05
A1 INDEX MARK
1.375
10.00
Typ.
1.40
8.00Typ.