9DB633
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
Six Output Differential Buffer for PCIe Gen3
1
DATASHEET
Recommended Application:
6 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB633 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB633 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB633 suitable for Express Card
applications.
Key Specifications:
•Cycle-to-cycle jitter < 50 ps
•Output-to-output skew < 50 ps
•PCIe Gen3 phase jitter < 1.0ps RMS
Features/Benefits:
•OE# pins/Suitable for Express Card applications
•PLL or bypass mode/PLL can dejitter incoming clock
•Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
•Spread Spectrum Compatible/tracks spreading input
clock for low EMI
•SMBus Interface/unused outputs can be disabled
Output Features:
•6 - 0.7V current mode differential HCSL output pairs
Block Diagram
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
SMBDAT
SMBCLK
SRC_IN
SRC_IN#
PLL_BW
IREF
DIF1
DIF4
OE4#
OE1#
DIF(0,2,3,5)
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
2
Datasheet
Power Distribution Table
Pin Configuration
VDD GND
7, 13, 16, 22 8,21 Differential Outputs
13 8 SMBus
N/A 27 IREF
28 27 Analog VDD & GND for PLL core
Description
Pin Number
PLL_BW 1 28 VDDA
SRC_IN 2 27 GNDA
SRC_IN# 3 26 IREF
vOE1# 4 25 vOE4#
DIF_0 5 24 DIF_5
DIF_0# 6 23 DIF_5#
VDD 7 22 VDD
GND 8 21 GND
DIF_1 9 20 DIF_4
DIF_1# 10 19 DIF_4#
DIF_2 11 18 DIF_3
DIF_2# 12 17 DIF_3#
VDD 13 16 VDD
SMBDAT
14
15
SMBCLK
9DB633
120K ohm pull down resistors
Note:Pins preceeded by ' v ' have internal
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
3
Datasheet
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 PLL_BW IN 3.3V input for selecting PLL Band Width
0 = low, 1= high
2
IN
0.7 V Differential SRC TRUE input
3 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY input
4 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5
DIF_0
OUT
0.7V differential true clock output
6
DIF_0#
OUT
0.7V differential Complementary clock output
7
VDD
PWR
Power supply, nominal 3.3V
8 GND IN Ground pin.
9 DIF_1 OUT 0.7V differential true clock output
10 DIF_1# OUT 0.7V differential Complementary clock output
11
DIF_2
OUT
0.7V differential true clock output
12
DIF_2#
OUT
0.7V differential Complementary clock output
13
VDD
PWR
Power supply, nominal 3.3V
14 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
15 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
16 VDD PWR Power supply, nominal 3.3V
17
DIF_3#
OUT
0.7V differential Complementary clock output
18
DIF_3
OUT
0.7V differential true clock output
19
DIF_4#
OUT
0.7V differential Complementary clock output
20 DIF_4 OUT 0.7V differential true clock output
21 GND PWR Ground pin.
22 VDD PWR Power supply, nominal 3.3V
23 DIF_5# OUT 0.7V differential Complementary clock output
24
DIF_5
OUT
0.7V differential true clock output
25 vOE4# IN Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26 IREF OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
27
GNDA
PWR
Ground pin for the PLL core.
28 VDDA PWR 3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
4
Datasheet
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150 °
C1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 70 °C 1
T
IND
Industrial range -40 85 °C 1
Input High Voltage VIH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs 2 VDD + 0.3 V 1
Input Low Voltage VIL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs GND - 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ibyp
V
DD
= 3.3 V, Bypass mode 10 110 MHz 2
F
ipll
V
DD
= 3.3 V, 100MHz PLL mode 33 100.00 110 MHz 2
Pin Inductance L
pin
7 nH 1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
COUT Output pin capacitance 6 pF 1
Clk Stabilization TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock 1.8 ms 1,2
Input SS Modulation
Frequency fMODIN
Allowable Frequency
(Triangular Modulation) 30 33 kHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion 1 3 cycles 1,3
Tdrive_PD# tDRVPD
DIF output enable after
PD# de-assertion 300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V 1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4 mA 1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1,5
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
5
The differential input clock must be running for the SMBus to be active
Ambient Operating
Temperature
Input Current
3
Time from deassertion until outputs are >200 mV
4DIF_IN input
Capacitance
Input Frequency
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
5
Datasheet
Electrical Characteristics - Clock Input Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN VIHDIF
Differential inputs
(single-ended measurement)
600 800 1150 mV 1
Input Low Voltage - DIF_IN VILDIF
Differential inputs
(single-ended measurement)
VSS - 300 0 300 mV 1
Input Common Mode
Voltage - DIF_IN
VCOM Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
T
A
= T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate
Trf
Scope averaging on
0.6
2.5
4
V/ns
1, 2, 3
Slew rate matching
∆
Trf
Slew rate matching, Scope averaging on
9.5
20
%
1, 2, 4
Voltage High VHigh 660 740 850 1
Voltage Low VLow -150 8 150 1
Max Voltage
Vmax
760
1150
1
Min Voltage
Vmin
-300
-3
1
Vswing
Vswing
Scope averaging off
300
1506
mV
1, 2
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
378
550
mV
1, 5
Crossing Voltage (var)
∆
-Vcross Scope averaging off 54 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averaging
on)
Measurement on single ended signal using absolute
value. (Scope averaging off) mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
=
6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω (100Ω differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
Electrical Characteristics - Current Consumption
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current IDD3.3OP All outputs active @100MHz, CL = Full load; 134 150 mA 1
I
DD3.3PD
All diff pairs driven N/A mA 1
I
DD3.3PDZ
All differential pairs tri-stated
N/A
mA
1
1Guaranteed by design and characterization, not 100% tested in production.
Powerdown Current
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
6
Datasheet
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in High BW Mode 2 2.3 4 MHz 1
-3dB point in Low BW Mode 0.4 0.5 1 MHz 1
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 1 2 dB 1
Duty Cycle t
DC
Measured differentially, PLL Mode 45 48 55 % 1
Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz -2 1 2 % 1,4
t
pdBYP
Bypass Mode, V
T
= 50% 2500 3660 4500 ps 1
t
pdPLL
Hi BW PLL Mode V
T
= 50% -250 0 250 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 15 50 ps 1
PLL mode 40 50 ps 1,3
Additive Jitter in Bypass Mode 10 50 ps 1,3
1Guaranteed by design and characterization, not 100% tested in production.
2 I
REF
= V
DD
/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω.
3 Measured from differential waveform
4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
Skew, Input to Output
Jitter, Cycle to cycle tjcyc-cyc
PLL Bandwidth BW
Electrical Characteristics - PCIe Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jphPCIeG1
PCIe Gen 1 32 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz 1.1 3 ps
(rms) 1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 2.3 3.1 ps
(rms) 1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz) 0.5 1ps
(rms) 1,2,4
tjphPCIeG1 PCIe Gen 1 2 5 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz 0.2 0.3 ps
(rms) 1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 0.8 1ps
(rms) 1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz) 0.1 0.2 ps
(rms) 1,2,4
1 Applies to all outputs.
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
tjphPCIeG2
2
See http://www.pcisig.com for complete specs
tjphPCIeG2
Phase Jitter, PLL Mode
Additive Phase Jitter,
Bypass Mode
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
7
Datasheet
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
SRC Reference Clock
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
8
Datasheet
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cable Connected AC Coupled Application (figure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
9
Datasheet
General SMBus serial interface information for the 9DB633
How to Write:
•Controller (host) sends a start bit.
•Controller (host) sends the write address D4 (H)
•ICS clock will acknowledge
•Controller (host) sends the begining byte location = N
•ICS clock will acknowledge
•Controller (host) sends the data byte count = X
•ICS clock will acknowledge
•Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
•ICS clock will acknowledge each byte one at a time
•Controller (host) sends a Stop bit
How to Read:
•Controller (host) will send start bit.
•Controller (host) sends the write address D4 (H)
•ICS clock will acknowledge
•Controller (host) sends the begining byte
location = N
•ICS clock will acknowledge
•Controller (host) will send a separate start bit.
•Controller (host) sends the read address D5 (H)
•ICS clock will acknowledge
•ICS clock will send the data byte count = X
•ICS clock sends Byte N + X -1
•ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
•Controller (host) will need to acknowledge each byte
•Controllor (host) will send a not acknowledge bit
•Controller (host) will send a stop bit
ICS (Sla ve/Receiver)
T
W R
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address D4(H )
Beginning Byte = N
W Rite
starT bit
Controller (Host)
T starT bit
W R W Rite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
P stoP bit
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address D3(H )
Index Block Read Operation
Slave Address D4(H )
Beginning Byte = N
ACK
ACK
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
10
Datasheet
SMBusTable: Device Control Register, READ/WRITE ADDRESS (D4/D5)
Pin # Name Control Function Type 0 1 Default
Bit 7 SW_EN Enables SMBus
Control of bits (1:0) RW
PLL controlled
by SMBus
registers
PLL controlled
by device pins 1
Bit 6 RW X
Bit 5 RW X
Bit 4 RW X
Bit 3 RW X
Bit 2 RW X
Bit 1 PLL BW #adjust Selects PLL
Bandwidth RW Low BW High BW 1
Bit 0 PLL Enable Bypasses PLL for
board test
RW PLL bypassed
(fan out mode)
PLL enabled
(ZDB mode)
1
SMBusTable: Output Enable Register
Pin # Name Control Function Type 0 1 Default
Bit 7 RW X
Bit 6 RW X
Bit 5 PCIEX5 Output Control RW Disable Enable 1
Bit 4 RW X
Bit 3 PCIEX3 Output Control RW Disable Enable 1
Bit 2 PCIEX2 Output Control RW Disable Enable 1
Bit 1 RW X
Bit 0 PCIEX0 Output Control RW Disable Enable 1
SMBusTable: Function Select Register
Pin # Name Control Function Type 0 1 Default
Bit 7
RW
X
Bit 6
RW
X
Bit 5
RW
X
Bit 4
RW
X
Bit 3
RW
X
Bit 2
RW
X
Bit 1
RW
X
Bit 0 RW X
SMBusTable: Vendor & Revision ID Register
Pin # Name Control Function Type 0 1 Default
Bit 7
RID3 R - - 0
Bit 6 RID2 R - - 0
Bit 5 RID1 R - - 0
Bit 4 RID0 R - - 1
Bit 3 VID3 R - - 0
Bit 2 VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0 VID0 R - - 1
-
RESERVED -
RESERVED -
RESERVED -
VENDOR ID
-
-
-
-
-
-
-
-
-
-
-
-
-
- -
Byte 3
RESERVED
-
18,17
11,12
-
5,6
Byte 2
-
-
RESERVED -
-
-
Byte 1
-
-
24,23
- RESERVED -
- RESERVED -
-
RESERVED -
RESERVED -
RESERVED
REVISION ID
-
RESERVED
Byte 0
-
- RESERVED
-
RESERVED
RESERVED -
RESERVED -
-
RESERVED -
RESERVED
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
11
Datasheet
SMBusTable: DEVICE ID
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
R 0
Bit 6
R 0
Bit 5
R 0
Bit 4
R 0
Bit 3
R 0
Bit 2
R 1
Bit 1
R 1
Bit 0 R 0
SMBusTable: Byte Count Register
Pin # Name Control
Function
Type 0 1 Default
Bit 7
BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5
BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3
BC3 RW - - 0
Bit 2
BC2 RW - - 1
Bit 1
BC1 RW - - 1
Bit 0 BC0 RW - - 0
Device ID
= 06 Hex
-
-
-
-
-
Byte 4
-
-
-
Byte 5
-
Writing to this
register will
configure how
many bytes will be
read back, default
is 06 = 6 bytes.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
12
Datasheet
28-pin SSOP Package Drawing and Dimensions
209 mil SSOP
MIN MAX MIN MAX
A -- 2.00 -- .079
A1 0.05 -- .002 --
A2 1.65 1.85 .065 .073
b 0.22 0.38 .009 .015
c 0.09 0.25 .0035 .010
D
E 7.40 8.20 .291 .323
E1 5.00 5.60 .197 .220
e
L 0.55 0.95 .022 .037
N
α0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
28 9.90 10.50 .390 .413
10-0033
Reference Doc.: JEDEC Publication 95, MO-150
0.0256 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
209 mil SSOP
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
SYMBOL
SEE VARIATIONS SEE VARIATIONS
0.65 BASIC
IDT® Six Output Differential Buffer for PCIe Gen3 1668C—04/20/11
9DB633
Six Output Differential Buffer for PCIe Gen3
13
Datasheet
28-pin TSSOP Package Drawing and Dimensions
INDEX
AREA
12
N
D
E1 E
a
SEATING
PLANE
A1
A
A2
e
-C-
b
c
L
aaa C
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.19 0.30 .007 .012
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
28 9.60 9.80 .378 .386
10-0035
SEE VARIATIONS SEE VARIATIONS
0.65 BASIC
Reference Doc.: JEDEC Publication 95, MO-153
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
4.40 mm. Body, 0.65 mm. Pitch TSSOP
6.40 BASIC 0.252 BASIC
0.0256 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
(173 mil) (25.6 mil)
SYMBOL
Ordering Information
Part / Order Number Shipping Packaging Package Temperature
9DB633AFLF Tubes 28-pin SSOP 0 to +70°C
9DB633AFLFT Tape and Reel 28-pin SSOP 0 to +70°C
9DB633AFILF Tubes 28-pin SSOP -40 to +85°C
9DB633AFLIFT Tape and Reel 28-pin SSOP -40 to +85°C
9DB633AGLF Tubes 28-pin TSSOP 0 to +70°C
9DB633AGLFT Tape and Reel 28-pin TSSOP 0 to +70°C
9DB633AGILF Tubes 28-pin TSSOP -40 to +85°C
9DB633AGILFT Tape and Reel 28-pin TSSOP -40 to +85°C
"LF" after the package code are the Pb-Free configuration and are RoHS compliant.
"A" is the device revision designator (will not correlate to the datasheet revision).
9DB633
Six Output Differential Buffer for PCIe Gen3
14
Datasheet
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© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
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Printed in USA
Revision History
Rev.
Originator
Issue Date
Description
Page #
A RDW 6/30/2010 Released to final
B RDW 7/12/2010 Changed "PWD" to "Default" in SMBus Register descriptions 10,11
C RDW 4/20/2011 Changed pull down indicator from '**' to 'v'.