LTC3862
1
3862fc
For more information www.linear.com/LTC3862
Typical applicaTion
FeaTures
applicaTions
DescripTion
Multi-Phase Current Mode
Step-Up DC/DC Controller
The LT C
®
3862 is a two phase constant frequency, current
mode boost and SEPIC controller that drives N-channel
power MOSFETs. Two phase operation reduces system
filtering capacitance and inductance requirements.
The operating frequency can be set with an external resistor
over a 75kHz to 500kHz range and can be synchronized
to an external clock using the internal PLL. Multi-phase
operation is possible using the SYNC input, the CLKOUT
output and the PHASEMODE control pin allowing 2-, 3-,
4-, 6- or 12-phase operation.
Other features include an internal 5V LDO with undervoltage
lockout protection for the gate drivers, a precision RUN
pin threshold with programmable hysteresis, soft-start
and programmable leading edge blanking and maximum
duty cycle.
n Wide VIN Range: 4V to 36V Operation
n 2-Phase Operation Reduces Input and Output
Capacitance
n Fixed Frequency, Peak Current Mode Control
n 5V Gate Drive for Logic-Level MOSFETs
n Adjustable Slope Compensation Gain
n Adjustable Max Duty Cycle (Up to 96%)
n Adjustable Leading Edge Blanking
n ±1% Internal Voltage Reference
n Programmable Operating Frequency with One
External Resistor (75kHz to 500kHz)
n Phase-Lockable Fixed Frequency 50kHz to 650kHz
n SYNC Input and CLKOUT for 2-, 3-, 4-, 6- or
12-Phase Operation (PHASEMODE Programmable)
n Internal 5V LDO Regulator
n 24-Lead Narrow SSOP Package
n 5mm × 5mm QFN with 0.65mm Lead Pitch and
24-Lead Thermally Enhanced TSSOP Packages
n Automotive, Telecom and Industrial Power Supplies
VIN
LTC3862
SGND
GATE1
SENSE1+
RUN
84.5k
24.9k
66.5k
10nF 10k
475k 12.4k 68.1k 100pF
0.006Ω
0.006Ω
19.4µH 19.4µH
22µF
50V
220µF
50V
10nF
1nF
10nF
4.7µF
INTVCC
SS
3V8
ITH
FB
VOUT
48V
5A (MAX)
3862 TA01
V
IN
5V TO 36V
BLANK
FREQ
SYNC
PLLFLTR
SENSE1–
GATE2
SENSE2+
SENSE2–
PGND
CLKOUT
SLOPE
DMAX
PHASEMODE
Efficiency vs Output Current
LOAD CURRENT (mA)
100
80
EFFICIENCY (%)
82
84
86
90
94
1000 10000
3862 TA01b
98
88
92
96
VOUT = 48V
VIN = 24V
VIN = 12V
VIN = 5V
PART NUMBER INTVCC VIN ON VIN OFF
LTC3862 5V 3.3V 2.9V
LTC3862-1 10V 7.5V 7.0V
LTC3862-2 10V 4.4V 3.9V
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6144194, 6498466, 6611131.
LTC3862
2
3862fc
For more information www.linear.com/LTC3862
absoluTe MaxiMuM raTings
Input Supply Voltage (VIN) ......................... –0.3V to 40V
INTVCC Voltage ............................................ –0.3V to 6V
INTVCC LDO RMS Output Current .........................50mA
RUN Voltage ................................................ –0.3V to 8V
SYNC Voltage ............................................... –0.3V to 6V
SLOPE, PHASEMODE, DMAX,
BLANK Voltage .......................................... –0.3V to V3V8
SENSE1+, SENSE1–, SENSE2+,
SENSE2– Voltage ...................................... –0.3V to V3V8
SS, PLLFLTR Voltage ................................ –0.3V to V3V8
(Notes 1, 2)
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
FE PACKAGE
24-LEAD PLASTIC TSSOP
24
23
22
21
20
19
18
17
16
15
14
13
DMAX
SLOPE
BLANK
PHASEMODE
FREQ
SS
ITH
FB
SGND
CLKOUT
SYNC
PLLFLTR
3V8
SENSE1+
SENSE1–
RUN
VIN
INTVCC
GATE1
PGND
GATE2
NC
SENSE2–
SENSE2+
25
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
DMAX
SLOPE
BLANK
PHASEMODE
FREQ
SS
ITH
FB
SGND
CLKOUT
SYNC
PLLFLTR
3V8
SENSE1+
SENSE1–
RUN
VIN
INTVCC
GATE1
PGND
GATE2
NC
SENSE2–
SENSE2+
TJMAX = 150°C, θJA = 85°C/W
24 23 22 21 20 19
789
TOP VIEW
25
UH PACKAGE
24-LEAD (5mm × 5mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18BLANK
PHASEMODE
FREQ
SS
ITH
FB
VIN
INTVCC
GATE1
PGND
GATE2
NC
SLOPE
DMAX
3V8
SENSE1+
SENSE1–
RUN
SGND
CLKOUT
SYNC
PLLFLTR
SENSE2+
SENSE2–
TJMAX = 150°C, θJA = 44°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
pin conFiguraTion
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3862EFE#PBF LTC3862EFE#TRPBF 3862FE 24-Lead Plastic TSSOP –40°C to 85°C
LTC3862IFE#PBF LTC3862IFE#TRPBF 3862FE 24-Lead Plastic TSSOP –40°C to 125°C
LTC3862HFE#PBF LTC3862HFE#TRPBF 3862FE 24-Lead Plastic TSSOP –40°C to 150°C
LTC3862EGN#PBF LTC3862EGN#TRPBF LTC3862GN 24-Lead Plastic SSOP –40°C to 85°C
LTC3862IGN#PBF LTC3862IGN#TRPBF LTC3862GN 24-Lead Plastic SSOP –40°C to 125°C
LTC3862HGN#PBF LTC3862HGN#TRPBF LTC3862GN 24-Lead Plastic SSOP –40°C to 150°C
LTC3862EUH#PBF LTC3862EUH#TRPBF 3862 24-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC3862IUH#PBF LTC3862IUH#TRPBF 3862 24-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3862HUH#PBF LTC3862HUH#TRPBF 3862 24-Lead (5mm × 5mm) Plastic QFN –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ITH Voltage ............................................... –0.3V to 2.7V
FB Voltage ................................................. –0.3V to V3V8
FREQ Voltage ............................................ –0.3V to 1.5V
Operating Junction Temperature Range (Notes 3, 4)
LTC3862E ............................................. –40°C to 85°C
LTC3862I............................................ –40°C to 125°C
LTC3862H .......................................... –40°C to 150°C
Storage Temperature Range ................... –65°C to 150°C
Reflow Peak Body Temperature ........................... 260°C
LTC3862
3
3862fc
For more information www.linear.com/LTC3862
elecTrical characTerisTics
(Notes 2, 3) The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, RUN = 2V and SS = open, unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Input and INTVCC Linear Regulator
VIN VIN Supply Voltage Range 4 36 V
IVIN VIN Supply Current
Normal Mode, No Switching
Shutdown
(Note 5)
VRUN = 0V
l
l
1.8
30
3.0
80
mA
µA
INTVCC LDO Regulator Output Voltage 4.8 5.0 5.2 V
dVINTVCC(LINE) Line Regulation 6V < VIN < 36V 0.002 0.02 %/V
dVINTVCC(LOAD) Load Regulation Load = 0mA to 20mA –2 %
VUVLO INTVCC UV+ Voltage Rising INTVCC 3.3 V
INTVCC UV– Voltage Falling INTVCC 2.9 V
3V8 LDO Regulator Output Voltage 3.8 V
Switcher Control Loop
VFB Reference Voltage VITH = 0.8V (Note 6) E-Grade (Note 3)
I-Grade and H-Grade (Note 3)
l
l
1.210
1.199
1.223
1.223
1.235
1.248
V
V
dVFB/dVIN Feedback Voltage VIN Line Regulation VIN = 4V to 36V (Note 6) ±0.002 0.01 %/V
dVFB/dVITH Feedback Voltage Load Regulation VITH = 0.5V to 1.2V (Note 6) 0.01 0.1 %
gmTransconductance Amplifier Gain VITH = 0.8V (Note 6), ITH Pin Load = ±5µA 660 µMho
f0dB Error Amplifier Unity-Gain Crossover
Frequency
(Note 7) 1.8 MHz
VITH Error Amplifier Maximum Output Voltage
(Internally Clamped)
VFB = 1V, No Load 2.7 V
Error Amplifier Minimum Output Voltage VFB = 1.5V, No Load 50 mV
IITH Error Amplifier Output Source Current –30 µA
Error Amplifier Output Sink Current 30 µA
IFB Error Amplifier Input Bias Currents (Note 6) –50 –200 nA
VITH(PSKIP) Pulse Skip Mode Operation ITH Pin Voltage Rising ITH Voltage (Note 6)
Hysteresis
0.275
25
V
mV
ISENSE(ON) SENSE Pin Current 0.01 2 µA
VSENSE(MAX) Maximum Current Sense Input Threshold VSLOPE = Float, Low Duty Cycle
(Note 3)
l
65
60
75
75
85
90
mV
mV
VSENSE(MATCH) CH1 to CH2 Maximum Current Sense
Threshold Matching
VSLOPE = Float, Low Duty Cycle (Note 3)
(VSENSE1 – VSENSE2)
l–10 10 mV
RUN/Soft-Start
IRUN RUN Source Current VRUN = 0V
VRUN = 1.5V
–0.5
–5
µA
µA
VRUN High Level RUN Channel Enable Threshold 1.22 V
VRUNHYS RUN Threshold Hysteresis 80 mV
ISS SS Pull-Up Current VSS = 0V –5 µA
RSS SS Pull-Down Resistance VRUN = 0V 10 kΩ
Oscillator
fOSC Oscillator Frequency RFREQ = 45.6k
RFREQ = 45.6k
l
280
260
300
300
320
340
kHz
kHz
Oscillator Frequency Range l75 500 kHz
VFREQ Nominal FREQ Pin Voltage RFREQ = 45.6k 1.223 V
LTC3862
4
3862fc
For more information www.linear.com/LTC3862
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSYNC SYNC Minimum Input Frequency VSYNC = External Clock l50 kHz
SYNC Maximum Input Frequency VSYNC = External Clock l650 kHz
VSYNC SYNC Input Threshold Rising Threshold 1.5 V
IPLLFLTR Phase Detector Sourcing Output Current fSYNC > fOSC –15 µA
Phase Detector Sinking Output Current fSYNC < fOSC 15 µA
CH1-CH2 Channel 1 to Channel 2 Phase Relationship VPHASEMODE = 0V
VPHASEMODE = Float
VPHASEMODE = 3V8
180
180
120
Deg
Deg
Deg
CH1-CLKOUT Channel 1 to CLKOUT Phase Relationship VPHASEMODE = 0V
VPHASEMODE = Float
VPHASEMODE = 3V8
90
60
240
Deg
Deg
Deg
DMAX Maximum Duty Cycle VDMAX = 0V (Note 9)
VDMAX = Float
VDMAX = 3V8
96
84
75
%
%
%
tON(MIN)1 Minimum On-Time VBLANK = 0V (Note 8) 180 ns
tON(MIN)2 Minimum On-Time VBLANK = Float (Note 8) 260 ns
tON(MIN)3 Minimum On-Time VBLANK = 3V8 (Note 8) 340 ns
Gate Driver
RDS(ON) Driver Pull-Up RDS(ON) 2.1 Ω
Driver Pull-Down RDS(ON) 0.7 Ω
Overvoltage
VFB(OV) VFB, Overvoltage Lockout Threshold VFB(OV) – VFB(NOM) in Percent 8 10 12 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: The LTC3862E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3862I is guaranteed
over the full –40°C to 125°C operating junction temperature range and
the LTC3862H is guaranteed over the full –40°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes. Operating lifetime is derated at junction temperatures greater
than 125°C.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 5: Supply current in normal operation is dominated by the current
needed to charge the external MOSFET gates. This current will vary with
supply voltage and the external MOSFETs used.
Note 6: The IC is tested in a feedback loop that adjusts VFB to achieve a
specified error amplifier output voltage.
Note 7: Guaranteed by design, not subject to test.
Note 8: The minimum on-time condition is specified for an inductor peak-
to-peak ripple current = 30% (see Minimum On-Time Considerations in the
Applications Information section).
Note 9: The maximum duty cycle limit is derived from an internal
clock that runs at 12x the programmed switching frequency. See the
Applications Information for additional information.
elecTrical characTerisTics
(Notes 2, 3) The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, RUN = 2V and SS = open, unless
otherwise noted.
LTC3862
5
3862fc
For more information www.linear.com/LTC3862
Typical perForMance characTerisTics
Efficiency vs Output Current
Efficiency and Power Loss vs
Input Voltage
Load Step Inductor Current at Light Load
Quiescent Current vs Input
Voltage
LOAD CURRENT (mA)
10
70
EFFICIENCY (%)
75
80
85
90
100 1000 10000
3862 G01
65
60
55
50
95
100
VOUT = 48V
VIN = 35V
VIN = 24V
VIN = 12V
INPUT VOLTAGE (V)
0
90
EFFICIENCY (%)
POWER LOSS (mW)
91
92
93
94
95
96
1500
2000
2500
3000
3500
4000
10 20 30 40
3862 G02
EFFICIENCY
POWER LOSS
VOUT = 48V
IOUT = 1A
ILOAD
5A/DIV
1A TO 5A
IL1
5A/DIV
IL2
5A/DIV
VOUT
500mV/DIV
500µs/DIVVIN = 24V
VOUT = 48V
3862 G03
SW1
50V/DIV
SW2
50V/DIV
IL1
2A/DIV
IL2
2A/DIV
1µs/DIVVIN = 12V
VOUT = 48V
ILOAD = 100mA
3862 G04
INPUT VOLTAGE (V)
4
0
QUIESCENT CURRENT (mA)
0.50
1.00
1.50
2.00
3.00
812 16 20
3862 G05
24 28 32 36
2.50
0.25
0.75
1.25
1.75
2.75
2.25
Quiescent Current vs Temperature
Shutdown Quiescent Current vs
Input Voltage
Shutdown Quiescent Current vs
Temperature
TEMPERATURE (°C)
–50
QUIESCENT CURRENT (mA)
1.70
1.80
150
3862 G06
1.60
1.50 050 100
–25 25 75 125
1.90
1.65
1.75
1.55
1.85
INPUT VOLTAGE (V)
4
SHUTDOWN CURRENT (µA)
25
30
35
36
3862 G07
20
15
012 20 28
816 24 32
10
5
45
40
TEMPERATURE (°C)
–50
30
40
25 75 150
3862 G08
20
10
0
–25 0 50 100 125
VIN = 12V
LTC3862
6
3862fc
For more information www.linear.com/LTC3862
Typical perForMance characTerisTics
INTVCC Line Regulation INTVCC Load Regulation INTVCC vs Temperature
INTVCC LDO Dropout vs Load
Current, Temperature
INTVCC UVLO Threshold vs
Temperature Feedback Voltage vs Temperature
Feedback Voltage Line
Regulation
Current Sense Threshold vs
ITH Voltage
Current Sense Threshold vs
Temperature
INPUT VOLTAGE (V)
0
5.00
5.25
20
3962 G09
5 10 15 25
4.75
INTVCC VOLTAGE (V)
INTVCC LOAD CURRENT (mA)
0
INTVCC VOLTAGE (V)
4.90
4.95
40
3862 G10
4.85
4.80 10 20 30 50
5.00
TEMPERATURE (°C)
–50
4.90
INTV
CC
VOLTAGE (V)
4.91
4.93
4.94
4.95
5.00
4.97
050 75
3862 G11
4.92
4.98
4.99
4.96
–25 25 100 125 150
INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
600
800
1000
30 50
3862 G12
400
200
010 20 40
1200
1400
1600
150°C
85°C
25°C
–40°C
125°C
TEMPERATURE (°C)
–50
2.6
INTVCC VOLTAGE (V)
2.7
2.9
3.0
3.1
3.6
3.3
050 75
3862 G13
2.8
3.4
3.5
3.2
–25 25 100 125 150
TEMPERATURE (°C)
–50
1.211
FB VOLTAGE (V)
1.215
1.219
1.223
1.227
1.235
–25 0 25 50
3862 G14
75 100 125 150
1.231
1.213
1.217
1.221
1.225
1.233
1.229
INPUT VOLTAGE (V)
4
1.220
FB VOLTAGE (V)
1.221
1.222
1.223
1.224
12 20 28 36
3862 G15
1.225
1.226
8 16 24 32
ITH VOLTAGE (V)
CURRENT SENSE THRESHOLD (mV)
50
60
70
3862 G16
30
00 0.4 0.8 1.2 1.6 2.0 2.4
80
40
20
10
TEMPERATURE (°C)
–50
70
CURRENT SENSE THRESHOLD (mV)
71
73
74
75
80
77
050 75
3862 G17
72
78
79
76
–25 25 100 125 150
LTC3862
7
3862fc
For more information www.linear.com/LTC3862
Typical perForMance characTerisTics
Maximum Current Sense
Threshold vs Duty Cycle RUN Threshold vs Temperature RUN Threshold vs Input Voltage
RUN (Off) Source Current vs
Temperature
RUN Source Current vs
Input Voltage
DUTY CYCLE (%)
50
MAXIMUM CURRENT SENSE THRESHOLD (mV)
60
70
80
55
65
75
20 40 60 80
3862 G18
100100 30 50 70 90
SLOPE = 0.625
SLOPE = 1.66
SLOPE = 1
TEMPERATURE (°C)
–50
1.10
RUN PIN VOLTAGE (V)
1.15
1.20
1.25
1.30
–25 0 25 50
3862 G09
75
ON
OFF
100 125 150
INPUT VOLTAGE (V)
0
RUN PIN VOLTAGE (V)
1.3
1.4
1.5
15 25 40
3862 G20
1.2
1.1
1.0
5 10 20
ON
OFF
30 35
RUN (On) Source Current vs
Temperature
TEMPERATURE (°C)
–50
–1.0
RUN PIN CURRENT (µA)
–0.9
–0.7
–0.6
–0.5
0
–0.3
050 75
3862 G21vv
–0.8
–0.2
–0.1
–0.4
–25 25 100 125 150
TEMPERATURE (°C)
–50
RUN PIN CURRENT (µA)
–4
–2
150
1344 G06
–6
–8 050 100
–25 25 75 125
0
–5
–3
–7
–1
INPUT VOLTAGE (V)
4 8
RUN PIN CURRENT (µA)
–3
–2
–1
28
3862 G23
–4
–5
12 16 20 32
24 36
–6
–7
0
Soft-Start Current vs
Soft-Start Voltage
Oscillator Frequency vs
Temperature
Soft-Start Current vs Temperature
TEMPERATURE (°C)
–50
–5.6
SOFT-START CURRENT (µA)
–5.5
–5.4
–5.3
–5.2
0 50 100 150
3862 G24
–5.1
–5.0
–25 25 75 125
SOFT-START VOLTAGE (V)
0
–6
SOFT-START CURRENT (µA)
–5
–4
–3
–2
1 2 34
3862 G25
–1
0
0.5 1.5 2.5 3.5
TEMPERATURE (°C)
–50
FREQUENCY (kHz)
302
303
304
305
150
3862 G26
301
300
298 050 100
–25 25 75 125
299
307
306
LTC3862
8
3862fc
For more information www.linear.com/LTC3862
Typical perForMance characTerisTics
Oscillator Frequency vs
Input Voltage RFREQ vs Frequency Frequency vs PLLFLTR Voltage
Frequency Voltage vs
Temperature
Minimum On-Time vs
Input Voltage
Minimum On-Time vs
Temperature
Gate Turn-On Waveform Driving
Renesas HAT2266
Gate Turn-Off Waveform Driving
Renesas HAT2266
INPUT VOLTAGE (V)
0
FREQUENCY (kHz)
300
305
310
32
3862 G27
295
290
280 816 24
4 36
12 20 28
285
320
315
FREQUENCY (kHz)
100
R
FREQ
(kΩ)
300
1000
3862 G28
10
100
200 1000
900
800700600
500
400
0
PLLFLTR VOLTAGE (V)
0
1000
1200
2
3862 G29
800
600
0.5 1 1.5 2.5
400
200
0
TEMPERATURE (°C)
–50
FREQ VOLTAGE (V)
1.223
1.229
1.231
150
3862 G30
1.221
1.219
1.211 050 100
–25 25 75 125
1.215
1.235
1.233
1.227
1.225
1.217
1.213
TEMPERATURE (°C)
–50
100
MINIMUM ON-TIME (ns)
150
200
250
300
0 50 100 150
3862 G31
350
400
–25 25 75 125
BLANK = 3V8
BLANK = FLOAT
BLANK = SGND
INPUT VOLTAGE (V)
4
100
MINIMUM ON-TIME (ns)
150
200
250
300
12 20 28 36
3862 G32
350
400
8 16 24 32
BLANK = 3V8
BLANK = FLOAT
BLANK = SGND
GATE
1V/DIV
20ns/DIVVIN = 12V
VOUT = 48V
IOUT = 1A
MOSFET RENESAS HAT2266
3862 G33
GATE
1V/DIV
20ns/DIVVIN = 12V
VOUT = 48V
IOUT = 1A
MOSFET RENESAS HAT2266
3862 G34
LTC3862
9
3862fc
For more information www.linear.com/LTC3862
pin FuncTions
3V8 (Pin 24/Pin 22/Pin 24): Output of the Internal 3.8V
LDO from INTVCC. Supply pin for the low voltage analog
and digital circuits. A low ESR 1nF ceramic bypass capacitor
should be connected between 3V8 and SGND, as close
as possible to the IC.
BLANK (Pin 3/Pin 1/Pin 3): Blanking Time. Floating this
pin provides a nominal minimum on-time of 260ns. Con-
necting this pin to 3V8 provides a minimum on-time of
340ns, while connecting it to SGND provides a minimum
on-time of 180ns.
CLKOUT (Pin 10/Pin 8/Pin 10): Digital Output Used for
Daisy-Chaining Multiple LTC3862 ICs in Multi-Phase
Systems. The PHASEMODE pin voltage controls the
relationship between CH1 and CH2 as well as between
CH1 and CLKOUT.
DMAX (Pin 1/Pin 23/Pin 1): Maximum Duty Cycle. This pin
programs the maximum duty cycle. Floating this pin pro-
vides 84% duty cycle. Connecting this pin to 3V8 provides
75% duty cycle, while connecting it to SGND provides 96%
duty cycle. The maximum duty cycle is derived from an
internal clock that runs at 12x the programmed switching
frequency. As a result, the maximum duty cycle limit DMAX
is extremely precise.
FB (Pin 8/Pin 6/Pin 8): Error Amplifier Input. The FB pin
should be connected through a resistive divider network
to VOUT to set the output voltage.
FREQ (Pin 5/Pin 3/Pin 5): A resistor from FREQ to SGND
sets the operating frequency.
GATE1 (Pin 18/Pin 16/Pin 18): Gate Drive Output. The
LTC3862 provides a 5V gate drive referenced to PGND to
drive a logic-level threshold MOSFET. The gate pin is rated
for an absolute maximum voltage of –0.3V minimum and
6V maximum.
GATE2 (Pin 16/Pin 14/Pin 16): Gate Drive Output. The
LTC3862 provides a 5V gate drive referenced to PGND to
drive a logic-level threshold MOSFET. The gate pin is rated
for an absolute maximum voltage of –0.3V minimum and
6V maximum.
INTVCC (Pin 19/Pin 17/Pin 19): Output of the Internal 5V
Low Dropout Regulator (LDO). A low ESR 4.7µF (X5R or
better) ceramic bypass capacitor should be connected
between INTVCC and PGND, as close as possible to the IC.
ITH (Pin 7/Pin 5/Pin 7): Error Amplifier Output. The current
comparator trip threshold increases with the ITH control
voltage. The ITH pin is also used for compensating the
control loop of the converter.
PGND (Pin 17/Pin 15, Exposed Pad Pin 25/Pin 17,
Exposed Pad Pin 25): Power Ground. Connect this pin
close to the sources of the power MOSFETs. PGND should
also be connected to the negative terminals of VIN and
INTVCC bypass capacitors. PGND is electrically isolated
from the SGND pin. The Exposed Pad of the FE and QFN
packages is connected to PGND and must be soldered
to PCB ground for electrical contact and rated thermal
performance.
PHASEMODE (Pin 4/Pin 2/Pin 4): The PHASEMODE pin
voltage programs the phase relationship between CH1 and
CH2 rising gate signals, as well as the phase relationship
between CH1 gate signal and CLKOUT. Floating this pin or
connecting it to either 3V8, or SGND changes the phase
relationship between CH1, CH2 and CLKOUT.
PLLFLTR (Pin 12/Pin 10/Pin 12): PLL Lowpass Filter Input.
When synchronizing to an external clock, this pin serves as
the lowpass filter input for the PLL. A series resistor and
capacitor connected from PLLFLTR to SGND compensate
the PLL feedback loop.
RUN (Pin 21/Pin 19/Pin 21): Run Control Input. A voltage
above 1.22V on the pin turns on the IC. Forcing the pin
below 1.22V causes the IC to shut down. There is a 0.5µA
pull-up current for this pin. Once the RUN pin raises above
1.22V, an additional 4.5µA pull-up current is added to the
pin for programmable hysteresis.
SENSE1+ (Pin 23/Pin 21/Pin 23): Positive Inputs to the
Current Comparators. The ITH pin voltage programs the
current comparator offset in order to set the peak current
trip threshold. This pin is normally connected to a sense
resistor in the source of the power MOSFET.
(SSOP/QFN/TSSOP)
LTC3862
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pin FuncTions
SENSE2+ (Pin 13/Pin 11/Pin 13): Positive Inputs to the
Current Comparators. The ITH pin voltage programs the
current comparator offset in order to set the peak current
trip threshold. This pin is normally connected to a sense
resistor in the source of the power MOSFET.
SENSE1– (Pin 22/Pin 20/Pin 22): Negative Inputs to the
Current Comparators. This pin is normally connected to
the bottom of the sense resistor.
SENSE2– (Pin 14/Pin 12/Pin 14): Negative Inputs to the
Current Comparators. This pin is normally connected to
the bottom of the sense resistor.
SGND (Pin 9/Pin 7/Pin 9): Signal Ground. All feedback and
soft-start connections should return to SGND. For optimum
load regulation, the SGND pin should be kelvin connected
to the PCB location between the negative terminals of the
output capacitors.
SLOPE (Pin 2/Pin 24/Pin 2): This pin programs the gain
of the internal slope compensation. Floating this pin
provides a normalized slope compensation gain of 1.00.
Connecting this pin to 3V8 increases the normalized
slope compensation by 66%, and connecting it to SGND
decreases the normalized slope compensation by 37.5%.
See Applications Information for more details.
SS (Pin 6/Pin 4/Pin 6): Soft-Start Input. For soft-start
operation, connecting a capacitor from this pin to SGND
will clamp the output of the error amp. An internal 5µA
current source will charge the capacitor and set the rate
of increase of the peak switch current of the converter.
SYNC (Pin 11/Pin 9/Pin 11): PLL Synchronization Input.
Applying an external clock between 50kHz and 650kHz
will cause the operating frequency to synchronize to the
clock. SYNC is pulled down by a 50k internal resistor. The
rising edge of the SYNC input waveform will align with the
rising edge of GATE1 in closed-loop operation. A SYNC
signal with an amplitude greater than 1.6V is considered
an active high, while any signal below 0.9V is considered
an active low.
VIN (Pin 20/Pin 18/Pin 20): Main Supply Input. A low ESR
ceramic capacitor should be connected between this pin
and SGND.
(SSOP/QFN/TSSOP)
LTC3862
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FuncTional DiagraM
+
DMAX
PHASEMODE
FREQ
SLOPE
RFREQ
RC
PLLFLTR
SYNC
CLKOUT
RP
CP
SLOPE
COMPENSATION
SYNC
DETECT
BLANK
SS
3V8
5µA
BLOGIC
BLANK
LOGIC LOGIC
OVER
TEMP BIAS
CSS
CC
CLK1
CLK2
DMAX
OT
OV
OT
UV
SD
1.223V
PSKIP
PSKIP
0.275V
PSKIP
ITRIP
UV
VCO
PWM LATCH
S
R1 Q
OT
UVLO 3.8V
LDO
5V
LDO
UV
SD
BLOGIC
R2
+
–
+–
ICMP RLOOP
V TO I
ITH
RUN
+–
OV
OV
1.345V
+
–
SD
RUN
4.5µA
1.22V
+
–
EA 0.5µA
SGND
VFB
R1
3862 FD
GATE
3V8
INTVCC
VIN
VIN
PGND
SENSE+
SENSE–
DUPLICATE FOR
SECOND CHANNEL
CVCC
CIN
COUT
VOUT
C3V8
M
D
L
R2
RS
LTC3862
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operaTion
The Control Loop
The LTC3862 uses a constant frequency, peak current
mode step-up architecture with its two channels operat-
ing 180 degrees out of phase. During normal operation,
each external MOSFET is turned on when the clock for
that channel sets the PWM latch, and is turned off when
the main current comparator, ICMP, resets the latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
compares the output feedback signal at the VFB pin to the
internal 1.223V reference and generates an error signal
at the ITH pin. When the load current increases it causes
a slight decrease in VFB relative to the reference voltage,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the MOSFET is turned off, the inductor current flows
through the boost diode into the output capacitor and load,
until the beginning of the next clock cycle.
Cascaded LDOs Supply Power to the Gate Driver and
Control Circuitry
The LTC3862 contains two cascaded PMOS output stage
low dropout voltage regulators (LDOs), one for the gate
drive supply (INTVCC) and one for the low voltage analog
and digital control circuitry (3V8). A block diagram of this
power supply arrangement is shown in Figure 1.
The Gate Driver Supply LDO (INTVCC)
The 5V output (INTVCC) of the first LDO is powered from
VIN and supplies power to the power MOSFET gate driv-
ers. The INTVCC pin should be bypassed to PGND with a
minimum of 4.7μF of ceramic capacitance (X5R or better),
placed as close as possible to the IC pins. If two power
MOSFETs are connected in parallel for each channel in
order to increase the output power level, or if a single
MOSFET with a QG greater than 50nC is used, then it is
recommended that the bypass capacitance be increased
to a minimum of 10μF.
An undervoltage lockout (UVLO) circuit senses the INTVCC
regulator output in order to protect the power MOSFETs
from operating with inadequate gate drive. For the LTC3862
the rising UVLO threshold is typically 3.3V and the hyster-
esis is typically 400mV. The LTC3862 was optimized for
logic-level power MOSFETs and applications where the
output voltage is less than 50V to 60V. For applications
requiring standard threshold power MOSFETs, please refer
to the LTC3862-1 data sheet.
–
+
SGND
R2 R1
1.223V
LTC3862
INTVCC
3V8
GATE
–
+
SGND
R4 R3
1.223V
P-CH
P-CH
ANALOG
CIRCUITS LOGIC
INTVCC
VIN
CIN
CVCC
C3V8
3862 F01
PGND
3V8
SGND
NOTE: PLACE CVCC AND C3V8 CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS
Figure 1. Cascaded LDOs Provide Gate Drive and Control Circuitry Power
LTC3862
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In multi-phase applications, all of the FB pins are connected
together and all of the error amplifier output pins (ITH) are
connected together. The INTVCC pins, however, should not
be connected together. The INTVCC regulator is capable of
sourcing current but is not capable of sinking current. As
a result, when two or more INTVCC regulator outputs are
connected together, the highest voltage regulator supplies
all of the gate drive and control circuit current, and the
other regulators are off. This would place a thermal burden
on the highest output voltage LDO and could cause the
maximum die temperature to be exceeded. In multi-phase
LTC3862 applications, each INTVCC regulator output should
be independently bypassed to its respective PGND pin as
close as possible to each IC.
The Low Voltage Analog and Digital Supply LDO (3V8)
The second LDO within the LTC3862 is powered off of
INTVCC and serves as the supply to the low voltage analog
and digital control circuitry, as shown in Figure 1. The
output voltage of this LDO (which also has a PMOS out-
put device) is 3.8V. Most of the analog and digital control
circuitry is powered from the internal 3V8 LDO. The 3V8
pin should be bypassed to SGND with a 1nF ceramic ca-
pacitor (X5R or better), placed as close as possible to the
IC pins. This LDO is not intended to be used as a supply
for external circuitry.
Thermal Considerations and Package Options
The LTC3862 is offered in two package options. The 5mm
× 5mm QFN package (UH24) has a thermal resistance
RTH(JA) of 34°C/W, the 24-pin TSSOP (FE24) package has a
thermal resistance of 38°C/W, and the 24-pin SSOP (GN24)
package has a thermal resistance of 85°C/W. The QFN and
TSSOP package options have a lead pitch of 0.65mm, and
the GN24 option has a lead pitch of 0.025in.
The INTVCC regulator can supply up to 50mA of total
current. As a result, care must be taken to ensure that the
maximum junction temperature of the IC is never exceed-
ed. The junction temperature can be estimated using the
following equations:
IQ(TOT) = IQ + QG(TOT) • f
PDISS = VIN • (IQ + QG(TOT) • f)
TJ = TA + PDISS • RTH(JA)
The total quiescent current (IQ(TOT)) consists of the static
supply current (IQ) and the current required to charge
the gate capacitance of the power MOSFETs. The value
of QG(TOT) should come from the plot of VGS vs QG in the
Typical Performance Characteristics section of the MOSFET
data sheet. The value listed in the electrical specifications
may be measured at a higher VGS, such as 10V, whereas
the value of interest is at the 5V INTVCC gate drive voltage.
As an example of the required thermal analysis, consider
a 2-phase boost converter with a 9V to 24V input voltage
range and an output voltage of 48V at 2A. The switching
frequency is 150kHz and the maximum ambient tempera-
ture is 70°C. The power MOSFET used for this application
is the Vishay Si7478DP
, which has a typical RDS(ON) of
8.8mΩ at VGS = 4.5V and 7.5mΩ at VGS = 10V. From the
plot of VGS vs QG, the total gate charge at VGS = 5V is
50nC (the temperature coefficient of the gate charge is
low). One power MOSFET is used for each phase. For the
QFN package option:
IQ(TOT) = 3mA + 2 • 50nC • 150kHz = 18mA
PDISS = 24V • 18mA = 432mW
TJ = 70°C + 432mW • 34°C/W = 84.7°C
In this example, the junction temperature rise is only 14.7°C.
These equations demonstrate how the gate charge current
typically dominates the quiescent current of the IC, and
how the choice of package option and board heat sinking
can have a significant effect on the thermal performance
of the solution.
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To prevent the maximum junction temperature from be-
ing exceeded, the input supply current to the IC should
be checked when operating in continuous mode (heavy
load) at maximum VIN. A tradeoff between the operating
frequency and the size of the power MOSFETs may need
to be made in order to maintain a reliable junction tem-
perature. Finally, it is important to verify the calculations
by performing a thermal analysis of the final PCB using
an infrared camera or thermal probe. As an option, an
external regulator shown in Figure 3 can be used to reduce
the total power dissipation on the IC.
Thermal Shutdown Protection
In the event of an overtemperature condition (external
or internal), an internal thermal monitor will shut down
the gate drivers and reset the soft-start capacitor if the
die temperature exceeds 170°C. This thermal sensor has
a hysteresis of 10°C to prevent erratic behavior at hot
temperatures. The LTC3862’s internal thermal sensor is
intended to protect the device during momentary over-
temperature conditions. Continuous operation above
the specified maximum operating junction temperature,
however, may result in device degradation.
Operation at Low Supply Voltage
The L
TC3862 has a minimum input voltage of 4V, making it
a good choice for applications that experience low supply
conditions. The gate driver for the LTC3862 consists of
PMOS pull-up and NMOS pull-down devices, allowing
the full INTVCC voltage to be applied to the gates during
power MOSFET switching. Nonetheless, care should be
taken to determine the minimum gate drive supply voltage
(INTVCC) in order to choose the optimum power MOSFETs.
Important parameters that can affect the minimum gate
drive voltage are the minimum input voltage (VIN(MIN)),
the LDO dropout voltage, the QG of the power MOSFETs,
and the operating frequency.
If the input voltage VIN is low enough for the INTVCC LDO
to be in dropout, then the minimum gate drive supply
voltage is:
VINTVCC = VIN(MIN) – VDROPOUT
The LDO dropout voltage is a function of the total gate
drive current and the quiescent current of the IC (typically
3mA). A curve of dropout voltage vs output current for the
LDO is shown in Figure 2. The temperature coefficient of
the LDO dropout voltage is approximately 6000ppm/°C.
The total Q-current (IQ(TOT)) flowing in the LDO is the sum
of the controller quiescent current (3mA) and the total gate
charge drive current.
IQ(TOT) = IQ + QG(TOT) • f
After the calculations have been completed, it is important
to measure the gate drive waveforms and the gate driv-
er supply voltage (INTVCC to PGND) over all operating
conditions (low VIN, nominal VIN and high VIN, as well
as from light load to full load) to ensure adequate power
MOSFET enhancement. Consult the power MOSFET data
sheet to determine the actual RDS(ON) for the measured
VGS, and verify your thermal calculations by measuring
the component temperatures using an infrared camera
or thermal probe.
INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
600
800
1000
30 50
3862 F02
400
200
010 20 40
1200
1400
1600
85°C
25°C
–40°C
125°C
150°C
Figure 2. INTVCC LDO Dropout Voltage vs Current
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Operation at High Supply Voltage
At high input voltages, the LTC3862’s internal LDO can
dissipate a significant amount of power, which could
cause the maximum junction temperature to be exceeded.
Conditions such as a high operating frequency, or the use
of more than one power MOSFET per channel, could push
the junction temperature rise to high levels. If the thermal
equations above indicate too high a rise in the junction
temperature, an external bias supply can always be used
to reduce the power dissipation on the IC, as shown in
Figure 3.
For example, a 5V or 12V system rail that is available
would be more suitable than the 24V main input power
rail to power the LTC3862. Also, the bias power can be
generated with a separate switching or LDO regulator. An
example of an LDO regulator is shown in Figure 3. The
output voltage of the LDO regulator can be set by selecting
an appropriate Zener diode to be higher than 5V but low
enough to divide the power dissipation between LTC3862
and Q1 in Figure 3. The absolute maximum voltage rating
of the INTVCC pin is 6V.
flow from the external INTVCC supply, through the body
diode of the LDO PMOS device, to the input capacitor
and VIN pin. This high current flow could trigger a latchup
condition and cause catastrophic failure of the IC.
If, however, the VIN supply to the IC comes up before the
INTVCC supply, the external INTVCC supply will act as a
load to the internal LDO in the LTC3862, and the LDO will
attempt to charge the INTVCC output with its short-circuit
current. This will result in excessive power dissipation and
possible thermal overload of the LTC3862.
If an independent 5V supply exists in the system, it may be
possible to short INTVCC and VIN together to 5V in order
to reduce gate drive power dissipation. With VIN and INT-
VCC shorted together, the LDO output PMOS transistor is
biased at VDS = 0V, and the current demand of the internal
analog and digital control circuitry, as well as the gate
drive current, will be supplied by the external 5V supply.
Programming the Output Voltage
The output voltage is set by a resistor divider according
to the following formula:
VV
R
R
OUT
=+
1223 12
1
.
The external resistor divider is connected to the output as
shown in Figure 4. Resistor R1 is normally chosen so that
the output voltage error caused by the current flowing out of
the VFB pin during normal operation is negligible compared
to the current in the divider. For an output voltage error
due to the error amp input bias current of less than 0.5%,
this translates to a maximum value of R1 of about 30k.
Figure 3. Using the LTC3862 with an External Bias Supply
Figure 4. Programming the Output Voltage
with a Resistor Divider
VIN
R1
Q1
D1
CVCC
(OPT)
3862 F03
LTC3862
VIN
INTVCC
LTC3862
FB
SGND
R2
R1
3862 F04
V
OUT
Power Supply Sequencing
As shown in Figure 1, there are body diodes in parallel
with the PMOS output transistors in the two LDO regula-
tors in the LTC3862. As a result, it is not possible to bias
the INTVCC and VIN pins of the chip from separate power
supplies. Independently biasing the INTVCC pin from a
separate power supply can cause one of two possible
failure modes during supply sequencing. If the INTVCC
supply comes up before the VIN supply, high current will
LTC3862
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Operation of the RUN Pin
The control circuitry in the LTC3862 is turned on and
off using the RUN pin. Pulling the RUN pin below 1.22V
forces shutdown mode and releasing it allows a 0.5μA
current source to pull this pin up, allowing a “normally
on” converter to be designed. Alternatively, the RUN pin
can be externally pulled up or driven directly by logic.
Care must be taken not to exceed the absolute maximum
rating of 8V for this pin.
The comparator on the RUN pin can also be used to sense
the input voltage, allowing an undervoltage detection
circuit to be designed. This is helpful in boost converter
applications where the input current can reach very high
levels at low input voltage:
I
IV
V
IN OUT OUT
IN
=•
•η
The 1.22V input threshold of the RUN comparator is derived
from a precise bandgap reference, in order to maximize
the accuracy of the undervoltage-sensing function. The
RUN comparator has 80mV built-in hysteresis. When
the voltage on the RUN pin exceeds 1.22V, the current
sourced into the RUN pin is switched from 0.5μA to 5μA
current. The user can therefore program both the rising
threshold and the amount of hysteresis using the values
of the resistors in the external divider, as shown in the
following equations:
VV
R
RµR
V
IN ON A
BA
IN OFF
()
()
.–
.•=+
=
1221 05
1.. –•22
15
VR
RµR
A
BA
+
Several of the possible RUN pin control techniques are
illustrated in Figure 5.
Frequency Selection and the Phase Lock Loop
The selection of the switching frequency is a tradeoff
between efficiency and component size. Low frequency
operation increases efficiency by reducing MOSFET
switching losses, but requires a larger inductor and output
capacitor to maintain low output ripple.
Figure 5a. Using the RUN Pin for a “Normally On” Converter
Figure 5b. On/Off Control Using External Logic
Figure 5c. Programming the Input Voltage Turn-On and Turn-Off
Thresholds Using the RUN Pin
–
+
RUN
COMPARATOR
1.22V
3862 F05a
VIN LTC3862
RUN
10V
INTERNAL 5V
0.5µA 4.5µA
SGND
BIAS AND
START-UP
CONTROL
–
+
RUN
COMPARATOR
1.22V
3862 F05b
VIN LTC3862
RUN
10V
INTERNAL 5V
EXTERNAL
LOGIC
CONTROL 0.5µA 4.5µA
SGND
BIAS AND
START-UP
CONTROL
–
+
RUN
COMPARATOR
1.22V
3862 F05c
VIN LTC3862
RUN
10V
INTERNAL 5V
0.5µA
RA
4.5µA
SGND
BIAS AND
START-UP
CONTROL
RB
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The LTC3862 uses a constant frequency architecture that
can be programmed over a 75kHz to 500kHz range using
a single resistor from the FREQ pin to ground. Figure 6
illustrates the relationship between the FREQ pin resistance
and the operating frequency.
The operating frequency of the LTC3862 can be approxi-
mated using the following formula:
RFREQ = 5.5096E9(fOSC)–0.9255
A phase-lock loop is available on the LTC3862 to syn-
chronize the internal oscillator to an external clock
source connected to the SYNC pin. Connect a series RC
network from the PLLFLTR pin to SGND to compensate
PLL’s feedback loop. Typical compensation components
are a 0.01μF capacitor in series with a 10k resistor. The
PLLFLTR pin is both the output of the phase detector and
the input to the voltage controlled oscillator (VCO). The
LTC3862 phase detector adjusts the voltage on the PLL-
FLTR pin to align the rising edge of GATE1 to the leading
edge of the external clock signal, as shown in Figure 7.
The rising edge of GATE2 will depend upon the voltage on
the PHASEMODE pin. The capture range of the LTC3862’s
PLL is 50kHz to 650kHz.
Because the operating frequency of the L
TC3862 can be
programmed using an external resistor, in synchronized
applications, it is recommended that the free-running fre-
quency (as defined by the external resistor) be set to the
same value as the synchronized frequency. This results in
a start-up of the IC at approximately the same frequency
as the external clock, so that when the sync signal comes
alive, no discontinuity at the output will be observed. It also
ensures that the operating frequency remains essentially
constant in the event the sync signal is lost. The SYNC
pin has an internal 50k resistor to ground.
Using the CLKOUT and PHASEMODE Pins
in Multi-Phase Applications
The LTC3862 features two pins (CLKOUT and PHASEMODE)
that allow multiple ICs to be daisy-chained together for
higher current multi-phase applications. For a 3- or 4-phase
FREQUENCY (kHz)
100
RFREQ (kΩ)
300
1000
3862 F06
10
100
200 1000
900
800700600
500
400
0
Figure 6. FREQ Pin Resistor Value vs Frequency
Figure 7. Synchronization of the LTC3862
to an External Clock Using the PLL
SYNC
10V/DIV
GATE1
10V/DIV
GATE2
10V/DIV
CLKOUT
10V/DIV
2µs/DIVVIN = 12V
VOUT = 48V 1A
PHASEMODE = SGND
3862 F07
design, the CLKOUT signal of the master controller is con-
nected to the SYNC input of the slave controller in order
to synchronize additional power stages for a single high
current output. The PHASEMODE pin is used to adjust
the phase relationship between channel 1 and channel 2,
as well as the phase relationship between channel 1 and
CLKOUT, as summarized in Table 1. The phases are cal-
culated relative to the zero degrees, defined as the rising
edge of the GATE1 output. In a 6-phase application the
CLKOUT pin of the master controller connects to the SYNC
input of the 2nd controller and the CLKOUT pin of the 2nd
controller connects to the SYNC pin of the 3rd controller.
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Table 1
PHASEMODE
CH-1 to CH-2
PHASE
CH-1 to CLKOUT
PHASE
APPLICATION
SGND 180° 90° 2-Phase, 4-Phase
Float 180° 60° 6-Phase
3V8 120° 240° 3-Phase
Using the LTC3862 Transconductance (gm) Error
Amplifier in Multi-Phase Applications
The LTC3862 error amplifier is a transconductance, or gm
amplifier, meaning that it has high DC gain but high output
impedance (the output of the error amplifier is a current
proportional to the differential input voltage). This style
of error amplifier greatly eases the task of implementing a
multi-phase solution, because the amplifiers from two or
more chips can be connected in parallel. In this case the
FB pins of multiple LTC3862s can be connected together,
as well as the ITH pins, as shown in Figure 8. The gm of the
composite error amplifier is simply n times the transcon-
ductance of one amplifier, or gm(TOT) = n • 660μS, where
n is the number of amplifiers connected in parallel. The
transfer function from the ITH pin to the current comparator
inputs was carefully designed to be accurate, both from
channel-to-channel and chip-to-chip. This way the peak
inductor current matching is kept accurate.
A buffered version of the output of the error amplifier
determines the threshold at the input of the current com-
parator. The ITH voltage that represents zero peak current
is 0.4V and the voltage that represents current limit is
1.2V (at low duty cycle). During an overload condition, the
output of the error amplifier is clamped to 2.6V at low duty
cycle, in order to reduce the latency when the overload
condition terminates. A patented circuit in the LTC3862 is
used to recover the slope compensation signal, so that the
maximum peak inductor current is not a strong function
of the duty cycle.
In multiphase applications that use more than one LTC3862
controller, it is possible for ground currents on the PCB
to disturb the control lines between the ICs, resulting in
erratic behavior. In these applications the FB pins should
be connected to each other through 100Ω resistors and
each slave FB pin should be decoupled locally with a 100pF
capacitor to ground, as shown in Figure 8.
Figure 8. LTC3862 Error Amplifier Configuration
for Multi-Phase Operation
Soft-Start
The start-up of the LTC3862 is controlled by the voltage on
the SS pin. An internal PNP transistor clamps the current
comparator sense threshold during soft-start, thereby
limiting the peak switch current. The base of the PNP is
connected to the SS pin and the emitter to an internal,
buffered ITH node (please note that the ITH pin voltage may
not track the soft-start voltage during this time period).
An internal 5μA current source charges the SS capacitor,
and clamps the peak sense threshold until the voltage on
the soft-start capacitor reaches approximately 0.6V. The
required amount of soft-start capacitance can be estimated
using the following equation:
CµAt
V
SS SS
=
506.
FREQ
FB
CLKOUT
SYNC
PLLFLTR
LTC3862
MASTER
SGND
ITH
VOUT
INTVCC
SS
RUN ON/OFF
CONTROL
ALL RUN PINS
CONNNECTED
TOGETHER
INDIVIDUAL
INTVCC PINS
LOCALLY
DECOUPLED
FREQ
FB
100pF
CLKOUT
SYNC
PLLFLTR
LTC3862
SLAVE
SGND
ITH
INTVCC
SS
RUN
SLAVE
3862 F08
ALL SS PINS
CONNNECTED
TOGETHER
FREQ
FB
ALL FB PINS
CONNECTED
TOGETHER
ALL ITH PINS
CONNECTED
TOGETHER
100Ω
CLKOUT
SYNC
PLLFLTR PHASEMODE
PHASEMODE
PHASEMODE
LTC3862
SGND
ITH
INTVCC
SS
RUN
100Ω 100Ω
100Ω
100pF
100pF
100pF
LTC3862
19
3862fc
For more information www.linear.com/LTC3862
operaTion
The SS pin has an internal open-drain NMOS pull-down
transistor that turns on when the RUN pin is pulled low,
when the voltage on the INTVCC pin is below its under-
voltage lockout threshold, or during an overtemperature
condition. In multi-phase applications that use more than
one LTC3862 chip, connect all of the SS pins together and
use one external capacitor to program the soft-start time.
In this case, the current into the soft-start capacitor will be
ISS = n • 5μA, where n is the number of SS pins connected
together. Figure 9 illustrates the start-up waveforms for a
2-phase LTC3862 application.
Pulse Skip Operation at Light Load
As the load current is decreased, the controller enters
discontinuous mode (DCM). The peak inductor current can
be reduced until the minimum on-time of the controller
is reached. Any further decrease in the load current will
cause pulse skipping to occur, in order to maintain output
regulation, which is normal. The minimum on-time of
the controller in this mode is approximately 180ns (with
the blanking time set to its minimum value), the majority
of which is leading edge blanking. Figure 10 illustrates
the LTC3862 switching waveforms at the onset of pulse
skipping.
Programmable Slope Compensation
For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
50%, in order to avoid sub-harmonic oscillation. For the
LTC3862, this ramp compensation is internal and user
adjustable. Having an internally fixed ramp compensation
waveform normally places some constraints on the value
of the inductor and the operating frequency. For example,
with a fixed amount of internal slope compensation, using
an excessively large inductor would result in too much
effective slope compensation, and the converter could
become unstable. Likewise, if too small an inductor were
used, the internal ramp compensation could be inadequate
to prevent sub-harmonic oscillation.
The LTC3862 contains a pin that allows the user to pro-
gram the slope compensation gain in order to optimize
performance for a wider range of inductance. With the
SLOPE pin left floating, the normalized slope gain is
1.00. Connecting the SLOPE pin to ground reduces the
normalized gain to 0.625 and connecting this pin to the
3V8 supply increases the normalized slope gain to 1.66.
With the normalized slope compensation gain set to 1.00,
the design equations assume an inductor ripple current of
20% to 40%, as with previous designs. Depending upon
the application circuit, however, a normalized gain of 1.00
may not be optimum for the inductor chosen. If the ripple
current in the inductor is greater than 40%, the normalized
slope gain can be increased to 1.66 (an increase of 66%)
by connecting the SLOPE pin to the 3V8 supply. If the
inductor ripple current is less than 20%, the normalized
slope gain can be reduced to 0.625 (a decrease of 37.5%)
by connecting the SLOPE pin to SGND.
To check the effectiveness of the slope compensation, apply
a load step to the output and monitor the cycle-by-cycle
RUN
5V/DIV
IL1
5A/DIV
IL2
5A/DIV
VOUT
50V/DIV
1ms/DIVVIN = 12V
VOUT = 48V
100Ω LOAD
3862 F09a
Figure 9. Typical Start-Up Waveforms for a
Boost Converter Using the LTC3862
Figure 10. Light Load Switching Waveforms for
the LTC3862 at the Onset of Pulse Skipping
SW1
10V/DIV
SW2
10V/DIV
IL1
1A/DIV
IL2
1A/DIV
1µs/DIV 3862 F10
VIN = 17V
VOUT = 24V
LIGHT LOAD (10mA)
LTC3862
20
3862fc
For more information www.linear.com/LTC3862
operaTion
Figure 12. Effect of Slope Gain on the Peak SENSE Threshold
behavior of the inductor current during the leading and
trailing edges of the load current. Vary the input voltage
over its full range and check for signs of cycle-by-cycle
SW node instability or sub-harmonic oscillation. When
the slope compensation is too low the converter can
suffer from excessive jitter or, worst case, sub-harmonic
oscillation. When excess slope compensation is applied to
the internal current sense signal, the phase margin of the
control loop suffers. Figure 11 illustrates inductor current
waveforms for a properly compensated loop.
The LTC3862 contains a patented circuit whereby most
of the applied slope compensation is recovered, in order
to provide a SENSE+ to SENSE– threshold which is not
a strong function of the duty cycle. This sense threshold
is, however, a function of the programmed slope gain, as
shown in Figure 12. The data sheet typical specification of
75mV for SENSE+ minus SENSE– is measured at a normal-
ized slope gain of 1.00 at low duty cycle. For applications
where the normalized slope gain is not 1.00, use Figure 12
to determine the correct value of the sense resistor.
Programmable Blanking and the Minimum On-Time
The BLANK pin on the LTC3862 allows the user to program
the amount of leading edge blanking at the SENSE pins.
Connecting the BLANK pin to SGND results in a minimum
on-time of 180ns, floating the pin increases this time to
260ns, and connecting the BLANK pin to the 3V8 supply
results in a minimum on-time of 340ns. The majority of the
minimum on-time consists of this leading edge blanking,
due to the inherently low propagation delay of the current
comparator (25ns typ) and logic circuitry (10ns to 15ns).
The purpose of leading edge blanking is to filter out noise on
the SENSE pins at the leading edge of the power MOSFET
turn-on. During the turn-on of the power MOSFET the gate
drive current, the discharge of any parasitic capacitance
on the SW node, the recovery of the boost diode charge,
and parasitic series inductance in the high di/dt path all
contribute to overshoot and high frequency noise that
could cause false-tripping of the current comparator. Due
to the wide range of applications the LTC3862 is well-suited
to, fixing one value of the internal leading edge blanking
time would have required the longest delay time to have
been used. Providing a means to program the blank time
allows users to optimize the SENSE pin filtering for each
application. Figure 13 illustrates the effect of the program-
mable leading edge blank time on the minimum on-time
of a boost converter
.
Programmable Maximum Duty Cycle
In order to maintain constant frequency and a low output
ripple voltage, a single-ended boost (or flyback or SEPIC)
converter is required to turn off the switch every cycle
for some minimum amount of time. This off-time allows
the transfer of energy from the inductor to the output
capacitor and load, and prevents excessive ripple current
and voltage. For inductor-based topologies like boost and
SEPIC converters, having a maximum duty cycle as close
as possible to 100% may be desirable, especially in low VIN
to high VOUT applications. However, for transformer-based
solutions, having a maximum duty cycle near 100% is
DUTY CYCLE (%)
50
MAXIMUM CURRENT SENSE THRESHOLD (mV)
60
70
80
55
65
75
20 40 60 80
3862 F12
100100 30 50 70 90
SLOPE = 0.625
SLOPE = 1.66
SLOPE = 1
Figure 11. Inductor Current Waveforms for a
Properly Compensated Control Loop
ILOAD
2A/DIV
200mA-3A
IL1
2A/DIV
IL2
2A/DIV
VOUT
2V/DIV
10µs/DIV 3862 F11
VIN = 24V
VOUT = 48V
LTC3862
21
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For more information www.linear.com/LTC3862
operaTion
Figure 13. Leading Edge Blanking Effects
on the Minimum On-Time
Figure 14. SW Node Waveforms with Different Duty Cycle Limits
SW NODE
20V/DIV
GATE
2V/DIV
200ns/DIV
MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = SGND
VIN = 30V
VOUT = 48V
MEASURED ON-TIME = 180ns
VIN = 30V
VOUT = 48V
MEASURED ON-TIME = 260ns
VIN = 30V
VOUT = 48V
MEASURED ON-TIME = 340ns
INDUCTOR
CURRENT
1A/DIV
SW NODE
20V/DIV
GATE
2V/DIV
INDUCTOR
CURRENT
1A/DIV
SW NODE
20V/DIV
GATE
2V/DIV
INDUCTOR
CURRENT
1A/DIV
200ns/DIV
MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = FLOAT
200ns/DIV 3862 F13
MINIMUM ON-TIME AT LIGHT LOAD WITH BLANK = 3V8
SW NODE
10V/DIV
SW NODE
10V/DIV
1µs/DIV
96% MAXIMUM DUTY CYCLE WITH DMAX = SGND
INDUCTOR
CURRENT
2A/DIV
1µs/DIV
84% MAXIMUM DUTY CYCLE WITH DMAX = FLOAT
INDUCTOR
CURRENT
2A/DIV
SW NODE
10V/DIV
INDUCTOR
CURRENT
2A/DIV
1µs/DIV 3862 F14
75% MAXIMUM DUTY CYCLE WITH DMAX = 3V8
undesirable, due to the need for V • sec reset during the
primary switch off-time.
In order to satisfy these different applications requirements,
the LTC3862 has a simple way to program the maximum
duty cycle. Connecting the DMAX pin to SGND limits the
maximum duty cycle to 96%. Floating this pin limits the
duty cycle to 84% and connecting the DMAX pin to the 3V8
supply limits it to 75%. Figure 14 illustrates the effect of
limiting the maximum duty cycle on the SW node waveform
of a boost converter.
The LTC3862 contains an oscillator that runs at 12x the
programmed switching frequency, in order to provide for
2-, 3-, 4-, 6- and 12-phase operation. A digital counter is
used to divide down the fundamental oscillator frequency in
order to obtain the operating frequency of the gate drivers.
Since the maximum duty cycle limit is obtained from
this digital counter, the percentage maximum duty cycle
does not vary with process tolerances or temperature.
The SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are high impedance inputs
to the CMOS current comparators for each channel.
Nominally, there is no DC current into or out of these
LTC3862
22
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For more information www.linear.com/LTC3862
pins. There are ESD protection diodes connected from
these pins to SGND, although even at hot temperature the
leakage current into the SENSE+ and SENSE– pins should
be less than 1μA.
Since the LTC3862 contains leading edge blanking, an
external RC filter is not required for proper operation.
However, if an external filter is used, the filter components
should be placed close to the SENSE+ and SENSE– pins on
the IC, as shown in Figure 15. The positive and negative
sense node traces should then run parallel to each other
to a Kelvin connection underneath the sense resistor, as
shown in Figure 16. Sensing current elsewhere on the
board can add parasitic inductance and capacitance to
the current sense element, degrading the information at
the sense pins and making the programmed current limit
unpredictable. Avoid the temptation to connect the SENSE–
line to the ground plane using a PCB via; this could result
in unpredictable behavior.
The sense resistor should be connected to the source of
the power MOSFET and the ground node using short, wide
PCB traces, as shown in Figure 16. Ideally, the bottom
terminal of the sense resistors will be immediately adjacent
to the negative terminal of the output capacitor, since this
path is a part of the high di/dt loop formed by the switch,
boost diode, output capacitor and sense resistor. Place-
ment of the inductors is less critical, since the current in
the inductors is a triangle waveform.
MOSFET SOURCE
TO SENSE
FILTER NEXT
TO CONTROLLER
RSENSE
GND
3862 F16
Figure 16. Connecting the SENSE+ and SENSE– Traces to the
Sense Resistor Using a Kelvin Connection
Checking the Load Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT
. ∆ILOAD also begins to charge or
discharge COUT
, generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem.
The availability of the ITH pin not only allows optimization
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin.
The ITH series RC • CC filter sets the dominant pole-zero
loop compensation. The transfer function for boost and
flyback converters contains a right half plane zero that
normally requires the loop crossover frequency to be
reduced significantly in order to maintain good phase
operaTion
SENSE–
SENSE+
LTC3862
GATE
VOUT
RSENSE
3862 F15
FILTER COMPONENTS
PLACED NEAR
SENSE PINS
VIN
PGND
INTVCC
VIN
Figure 15. Proper Current Sense Filter Component Placement
LTC3862
23
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For more information www.linear.com/LTC3862
operaTion
Figure 17. Load Step Response of a Properly
Compensated Boost Converter
ILOAD
5A/DIV
1A TO 5A
IL1
5A/DIV
IL2
5A/DIV
VOUT
500mV/DIV
500µs/DIVVIN = 24V
VOUT = 48V
3862 F17
margin. The RC • CC filter values can typically be modified
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the final PC layout is done
and the particular output capacitor type(s) and value(s)
have been determined. The output capacitor configuration
needs to be selected in advance because the effective ESR
and bulk capacitance have a significant effect on the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET and load
resistor directly across the output capacitor and driving
the gate with an appropriate signal generator is a practi-
cal way to produce a fast load step condition. The initial
output voltage step resulting from the step change in the
output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the filtered
and compensated control loop response. The gain of the
loop will be increased by increasing RC and the bandwidth
of the loop will be increased by decreasing CC. If RC is
increased by the same factor that CC is decreased, the
zero frequency will be kept the same, thereby keeping the
phase shift the same in the most critical frequency range
of the feedback loop. The output voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
Figure 17 illustrates the load step response of a properly
compensated boost converter.
LTC3862
24
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For more information www.linear.com/LTC3862
Figure 18. A Typical 2-Phase, Single Output Boost Converter Application Circuit
Typical Boost Applications Circuit
A basic 2-phase, single output LTC3862 application circuit
is shown in Figure 18. External component selection is
driven by the characteristics of the load and the input supply.
Duty Cycle Considerations
For a boost converter operating in a continuous conduction
mode (CCM), the duty cycle of the main switch is:
DVVV
VV
tf
OFIN
OF ON
=+
+
=
–•
where VF is the forward voltage of the boost diode. The
minimum on-time for a given application operating in
CCM is:
tf
VVV
VV
ON MIN
OFIN MAX
OF
()
()
–
=+
+
1
For a given input voltage range and output voltage, it is
important to know how close the minimum on-time of the
application comes to the minimum on-time of the control
IC. The LTC3862 minimum on-time can be programmed
from 180ns to 340ns using the BLANK pin.
Minimum On-Time Limitations
In a single-ended boost converter, two steady-state con-
ditions can result in operation at the minimum on-time of
the controller. The first condition is when the input voltage
is close to the output voltage. When VIN approaches VOUT
the voltage across the inductor approaches zero during
the switch off-time. Under this operating condition the
converter can become unstable and the output can experi-
ence high ripple voltage oscillation at audible frequencies.
For applications where the input voltage can approach
or exceed the output voltage, consider using a SEPIC or
buck-boost topology instead of a boost converter.
The second condition that can result in operation at the
minimum on-time of the controller is at light load, in deep
discontinuous mode. As the load current is decreased,
the on-time of the switch decreases, until the minimum
on-time limit of the controller is reached. Any further de-
crease in the output current will result in pulse skipping,
a typically benign condition where cycles are skipped in
order to maintain output regulation.
applicaTions inForMaTion
SENSE1+
3V8
SLOPE
BLANK
CLKOUT
SYNC
PLLFLTR
PHASEMODE
DMAX
10nF
SENSE1–
SENSE2–
SENSE2+
RUN
FREQ
SS VIN
66.5k 24.9k
84.5k
10Ω
VIN
5V TO 36V D1
PDS760
D2
PDS760
10Ω
L2
19.4µH
PA2020-193
ITH
SGND
VOUT
12.4k
FB
68.1k
475k
10nF 1µF
1nF
6.8µF 50V
0.006Ω
1W
Q1
HAT2266H
Q2
HAT2266H
0.006Ω
1W
VOUT
48V
2A TO 5A
3862 F18
100µF
63V
100µF
63V
6.8µF 50V
6.8µF 50V
6.8µF 50V
LTC3862
10nF
100pF INTVCC
GATE1
GATE2
PGND
4.7µF
10nF
6.8µF 50V
6.8µF 50V
6.8µF 50V
L1
19.4µH
PA2020-193
+
+
LTC3862
25
3862fc
For more information www.linear.com/LTC3862
applicaTions inForMaTion
Maximum Duty Cycle Limitations
Another operating extreme occurs at high duty cycle,
when the input voltage is low and the output voltage is
high. In this case:
DVVV
VV
MAX
OFIN MIN
OF
=+
+
–()
A single-ended boost converter needs a minimum off-time
every cycle in order to allow energy transfer from the input
inductor to the output capacitor. This minimum off-time
translates to a maximum duty cycle for the converter. The
equation above can be rearranged to obtain the maximum
output voltage for a given minimum input or maximum
duty cycle.
VV
DV
OMAX IN
MAXF() ––=
1
The equation for DMAX above can be used as an initial
guideline for determining the maximum duty cycle of
the application circuit. However, losses in the inductor,
input and output capacitors, the power MOSFETs, the
sense resistors and the controller (gate drive losses) all
contribute to an increasing of the duty cycle. The effect
of these losses will be to decrease the maximum output
voltage for a given minimum input voltage.
After the initial calculations have been completed for an
application circuit, it is important to build a prototype of
the circuit and measure it over the entire input voltage
range, from light load to full load, and over temperature,
in order to verify proper operation of the circuit.
Peak and Average Input Currents
The control circuit in the LTC3862 measures the input
current (by means of resistors in the sources of the power
MOSFETs), so the output current needs to be reflected back
to the input in order to dimension the power MOSFETs prop-
erly. Based on the fact that, ideally, the output power is equal
to the input power, the maximum average input current is:
II
D
IN MAX
OMAX
MAX
()
()
–
=
1
The peak current in each inductor is:
In
I
D
IN PK
OMAX
MAX
()
()
••
–
=+
1121
χ
where n represents the number of phases and χ rep-
resents the percentage peak-to-peak ripple current in the
inductor. For example, if the design goal is to have 30%
ripple current in the inductor, then χ = 0.30, and the peak
current is 15% greater than the average.
Inductor Selection
Given an input voltage range, operating frequency and
ripple current, the inductor value can be determined using
the following equation:
LV
If
D
IN MIN
LMAX
=()
••
∆
where:
∆In
I
D
L
OMAX
MAX
=χ•–
()
1
Choosing a larger value of ∆IL allows the use of a lower
value inductor but results in higher output voltage ripple,
greater core losses, and higher ripple current ratings for
the input and output capacitors. A reasonable starting
point is 30% ripple current in the inductor (χ = 0.3), or:
∆In
I
D
L
OMAX
MAX
=03
1
.•–
()
The inductor saturation current rating needs to be higher
than the worst-case peak inductor current during an
overload condition. If IO(MAX) is the maximum rated load
current, then the maximum current limit value (IO(CL))
would normally be chosen to be some factor (e.g., 30%)
greater than IO(MAX).
IO(CL) = 1.3 • IO(MAX)
LTC3862
26
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For more information www.linear.com/LTC3862
applicaTions inForMaTion
Reflecting this back to the input, where the current is being
measured, and accounting for the ripple current, gives a
minimum saturation current rating for the inductor of:
In
I
D
LSAT
OMAX
MAX
()
()
••
.•
–
≥+
112
13
1
χ
The saturation current rating for the inductor should be
determined at the minimum input voltage (which results
in the highest duty cycle and maximum input current),
maximum output current and the maximum expected
core temperature. The saturation current ratings for most
commercially available inductors drop at high temperature.
To verify safe operation, it is a good idea to characterize
the inductor’s core/winding temperature under the fol-
lowing conditions: 1) worst-case operating conditions,
2) maximum allowable ambient temperature and 3) with
the power supply mounted in the final enclosure. Thermal
characterization can be done by placing a thermocouple
in intimate contact with the winding/core structure, or by
burying the thermocouple within the windings themselves.
Remember that a single-ended boost converter is not
short-circuit protected, and that under a shorted output
condition, the output current is limited only by the input
supply capability. For applications requiring a step-up
converter that is short-circuit protected, consider using
a SEPIC or forward converter topology.
Power MOSFET Selection
The peak-to-peak gate drive level is set by the INTVCC
voltage is 5V for the LTC3862 under normal operating con-
ditions. Selection criteria for the power MOSFETs include
the RDS(ON), gate charge QG, drain-to-source breakdown
voltage BVDSS, maximum continuous drain current ID(-
MAX), and thermal resistances RTH(JA) and RTH(JC)—both
junction-to-ambient and junction-to-case.
The gate driver for the LTC3862 consists of PMOS pull-up
and NMOS pull-down devices, allowing the full INTVCC
voltage to be applied to the gates during power MOSFET
switching. Nonetheless, care must be taken to ensure
that the minimum gate drive voltage is still sufficient to
full enhance the power MOSFET. Check the MOSFET data
sheet carefully to verify that the RDS(ON) of the MOSFET
is specified for a voltage less than or equal to the nominal
INTVCC voltage of 5V. For applications that require a power
MOSFET rated at 6V or 10V, please refer to the LTC3862-1
data sheet.
Also pay close attention to the BVDSS specifications for the
MOSFETs relative to the maximum actual switch voltage
in the application. Check the switching waveforms of
the MOSFET directly on the drain terminal using a single
probe and a high bandwidth oscilloscope. Ensure that the
drain voltage ringing does not approach the BVDSS of the
MOSFET. Excessive ringing at high frequency is normally
an indicator of too much series inductance in the high di/
dt current path that includes the MOSFET, the boost diode,
the output capacitor, the sense resistor and the PCB traces
connecting these components.
The GATE of MOSFET Q1 could experience transient
voltage spikes during turn-on and turn-off of the MOS-
FET, due to parasitic lead inductance and improper PCB
layout. These voltage spikes could exceed the absolute
maximum voltage rating of LTC3862’s GATE pin. The GATE
pins are rated for an absolute maximum voltage of –0.3V
minimum and 6V maximum. Hence it is recommended to
add an external buffer close to the GATE of the MOSFET
as shown in Figure 19.
Figure 19. External Buffer Circuit
LTC3862
GATE1, 2
VOUT
RSENSE
COUT
3862 F19
L
Q2A
PBS4140DPN
Q1
Q2B
10Ω
PGND
SGND
INTVCC
VIN
LTC3862
27
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For more information www.linear.com/LTC3862
Finally, check the MOSFET manufacturer’s data sheet for
an avalanche energy rating (EAS). Some MOSFETs are not
rated for body diode avalanche and will fail catastrophi-
cally if the VDS exceeds the device BVDSS, even if only by
a fraction of a volt. Avalanche-rated MOSFETs are better
able to sustain high frequency drain-to-source ringing near
the device BVDSS during the turn-off transition.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be known.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to
the positive temperature coefficient of its RDS(ON)). As a
result, some iterative calculation is normally required to
determine a reasonably accurate value.
The power dissipated by the MOSFET in a multi-phase
boost converter with n phases is:
PI
nD RD
FET
OMAX
MAX
DS ON MAX
=
()
()
()
•– •••
1
2
ρρT
OUT
OMAX
MAX
RSS
kV I
nD
Cf
+
()
••
•–
••
()
2
1
The first term in the equation above represents the I2R
losses in the device, and the second term, the switching
losses. The constant, k = 1.7, is an empirical factor inversely
related to the gate drive current and has the dimension
of 1/current.
The ρT term accounts for the temperature coefficient of
the RDS(ON) of the MOSFET, which is typically 0.4%/ºC.
Figure 20 illustrates the variation of normalized RDS(ON)
over temperature for a typical power MOSFET.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + PFET • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(CA)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
It is tempting to choose a power MOSFET with a very low
RDS(ON) in order to reduce conduction losses. In doing
so, however, the gate charge QG is usually significantly
higher, which increases switching and gate drive losses.
Since the switching losses increase with the square of
the output voltage, applications with a low output voltage
generally have higher MOSFET conduction losses, and
high output voltage applications generally have higher
MOSFET switching losses. At high output voltages, the
highest efficiency is usually obtained by using a MOSFET
with a higher RDS(ON) and lower QG. The equation above
can easily be split into two components (conduction and
switching) and entered into a spreadsheet, in order to
compare the performance of different MOSFETs.
applicaTions inForMaTion
Figure 20. Normalized Power MOSFET RDS(ON) vs Temperature
JUNCTION TEMPERATURE (°C)
–50
ρT NORMALIZED ON RESISTANCE
1.0
1.5
150
3862 F20
0.5
0050 100
2.0
LTC3862
28
3862fc
For more information www.linear.com/LTC3862
Figure 21. Maximum Sense Voltage Variation
with Duty Cycle and Slope Gain
Programming the Current Limit
The peak sense voltage threshold for the LTC3862 is 75mV
at low duty cycle and with a normalized slope gain of
1.00, and is measured from SENSE+ to SENSE–. Figure 21
illustrates the change in the sense threshold with varying
duty cycle and slope gain.
The average power dissipated in the sense resistor can
easily be calculated as:
PI
nD R
RSENSE
OMAX
MAX
SEN()
()
.•
•– •=
()
13
1
2
SSE MAX
D•
This equation assumes no temperature coefficient for
the sense resistor. If the resistor chosen has a significant
temperature coefficient, then substitute the worst-case
high resistance value into the equation.
The resistor temperature can be calculated using the
equation:
TD = TA + PR(SENSE) • RTH(JA)
Selecting the Output Diodes
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is required. The
output diode in a boost converter conducts current during
the switch off-time. The peak reverse voltage that the diode
must withstand is equal to the regulator output voltage.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to the
peak inductor current:
In
I
D
DPEAK
OMAX
MAX
()
()
••
–
=+
1121
χ
Although the average diode current is equal to the output
current, in very high duty cycle applications (low VIN to
high VOUT) the peak diode current can be several times
higher than the average, as shown in Figure 22. In this
applicaTions inForMaTion
Figure 22. Diode Current Waveform for a
High Duty Cycle Application
For a boost converter where the current limit value is
chosen to be 30% higher than the maximum load current,
the peak current in the MOSFET and sense resistor is:
II n
I
SW MAXRSENSE
OMAX
() ()
(
••
.•
==+
112
13
χ))
–1D
MAX
The sense resistor value is then:
RVnD
SENSE
SENSEMAX MAX
=
()
+
()
•• –
.•
1
13 1
2
χ•• ()
IOMAX
Again, the factor n is the number of phases used, and χ
represents the percentage ripple current in the inductor.
The number 1.3 represents the factor by which the current
limit exceeds the maximum load current, IO(MAX). For
example, if the current limit needs to exceed the maxi-
mum load current by 50%, then the 1.3 factor should be
replaced with 1.5.
SW NODE
10V/DIV
INDUCTOR
CURRENT
2A/DIV
DIODE
CURRENT
2A/DIV
1µs/DIV 3862 F22
VIN = 6V
VOUT = 24V
DUTY CYCLE (%)
50
MAXIMUM CURRENT SENSE THRESHOLD (mV)
60
70
80
55
65
75
20 40 60 80
3862 F21
100100 30 50 70 90
SLOPE = 0.625
SLOPE = 1.66
SLOPE = 1
LTC3862
29
3862fc
For more information www.linear.com/LTC3862
case check the diode manufacturer’s data sheet to ensure
that its peak current rating exceeds the peak current in
the equation above. In addition, when calculating the
power dissipation in the diode, use the value of the for-
ward voltage (VF) measured at the peak current, not the
average output current. Excess power will be dissipated
in the series resistance of the diode, which would not be
accounted for if the average output current and forward
voltage were used in the equations. Finally, this additional
power dissipation is important when deciding on a diode
current rating, package type, and method of heat sinking.
To a close approximation, the power dissipated by the
diode is:
PD = ID(PEAK) • VF(PEAK) • (1 – DMAX)
The diode junction temperature is:
TJ = TA + PD • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
Once the proper diode has been selected and the circuit
performance has been verified, measure the temperature
of the power components using a thermal probe or infrared
camera over all operating conditions to ensure a good
thermal design.
Finally, remember to keep the diode lead lengths short
and to observe proper switch-node layout (see Board
Layout Checklist) to avoid excessive ringing and increased
dissipation.
Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct combination
of output capacitors for a boost converter application. The
effects of these three parameters on the output voltage
ripple waveform are illustrated in Figure 23 for a typical
boost converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ΔV. This percentage
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modified.
One of the key benefits of multi-phase operation is a re-
duction in the peak current supplied to the output capacitor
by the boost diodes. As a result, the ESR requirement
of the capacitor is relaxed. For a 1% contribution to the
total ripple voltage, the ESR of the output capacitor can
be determined using the following equation:
ESRV
I
COUT OUT
DPEAK
≤001.•
()
where:
In
I
D
DPEAK
OMAX
MAX
()
()
••
–
=+
1121
χ
The factor n represents the number of phases and the
factor χ represents the percentage inductor ripple current.
applicaTions inForMaTion
Figure 23. Switching Waveforms for a Boost Converter
SW1
50V/DIV
SW2
50V/DIV
1µs/DIVVIN = 10V
VOUT = 48V
500mA LOAD
3862 F23
VOUT
50mV/DIV
AC COUPLED
IL1 2A/DIV
IL2 2A/DIV
LTC3862
30
3862fc
For more information www.linear.com/LTC3862
For the bulk capacitance, which we assume contributes
1% to the total output ripple, the minimum required ca-
pacitance is approximately:
CI
nV f
OUT
OMAX
OUT
≥()
.•
••
001
For many designs it will be necessary to use one type of
capacitor to obtain the required ESR, and another type
to satisfy the bulk capacitance. For example, using a
low ESR ceramic capacitor can minimize the ESR step,
while an electrolytic capacitor can be used to supply the
required bulk C.
The voltage rating of the output capacitor must be greater
than the maximum output voltage, with sufficient derating
to account for the maximum capacitor temperature.
Because the ripple current in the output capacitor is a
square wave, the ripple current requirements for this ca-
pacitor depend on the duty cycle, the number of phases
and the maximum output current. Figure 24 illustrates the
normalized output capacitor ripple current as a function of
duty cycle. In order to choose a ripple current rating for
the output capacitor
, first establish the duty cycle range,
based on the output voltage and range of input voltage.
Referring to Figure 24, choose the worst-case high nor-
malized ripple current, as a percentage of the maximum
load current.
The output ripple current is divided between the various
capacitors connected in parallel at the output voltage.
Although ceramic capacitors are generally known for low
ESR (especially X5R and X7R), these capacitors suffer
from a relatively high voltage coefficient. Therefore, it is
not safe to assume that the entire ripple current flows in
the ceramic capacitor. Aluminum electrolytic capacitors are
generally chosen because of their high bulk capacitance,
but they have a relatively high ESR. As a result, some
amount of ripple current will flow in this capacitor. If the
ripple current flowing into a capacitor exceeds its RMS
rating, the capacitor will heat up, reducing its effective
capacitance and adversely affecting its reliability. After
the output capacitor configuration has been determined
using the equations provided, measure the individual ca-
pacitor case temperatures in order to verify good thermal
performance.
Input Capacitor Selection
The input capacitor voltage rating in a boost converter
should comfortably exceed the maximum input voltage.
Although ceramic capacitors can be relatively tolerant of
overvoltage conditions, aluminum electrolytic capacitors
are not. Be sure to characterize the input voltage for any
possible overvoltage transients that could apply excess
stress to the input capacitors.
The value of the input capacitor is a function of the
source impedance, and in general, the higher the source
impedance, the higher the required input capacitance.
The required amount of input capacitance is also greatly
affected by the duty cycle. High output current applica-
tions that also experience high duty cycles can place great
demands on the input supply, both in terms of DC current
and ripple current.
The input ripple current in a multi-phase boost converter
is relatively low (compared with the output ripple current),
because this current is continuous and is being divided
between two or more inductors. Nonetheless, significant
stress can be placed on the input capacitor, especially
applicaTions inForMaTion
Figure 24. Normalized Output Capacitor
Ripple Current (RMS) for a Boost Converter
0.1
IORIPPLE/IOUT
0.9
3862 F24
0.3 0.5 0.7 0.8
0.2 0.4 0.6
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
DUTY CYCLE OR (1-VIN/VOUT)
1-PHASE
2-PHASE
LTC3862
31
3862fc
For more information www.linear.com/LTC3862
Figure 25. Normalized Input Peak-to-Peak Ripple Current
in high duty cycle applications. Figure 25 illustrates the
normalized input ripple current, where:
IV
Lf
NORM IN
=
•
applicaTions inForMaTion
3. The minimum on-time for this application operating
in CCM is:
tf
VVV
VV k
ON MIN
OFIN MAX
OF
()
()
•–
=+
+
=
11
300 HHz
VVV
VV ns
•
.–
.
48 05 36
48 05 859
+
+
=
The maximum DC input current is:
II
D
AA
IN MAX
OMAX
MAX
()
()
––..== =
1
5
10505 10 1
4. A ripple current of 40% is chosen so the peak current
in each inductor is:
In
I
D
IN PK
OMAX
MAX
()
()
•– •–
•.
=
=+
1121
1
210
χ
44
2
5
10505 606
=•–. .
AA
5. The inductor ripple current is:
∆In
I
D
AA
L
OMAX
MAX
== =
χ•–
.•–. .
()
1
04
2
5
10505 202
6. The inductor value is therefore:
LV
If
DV
AkHz
IN MIN
LMAX
==
=
()
••.• •.
∆
24
202300 0505
220µH
7. For a current limit value 30% higher than the maximum
load current:
IO(CL) = 1.3 • IO(MAX) = 1.3 • 5A = 6.5A
A Design Example
Consider the LTC3862 application circuit is shown in Fig-
ure 26a. The output voltage is 48V and the input voltage
range is 5V to 36V. The maximum output current is 5A
when the input voltage is 24V to 36V
. Below 24V, current
limit will linearly reduce the maximum load to 1A at 5V
in (see Figure 26b).
1. The duty cycle range (where 5A is available at the
output) is:
DVVV
VV
VVV
V
MAXOFIN
OF
=+
+
=+
+
–
.–48 05 24
48 0..
.%
.–
.
550 5
48 05 36
48 05
V
DVVV
VV
MIN
=
=+
+
=25 8.%
2. The operating frequency is chosen to be 300kHz so
the period is 3.33μs. From Figure 6, the resistor from
the FREQ pin to ground is 45.3k.
DUTY CYCLE
0
∆IIN/INORM
1.00
0.90
0.80
0.60
0.70
0.50
0.40
0.30
0.20
0.10
00.8
3862 F25
0.2 0.4 0.6 1.0
1-PHASE
2-PHASE
LTC3862
32
3862fc
For more information www.linear.com/LTC3862
applicaTions inForMaTion
Figure 26a. A 5V to 36V Input, 48V/5A Output 2-Phase Boost Converter Application Circuit
Figure 26b. Output Current vs Input Voltage
The saturation current rating of the inductors must
therefore exceed:
In
I
D
LSAT
OMAX
MAX
()
()
••
.•
–
•
≥+
=
112
13
1
1
2
χ
11 04
2
13 5
10505 79+
=
.•.•
–. .
AA
The inductor value chosen was 18.7μH and the part
number is PB2020-223, manufactured by Pulse Engi-
neering. This inductor has a saturation current rating
of 20A.
8. The power MOSFET chosen for this application is
a Renesas HAT2266H. This MOSFET has a typical
RDS(ON) of 11mΩ at VGS = 4.5V and 9.2mΩ at VGS
= 10V. The BVDSS is rated at a minimum of 60V and
the maximum continuous drain current is 30A. The
typical gate charge is 25nC for a VGS = 4.5V. Last but
not least, this MOSFET has an absolute maximum
avalanche energy rating EAS of 34mJ, indicating that
it is capable of avalanche without catastrophic failure.
9. The total IC quiescent current, IC power dissipation
and maximum junction temperature are approximately:
IQ(TOT) = IQ + 2 • QG(TOT) • f
= 3mA + 2 • 25nC • 300kHz = 18mA
PDISS = 24V • 18mA = 432mW
TJ = 70°C + 432mW • 34°C/W = 84.7°C
INPUT VOLTAGE (V)
0
1
0
OUTPUT LOAD CURRENT (A)
2
3
4
5
6
10 20 30 40
3862 F26b
SENSE1+
3V8
SLOPE
BLANK
CLKOUT
SYNC
PLLFLTR
PHASEMODE
DMAX
10nF
SENSE1–
SENSE2–
SENSE2+
RUN
FREQ
SS VIN
45.3k 24.9k
84.5k
10Ω
VIN
5V TO 36V D1
30BQ060
D2
30BQ060
10Ω
L2
18.7µH
PB2020-223
ITH
SGND
VOUT
12.4k
FB
30.1k
475k
10nF 1µF
1nF
6.8µF 50V
0.008Ω
1W
Q1
HAT2266H
Q2
HAT2266H
0.008Ω
1W
VOUT
48V
5A (MAX)
3862 F26a
100µF
63V
100µF
63V
6.8µF 50V
6.8µF 50V
10µF ×4 50V
LTC3862
4.7nF
100pF INTVCC
GATE1
GATE2
PGND
4.7µF
10nF
10µF ×4 50V
10µF ×4 50V
10µF ×4 50V
L1
18.7µH
PB2020-223
+
+
LTC3862
33
3862fc
For more information www.linear.com/LTC3862
10. The inductor ripple current was chosen to be 40%
and the maximum load current is 5A. For a current
limit set at 30% above the maximum load current, the
maximum switch and sense resistor currents are:
II n
I
SW MAXRSENSE
OMAX
() ()
(
••
.•
==+
112
13
χ))
–
•.•.•
–. .
1
1
2104
2
13 5
10505 79
D
AA
MAX
=+
=
11. The maximum current sense threshold for the LTC3862
is 75mV at low duty cycle and a normalized slope gain
of 1.0. Using Figure 21, the maximum sense voltage
drops to 73mV at a duty cycle of 51% with a normalized
slope gain of 1, so the sense resistor is calculated to
be:
RV
I
mV
Am
SENSE
SENSEMAX
SW MAX
===
()
() ..
73
79 92 Ω
For this application a 8mΩ, 1W surface mount resistor
was used for each phase.
12. The power dissipated in the sense resistors in current
limit is:
PI
nD R
RSENSE
OMAX
MAX
SEN()
()
.•
•– •=
()
13
1
2
SSE MAX
D•
.•
•–.•. •.=
()
13 5
210505 0009 050
2
55
020=.W
13. The average current in the boost diodes is half the
output current (5A/2 = 2.5A), but the peak current in
each diode is:
In
I
D
DPEAK
OMAX
MAX
()
()
••
–
•
=+
=+
1121
1
210
χ
.. •–. .
4
2
5
10505 606
=
AA
The diode chosen for this application is the 30BQ060,
manufactured by International Rectifier. This surface
mount diode has a maximum average forward current
of 3A at 125°C and a maximum reverse voltage of 60V.
The maximum forward voltage drop at 25°C is 0.65V
and is 0.42V at 125°C (the positive TC of the series
resistance is compensated by the negative TC of the
diode forward voltage).
The power dissipated by the diode is approximately:
PD = ID(PEAK) • VF(PEAK) • (1 – DMAX)
= 6.06A • 0.42V • (1 – 0.505) = 1.26W
14.
Two types of output capacitors are connected in parallel
for this application; a low ESR ceramic capacitor and
an aluminum electrolytic for bulk storage. For a 1%
contribution to the total ripple voltage, the maximum
ESR of the composite output capacitance is approxi-
mately:
ESRV
I
V
A
COUT OUT
DPEAK
≤==
00100148
44 010
.• .•
..
()
99Ω
For the bulk capacitance, which we assume contributes
1% to the total output ripple, the minimum required
capacitance is approximately:
CI
nV f
A
Vk
OUT
OMAX
OUT
≥=
()
.•••.•••001
5
0012 48 300 HHz T
µF=17 5.
For this application, in order to obtain both low ESR
and an adequate ripple current rating (see Figure 24),
two 100μF, 63V aluminum electrolytic capacitors were
connected in parallel with four 6.8μF, 50V ceramic
capacitors. Figure 27 illustrates the switching wave-
forms for this application circuit.
applicaTions inForMaTion
LTC3862
34
3862fc
For more information www.linear.com/LTC3862
5. Place the INTVCC decoupling capacitor as close as
possible to the INTVCC and PGND pins, on the same
layer as the IC. A low ESR (X5R or better) 4.7μF to
10μF ceramic capacitor should be used.
6. Use a local via to ground plane for all pads that
connect to the ground. Use multiple vias for power
components.
7. Place the small-signal components away from high
frequency switching nodes on the board. The pinout
of the LTC3862 was carefully designed in order to
make component placement easy. All of the power
components can be placed on one side of the IC, away
from all of the small-signal components.
8. The exposed area on the bottom of the QFN package
is internally connected to PGND; however it should
not be used as the main path for high current flow.
9. The MOSFETs should also be placed on the same
layer of the board as the sense resistors. The MOSFET
source should connect to the sense resistor using a
short, wide PCB trace.
10. The output resistor divider should be located as
close as possible to the IC, with the bottom resistor
connected between FB and SGND. The PCB trace
connecting the top resistor to the upper terminal of
the output capacitor should avoid any high frequency
switching nodes.
11. Since the inductor acts like a current source in a peak
current mode control topology, its placement on the
board is less critical than the high di/dt components.
12. The SENSE+ and SENSE– PCB traces should be
routed parallel to one another with minimum spacing
in between all the way to the sense resistor. These
traces should avoid any high frequency switching
nodes in the layout. These PCB traces should also be
Kelvin-connected to the interior of the sense resistor
pads, in order to avoid sensing errors due to parasitic
PCB resistance IR drops.
applicaTions inForMaTion
Figure 27. LTC3862 Switching Waveforms for Boost Converter
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the converter:
1. For lower power applications a 2-layer PC board
is sufficient. However, for higher power levels, a
multilayer PC board is recommended. Using a solid
ground plane and proper component placement under
the circuit is the easiest way to ensure that switching
noise does not affect the operation.
2. In order to help dissipate the power from the MOS-
FETs and diodes, keep the ground plane on the layers
closest to the power components. Use power planes
for the MOSFETs and diodes in order to maximize the
heat spreading from these components into the PCB.
3. Place all power components in a tight area. This will
minimize the size of high current loops. The high di/
dt loops formed by the sense resistor, power MOSFET,
the boost diode and the output capacitor should be
kept as small as possible to avoid EMI.
4. Orient the input and output capacitors and current
sense resistors in a way that minimizes the distance
between the pads connected to the ground plane.
Keep the capacitors for INTVCC, 3V8 and VIN as close
as possible to LTC3862.
SW1
50V/DIV
SW2
50V/DIV
2.5µs/DIVVIN = 24V
VOUT = 48V, 1.5A
3862 F27
VOUT
100mV/DIV
AC COUPLED
IL1
5A/DIV
IL2
5A/DIV
LTC3862
35
3862fc
For more information www.linear.com/LTC3862
applicaTions inForMaTion
13. If an external RC filter is used between the sense
resistor and the SENSE+ and SENSE– pins, these filter
components should be placed as close as possible to
the SENSE+ and SENSE– pins of the IC. Ensure that
the SENSE– line is connected to the ground only at the
point where the current sense resistor is grounded.
14. Keep the MOSFET drain nodes (SW1, SW2) away
from sensitive small-signal nodes, especially from
the opposite channel’s current-sensing signals. The
SW nodes can have slew rates in excess of 1V/ns
relative to ground and should therefore be kept on
the “output side” of the LTC3862.
15. Check the stress on the power MOSFETs by inde-
pendently measuring the drain-to-source voltages
directly across the devices terminals. Beware of
inductive ringing that could exceed the maximum
voltage rating of the MOSFET. If this ringing cannot
be avoided and exceeds the maximum rating of the
device, choose a higher voltage rated MOSFET or
consider using a snubber.
16. When synchronizing the LTC3862 to an external clock,
use a low impedance source such as a logic gate to
drive the SYNC pin and keep the lead as short as
possible.
LTC3862
36
3862fc
For more information www.linear.com/LTC3862
Typical applicaTions
A 12V Input, 24V/5A Output 2-Phase Boost Converter Application Circuit
Start-Up Load Step
ILOAD
5A/DIV
IL1
5A/DIV
IL2
5A/DIV
VOUT
500mV/DIV
500µs/DIV 3862 TA02c
VIN = 12V
VOUT = 24V
ILOAD = 2A TO 5A
LOAD CURRENT (mA)
EFFICIENCY (%)
POWER LOSS (mW)
100
95
90
3862 TA02d
75
10000
1000
100
85
80
10000
100 1000
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = 24V
Efficiency
RUN
5V/DIV
IL1
5A/DIV
IL2
5A/DIV
VOUT
20V/DIV
1ms/DIV 3862 TA02b
VIN = 12V
VOUT = 24V
ILOAD = 5A
SENSE1+
3V8
SLOPE
BLANK
CLKOUT
SYNC
PLLFLTR
PHASEMODE
DMAX
10nF
SENSE1–
SENSE2–
SENSE2+
RUN
FREQ
SS VIN
45.3k 15k
100k
10Ω
VIN
5V TO 24V D1
MBRD835L
D2
MBRD835L
10Ω
L2
4.2µH
CDEP145-4R2
ITH
SGND
VOUT
6.98k
FB
26.7k
130k
10nF 1µF
1nF
22µF 25V
0.007Ω
1W
Q1
Si7386DP
Q2
Si7386DP
0.007Ω
1W
VOUT
24V
5A (MAX)
3862 TA02a
100µF
35V
100µF
35V
22µF 25V
22µF 25V
10µF 50V
LTC3862
1nF
100pF INTVCC
GATE1
GATE2
PGND
4.7µF
10nF
10µF 50V
10µF 50V
10µF 50V
L1
4.2µH
CDEP145-4R2
+
+
LTC3862
37
3862fc
For more information www.linear.com/LTC3862
Typical applicaTions
A 4.5V to 5.5V Input, 12V/15A Output 4-Phase Boost Converter Application Circuit
VIN
5V/DIV
IL1 MASTER
5A/DIV
IL2 MASTER
5A/DIV
IL1 SLAVE
5A/DIV
IL2 SLAVE
5A/DIV
VOUT
10V/DIV
1ms/DIV 3862 TA03b
VIN = 5V
VOUT = 12V
RLOAD = 10Ω
ILOAD
2.5A-5A
5A DIV
IL1 MASTER
5A/DIV
IL2 MASTER
5A/DIV
IL1 SLAVE
5A/DIV
IL2 SLAVE
5A/DIV
VOUT
200mV/DIV
250µs/DIV 3862 TA03c
VIN = 5V
VOUT = 12V
LOAD CURRENT (mA)
100
80
EFFICIENCY (%)
POWER LOSS (mW)
90
100
1000 10000 100000
3862 TA03d
70
75
85
95
65
60
10000
100000
1000
100
EFFICIENCY
POWER LOSS
VIN = 5V
VOUT = 12V
Start-Up Load Step Efficiency
SENSE1+
3V8
SLOPE
BLANK
CLKOUT
SYNC
PLLFLTR
PHASEMODE
DMAX
10nF ON/OFF
CONTROL
SENSE1–
SENSE2–
SENSE2+
RUN
FREQ
SS VIN
45.3k
10Ω
VIN
4.5V TO 5.5V D1
MBRB2515LT41
D2
MBRB2515LT41
10Ω
L2
2.7µH
CDEP145-2R7
ITH
SGND
VOUT
18.7k
FB
3.83k
165k
10nF 1µF
1nF
33µF 10V
33µF 10V
33µF 10V
0.005Ω
1W
Q1
HAT2165H
Q3
HAT2165H
0.005Ω
1W
VOUT
12V
15A
220µF
16V
220µF
16V
LTC3862
10nF
330pF INTVCC
GATE1
GATE2
PGND
4.7µF
10nF
15µF 25V
15µF 25V
15µF 25V
15µF 25V
L1
2.7µH
CDEP145-2R7
+
+
SENSE1+
3V8
SLOPE
BLANK
CLKOUT
SYNC
PLLFLTR
PHASEMODE
DMAX
10nF
SENSE1–
SENSE2–
SENSE2+
RUN
FREQ
SS VIN
45.3k
10Ω
D1
MBRB2515LT41
D2
MBRB2515LT41
10Ω
L2
2.7µH
CDEP145-2R7
ITH
SGND
FB
10k
1µF
1nF
33µF 10V
33µF 10V
33µF 10V
0.005Ω
1W
Q1
HAT2165H
Q3
HAT2165H
0.005Ω
1W
3862 TA03a
220µF
16V
220µF
16V
LTC3862
10nF
INTVCC
GATE1
GATE2
PGND
4.7µF
330pF
10nF
15µF 25V
15µF 25V
15µF 25V
15µF 25V
L1
2.7µH
CDEP145-2R7
+
+
LTC3862
38
3862fc
For more information www.linear.com/LTC3862
FE24 (AA) TSSOP REV B 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12
14 13
7.70 – 7.90*
(.303 – .311)
3.25
(.128)
2.74
(.108)
2021222324 19 18 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.25
(.128)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev B)
Exposed Pad Variation AA
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3862
39
3862fc
For more information www.linear.com/LTC3862
.337 – .344*
(8.560 – 8.738)
GN24 REV B 0212
1 2 345678 9 10 11 12
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
161718192021222324 15 1413
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) × 45°
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3862
40
3862fc
For more information www.linear.com/LTC3862
UH Package
24-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1747 Rev A)
5.00 ± 0.10
5.00 ± 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.55 ± 0.10
23
1
2
24
BOTTOM VIEW—EXPOSED PAD
3.25 REF
3.20 ± 0.10
3.20 ± 0.10
0.75 ± 0.05 R = 0.150
TYP
0.30 ± 0.05
(UH24) QFN 0708 REV A
0.65 BSC
0.200 REF
0.00 – 0.05
0.75 ±0.05
3.25 REF
3.90 ±0.05
5.40 ±0.05
0.30 ± 0.05
PACKAGE OUTLINE
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 × 45°
CHAMFER
R = 0.05
TYP
3.20 ± 0.05
3.20 ± 0.05
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3862
41
3862fc
For more information www.linear.com/LTC3862
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
C 12/13 Added Comparison table
Added Note 9
Added pin number registers
1
4
9
(Revision history begins at Rev C)
LTC3862
42
3862fc
For more information www.linear.com/LTC3862
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2008
LT 1213 REV C • PRINTED IN USA
SENSE1+
3V8
SLOPE
BLANK
CLKOUT
SYNC
PLLFLTR
PHASEMODE
DMAX
10nF
SENSE1–
SENSE2–
SENSE2+
RUN
FREQ
SS VIN
45.3k 15k
100k
10Ω
VIN
5V TO 24V D1
MBRD835L
D2
MBRD835L
10Ω
L2
4.2µH
CDEP145-4R2
ITH
SGND
VOUT
6.98k
FB
26.7k
130k
10nF 1µF
1nF
22µF 25V
0.007Ω
1W
Q1
Si7386DP
Q2
Si7386DP
0.007Ω
1W
VOUT
24V
5A (MAX)
3862 TA04
100µF
35V
100µF
35V
22µF 25V
22µF 25V
10µF 50V
LTC3862
1nF
100pF INTVCC
GATE1
GATE2
PGND
4.7µF
10nF
10µF 50V
10µF 50V
10µF 50V
L1
4.2µH
CDEP145-4R2
+
+
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC3787/
LTC3787-1
Single Output, Dual Channel Multiphase Synchronous
Step-Up Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to
900kHz Operating Frequency, 4mm × 5mm QFN-28, SSOP-28
LTC3788-1 Dual Output, Multiphase Synchronous Step-Up
Controller
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to
900kHz Fixed Frequency, 5mm × 5mm QFN-32, SSOP-28
LTC3786 Low IQ Synchronous Step-Up Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 50kHz to
900kHz Fixed Operating Frequency, 3mm × 3mm QFN-16, MSOP-16E
LT3757A Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages
LTC3859AL Low IQ, Triple Output Buck/Buck/Boost Synchronous
DC/DC Controller
All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to 2.5V
After Start-Up) ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V,
IQ = 28μA
LTC3789 High Efficiency Synchronous 4-Switch Buck-Boost
DC/DC Controller
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, 4mm × 5mm QFN-28, SSOP-28
A 12V Input, 24V/5A Output 2-Phase Boost Converter Application Circuit