1
®
FN2954.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HD-4702
CMOS Programmable Bit Rate Generator
The HD-4702 Bit R ate Generator provides the nece ssa ry
clock signals for digital dat a transmission systems, such as a
UART. It generates 13 commonly used bi t rates using an on-
chip crysta l o s ci ll ator or an external in pu t. Fo r co nventional
operation gen era t in g 1 6 o utp ut clock pulses per bi t pe rio d,
the input clock freque ncy mu st be 2.4576MHz (i .e . 96 00
Baud x 16 x 1 6, since there is an internal ³ 16 prescaler). A
lower input frequency will result in a proportionally lower
output frequency.
The HD-4702 ca n provide multi-channel operation w ith a
minimum of external l ogi c by h aving the clock frequency CO
and the ³ 8 prescaler outputs Q0, Q1, Q2 available externally .
All signals have a 50% duty cycle except 1800 Baud, w hi ch
has less than 0.39% distortion.
The four rate sele ct in pu ts (S0-S3) select which bit ra te is at
the output (Z). See Truth Table for Rate Select Inputs for
select code and output bit rate. Two of the 16 select codes for
the HD-4702 do not select an internally generated frequency,
but select an in put into which the user ca n fe ed either a
different frequency , or a static level (High or Low) to generate
“ZERO BAUD”.
The bit rate s mo st commonly used in modern dat a terminals
(110, 150, 300, 1200, 2400 Baud) requir e th at no more than
one input be grounded for the HD-4702, which is easily
achieved wi th a single 5-position swi tch.
The HD-4702 h as a n i nit ia li zati on circui t w hi ch ge ne rate s a
master reset for the scan counter. This signal is derived from
a digit al differenti ato r tha t sen s es th e fi rst high level on the
CP input after the ECP inp ut go es low. When ECP is high,
selecting the crystal input, CP must be low. A high level on
CP would apply a continuous reset. See Clock Modes and
Initialization below.
Features
• HD-4702 Provides 13 Commonly Used Bit Rates
• Uses a 2.4576MHz Crystal/Input for Standard Frequency
Output (16 Times Bit Rate)
• Low Power Dissipation
• Conforms to EIA RS-404
• One HD-4702 Controls up to Eight Transmission
Channels
• Initialization Circuit Facilitates Diagnostic Fault Isolation
• On-Chip Input Pull-Up Circuit
Truth Table Pinout
HD-4702 (16 Ld PDIP)
TOP VIEW
Ordering Information
PACKAGE
TEMP.
RANGE
(oC) PART
NUMBER PART
MARKING PKG.
NO.
PDIP -40 to +85 HD3-4702-9 HD3-4702-9 E16.3
PDIP
(Pb-free) -40 to +85 HD3-4702-9Z* HD3-4702-9Z E16.3
CerDIP
SMD# -55 to +125 5962-9051801MEA F16.3
*Pb-free PDIPs can be used for through hole wave solder
processing only. Th ey are not intended for use in Reflow solder
processing applications.
TRUTH TABLE FOR RATE SELECT INPUTS
(Using 2.4576MHz Crystal)
S3 S2 S1 S0 OUTPUT RATE (Z)
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
MUX Input (IM)
MUX Input (IM)
50 Baud
75 Baud
134.5 Baud
200 Baud
600 Baud
2400 Baud
9600 Baud
4800 Baud
1800 Baud
1200 Baud
2400 Baud
300 Baud
150 Baud
110 Baud
NOTE: 19200 Baud by connecting Q2 to IM.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q0
Q1
Q2
ECP
CP
OX
GND
IX
VCC
S0
S1
S2
S3
Z
CO
IM
Data Sheet August 24, 2006
2FN2954.2
August 24, 2006
Pin Description
PIN NUMBER TYPE SYMBOL DESCRIPTION
16 VCC VCC: Is the +5V power supply pin. A 0.1μF capacitor between pins 16 and 8 is
recommended for decoupling.
8GNDGROUND
5 I CP EXTERNAL CLOCK INPUT
4IE
CP EXTERNAL CLOCK ENABLE: A low signal on this input allows the baud rate to be
generated from the CP input.
7II
XCRYSTAL INPUT
6OO
XCRYSTAL DRIVE OUTPUT
15 I IMMULTIPLEXED INPUT
11, 12, 13, 14 I S0 - S3 BAUD RATE SELECT INPUTS
9 O CO CLOCK OUTPUT
1, 2, 3 O Q0 - Q2SCAN COUNTER OUTPUTS
10 O Z BIT RATE OUTPUT
CLOCK MODES AND INITIALIZATION
IX ECP CP OPERATION
H L Clocked from IX
X L Clocked from CP
X H H Continuous Reset
X L Reset During 1st CP = High
Time
H = HIGH Level
L = LOW Level
X = Don’t Care
= Clock Pulse
= 1st HIGH Level Clock Pulse after ECP goes LOW
NOTE: Actual output frequency is 16 times the indicated Output
Rate, assuming a clock frequency of 2.4576MHz.
HD-4702
3FN2954.2
August 24, 2006
Block Diagram
OSCILLATOR
CIRCUIT
IX
10
7
6
4
5
OX
CO
INITIALIZATION
CP
ECP
DQ
FF
CP Q
MR
CIRCUIT
MR
9
Q0Q1Q2
1 2 3
=
PIN 16VDD
VSS PIN 8
PIN NUMBER
=
=
SCAN
COUNTER
CP
MR
9600
4800
2400
1200
600
300
150
75
0
IM
Z
COUNTER NETWORK MULTIPLEXER
15 14 13 12 11
S0 S1 S2 S3
CP 8
MR ÷
DQ
FF
CP
MR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
50
75
134.5
200
600
2400
9600
4800
1800
1200
2400
300
150
110
CP 4
÷Q
MR
CP 18
÷Q
MR
CP 6
÷Q
MR
CP 16/3
÷ Q
MR
CP 22
÷Q
MR
(NOTE)
NOTE: See Figure 4 in Design Information for Crystal Specifications.
HD-4702
4FN2954.2
August 24, 2006
Application Information
Single Channel Bit Rate Generator
Figure 1 shows the simplest application of the HD-4702. This
circuit generates one of five possible bit rates as determined by
the setting of a single pole, 5-position switch. The Bit Rate Out-
put (Z) drives one standard TTL load or four low power Schot-
tky loads over the full temperature range. The possible output
frequencies correspond to 110, 150, 300, 1200, and 2400
Baud. For many low cost terminals, these five bit rates are ade-
quate.
FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR
CONFIGURATION PROVIDING FIVE BIT RATES
Simultaneous Generation of Several Bit Rates
Figure 2 shows a simple scheme that g enerates eight bit rates
on eight output lines, using one HD-4702 and one 93L34 Bit
Addressable Latch. This and the following applications take
advantage of the built-in scan counter (prescaler) outputs. As
shown in the block diagram, these outputs (Q0 to Q2) go
through a complete sequence of eight states for every half-
period of the highest output frequency (9600 Baud). Feeding
these Scan Counter Outputs back to the Select Inputs of the
multiplexer causes the HD-4702 to interrogate sequentially
eight different frequency signals. The 93L34 8-bit addressable
Latch, addressed by the same Scan Counter Outputs, re-con-
verts the multiplexed single Output (Z) of the HD-4702 into
eight parallel output frequency signals. In the simple scheme of
Figure 2, input S3 is left open (HIGH) and the following bit rates
are generated:
Other bit rate combinations can be generate d by changing the
Scan Counter to Selector interconnection or by inserting logic
gates into this path.
19200 Baud Operation
Though a 19200 Baud signal is not internally routed to the mul-
tiplexer, the HD-4702 can be used to generate this bit rate by
connecting the Q2 output to IM input and applying select code.
An additional 2-input NOR gate can be used to retain the “Zero
Baud” feature on select code 1 for the HD-4702 (See Figure 3).
SWITCH POSITION HD-4702 BIT RATE
1 110 Baud
2 150 Baud
3 300 Baud
4 1200 Baud
5 2400 Baud
Q0: 110 Baud Q1: 9600 Baud Q2: 4800 Baud
Q3: 1800 Baud Q4: 1200 Baud Q5: 2400 Baud
Q6: 300 Baud Q7: 150 Baud
HD-4702
IMS0 S1 S2 S3
CP
ECP
IX
OXCOQ0Q1Q2Z
OUTPUT
SPST SWITCH
2.4576 MHz
CRYSTAL
†
10M
56pF
56pF
2
1
34
5
†See Table 1.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETERS TYPICAL CRYSTAL SPEC
Frequency 2.4576MHz “AT” Cut
Series Resistance (Max) 250
Unwanted Modes -6.0dB (Min)
Type of Operation Parallel
Load Capacitance 32pF +0.5
HD-4702
IMS0 S1 S2 S3
CP
ECP
IX
OXCOQ0Q1Q2Z
2.4576 MHz
CRYSTAL
†
10M
56pF
56pF
CL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A0
A1
A2
9600
110
4800
1800
1200
2400
300
150
93L34
ED
†See Table 1.
FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH
EIGHT SIMULTANEOUS FREQUENCIES
HD-4702
IMS0 S1 S2 S3
CP
ECP
IX
OXCOQ0Q1Q2Z
OUTPUT
2.4576 MHz
CRYSTAL
†
10M
56pF
56pF
†See Table 1.
FIGURE 3. 19200 BAUD OPERATION
HD-4702
5FN2954.2
August 24, 2006
Absolute Maximum Ratings Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Resistance (Typical) θJA θJC
CERDIP Package. . . . . . . . . . . . . . . 78oC/W 23oC/W
PDIP Package . . . . . . . . . . . . . . . . . 90oC/W N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .+300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .720 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V Operating Temperature Range
HD-4702-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
HD-4702-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8)
SYMBOL PARAMETER
LIMITS
UNITS TEST CONDITIONSMIN MAX
VIH Input High Voltage VCC 70% - V VCC = 4.5V
VIL Input Low Voltage - VCC 30% V VCC = 4.5V
VOH1 Output High Voltage VCC -0.1 - V IOH ≤ -1μA, VCC = 4.5V, (Note 1)
VOL1 Output Low Voltage - 0.1 V IOL ≤ +1μA, VCC = 4.5V, (Note 1)
IIH Input High Current -1 +1 μAV
IN = VCC, All 0ther Pins = 0V, VCC = 5.5V
IILX Input Low Current
(lX Input) -1 +1 μAV
IN = 0V, All Other Pins = VCC, VCC = 5.5V
IIL Input Low Current
(All Other Inputs) --100μAV
IN = 0V, All Other Pins = VCC, VCC = 5.5V
(Note 2)
IOHX Output High Current
(OX)-0.1 - mA VOUT = VCC - 0.5, VCC = 4.5V, Input at 0V
or VCC per Logic Function or Truth Table
IOH1 Output High Current
(All Other Outputs) -1.0 - mA VOUT = 2.5V, VCC = 4.5V, Input at 0V
or VCC per Logic Function or Truth Table
IOH2 Output High Current
(All Other Outputs) -0.3 - mA VOUT = VCC -0.5, VCC = 4.5V, Input at 0V
or VCC per Logic Function or Truth Table
IOLX Output Low Current
(OX)0.1 - mA VOUT = 0.4V, VCC = 4.5V, Input at 0V
or VCC per Logic Function or Truth Table
IOL Output Low Current
(All Other Outputs) 1.6 - mA VOUT = 0.4V, VCC = 4.5V Input, at 0V
or VCC per Logic Function or Truth Table
ICC Supply Current
(Static) - 1500 μAE
CP = VCC, CP = 0V, VCC = 5.5V,
All Other Inputs = GND, (Note 2)
- 1000 μAE
CP = VCC, CP = 0V, VCC = 5.5V,
All Other Inputs = VCC, (Note 2)
NOTES:
1. Interchanging of force and sense conditions is permitted.
2. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up cir cuits on all inputs
except IX.
HD-4702
6FN2954.2
August 24, 2006
Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8)
SYMBOL AC PARAMETER
LIMITS
UNITS TEST
CONDITIONSMIN MAX
tPLH Propagation Delay, IX to CO - 350 ns
VCC = 4.5V
CL ≤ 7pF on OX
CL = 50pF
(Note 1)
tPHL - 275 ns
tPLH Propagation Delay, CP to CO - 260 ns
tPHL - 220 ns
tPLH Propagation Delay, CO to Qn - (Note 2) ns
tPHL - (Note 2) ns
tPLH Propagation Delay, CO to Z - 85 ns
tPHL -75ns
tTLH Output Transition Time (Except OX) - 160 ns
tTHL -75ns
tsSet-Up Time, Select to CO 350 - ns
thHold Time, Select to CO 0 - ns
tsSet-Up Time, IM to CO 350 - ns
thHold Time, IM to CO 0 - ns
twCP(L) Minimum Clock Pulse Width, Low (Notes 3, 4) 120 - ns
twCP(H) Minimum Clock Pulse Width, High (Notes 3, 4) 120 - ns
twCP(L) M inimum IX Pulse Width, Low (Note 4) 160 - ns
twCP(H) Minimum IX Pulse Width, High (Note 4) 160 - ns
tPLH Propagation Delay IX to CO - 300 ns
VCC = 4.5V
CL ≤ 7pF on OX
CL = 15pF
(Note 1)
tPHL - 250 ns
tPLH Propagation Delay CP to CO - 215 ns
tPHL - 195 ns
tPLH Propagation Delay CO to Qn - (Note 2) ns
tPHL - (Note 2) ns
tPLH Propagation Delay CO to Z - 75 ns
tPHL -65ns
tTLH Output Transition Time (Except OX) - 80 ns
tTHL -40ns
NOTES:
1. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Cap acitance (CL). Setup T imes
(ts), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.
2. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be ≤ 367ns.
3. The first High Level Clock Pulse after ECP goes Low must be at least 350ns long to guarantee reset of all Counters.
4. It is recommended that input rise and fall times to the clock inputs (CP, IX) be less than 15ns.
HD-4702
7FN2954.2
August 24, 2006
Switching Waveforms
AC Testing Input, Output Waveform
Capacitance TA = +25oC ; Frequency = 1MHz
SYMBOL PARAMETER TYPICAL UNITS CONDITIONS
CIN Input Capacitance 7 pF All measurements are referenced the
device GND
COUT Output Capacitance 15 pF
50% 50% 50%
tW(H) tW(L)
50%
50%
tsth
CP/IX
CO
IM/SN
NOTE:
1. Setup and Hold times are shown as positive values but may be specified as negative values.
50%
VIL
VIH
INPUT
50% VOH
VOL
OUTPUT
NOTE:
1. AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt.
HD-4702
8FN2954.2
August 24, 2006
Dual-In-Line Plastic Packages (PDIP)
NOTES:
2. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
5. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
6. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
7. E and are measured with the leads constrained to be perpendic-
ular to datum .
8. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
9. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
10. N is the maximum number of terminal positions.
11. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
HD-4702
