©2008 Integrated Device Technology, Inc.
OCTOBER 2008
DSC-5648/3
1
Functional Block Diagram
Features:
◆True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆High-speed clock to data access
– Commercial: 6/7.5/9/12ns (max.)
– Industrial: 7.5ns (max.)
◆Low-power operation
– IDT70V9369L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
◆Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
◆Counter enable and reset features
◆Dual chip enables allow for depth expansion without
additional logic
◆Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
◆Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
◆LVTTL- compatible, single 3.3V (±0.3V) power supply
◆Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆Available in a 100-pin Thin Quad Flatpack (TQFP)
IDT70V9369L
0a 1a 0b 1b 0/1
ab
I/O
Control
1
0/1
0
FT
/PIPE
R
R/
W
R
UB
R
LB
R
CE
0R
OE
R
CE
1R
MEMORY
ARRAY
Counter/
Address
Reg.
5648 drw 01
A
13R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
I/O
9R
-I/O
17R
I/O
0R
-I/O
8R
A
0L
CLK
L
ADS
L
A
13L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
R/
W
L
UB
L
LB
L
CE
0L
OE
L
CE
1L
1
0/1
0
1b 0b 1a 0a
0/1 ba
I/O
Control
FT
/PIPE
L
HIGH-SPEED 3.3V 16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
100-Pin TQFP
Top View
(5)
A
9L
A
10L
A
11L
A
12L
A
13L
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
V
DD
FT/PIPE
L
I/O
16L
I/O
17L
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
5648 drw 02
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
NC
NC
LB
R
UB
R
CE
0R
CNTRST
R
R/W
R
V
SS
OE
R
FT/PIPE
R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
CE
1R
I/O
17R
V
SS
I/O
16R
I/O
15R
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
V
SS
Vss
ADS
R
CLK
R
CNTEN
R
A
0R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
I/O
9L
I/O
8L
V
DD
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
I/O
1L
V
SS
I/O
0L
I/O
4R
I/O
5R
I/O
6R
I/O
3R
I/O
0R
I/O
1R
I/O
2R
I/O
7R
I/O
8R
I/O
9R
I/O
10R
A
1R
.
70V9369PF
PN100-1
(4)
V
SS
V
SS
V
DD
01/09/02
Description:
The IDT70V9369 is a high-speed 16K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times.
Pin Configuration(1,2,3)
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
With an input data register, the IDT70V9369 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 500mW of power.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
3
NOTES:
1. "H" = VIH, "L" = V IL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table I—Read/Write and Enable Control(1,2,3)
Pin Names
Left Port Right Port Names
CE
0L,
CE
1L
CE
0R,
CE
1R
Chip E nab le s
(2)
R/W
L
R/W
R
Re ad/ Wri te E nab l e
OE
L
OE
R
Outp ut Enable
A
0L
- A
13L
A
0R
- A
13R
Address
I/O
0L
- I/ O
17L
I/O
0R
- I/ O
17R
Da ta Inp ut/ Outp u t
CLK
L
CLK
R
Clock
UB
L
UB
R
Up pe r Byte Selec t
(1)
LB
L
LB
R
Lowe r Byte Select
(1)
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Coun ter E n ab l e
CNTRST
L
CNTRST
R
Co un ter Res e t
FT/PIPE
L
FT/PIPE
R
Flow-Through / Pipeline
V
DD
Power (3.3V)
V
SS
Gro und (0V)
5648 t bl 01
OE CLK CE
0
CE
1
UB LB R/WUpp er By te
I/O
9-17
(4)
Lower Byte
I/O
0-8
(5)
MODE
X↑H X X X X Hi g h- Z Hi g h-Z De s e le c te d –Po we r Do wn
X↑X L X X X Hi g h- Z Hi g h-Z De s e le c te d –Po we r Do wn
X↑L H H H X Hi g h- Z Hi g h-Z Bo th B y te s De se l e cte d
X↑LHLHL DATA
IN
High-Z Write to Upper Byte Only
X↑LHHLL High-Z DATA
IN
Wri te to Lowe r B y te O nly
X↑LHLLL DATA
IN
DATA
IN
Wri te to B o th B y te s
L↑LHLHH DATA
OUT
Hi g h-Z Re ad Up p e r B y te On ly
L↑LHHLH High-Z DATA
OUT
Re ad Lo w er B y te On ly
L↑LHLLH DATA
OUT
DATA
OUT
Re ad Both Bytes
H X L H L L X Hig h-Z Hi gh-Z Outp uts Dis ab le d
5648 tb l 02
NOTES:
1. LB and UB are single buffered regardless of state of FT/PIPE.
2. CE0 and CE1 are single buffered when FT/PIPE = VIL,
CE0 and CE1 are double buffered when FT/PIPE = VIH, i.e., the signals
take two cycles to deselect.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
Recommended Operating
Temperature and Supply Voltage(1) Recommended DC Operating
Conditions
Absolute Maximum Ratings(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Truth Table II—Address Counter Control(1,2,6)
NOTES:
1. "H" = VIH, "L" = V IL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD +0.3V.
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip deselect.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Address
Previous
Internal
Address
Internal
Address
Used CLK
(6
)
ADS CNTEN CNTRST I/O
(3)
MODE
An X An ↑ L
(4)
XHD
I/O
(n) Exte rnal Address Used
XAnAn + 1
↑H L
(5)
HD
I/O
(n+1) Counter Enab led—Inte rnal Addres s g eneration
XAn + 1An + 1
↑HH HD
I/O
(n+1) External Address Blocked—Counter disabled (An + 1 reused)
XXA
0
↑XX L
(4)
D
I/O
(0) Counter Reset to Address 0
5648 tb l 03
Grade Ambient
Temperature
(1)
GND V
DD
Commercial 0
O
C to + 70
O
C0V3.3V
+
0. 3V
Industrial -40
O
C to + 85
O
C0V 3.3V
+
0. 3V
5648 tb l 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Sup ply Vo ltage 3.0 3.3 3.6 V
Vss Ground 0 0 0 V
V
IH
Input High Voltage 2.0V
____
V
DD
+0.3V
(2)
V
V
IL
Inp ut Lo w Vo ltag e -0. 3
(1)
____
0.8 V
5648 tbl 05
Symbol Rating Commercial
& Industrial Unit
V
TERM
(2)
Te rminal Vo ltage
with Re s pe c t to
GND
-0. 5 to + 4. 6 V
T
BIAS
(3)
Temperature
Und e r B ias -55 to + 125
o
C
T
STG
Storage
Temperature -65 to +150
o
C
T
JN
Junction Temperature +150
o
C
I
OUT
DC Outp ut Curre nt 50 mA
5648 tb l 06
Symbol Parameter Conditions Max. Unit
C
IN
Inp ut Cap ac itan ce V
IN
= 0V 9 pF
C
OUT
(2)
Ou tp ut Ca p ac i tance V
OUT
= 0V 10 pF
5648 tbl 07
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
NOTE:
1. At VDD < 2.0V input leakages are undefined.
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
Symbol Parameter Test Conditions
70V9369L
UnitMin. Max.
|I
LI
| Input Le a k ag e Curr e nt
(1)
V
DD
= 3.6V, V
IN
= 0V to V
DD
___
5µA
|I
LO
| Output Leakage Current CE
O
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DD
___
5µA
V
OL
Output Lo w Vo l tag e I
OL
= +4mA
___
0.4 V
V
OH
Output Hi g h Vo l tage I
OH
= -4mA 2.4
___
V
5648 tb l 08
70V9369L6
Com 'l Onl y 70V9369L7
Com'l
& I nd
70V9369L9
Com 'l Only 70V9369L12
Com 'l On ly
Symbol Param eter Test Con dition Version Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Unit
I
DD
Dy nami c Op e rating
Curre nt (Bo th
Ports Ac tive )
CEL and CER= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
COM'L L 220 350 200 290 180 225 150 205 mA
IND L
____ ____
200 335
____ ____ ____ ____
I
SB1
S tand b y Curre nt
(Bo th Ports - TTL
Le v e l Inp uts )
CE
L
= CE
R
= V
IH
f = f
MAX
(1)
COM'L L 70 130 65 100 50 65 40 50 mA
IND L
____ ____
65 115
____ ____ ____ ____
I
SB2
Standby
Curre nt (One
Po rt - TTL
Le v e l Inp uts )
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs
Dis ab l e d , f= f
MAX
(1)
COM'L L 150 250 140 210 110 150 100 140 mA
IND L
____ ____
140 240
____ ____ ____ ____
I
SB3
Full Standby
Curre nt (Bo th
Ports - CMOS
Le v e l Inp uts )
Both Ports CE
L
and
CE
R
> V
DD
- 0 .2 V,
V
IN
> V
DD
- 0. 2V o r
V
IN
< 0. 2V, f = 0
(2)
COM'LL0.450.450.450.45
mA
IND L
____ ____
0.4 15
____ ____ ____ ____
I
SB4
Full Standby
Curre nt (One
Po rt - CMOS
Le v e l Inp uts )
CE
"A"
< 0. 2V and
CE
"B"
> V
DD
- 0. 2V
(5)
V
IN
> V
DD
- 0. 2V o r
V
IN
< 0.2V, Active Port,
Outputs Disabled, f = f
MAX
(1)
COM'L L 140 240 130 200 100 140 90 130 mA
IND L
____ ____
130 230
____ ____ ____ ____
5648 tb l 09
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
AC Test Conditions
Figure 1. AC Output Test load. Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
5648 drw 04
590Ω
30pF
435Ω
3.3V
DATA
OUT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
5648 drw 03
.
1
2
3
4
5
6
7
8
20 40 10060 80 120 140 160 180 200
tCD
1
,
tCD
2
(
Typical, ns)
Capacitance (pF)
5648 drw 05
-1
0
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
.
In p ut P ul s e Le v e l s
In p ut R ise / F all Tim e s
In p ut Ti m ing Re fere nce L e v e l s
Outp ut Refe re nce Le ve ls
Outp ut Lo ad
GND to 3.0V
3ns Max .
1.5V
1.5V
F ig ure s 1, 2, and 3
5648 tbl 10
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
70V9369L6
Com ' l Onl y 70V9369L7
Com ' l Onl y
& I nd
70V9369L9
Com'l Onl y 70V9369L12
Com'l Onl y
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
t
CYC1
Clo c k Cy cl e Time (Fl ow-Thro ugh)
(2)
19
____
22
____
25
____
30
____
ns
t
CYC2
Clock Cycle Time (Pipeline d)
(2)
10
____
12
____
15
____
20
____
ns
t
CH1
Cl ock H i gh Tim e (F l ow- Throu gh)
(2)
6.5
____
7.5
____
12
____
12
____
ns
t
CL1
Cl ock L ow Ti m e ( Flow- Th rou g h )
(2)
6.5
____
7.5
____
12
____
12
____
ns
t
CH2
Clock High Time (Pipelined)
(2)
4
____
5
____
6
____
8
____
ns
t
CL2
Cl ock L ow Ti m e ( P i pel i n ed)
(2)
4
____
5
____
6
____
8
____
ns
t
R
Clock Rise Time
____
3
____
3
____
3
____
3ns
t
F
Clock Fall Time
____
3
____
3
____
3
____
3ns
t
SA
Address Setup Time 3.5
____
4
____
4
____
4
____
ns
t
HA
Ad dre ss Hold Time 0
____
0
____
1
____
1
____
ns
t
SC
Chip Enable Se tup Time 3.5
____
4
____
4
____
4
____
ns
t
HC
Chip E nab l e Ho ld Time 0
____
0
____
1
____
1
____
ns
t
SW
R/ W Se tup Time 3.5
____
4
____
4
____
4
____
ns
t
HW
R/ W Ho ld Tim e 0
____
0
____
1
____
1
____
ns
t
SD
Input Data S e tu p Tim e 3. 5
____
4
____
4
____
4
____
ns
t
HD
Input Data Ho l d Ti me 0
____
0
____
1
____
1
____
ns
t
SAD
ADS Setup Time 3.5
____
4
____
4
____
4
____
ns
t
HAD
ADS Hol d Time 0
____
0
____
1
____
1
____
ns
t
SCN
CNTEN Setup Time 3.5
____
4
____
4
____
4
____
ns
t
HCN
CNTEN Ho l d Time 0
____
0
____
1
____
1
____
ns
t
SRST
CNTRST Se tup Time 3.5
____
4
____
4
____
4
____
ns
t
HRST
CNTRST Ho l d Ti me 0
____
0
____
1
____
1
____
ns
t
OE
Outpu t En ab l e to Da ta Va li d
____
6.5
____
7.5
____
9
____
12 ns
t
OLZ
Outp ut Enab le to Outp ut Lo w-Z
(1)
2
____
2
____
2
____
2
____
ns
t
OHZ
Outp ut Enab le to Outp ut Hig h-Z
(1)
17 17 17 17ns
t
CD1
Clo c k to Data Val id (Flo w-Throug h)
(2)
____
15
____
18
____
20
____
25 ns
t
CD2
Clock to Data Valid (Pipelined)
(2)
____
6.5
____
7.5
____
9
____
12 ns
t
DC
Data Ou tp ut Ho l d A fte r Cl o ck Hi gh 2
____
2
____
2
____
2
____
ns
t
CKHZ
Cl ock H i gh to Ou tpu t High -Z
(1)
29292929ns
t
CKLZ
Cl oc k High to Output Lo w- Z
(1)
2
____
2
____
2
____
2
____
ns
Port-to -Po rt Delay
t
CWDD
Write Port Clo ck Hi g h to Re ad Data De l ay
____
24
____
28
____
35
____
40 ns
t
CCS
Cl o c k-to- Cl o c k S e tu p Tim e
____
9
____
10
____
15
____
15 ns
5648 tb l 11
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
8
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(3,7)
Timing W aveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,7)
An An + 1 An + 2 An + 3
t
CYC1
t
CH1
t
CL1
R/
W
ADDRESS
DATA
OUT
CE
0
CLK
OE
t
SC
t
HC
t
CD1
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
t
CKHZ
5648 drw 06
(1)
(1) (1)
(1)
(2)
CE
1
UB,LB
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
DC
(5)
t
SC
t
HC
t
SB
t
HB
An An + 1 An + 2 An + 3
t
CYC2
t
CH2
t
CL2
R/
W
ADDRESS
CE
0
CLK
CE
1
UB,LB
(4)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
5648drw 07
(1) (1)
(1)
(2)
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
t
SB
t
HB
(5)
(1 Latency)
(6)
(6)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Notes under
Pin Names Table.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X' here denotes Left or Right port. The diagram is with respect to that port.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
9
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
5648 drw 08
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
(3)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
(3) (3)
t
SC
t
HC
(3)
t
CKHZ
(3)
t
CKLZ
(3)
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9369 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
Timing Wa vef orm of Left Port Write to Pipelined Right Port Read(1,2,4)
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
CLK
"A"
R/W
"A
"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO(3)
t
CD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
5648 drw 09
t
DC
,
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
DATA
IN "A"
CLK
"B"
R/W
"B"
ADDRESS
"A"
R/W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CWDD
t
CD1
t
DC
DATA
OUT "B"
5648 drw 10
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
CD1
t
CCS
t
DC
t
SA
t
SW
t
HA
(6)
(6)
.
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9369 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
Timing Waveform with Port-to-Port Flow-Through Read(4,5,7)
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
11
Timing W aveform of Pipelined Read-to-Write-to-R ead (OE = VIL)(3)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
R/
W
ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4
DATA
IN
Dn + 2
CE
0
CLK
5648 drw 11
Qn Qn + 3
DATA
OUT
CE
1
UB,LB
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ NOP READ
t
SD
t
HD
(4)
(2) (1) (1)
t
SW
t
HW
WRITE
(5)
.
R/
W
ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5
DATA
IN
Dn + 3
Dn + 2
CE
0
CLK
5648 drw 12
DATA
OUT
Qn Qn + 4
CE
1
UB,LB
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
(1)
t
CD2
t
OHZ
(1)
t
CD2
t
SD
t
HD
READ WRITE READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(4)
(2)
t
SW
t
HW
.
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5
(4)
DATA
IN
Dn + 2
CE
0
CLK
5648 drw 14
Qn
DATA
OUT
CE
1
UB,LB
t
CD1
t
CH1
t
CL1
CYC1
t
SD
t
HD
t
CD1
t
DC
Qn + 4
t
CD1
t
DC
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
READ WRITE READ
t
CKLZ
(2)
Dn + 3
t
OHZ
(1)
(1)
t
SW
t
HW
OE
t
OE
Timing Wav eform of Flow-Through Read-to-Write-to-R ead (OE = VIL)(3)
R/
W
ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4
DATA
IN
Dn + 2
CE
0
CLK
5648 drw 13
Qn
DATA
OUT
CE
1
UB,LB
t
CD1
Qn + 1
t
CH1
t
CL1
t
CYC1
t
SD
t
HD
t
CD1
t
CD1
t
DC
t
CKHZ
Qn + 3
t
CD1
t
DC
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
READ NOP READ
t
CKLZ
(4)
(2)
(1) (1)
t
SW
t
HW
WRITE
(5)
.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
13
Timing Waveform of Pipelined Read with Address Counter Advance(1)
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
ADDRESS An
CLK
DATA
OUT
Qx - 1
(2)
Qx Qn Qn + 2
(2)
Qn + 3
ADS
CNTEN
t
CYC2
t
CH2
t
CL2
5648 drw 15
t
SA
t
HA
t
SAD
t
HAD
t
CD2
t
DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER COUNTER
HOLD
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
Qn + 1
.
ADDRESS An
CLK
DATA
OUT
Qx
(2)
Qn Qn + 1 Qn + 2 Qn + 3
(2)
Qn + 4
ADS
CNTEN
t
CYC1
t
CH1
t
CL1
5648 drw 16
t
SA
t
HA
t
SAD
t
HAD
READ
EXTERNAL
ADDRESS
READ WITH COUNTER COUNTER
HOLD
t
CD1
t
DC
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
14
ADDRESS
(4)
An
D
0
t
CH2
t
CL2
t
CYC2
Q
0
Q
1
0
CLK
DATA
IN
R/
W
CNTRST
5648 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
t
SRST
t
HRST
t
SD
t
HD
t
SW
t
HW
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDRESS 1 READ
ADDRESS n
Qn
An + 1 An + 2
READ
ADDRESS n+1
DATA
OUT
(5)
t
SA
t
HA
1An An + 1
(6)
Ax
t
SA
D
t
HAD
t
SCN
t
HCN
(6)
.
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4 . Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ Address is written to during this cycle.
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
ADDRESS An
CLK
DATA
IN
Dn Dn + 1 Dn + 1 Dn + 2
ADS
CNTEN
(7)
t
CH2
t
CL2
t
CYC2
5648 drw 17
INTERNAL
(3)
ADDRESS An
(7)
An + 1 An + 2 An + 3 An + 4
Dn + 3 Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Depth and Width Expansion
The IDT70V9369 features dual chip enables (refer to Truth Table I)
in order to facilitate rapid and simple depth expansion with no requirements
for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
The IDT70V9369 can also be used in applications requiring expanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the input
signals for the various devices as required to allow for 36-bit or wider
applications.
5648 drw 19
IDT70V9369
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
14
CE
1
CE
0
V
DD
V
DD
IDT70V9369
IDT70V9369
IDT70V9369
Control Inputs
Control Inputs
Control Inputs
Control Inputs CNTRST
CLK
ADS
CNTEN
R/W
LB,UB
OE
Figure 4. Depth and Width Expansion with IDT70V9369
Functional Description
The IDT70V9369 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal, however, the self-timed internal write
pulse is independent of the LOW to HIGH transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operation of the address counters for fast interleaved memory applications.
CE0 = VIL and CE1 = VIH for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip enables
allow easier banking of multiple IDT70V9369's for depth expansion
configurations. When the Pipelined output mode is enabled, two cycles are
required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
16
Ordering Information
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
A
Power 99
Speed A
Package A
Process/
Temperature
Range
Blank
I
(1)
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
100-pin TQFP (PN100-1) x18 Only
128-pin TQFP (PK128) x 16 Only
288K (16K x 18-Bit) 3.3V Synchronous Dual-Port RAM
Speed in nanoseconds
Low Power
Commercial Only
Commercial & Industrial
Commercial Only
Commercial Only
PF
PRF
6
7
9
12
XXXXX
Device
Type
70V9369
5648 drw 20
L
Datasheet Document History
01/08/02: Initial Public Release
10/11/04: Removed "Preliminary" status
Page 4 Updated Truth Table II
Updated Absolute Maximum Ratings
Updated Capacitance table
Page 5 Added 6ns speed grade and 7ns I-temp, removed 9ns I-temp and updated DC power numbers
in the DC Electrical Characteristics Table
Page 7 Added 6ns speed grade and 7ns I-temp and removed 9ns I-temp AC timing numbers
from the AC Electrical Characteristics Table
Updated tOE for 7ns and 9ns speed grades
Page 9 Added Timing Waveform of Left Port Write to Pipelined Right Port Read
Page 16 Added 6ns speed grade and 7ns I-temp and removed 9ns I-temp to ordering information
Page 1 & 16 Replaced old TM logo with new TM logo
10/23/08: Page 16 Removed "IDT" from orderable part number
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com