TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
12-BIT, 200-KSPS, 11-CHANNEL, LOW-POWER, SERIAL ADC
1
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FEATURES
D
12-Bit-Resolution A/D Converter
D
Up to 200 KSPS (150 KSPS for 3 V)
Throughput Over Operating Temperature
Range With 12-Bit Output Mode
D
11 Analog Input Channels
D
3 Built-In Self-Test Modes
D
Inherent Sample and Hold Function
D
Linearity Error ...±1 LSB Max
D
On-Chip Conversion Clock
D
Unipolar or Bipolar Output Operation
D
Programmable MSB or LSB First
D
Programmable Power Down
D
Programmable Output Data Length
D
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL=0, CPHA=0)
APPLICATIONS
D
Process Control
D
Portable Data Logging
D
Battery-Powered Instruments
D
Automotive
DESCRIPTION
The TLV2553 is a 12-bit, switched-capacitor,
successive-approximation, analog-to-digital converter.
The ADC has three control inputs [chip select (CS), the
input-output clock, and the address/control input
(DATAIN)], designed for communication with the serial
port of a host processor or peripheral through a serial
3-state output.
In addition to the high-speed converter and versatile
control capability , the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any
one of three internal self-test voltages using
configuration register 1. The sample-and-hold function
is automatic. At the end of conversion, when
programmed as EOC, the pin 19 output goes high to
indicate that conversion is complete. The converter
incorporated in the device features differential, high-
impedance reference inputs that facilitate ratiometric
conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor
design allows low-error conversion over the full
operating temperature range.
The TLV2553I is characterized for operation from
TA = –40°C to 85°C. See available options table for
package options.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
VCC
EOC
I/O CLOCK
DATA IN
DATA OUT
CS
REF+
REF–
AIN10
AIN9
(TOP VIEW)
DW AND PW PACKAGE
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
2www.ti.com
AVAILABLE OPTIONS
PACKAGE
TASMALL OUTLINE
A
20-TSSOP (PW) 20-SOWB (DW)
–40°C to 85°C TLV2553IPW TLV2553IDW
functional block diagram
14-Channel
Analog
Multiplexer
Reference CTRL
12-to-1
Data
Selector
and Driver
Control Logic
and I/O
Counters
Input Address
Register
412
4
REF+ REF–
DATA
OUT
DATA IN
I/O CLOCK
CS
3
EOC
17
15
18
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
1
2
3
4
5
6
7
8
9
11
12
14 13
19
Low Power
12-Bit
SAR ADC
Sample
and Hold
Output Data
Register
12
16
20
VCC
10
GND
Internal OSC
Self Test
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
3
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AIN0 – AIN10 1–9,
11, 12 IAnalog input. These 11 analog-signal inputs are internally multiplexed.
CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DA T A OUT,
DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK within a setup time.
DATA IN 17 I Serial data input. The 4-bit serial data can be used as address selects the desired analog input channel or
test voltage to be converted next, or a command to activate other other features. The input data is presented
with the MSB (D7) first and is shifted in on the first four rising edges of the I/O CLOCK. After the four
address/command bits are read into the command register CMR, I/O CLOCK clocks the remaining four bits
of configuration in.
DATA OUT 16 O The 3-state serial output for the A/D conversion result. DAT A OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state
and is driven to the logic level corresponding to the MSB(most significant bit)/LSB(least significant bit) value
of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level
corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
EOC 19 O Status output, used to indicate the end of conversion (EOC) to the host processor.
EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until
the conversion is complete and the data is ready for transfer.
GND 10 Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
I/O CLOCK 18 I Input/output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK.
3. The remaining 1 1 bits of the previous conversion data are shifted out on DA T A OUT. Data changes on the
falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge of the last
I/O CLOCK.
REF+ 14 I/O Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The
maximum analog input voltage range is determined by the difference between the voltage applied to terminals
REF+ and REF–.
REF–13 I/O Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–. This
pin is connected to analog ground (GND of the ADC) when internal reference is used.
VCC 20 Positive supply voltage
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
4www.ti.com
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO–0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive reference voltage, Vref+ –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative reference voltage, Vref––0.3 V to VCC +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current, II (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
recommended operating conditions
PARAMETERS MIN NOM MAX UNIT
Supply voltage, VCC 2.7 5.5 V
16-bit I/O 0.01 15
I/O CLOCK frequency
VCC = 4.5 V to 5.5 V 12-bit I/O 0.01 15
MHz
I/O
CLOCK
frequency
8-bit I/O 0.01 15
MHz
VCC = 2.7 V to 3.6 V 0.01 10
Tolerable clock jitter, I/O CLOCK VCC = 4.5 V to 5.5 V 0.38 ns
Aperature jitter VCC = 4.5 V to 5.5 V 100 ps
VCC = 4.5 V to 5.5 V 0 (REF+) – (REF–)
Analog input voltage (see Note 2) VCC = 3.0 V to 3.6 V 0(REF+ ) –(REF–)V
VCC = 2.7 V to 3.0 V 0(REF+) –(REF–)
High level control in
p
ut voltage VIH
VCC = 4.5 V to 5.5 V 2.0
V
High
-
level
control
input
voltage
,
V
IH VCC = 2.7 V to 3.6 V 2.1
V
Low level control in
p
ut voltage VIL
VCC = 4.5 V to 5.5 V 0.8
V
Low
-
level
control
input
voltage
,
V
IL VCC = 2.7 V to 3.6 V 0.6
V
Operating free-air temperature, TATLV2553I –40 85 °C
NOTE 2: Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
5
www.ti.com
electrical characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
I/O CLOCK frequency = 15 MHz when VCC = 5 V , VREF+ = 2.5 V , I/O CLOCK frequency = 10 MHz when
VCC = 2.7 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH
High level out
p
ut voltage
VCC = 4.5 V, IOH = –1.6 mA
VCC = 2.7 V, IOH = –0.2 mA 30 pF 2.4
V
V
OH
High
-
level
output
voltage
VCC = 4.5 V, IOH = –20 µA
VCC = 2.7 V, IOH = –20 µA30 pF VCC –0.1
V
VOL
Low level out
p
ut voltage
VCC = 5.5 V, IOL = 1.6 mA
VCC = 3.6 V, IOH = 0.8 mA 30 pF 0.4
V
V
OL
Low
-
level
output
voltage
VCC = 5.5 V, IOL = –20 µA
VCC = 3.6 V, IOH = –20 µA30 pF 0.1
V
IOZ
High im
p
edance off state out
p
ut current
VO = VCC, CS at VCC 1 2.5
µA
I
OZ
High
-
impedance
off
-
state
output
current
VO = 0 V, CS at VCC –1–2.5 µ
A
ICC
O
p
erating su
pp
ly current
VCC = 5 V 1.2
mA
I
CC
Operating
supply
current
,
.
VCC = 2.7 V 0.9
mA
I
CC(PD)
Power-down current
For all digital inputs,
0 ≤ VI ≤ 0.5 V or
Software power
down 0.1 1
µ
A
CC(PD)
I
–
.
,
I/O CLOCK = 0 V Auto power down 0.1 10
µ
IIH High-level input current VI = VCC 0.005 2.5 µA
IIL Low-level input current VI = 0 V –0.005 –2.5 µA
Ilk
Selected channel leakage current
Selected channel at VCC , Unselected
channel at 0 V 1
µA
I
lkg
Selected
channel
leakage
current
Selected channel at 0 V, Unselected
channel at VCC –1µ
A
f(OSC)
Internal oscillator frequency
VCC = 4.5 V to 5.5 V 3.27
MHz
f
(OSC)
Internal
oscillator
frequency
VCC = 2.7 V to 3.6 V 2.56
MHz
tt
Conversion time = 13 5X [f(OSC)]+25ns
VCC = 4.5 V to 5.5 V 4.15
µs
t
convert
Conversion
time
=
13
.
5X
[f
(OSC)
]
+
25
ns
VCC = 2.7 V to 3.6 V 5.54 µ
s
Internal oscillator frequency voltage 3.6 4.1 V
Zi
In
p
ut im
p
edance‡
Analog in
p
uts
VCC = 4.5 V 500
Ω
Z
i
Input
impedance‡
Analog
inputs
VCC = 2.7 V 600
Ω
Ci
In
p
ut ca
p
acitance
Analog inputs 45 55 p
F
C
i
Input
capacitance
Control inputs 5 15
pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡The switch resistance is very nonlinear and varies with input voltage and supply voltage. This is the worst case.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
6www.ti.com
external reference specifications
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
Reference in
p
ut voltage REF
VCC = 4.5 V to 5.5 V –0.1 0 0.1
V
Reference
input
voltage
,
REF
–VCC = 2.7 V to 3.6 V –0.1 0 0.1
V
Reference in
p
ut voltage REF+
VCC = 4.5 V to 5.5 V 2 VCC
V
Reference
input
voltage
,
REF
+VCC = 2.7 V to 3.6 V 2 VCC
V
External reference input volta
g
e difference, VCC = 4.5 V to 5.5 V 1.9 VCC
V
g,
(REF+) – (REF–)VCC = 2.7 V to 3.6 V 1.9 VCC
V
External reference su
pp
ly current
CS at 0 V
VCC = 4.5 V to 5.5 V 0.94
mA
External
reference
supply
current
CS
at
0
V
VCC = 2.7 V to 3.6 V 0.62
mA
VCC =5V
Static 1 MΩ
Reference in
p
ut im
p
edance
V
CC =
5
V
During sampling/conversion 6 9 kΩ
Reference
input
impedance
VCC =27V
Static 1 MΩ
V
CC =
2
.
7
V
During sampling/conversion 6 9 kΩ
†All typical values are at TA = 25°C.
NOTE: Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
operating characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
I/O CLOCK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz when
VCC = 2.7 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
INL Integral linearity error (see Note 3) –1 1 LSB
DNL Differential linearity error –1 1 LSB
EOOffset error (see Note 4) See Note 2 –2 2 mV
EGGain error (see Note 4) See Note 2 –3 3 mV
ETTotal unadjusted error (see Note 5) ±1.5 LSB
Address data input = 1011 2048
Self-test output code (see Table 2 and Note 6) Address data input = 1100 0
Address data input = 1101 4095
†All typical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF– convert as all zeros (000000000000).
3. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
4. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the of fset error has been adjusted to zero. Of fset error is the difference between the actual midstep value an d the
nominal midstep value at the offset point.
5. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
6. Both the input address and the output codes are expressed in positive logic.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
7
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timing characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
I/O CLOCK frequency = 15 MHz, VCC = 5 V, load = 25 pF (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw1 Pulse duration I/O CLOCK high or low 26.7 100000 ns
tsu1 Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26) 12 ns
th1 Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26) 0 ns
tsu2 Setup time CS low before first rising I/O CLOCK edge
(see Note 7 and Figure 27) 25 ns
th2 Hold time CS pulse duration high time (see Figure 27) 100 ns
th3 Hold time CS low after last I/O CLOCK falling edge (see Figure 27) 0 ns
th4 Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28) 2 ns
th5 Hold time CS high after EOC rising edge when CS is toggled (see Figure 31) 0 ns
td1
Delay time CS fallin
g
ed
g
e to DATA OUT valid Load = 25 pF 28 ns
t
d1
ygg
(MSB or LSB) (see Figure 25) Load = 10 pF 20 ns
td2 Delay time CS rising edge to DATA OUT high impedance (see Figure 25) 10 ns
td3 Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28) 2 20 ns
td4 Delay time Last I/O CLOCK falling edge to EOC falling edge 55 ns
td5 Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion 1.5 µs
tt1 T ransition time I/O CLOCK (see Note 7 and Figure 28) 1µs
tt2 T ransition time DATA OUT (see Figure 28) 5 ns
tt3 T ransition time INT/EOC, CL at 7 pF (see Figure 30) 2.4 ns
tt4 T ransition time DATA IN, CS 10 µs
tcycle Total cycle time (sample, conversion and delays) (see Note 7) MAX(tconvert) +
I/O period
(8/12/16 CLKs) µs
Source impedance = 25 Ω600
tl
Channel acquisition time (sample), at 1 kΩSource impedance = 100 Ω650
ns
t
sample
q(),
See Figures 33–38 and Note 7 Source impedance = 500 Ω700
ns
Source impedance = 1 kΩ1000
NOTE 7: I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on
I/O format selected.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
8www.ti.com
timing characteristics over recommended operating free-air temperature range, VREF+ = 2.5 V,
I/O CLOCK frequency = 10 MHz, VCC = 2.7 V, load = 25 pF (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tw1 Pulse duration I/O CLOCK high or low 40 100000 ns
tsu1 Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26) 22 ns
th1 Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26) 0 ns
tsu2 Setup time CS low before first rising I/O CLOCK edge
(see Note 7 and Figure 27) 33 ns
th2 Hold time CS pulse duration high time (see Figure 27) 100 ns
th3 Hold time CS low after last I/O CLOCK falling edge (see Figure 27) 0 ns
th4 Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28) 2 ns
th5 Hold time CS high after EOC rising edge when CS is toggled (see Figure 31) 0 ns
td1
Delay time CS fallin
g
ed
g
e to DATA OUT valid Load = 25 pF 30 ns
t
d1
ygg
(MSB or LSB) (see Figure 25) Load = 10 pF 22 ns
td2 Delay time CS rising edge to DATA OUT high impedance (see Figure 25) 10 ns
td3 Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28) 2 33 ns
td4 Delay time Last I/O CLOCK falling edge to EOC falling edge 75 ns
td5 Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion 1.5 µs
tt1 T ransition time I/O CLOCK (see Note 7 and Figure 28) 1µs
tt2 T ransition time DATA OUT (see Figure 28) 5 ns
tt3 T ransition time INT/EOC, CL at 7 pF (see Figure 30) 4 ns
tt4 T ransition time DATA IN, CS 10 µs
tcycle Total cycle time (sample, conversion and delays) (see Note 7) MAX(tconvert) +
I/O period
(8/12/16 CLKs) µs
Source impedance = 25 Ω800
tl
Channel acquisition time (sample), at 1 kΩSource impedance = 100 Ω850
ns
t
sample
q(),
See Figures 33–38 and Note 7 Source impedance = 500 Ω1000
ns
Source impedance = 1 kΩ1600
NOTE 7: I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on
I/O format selected.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
9
www.ti.com
TYPICAL CHARACTERISTICS
Figure 1
0.58
0.585
0.590
0.595
0.600
0.605
0.610
0.615
0.620
0.625
–40 –25 –105 2035506580
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
TA – Free-Air Temperature – °C
ICC – Supply Current – mA
Figure 2
0.33
0.34
0.35
0.36
0.37
0.38
0.39
0.40
0.41
0.42
0.43
–40 –25 –105 2035506580
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
External Reference Current – mA
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
Figure 3
0.0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
–40 –25 –105 2035506580
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Current –
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
µA
Figure 4
0
0.01
0.02
0.03
0.04
0.05
0.06
–40 –25 –105 2035506580
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Current –
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
µA
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
10 www.ti.com
TYPICAL CHARACTERISTICS
Figure 5
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–40 –25 –105 2035506580
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Maximum Differential Nonlinearity – LSB
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
Figure 6
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
–0.0
–40 –25 –105 2035506580
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Minimum Differential Nonlinearity – LSB
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
Figure 7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
–40 –25 –105 2035506580
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Maximum Integral Nonlinearity – LSB
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
Figure 8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
–0.0
–40 –25 –105 2035506580
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Minimum Integral Nonlinearity – LSB
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
11
www.ti.com
TYPICAL CHARACTERISTICS
Figure 9
–0.5
–0.4
–0.3
–0.2
–0.1
–0.0
0.1
0.2
0.3
0.4
0.5
0 1024 2048 3072 4096
DNL – Differential Nonlinearity – LSB
Digital Output Code
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
VCC = 2.7 V, VREF+ = 2.5 V, VREF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
Figure 10
–0.8
–0.6
–0.4
–0.2
–0.0
0.2
0.4
0.6
0.8
0 1024 2048 3072 4096
INL – Integral Nonlinearity – LSB
Digital Output Code
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
VCC = 2.7 V, VREF+ = 2.5 V, VREF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
12 www.ti.com
TYPICAL CHARACTERISTICS
Figure 11
0.0
0.1
0.2
0.3
0.4
0.5
0.6
–40 –25 –105 2035506580
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
EO– Offset Error – mV
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
Figure 12
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–40 –25 –105 2035506580
GAIN ERROR
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
EG– Gain Error – mV
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
Figure 13
0.84
0.86
0.88
0.90
0.92
0.94
0.96
0.98
–40 –25 –105 2035506580
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
ICC – Supply Current – mA
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
Figure 14
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
–40 –25 –105 2035506580
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
External Reference Current – mA
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
13
www.ti.com
TYPICAL CHARACTERISTICS
Figure 15
0.0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
–40 –25 –105 2035506580
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Current –
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
µA
Figure 16
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
–40 –25 –105 2035506580
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Current –
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
µA
Figure 17
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–40 –25 –105 2035506580
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Maximum Differential Nonlinearity – LSB
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
Figure 18
–0.45
–0.40
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
–0.00
–40 –25 –105 2035506580
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Minimum Differential Nonlinearity – LSB
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
14 www.ti.com
TYPICAL CHARACTERISTICS
Figure 19
0.74
0.76
0.78
0.80
0.82
0.84
0.86
0.88
0.90
–40 –25 –105 2035506580
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Maximum Integral Nonlinearity – LSB
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
Figure 20
–0.338
–0.337
–0.336
–0.335
–0.334
–0.333
–0.332
–0.331
–0.330
–0.329
–40 –25 –105 2035506580
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Minimum Integral Nonlinearity – LSB
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
Figure 21
–0.3
–0.2
–0.1
–0.0
0.1
0.2
0.3
0 1024 2048 3072 4096
DNL – Differential Nonlinearity – LSB
Digital Output Code
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
VCC = 5.5 V, VREF+ = 4.096 V, VREF– = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
15
www.ti.com
TYPICAL CHARACTERISTICS
Figure 22
–0.8
–0.6
–0.4
–0.2
–0.0
0.2
0.4
0.6
0.8
0 1024 2048 3072 4096
INL – Integral Nonlinearity – LSB
Digital Output Code
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
VCC = 5.5 V, VREF+ = 4.096 V, VREF– = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
Figure 23
–0.5
–0.45
–0.40
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
–0.00
–40 –25 –105 2035506580
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
EO– Offset Error – mV
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
Figure 24
–1
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
–0.0
–40 –25 –105 2035506580
GAIN ERROR
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
EG– Gain Error – mV
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
16 www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 25. DATA OUT to Hi-Z Voltage Waveforms
VIL
VIH
VOH
VOL
td1 td2
CS
Data Out
VIH
VIL
Data Valid
tsu1
DATA IN
I/O
CLOCK VIL
VIH
th1
Figure 26. DATA IN and I/O CLOCK Voltage
VIL
VIH
th2
VIL
VIH
tsu2 th3
CS
I/O
CLOCK Last
Clock
VIL
VIH
tt1 tt1
I/O CLK Period
td3
th4 VOH
VOL
tt2
I/O
CLOCK
Data Out
Figure 27. CS and I/O CLOCK Voltage
Waveforms Figure 28. I/O CLOCK and DATA OUT Voltage
Waveforms
VOH
VOL
VIL
VIH
Last
Clock tconvert
td2
tt3
I/O
CLOCK
VOH
VOL
tt3
tt3 VOH
VOL
MSB
Valid
Data Out
Figure 29. I/O CLOCK and EOC Voltage
Waveforms Figure 30. EOC and DATA OUT Voltage
Waveforms
EOC
EOC
VIL
VIH
VOH
VOL
th5
EOC
CS VIL
VIH
VOH
VOL
1
EOC
I/O
CLOCK
Figure 31. CS and EOC Waveforms Figure 32. I/O CLOCK and DATA OUT Voltage
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
17
www.ti.com
PARAMETER MEASUREMENT INFORMATION
timing diagrams
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
1235
4610 11 12 1
MSB–1MSB–2MSB–3MSB–4MSB–5MSB–8MSB–9LSB+1 LSB Hi–Z State
23
D6 D5 D4 D3 D2 D1 D0 D6 D5D7
8
79
MSB–6MSB–7
D7
Previous Conversion Data
MSB MSB MSB–2MSB–1
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access
Cycle Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
CS
I/O
CLOCK
DATA
OUT
DATA
IN
EOC
Initialize Initialize
Figure 33. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
MSB
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
1235
46101112 1
MSB–1MSB–2MSB–3MSB–4MSB–5MSB–8MSB–9LSB+1 LSB
23
D6 D5
8
79
MSB–6MSB–7
D7
Low Level
MSB
D6 D5 D4 D3 D2 D1 D0D7
MSB–2MSB–1
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access
Cycle Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
Initialize Initialize
Figure 34. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
18 www.ti.com
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
ÎÎÎÎ
ÎÎÎÎÎÎ
1235
461
MSB–1MSB–2MSB–3MSB–4MSB–5LSB+1 LSB Hi–Z State
23
D6 D5 D4 D3 D2 D1 D0 D6 D5D7
8
7
ÎÎÎ
D7
MSB MSB MSB–2MSB–1
45 6 7
D4 D3
MSB–4MSB–3
D2 D1
MSB–6MSB–5
Access
Cycle Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
Initialize Initialize
Figure 35. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
MSB
ÎÎÎÎ
ÎÎÎÎÎÎ
1235
461
MSB–1MSB–2MSB–3MSB–4MSB–5LSB+1 LSB
23
D6 D5
8
7
ÎÎ
D7
Low Level
MSB
D6 D5 D4 D3 D2 D1 D0D7
MSB–2
MSB–1
4567
D4 D3
MSB–4MSB–3
D2 D1
MSB–6
MSB–5
Access
Cycle Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
Initialize Initialize
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
Figure 36. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
19
www.ti.com
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Pad
Zeros
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1235
46101112 1
MSB–1MSB–2MSB–3MSB–4MSB–5MSB–8MSB–9LSB+1 LSB Hi–Z State
D6 D5 D4 D3 D2 D1 D0D7
8
79
MSB–6MSB–7
ÎÎ
D7
MSB MSB
16
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access Cycle Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tCONV
Previous Conversion Data
Initialize Initialize
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
Figure 37. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Pad
Zeros
MSB
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1235
46101112 1
MSB–1MSB–2MSB–3MSB–4MSB–5MSB–8MSB–9LSB+1 LSB
16
8
79
MSB–6MSB–7
ÎÎ
ÎÎ
Low Level
MSB
D6 D5 D4 D3 D2 D1 D0D7 D7
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access Cycle Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
Previous Conversion Data
Initialize
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
tCONV
Initialize
Figure 38. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
20 www.ti.com
PRINCIPLES OF OPERATION
detailed description
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DA TA IN and
removes DA T A OUT from the high-impedance state. The input data is an 8–bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). Configuration register 1, CFGR1, which
controls output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB
first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN)
except for command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data
to the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion
result from the output data register to DA TA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock
cycles long depending on the data-length selection in the input data register. Sampling of the analog input
begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the
I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the
conversion.
converter operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2)
the sampling cycle and 3) the conversion cycle. The first two are partially overlapped.
data I/O cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously . An 8-bit data stream consisting of address/command and configuration information is provided
to DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA
INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length
of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on
the rising edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling
edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each
succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.
sampling cycle
During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter
to store the analog input signal. The converter starts sampling the selected input immediately after the four
address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence
of external digital noise.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
21
www.ti.com
PRINCIPLES OF OPERATION
conversion cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns)
to start the OSC. During the conversion period, the device performs a successive-approximation conversion
on the analog input voltage.
EOC goes low at the start of the conversion cycle and goes high when the conversion is complete and the output
data register is latched. After EOC goes low , the analog input can be changed without affecting the conversion
result. Since the delay from the falling edge of the last I/O CLOCK to the falling edge of EOC is fixed, any
time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic
distortion or noise due to timing uncertainty.
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the
configuration register is set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low
to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may
not read accurately due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT
Current (N) conversion cycle The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the out-
put register when conversion is complete.
Current (N) conversion result The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle The conversion cycle just prior to the current I/O cycle
Next (N+1) I/O cycle The I/O period that follows the current conversion cycle
Example:
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
data input
The data input is internally connected to an 8-bit serial-input address and control register . The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
22 www.ti.com
PRINCIPLES OF OPERATION
Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
Binary, HEX COMMAND
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
SELECT analog input channel 0
SELECT analog input channel 1
SELECT analog input channel 2
SELECT analog input channel 3
SELECT analog input channel 4
SELECT analog input channel 5
SELECT analog input channel 6
SELECT analog input channel 7
SELECT analog input channel 8
SELECT analog input channel 9
SELECT analog input channel 10
SELECT TEST,
Voltage = (VREF+ + VREF–)/2
SELECT TEST, Voltage = REFM
SELECT TEST, Voltage = REFP
SW POWERDOWN (analog + reference)
Reserved
CONFIGURATION
CFGR1
SDI
D[3:0]
D[3:2]
D1
D0
01: 8-bit output length
X0: 12-bit output length (see Note)
11: 16-bit output length
0: MSB out first
1: LSB out first
0: Unipolar binary
1: Bipolar 2s complement
NOTE: Select 12-bit output mode to achieve 200 KSPS
sampling rate.
data input—address/command bits
The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address
one of the 11 input channels, address one of three reference-test voltages, or activate software power-down
mode. All address/command bits affect the current conversion, which is the conversion that immediately follows
the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.
data output length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid
for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly
12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 1 1, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
23
www.ti.com
PRINCIPLES OF OPERATION
data output length (continued)
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
of the current I/O cycle.
Since the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, since at the time the data length change becomes effective (six
rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,
when different data lengths are required within an application and the data length is changed between two
conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
LSB out first
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
bipolar output format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared
to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result
of an input voltage equal to or less than VREF– is a code with all zeros (000 . . . 0) and the conversion result of
an input voltage equal to or greater than VREF+ is a code of all ones (1 11 . . . 1). The conversion result of (VREF+
+ VREF–)/2 is a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally , conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100 . . . 0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones
(01 1 . . . 1). The conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted
as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s
complement.
Selection of the unipolar or bipolar format always af fects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
reference
An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels
applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and
zero-scale reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive
supply or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at
full scale when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or
lower than REF–.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
24 www.ti.com
PRINCIPLES OF OPERATION
C1
0.1 µF
Decoupling Cap
GND
Analog
Supply
Sample
∼50 pF
CDAC
Convert
REF+
REF–
VCC
Figure 39. Reference Block
EOC output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register . The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DAT A OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
chip-select input (CS)
CS enables and disables the device. During normal operation, CS should be low . Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK
is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low , I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
25
www.ti.com
PRINCIPLES OF OPERATION
chip-select input (CS) (continued)
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DA T A OUT on the rising edge of EOC. Note that the first cycle in the series still requires a transition CS from
high to low . When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the
serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DA TA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit
in the serial conversion result until the required number of bits has been output.
power-down features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles,
the software power-down mode is selected. Software power down is activated on the falling edge of the fourth
I/O CLOCK pulse.
During software power-down, all internal circuitry is put in a low-current standby mode. No conversions is
performed. The internal output buffer keeps the previous conversion cycle data results, provided that all digital
inputs are held above VCC – 0.5 V or below 0.5 V . The I/O logic remains active so the current I/O cycle must be
completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,
the converter normally begins in the power-down mode. The device remains in the software power-down mode
until a valid input address (other than command 1 110b or 1 111b) is clocked in. Upon completion of that I/O cycle,
a normal conversion is performed with the results being shifted out during the next I/O cycle.
The ADC also has an auto power-down mode. This is transparent to users. The ADC gets into auto power-down
within 1 I/O CLOCK cycle after the conversion is complete and resumes, with a small delay, after an active CS
is sent to the ADC. The resumption is fast enough to be used between cycles
analog MUX
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2553IDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2553IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2553IDWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2553IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2553IPW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2553IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2553IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2553IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2553IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2553IPWR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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