Semiconductor Components Industries, LLC, 2002
June, 2002 – Rev. 8 1Publication Order Number:
MAC97/D
MAC97 Series
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors
Designed for use in solid state relays, MPU interface, TTL logic and
any other light industrial or consumer application. Supplied in an
inexpensive TO–92 package which is readily adaptable for use in
automatic insertion equipment.
One–Piece, Injection–Molded Package
Blocking Voltage to 600 Volts
Sensitive Gate Triggering in Four Trigger Modes (Quadrants) for all
possible Combinations of Trigger Sources, and especially for Circuits
that Source Gate Drives
All Diffused and Glassivated Junctions for Maximum Uniformity of
Parameters and Reliability
Device Marking: Device Type, e.g., MAC97A4, Date Code
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage
(TJ = –40 to +110°C) (Note 1)
Sine Wave 50 to 60 Hz, Gate Open
MAC97A4
MAC97A6
MAC97–8,
MAC97A8
VDRM,
VRRM
200
400
600
Volts
On-State RMS Current
Full Cycle Sine Wave 50 to 60 Hz
(TC = +50°C)
IT(RMS) 0.6 Amp
Peak Non–Repetitive Surge Current
One Full Cycle, Sine Wave 60 Hz
(TC = 110°C)
ITSM 8.0 Amps
Circuit Fusing Considerations (t = 8.3 ms) I2t 0.26 A2s
Peak Gate Voltage
(t 2.0 s, TC = +80°C) VGM 5.0 Volts
Peak Gate Power
(t 2.0 s, TC = +80°C) PGM 5.0 Watts
Average Gate Power
(TC = 80°C, t 8.3 ms) PG(AV) 0.1 Watt
Peak Gate Current
(t 2.0 s, TC = +80°C) IGM 1.0 Amp
Operating Junction Temperature Range TJ–40 to +110 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
TRIACS
0.8 AMPERE RMS
200 thru 600 VOLTS
Preferred devices are recommended choices for future use
and best overall value.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
MT1
G
MT2
TO–92 (TO–226AA)
CASE 029
STYLE 12
3
2
1
PIN ASSIGNMENT
1
2
3
Gate
Main Terminal 2
Main Terminal 1
http://onsemi.com
MAC97 Series
http://onsemi.com
2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RJC 75 °C/W
Thermal Resistance, Junction to Ambient RJA 200 °C/W
Maximum Lead Temperature for Soldering Purposes for 10 Seconds TL260 °C
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open) TJ = 25°C
TJ = +110°C
IDRM, IRRM
10
100 A
A
ON CHARACTERISTICS
Peak On–State Voltage
(ITM = .85 A Peak; Pulse Width 2.0 ms, Duty Cycle 2.0%) VTM 1.9 Volts
Gate Trigger Current (Continuous dc)
(VD = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) MAC97–8 Device
MT2(+), G(–)
MT2(–), G(–)
MT2(–), G(+)
MT2(+), G(+) MAC97A4,A6,A8 Devices
MT2(+), G(–)
MT2(–), G(–)
MT2(–), G(+)
IGT
10
10
10
10
5.0
5.0
5.0
7.0
mA
Gate Trigger Voltage (Continuous dc)
(VD = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) All Types
MT2(+), G(–) All Types
MT2(–), G(–) All Types
MT2(–), G(+) All Types
VGT
.66
.77
.84
.88
2.0
2.0
2.0
2.5
Volts
Gate Non–Trigger Voltage
(VD = 12 V, RL = 100 Ohms, TJ = 110°C)
All Four Quadrants
VGD 0.1 Volts
Holding Current
(VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) IH 1.5 10 mA
Turn-On Time
(VD = Rated VDRM, ITM = 1.0 A pk, IG = 25 mA) tgt 2.0 s
DYNAMIC CHARACTERISTICS
Critical Rate–of–Rise of Commutation Voltage
(VD = Rated VDRM, ITM = .84 A,
Commutating di/dt = .3 A/ms, Gate Unenergized, TC = 50°C)
dV/dt(c) 5.0 V/s
Critical Rate of Rise of Off–State Voltage
(VD = Rated VDRM, TC = 110°C, Gate Open, Exponential Waveform dv/dt 25 V/s
MAC97 Series
http://onsemi.com
3
+ Current
+ Voltage
VTM
IH
Symbol Parameter
VDRM Peak Repetitive Forward Off State Voltage
IDRM Peak Forward Blocking Current
VRRM Peak Repetitive Reverse Off State Voltage
IRRM Peak Reverse Blocking Current
Voltage Current Characteristic of Triacs
(Bidirectional Device)
IDRM at VDRM
on state
off state
IRRM at VRRM
Quadrant 1
MainTerminal 2 +
Quadrant 3
MainTerminal 2 – VTM
IH
VTM Maximum On State Voltage
IHHolding Current
MT1
(+) IGT
GATE
(+) MT2
REF
MT1
(–) IGT
GATE
(+) MT2
REF
MT1
(+) IGT
GATE
(–) MT2
REF
MT1
(–) IGT
GATE
(–) MT2
REF
MT2 NEGATIVE
(Negative Half Cycle)
MT2 POSITIVE
(Positive Half Cycle)
+
Quadrant III Quadrant IV
Quadrant II Quadrant I
Quadrant Definitions for a Triac
IGT + IGT
All polarities are referenced to MT1.
With in–phase signals (using standard AC lines) quadrants I and III are used.
MAC97 Series
http://onsemi.com
4
= CONDUCTION ANGLE
0.5 0.6 0.7 0.80.1 0.2 0.3 0.40
110
100
90
80
70
60
IT(RMS), RMS ON-STATE CURRENT (AMPS)
T , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)
C°
= 30°
60°
90°
DC
180°
120°
50
40
30
Figure 1. RMS Current Derating Figure 2. RMS Current Derating
= CONDUCTION ANGLE
0.25 0.3 0.35 0.40.05 0.1 0.15 0.20
90
80
70
60
50
40
IT(RMS), RMS ON-STATE CURRENT (AMPS)
30
20
100
110
= 30°
60°90°
DC
180°
120°
, MAXIMUM ALLOWABLE
AMBIENT TEMPERATURE ( C)°
T(RMS)
I
Figure 3. Power Dissipation
0.4 0.5 0.6 0.70 0.1 0.2 0.3
0.6
0.4
0.2
0
IT(RMS), RMS ON-STATE CURRENT (AMPS)
0.8
= CONDUCTION ANGLE
0.8
1.0
1.2
P , MAXIMUM AVERAGE POWER DISSIPATION (WATTS)
(AV)
= 30°
60°90°
DC
180°
120°
0.006
0.01
0.02
0.04
0.06
0.1
0.2
0.4
0.6
1.0
2.0
4.0
6.0
TJ = 110°C
25°C
ITM, INSTANTANEOUS ONSTATE CURRENT (AMP)
0.4 1.2 2.0 2.8 3.6 4.4 5.2 6.0
VTM, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
Figure 4. On–State Characteristics
MAC97 Series
http://onsemi.com
5
Figure 5. Transient Thermal Response Figure 6. Maximum Allowable Surge Current
0.1 1.0 10 100
1.0
t, TIME (ms)
0.1
0.01 110311043.0 30 501.0 2.0 100
3.0
2.0
1.0
NUMBER OF CYCLES
5.0
10
ZJC(t) = RJC(t) r(t)
105.0
Surge is preceded and followed by rated current.
TJ = 110°C
f = 60 Hz CYCLE
I , PEAK SURGE CURRENT (AMPS)
TSM
R , TRANSIENT THERMAL RESISTANCE (NORMALIZED)
(t)
Figure 7. Typical Gate Trigger Current versus
Junction Temperature Figure 8. Typical Gate Trigger Voltage versus
Junction Temperature
Figure 9. Typical Latching Current versus
Junction Temperature Figure 10. Typical Holding Current versus
Junction Temperature
100
10
1
0
TJ, JUNCTION TEMPERATURE (°C)
1.2
0.4
TJ, JUNCTION TEMPERATURE (°C)
0.3
TJ, JUNCTION TEMPERATURE (°C)
1
TJ, JUNCTION TEMPERATURE (°C)
0.1
35 50 80-40 -25 5 20 95 110 20 35 80-40 -25 -10 5 95 110
10
, GATE TRIGGER CURRENT (mA)
GT
, GATE TRIGGER VOLTAGE (V)
GT
, LATCHING CURRENT (mA)
L
-10 65
I
Q4
Q3
Q2
Q1
0.5
0.6
0.7
0.8
0.9
1.0
1.1
V
50 65
Q4
Q3
Q2
Q1
I
100
10
1
0
35 50 80-40 -25 5 20 95 110-10 65
Q4 Q3
Q2
Q1
35 50 80-40 -25 5 20 95 110-10 65
, HOLDING CURRENT (mA)
H
I
MT2 Negative
MT2 Positive
MAC97 Series
http://onsemi.com
6
Figure 11. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage
(dV/dt)c
LL1N4007
200 V
+
MEASURE
I
-
CHARGE
CONTROL
CHARGE TRIGGER
NONPOLAR
CL
51
MT2
MT1
1N914
G
TRIGGER CONTROL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.
RS
ADJUST FOR
dV/dt(c)
CS
MAC97 Series
http://onsemi.com
7
TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A
H
F1 F2
P2 P2
P1 P
D
W
W1
L1
W2
H2B H2B
T1
T
T2
H4 H5
H1
L
Figure 12. Device Positioning on Tape
Specification
Symbol Item Inches Millimeter
Symbol Item Min Max Min Max
DTape Feedhole Diameter 0.1496 0.1653 3.8 4.2
D2 Component Lead Thickness Dimension 0.015 0.020 0.38 0.51
F1, F2 Component Lead Pitch 0.0945 0.110 2.4 2.8
HBottom of Component to Seating Plane .059 0.156 1.5 4.0
H1 Feedhole Location 0.3346 0.3741 8.5 9.5
H2A Deflection Left or Right 0 0.039 0 1.0
H2B Deflection Front or Rear 0 0.051 0 1.0
H4 Feedhole to Bottom of Component 0.7086 0.768 18 19.5
H5 Feedhole to Seating Plane 0.610 0.649 15.5 16.5
LDefective Unit Clipped Dimension 0.3346 0.433 8.5 11
L1 Lead Wire Enclosure 0.09842 2.5
PFeedhole Pitch 0.4921 0.5079 12.5 12.9
P1 Feedhole Center to Center Lead 0.2342 0.2658 5.95 6.75
P2 First Lead Spacing Dimension 0.1397 0.1556 3.55 3.95
TAdhesive Tape Thickness 0.06 0.08 0.15 0.20
T1 Overall Taped Package Thickness 0.0567 1.44
T2 Carrier Strip Thickness 0.014 0.027 0.35 0.65
WCarrier Strip Width 0.6889 0.7481 17.5 19
W1 Adhesive Tape Width 0.2165 0.2841 5.5 6.3
W2 Adhesive Tape Position 0.0059 0.01968 0.15 0.5
NOTES:
2. Maximum alignment deviation between leads not to be greater than 0.2 mm.
3. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm.
4. Component lead to tape adhesion must meet the pull test requirements.
5. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.
6. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.
7. No more than 1 consecutive missing component is permitted.
8. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.
9. Splices will not interfere with the sprocket feed holes.
MAC97 Series
http://onsemi.com
8
ORDERING & SHIPPING INFORMATION: MAC97 Series packaging options, Device Suffix
U.S. Europe
Equivalent Shipping Description of TO92 Tape Orientation
MAC97A6RL1, A8RL1 Radial Tape and Reel (2K/Reel) Flat side of TO92 and adhesive tape visible
MAC97–8,
MAC97A4,A6,A8 Bulk in Box (5K/Box) N/A, Bulk
MAC97A6RLRF Radial Tape and Reel (2K/Reel) Round side of TO92 and adhesive tape on
reverse side
MAC97A8RLRP Radial Tape and Fan Fold Box
(2K/Box) Round side of TO92 and adhesive tape vis-
ible
MAC97 Series
http://onsemi.com
9
PACKAGE DIMENSIONS
TO–92 (TO–226AA)
CASE 029–11
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X–X
C
V
D
N
N
XX
SEATING
PLANE DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.45 5.20
B0.170 0.210 4.32 5.33
C0.125 0.165 3.18 4.19
D0.016 0.021 0.407 0.533
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.015 0.020 0.39 0.50
K0.500 --- 12.70 ---
L0.250 --- 6.35 ---
N0.080 0.105 2.04 2.66
P--- 0.100 --- 2.54
R0.115 --- 2.93 ---
V0.135 --- 3.43 ---
1
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
MAC97 Series
http://onsemi.com
10
Notes
MAC97 Series
http://onsemi.com
11
Notes
MAC97 Series
http://onsemi.com
12
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
MAC97/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800–282–9855 Toll Free USA/Canada