16-Bit, 1 MSPS Module Data Acquisition System ADAQ7980/ADAQ7988 Data Sheet FUNCTIONAL BLOCK DIAGRAM Easy to use Module data acquisition system All active components designed by Analog Devices, Inc. 50% PCB area savings Includes critical passive components SPI-/QSPI-/MICROWIRETM-/DSP-compatible serial interface Daisy-chain multiple ADAQ7980/ADAQ7988 devices Versatile supply configuration with 1.8 V/2.5 V/3 V/5 V logic interface High performance 16-bit resolution with no missing codes Throughput: 1 MSPS (ADAQ7980) and 500 kSPS (ADAQ7988) INL: 8 ppm typical and 20 ppm maximum SNR: 91.5 dB typical at 10 kHz (unity gain) THD: -105 dB at 10 kHz Zero error: 0.06 mV typical (unity gain) Zero error temperature drift: 1.3 V/C maximum Low power dissipation 21 mW typical at 1 MSPS (ADAQ7980) 16.5 mW typical at 500 kSPS (ADAQ7988) Flexible power-down modes Small, 24-lead, 5 mm x 4 mm LGA package Excellent ESD ratings 3500 V human body model (HBM) 1250 V field-induced charged device model (FICDM) Wide operating temperature range: -55C to +125C APPLICATIONS LDO_OUT VDD PD_REF LDO 10F IN+ VIO SDI SCK 20 IN- PD_LDO 2.2F ADC SDO AMP_OUT CNV 1.8nF V- PD_AMP ADAQ7980/ ADAQ7988 ADCN GND Figure 1. The ADAQ7980/ADAQ7988 contain a high accuracy, low power, 16-bit SAR ADC, a low power, high bandwidth, high input impedance ADC driver, a low power, stable reference buffer, and an efficient power management block. Housed within a tiny, 5 mm x 4 mm LGA package, these products simplify the design process for data acquisition systems. The level of system integration of the ADAQ7980/ADAQ7988 solves many design challenges, while the devices still provide the flexibility of a configurable ADC driver feedback loop to allow gain and/or common-mode adjustments. A set of four device supplies provides optimal system performance; however, single-supply operation is possible with minimal impact on device operating specifications. The ADAQ7980/ADAQ7988 integrate within a compact, integrated circuit (IC)-like form factor key components commonly used in data acquisition signal chain designs. The Module family transfers the design burden of component selection, optimization, and layout from designer to device, shortening overall design time, system troubleshooting, and ultimately improving time to market. Automated test equipment (ATE) Battery powered instrumentation Communications Data acquisition Process control Medical instruments GENERAL DESCRIPTION The ADAQ7980/ADAQ7988 are 16-bit analog-to-digital converter (ADC) Module(R) data acquisition systems that integrate four common signal processing and conditioning blocks into a system in package (SiP) design that supports a variety of applications. These devices contain the most critical passive components, eliminating many of the design challenges associated with traditional signal chains that use successive approximation register (SAR) ADCs. These passive components are crucial to achieving the specified device performance. Rev. A V+ REF REF_OUT 15060-001 FEATURES The serial peripheral interface (SPI)-compatible serial interface features the ability to daisy-chain multiple devices on a single, 3wire bus and provides an optional busy indicator. The user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic. Specified operation of these devices is from -55C to +125C. Table 1. Integrated SAR ADC Modules Type 16-Bit 500 kSPS ADAQ7988 1000 kSPS ADAQ7980 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADAQ7980/ADAQ7988 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Slew Enhancement ..................................................................... 33 Applications ....................................................................................... 1 Effect of Feedback Resistor on Frequency Response ............ 33 General Description ......................................................................... 1 Voltage Reference Input ............................................................ 33 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 35 Revision History ............................................................................... 2 Specifications..................................................................................... 3 LDO Regulator Current-Limit and Thermal Overload Protection .................................................................................... 36 Dual-Supply Configuration ........................................................ 3 LDO Regulator Thermal Considerations ............................... 36 Single-Supply Configuration ...................................................... 7 Digital Interface .......................................................................... 37 Timing Specifications ................................................................ 11 3-Wire CS Mode Without the Busy Indicator ........................ 38 Absolute Maximum Ratings .......................................................... 13 3-Wire CS Mode with the Busy Indicator ............................... 39 Thermal Data .............................................................................. 13 4-Wire CS Mode Without the Busy Indicator ........................ 40 Thermal Resistance .................................................................... 13 4-Wire CS Mode with the Busy Indicator ............................... 41 ESD Caution ................................................................................ 13 Chain Mode Without the Busy Indicator................................ 42 Pin Configuration and Function Descriptions ........................... 15 Chain Mode with the Busy Indicator ...................................... 43 Typical Performance Characteristics ........................................... 17 Application Circuits ....................................................................... 44 Terminology .................................................................................... 25 Nonunity Gain Configurations ................................................ 45 Theory of Operation ...................................................................... 26 Inverting Configuration with Level Shift ................................ 46 Circuit Information .................................................................... 26 Using the ADAQ7980/ADAQ7988 With Active Filters ........ 47 Converter Operation .................................................................. 26 Applications Information .............................................................. 48 Typical Connection Diagram.................................................... 27 Layout .......................................................................................... 48 ADC Driver Input ...................................................................... 28 Evaluating the Performance of the ADAQ7980/ADAQ7988 ... 48 Input Protection .......................................................................... 28 Outline Dimensions ....................................................................... 49 Noise Considerations And Signal Settling .............................. 28 Ordering Guide .......................................................................... 49 PD_AMP Operation .................................................................. 31 Dynamic Power Scaling (DPS) ................................................. 31 REVISION HISTORY 8/2017--Rev. 0 to Rev. A Changed Integrated Data Acquisition System to Module, Subsystem to Module Data Acquisition System, Subsystems to Module Data Acquisition Systems, and DAQ Subsystem to Module Data Acquisition System .............................. Throughout Changes to Features Section and Table 1 Title ............................. 1 Moved General Description Section .............................................. 3 Changes to General Description Section ...................................... 3 Change to 0.1 Hz to 10 Hz Voltage Noise Parameter Heading, Table 2 ................................................................................................ 4 Change to 0.1 Hz to 10 Hz Voltage Noise Parameter Heading, Table 4 .................................................................................................8 Changes to Human Body Model (HBM) Parameter and Endnote 4, Table 7 .......................................................................... 14 Change to Figure 27 Caption ........................................................ 21 Changes to Circuit Information Section ..................................... 27 Change to Table 15 Title ................................................................ 45 3/2017--Revision 0: Initial Version Rev. A | Page 2 of 49 ADAQ7980/ADAQ7988 Data Sheet SPECIFICATIONS DUAL-SUPPLY CONFIGURATION VDD = 3.5 V to 10 V, V+ = 6.3 V to 7.7 V, V- = -2.5 V to -0.2 V, VIO = 1.7 V to 5.5 V, VREF = 5 V, TA = -55C to +125C, ADC driver in a unity-gain buffer configuration, fSAMPLE = 1 MSPS (ADAQ7980), and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 2. Parameter RESOLUTION SYSTEM ACCURACY No Missing Codes Differential Nonlinearity Error (DNL) Integral Nonlinearity Error (INL) Transition Noise Gain Error Gain Error Temperature Drift Zero Error Zero Error Temperature Drift Common-Mode Rejection Ratio Power Supply Rejection Ratio Positive Negative SYSTEM AC PERFORMANCE Dynamic Range Test Conditions/Comments Min 16 16 -14 -20 Spurious-Free Dynamic Range Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio Effective Number of Bits Noise Free Code Resolution SYSTEM SAMPLING DYNAMICS Conversion Rate ADAQ7980 ADAQ7988 Transient Response -3 dB Input Bandwidth -1 dB Frequency -0.1 dB Frequency 0.1 Hz to 10 Hz Voltage Noise Aperture Delay Aperture Jitter 1 2 Max +14 +20 Unit Bits Bits ppm 1 ppm1 LSB1 rms %FS ppm/C mV V/C dB TA = 25C -0.01 TA = 25C -0.5 ADC driver configured as difference amplifier 103 7 8 0.6 0.002 0.1 0.06 0.3 130 V+ = +6.3 V to +8 V, V- = -2 V V+ = +7 V, V- = -1.0 V to -2.5 V 75 80 105 110 dB dB 92 87 44.4 111 91.5 86.5 106 -105 91 86 14.8 14.1 dB 2 dB2 V rms dB2 dB2 dB2 dB2 dB2 dB2 dB2 Bits Bits VREF = 2.5 V Total RMS Noise Oversampled Dynamic Range Signal-to-Noise Ratio (SNR) Typ Oversample dynamic range frequency (fODR) = 10 kSPS Input frequency (fIN) = 10 kHz fIN = 10 kHz, VREF = 2.5 V fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz, VREF = 2.5 V fIN = 10 kHz VIO 3.0 V VIO 1.7 V VIO 1.7 V Full-scale step ADC driver RC filter ADC driver RC filter ADC driver RC filter 90.5 84.5 90 84 14.65 0 0 0 430 4.42 2.2 0.67 17 2.0 2.0 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 V and 1 LSB = 15.26 ppm. All specifications in dB are referred to a full-scale input, FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. A | Page 3 of 49 +0.01 0.4 +0.5 1.3 -100 1 833 500 500 MSPS kSPS kSPS ns MHz MHz MHz V p-p ns ns ADAQ7980/ADAQ7988 Data Sheet VDD = 3.5 V to 10 V, V+ = 6.3 V to 7.7 V, V- = -2.5 V to -0.2 V, VIO = 1.7 V to 5.5 V, VREF = 5 V, TA = -55C to +125C, ADC driver in a unity-gain buffer configuration, and fSAMPLE = 1 MSPS (ADAQ7980) and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 3. Parameter REFERENCE Input Voltage Range Load Current Buffer Input Resistance Capacitance Bias Current Offset Voltage Offset Voltage Drift Voltage Noise Voltage Noise 1/f Corner Frequency Current Noise 0.1 Hz to 10 Hz Voltage Noise Linear Output Current Short-Circuit Current ADC DRIVER CHARACTERISTICS Voltage Range Absolute Input Voltage -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Input Voltage Noise 1/f Corner Frequency 0.1 Hz to 10 Hz Voltage Noise Input Current Noise Bias Offset Input Offset Voltage Drift Open-Loop Gain Input Resistance Common Mode Differential Mode Input Capacitance Input Common-Mode Voltage Range Output Overdrive Recovery Time Linear Output Current Short-Circuit Current DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) High (VIH) Test Conditions/Comments Min Voltage at REF pin REFOUT 2.4 REF REF TA = 25C fIN = 100 kHz fIN = 100 kHz REFOUT REFOUT sinking/sourcing IN+, IN-, AMP_OUT IN+, IN-, AMP_OUT ADCN G = +1, VAMP_OUT = 0.02 V p-p G = +1, VAMP_OUT = 2 V p-p G = +1, VAMP_OUT = 0.1 V p-p G = +1, VAMP_OUT = 2 V step G = +1, VAMP_OUT = 5 V step f = 100 kHz Typ Max Unit 5.1 330 V A 50 1 550 13 0.2 5.2 8 0.7 44 40 85/73 M pF nA V V/C nV/Hz Hz pA/Hz nV rms mA mA 0 -0.1 -0.1 800 125 1.3 VREF +5.1 +0.1 37 35 4 110 40 5.2 8 44 f = 100 kHz IN+, IN- 0.7 550 2.1 13 0.2 111 TA = 25C 800 125 1.3 V V V MHz MHz MHz V/s V/s nV/Hz Hz nV rms pA/Hz nA nA V V/C dB IN+, IN- IN+, IN- Specified performance VIN+ = 10% overdrive, fIN = 10 kHz 50 260 1 -0.1 -0.3 -0.3 0.7 x VIO 0.9 x VIO Rev. A | Page 4 of 49 +0.3 x VIO +0.1 x VIO VIO + 0.3 VIO + 0.3 V V V V 500 40 85/73 Sinking/sourcing VIO > 3.0 V VIO 3.0 V VIO > 3.0 V VIO 3.0 V V+ - 1.3V M k pF V ns mA mA Data Sheet ADAQ7980/ADAQ7988 Parameter Input Current Low (IIL) High (IIH) DIGITAL OUTPUTS Data Format Pipeline Delay Test Conditions/Comments VOL VOH POWER-DOWN SIGNALING ADC Driver/REF Buffer PD_AMP, PD_REF Voltage Low High Turn-Off Time ISINK = 500 A ISOURCE = -500 A Turn-On Time Dynamic Power Scaling Period Low Dropout (LDO) Regulator PD_LDO Voltage Low High PD_LDO Logic Hysteresis Turn-Off Time Turn-On Time POWER REQUIREMENTS VDD LDO Voltage Accuracy LDO Line Regulation LDO Load Regulation LDO Start-Up Time LDO Current-Limit Threshold LDO Thermal Shutdown Threshold Hysteresis LDO Dropout Voltage V+ V- VIO Total Standby Current 1, 2 ADAQ7980 Current Draw VIO V+/V- VDD Min Typ -1 -1 10 Powered down Enabled 1.06 1.15 2.2 F capacitive load 3.5 -0.8 -1.8 TJ rising ILDO_OUT = 10 mA ILDO_OUT = 100 mA 3.7 V+ - 10 1.7 Rev. A | Page 5 of 49 +1 +1 A A V V <2.2 >2.6 1.25 2.75 2 7.25 s s 1.12 1.22 100 460 370 1.18 1.30 650 425 V V mV s s 5 10 +0.8 +1.8 V % % +0.015 0.004 460 %/V %/mA s mA 1.2 56 14 60 420 V- + 10 +0.1 5.5 1.7 103 23 C C mV mV V V V mA A A 0.3 1.5 1.45 0.34 2.0 1.6 mA mA mA -0.015 250 Static, all devices enabled ADC driver, REF buffer disable ADC driver, REF buffer, LDO disable 1 MSPS Unit Serial 16 bits, straight binary Conversion results available immediately after completed conversion 0.4 VIO - 0.3 Powered down Enabled 50% of PD_AMP, PD_REF to <10% of enabled quiescent current Specified performance Specified performance ILDO_OUT = 10 mA, TA = 25C 100 A < ILDO_OUT < 100 mA, VDD = 3.5 V to 10 V VDD = 3.5 V to 10 V ILDO_OUT = 100 A to 100 mA VLDO_OUT = 2.5 V Max 0.002 380 360 150 15 30 200 7 -2 V V s ADAQ7980/ADAQ7988 Parameter ADAQ7980 Power Dissipation V+/V-/VDD Data Sheet Test Conditions/Comments 1 MSPS Min 1 kSPS, dynamic power scaling enabled 3 VIO Total ADAQ7988 Current Draw VIO V+/V- VDD ADAQ7988 Power Dissipation V+/V-/VDD Max Unit 20 5.8 1.0 21 36 9 1.9 37.9 4 mW mW mW mW 0.15 1.35 0.73 0.17 1.85 0.8 mA mA mA 16 5.8 0.5 16.5 26.5 9 0.95 27.54 mW mW mW mW +125 C 500 kSPS 1 kSPS, dynamic power scaling enabled3 VIO Total TEMPERATURE RANGE Specified Performance Typ TMIN to TMAX -55 With all digital inputs forced to VIO or GND as required. During the acquisition phase. 3 Dynamic power scaling duty cycle is 10%. 4 Calculated with the maximum supply differential and not the typical supply values. 1 2 Rev. A | Page 6 of 49 Data Sheet ADAQ7980/ADAQ7988 SINGLE-SUPPLY CONFIGURATION VDD = V+ = 5.0 V, V- = 0 V, VIO = 1.7 V to 5.5 V, VREF = 3.3 V, TA = -55C to +125C, the ADC driver in a unity-gain buffer configuration, and fSAMPLE = 1 MSPS (ADAQ7980) and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 4. Parameter RESOLUTION SYSTEM ACCURACY Differential Nonlinearity Error 1 Integral Nonlinearity Error1 Transition Noise Gain Error Gain Error Temperature Drift Zero Error Zero Error Temperature Drift Common-Mode Rejection Ratio Power Supply Rejection Ratio Positive SYSTEM AC PERFORMANCE Dynamic Range Total RMS Noise Oversampled Dynamic Range Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-Noise-and-Distortion Ratio Effective Number of Bits Noise Free Code Resolution SYSTEM SAMPLING DYNAMICS Conversion Rate ADAQ7980 ADAQ7988 Transient Response -3 dB Input Bandwidth -1 dB Frequency -0.1 dB Frequency 0.1 Hz to 10 Hz Voltage Noise Aperture Delay Aperture Jitter 1 2 3 Test Conditions/Comments Min 16 Typ Max Unit Bits -14 -20 +14 +20 103 7 8 0.8 0.002 0.1 0.06 0.35 133 ppm 2 ppm2 LSB2 rms %FS ppm/C mV V/C dB 75 92 dB 89 41.4 109 88.7 103 -113 88.4 14.4 13.5 dB 3 V rms dB3 dB3 dB3 dB3 dB3 Bits Bits TA = 25C -0.013 TA = 25C -0.5 V+ = 4.5 V to 5.5 V, V- = 0 V fODR = 10 kSPS Input frequency (fIN) = 10 kHz fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz fIN = 10 kHz VIO 3.0 V VIO 1.7 V VIO 1.7 V Full-scale step ADC driver RC filter ADC driver RC filter ADC driver RC filter 87.3 87 14.1 0 0 0 430 4.42 2.2 0.67 17 2.0 2.0 +0.013 0.4 +0.5 1.75 -100 1 833 500 500 Nonlinearity guaranteed over input voltage range. Codes below 150 mV are not represented with a unipolar supply configuration. LSB means least significant bit. With the 3.3 V input range, 1 LSB = 50.4 V, and 1 LSB = 15.26 ppm. All specifications in dB are referred to a full-scale input, FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. A | Page 7 of 49 MSPS kSPS kSPS ns MHz MHz MHz V p-p ns ns ADAQ7980/ADAQ7988 Data Sheet VDD = V+ = 5.0 V, V- = 0 V, VIO = 1.7 V to 5.5 V, VREF = 3.3 V, TA = -55C to +125C, the ADC driver in a unity-gain buffer configuration, and fSAMPLE = 1 MSPS (ADAQ7980) and fSAMPLE = 500 kSPS (ADAQ7988), unless otherwise noted. Table 5. Parameter REFERENCE Input Voltage Range Load Current Buffer Input Resistance Capacitance Bias Current Offset Voltage Offset Voltage Drift Voltage Noise Voltage Noise 1/f Corner Frequency Current Noise 0.1 Hz to 10 Hz Voltage Noise Linear Output Current Short-Circuit Current ADC DRIVER CHARACTERISTICS Specified Voltage Range Absolute Input Voltage -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Input Voltage Noise 1/f Corner Frequency 0.1 Hz to 10 Hz Voltage Noise Input Current Noise Bias Offset Input Offset Voltage Open-Loop Gain Input Resistance Common Mode Differential Mode Input Capacitance Input Common-Mode Voltage Range Output Overdrive Recovery Time Linear Output Current Short-Circuit Current DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) High (VIH) Test Conditions/Comments Min Voltage at REF pin REFOUT 2.4 REF REF TA = 25C fIN = 100kHz fIN = 100kHz REFOUT REFOUT sinking/sourcing IN+, IN-, AMP_OUT IN+, IN-, AMP_OUT ADCN G = +1, VAMP_OUT = 0.02 V p-p G = +1, VAMP_OUT = 2 V p-p G = +1, VAMP_OUT = 0.1 V p-p G = +1, VAMP_OUT = 2 V step G = +1, VAMP_OUT = 3.15 V step f = 100 kHz Typ Max Unit V+ - 1.3 330 V A 50 1 470 9 0.2 5.9 8 0.6 54 40 73/63 M pF nA V V/C nV/Hz Hz pA/Hz nV rms mA mA 0.15 -0.1 -0.1 720 125 1.5 VREF V+ - 1.3 +0.1 31 30 4 31 20 5.9 8 54 f = 100 kHz IN+, IN- 0.6 470 0.4 9 109 TA = 25C 720 125 V V V MHz MHz MHz V/s V/s nV/Hz Hz nV rms pA/Hz nA nA V dB IN+, IN- IN+, IN- Specified performance VIN+ = 10% overdrive, fIN = 10 kHz 50 260 1 -0.1 -0.3 -0.3 0.7 x VIO 0.9 x VIO Rev. A | Page 8 of 49 +0.3 x VIO +0.1 x VIO VIO + 0.3 VIO + 0.3 V V V V 800 40 73/63 Sinking/sourcing VIO > 3.0 V VIO 3.0 V VIO > 3.0 V VIO 3.0 V V+ - 1.3 M k pF V ns mA mA Data Sheet ADAQ7980/ADAQ7988 Parameter Input Current Low (IIL) High (IIH) DIGITAL OUTPUTS Data Format Pipeline Delay Test Conditions/Comments VOL VOH POWER-DOWN SIGNALING ADC Driver/Reference Buffer PD_AMP, PD_REF Voltage Low High Turn-Off Time ISINK = 500 A ISOURCE = -500 A Turn-On Time Dynamic Power Scaling Period LDO PD_LDO Voltage Low High PD_LDO Logic Hysteresis Turn-Off Time Turn-On Time POWER REQUIREMENTS VDD LDO Voltage Accuracy LDO Line Regulation LDO Load Regulation LDO Start-Up Time LDO Current-Limit Threshold LDO Thermal Shutdown Threshold Hysteresis LDO Dropout Voltage V+ V- VIO Total Standby Current 1, 2 ADAQ7980 Current Draw VIO V+/V- VDD Min Typ -1 -1 Max Unit +1 +1 A A Serial 16 bits straight binary Conversion results available immediately after completed conversion 0.4 VIO - 0.3 Powered down Enabled 50% of PD_AMP, PD_REF to <10% of enabled quiescent current Specified performance Specified performance 10 Powered down Enabled 1.06 1.15 2.2 F capacitive load ILDO_OUT = 10 mA, TA = 25C 100 A < ILDO_OUT < 100 mA, VDD = 3.5 V to 10 V VDD = 3.5 V to 10 V ILDO_OUT = 100 A to 100 mA VLDO_OUT = 2.5 V 3.5 -0.8 -1.8 -0.015 250 TJ rising ILDO_OUT = 10 mA ILDO_OUT = 100 mA 3.7 V+ - 10 1.7 Static, all devices enabled ADC driver, REF buffer disabled ADC driver, REF buffer, LDO disabled 1 MSPS Rev. A | Page 9 of 49 V V <1.5 >1.9 0.9 1.25 2 7.25 s s 1.12 1.22 100 460 370 1.18 1.30 V V mV s s 5 650 425 460 V % % %/V %/mA s mA 1.1 50 7 60 420 V- + 10 +0.1 5.5 1.7 103 23 C C mV mV V V V mA A A 0.3 1.3 1.45 0.34 2.0 1.6 mA mA mA 0.002 380 360 150 15 30 200 5 0 10 +0.8 +1.8 +0.015 0.004 V V s ADAQ7980/ADAQ7988 Parameter ADAQ7980 Power Dissipation V+/V-/VDD Data Sheet Test Conditions/Comments 1MSPS Min 1 kSPS, ADC driver dynamic power scaling enabled 3 VIO Total ADAQ7988 Current Draw VIO V+/V- VDD ADAQ7988 Power Dissipation V+/V-/VDD Max Unit 13.75 2.9 1.0 14.75 36 9 1.9 37.9 4 mW mW mW mW 0.15 1.15 0.73 0.17 1.85 0.8 mA mA mA 9.4 2.9 0.5 9.9 26.5 9 0.95 27.54 mW mW mW mW +125 C 500 kSPS 1 kSPS, ADC driver dynamic power scaling enabled3 VIO Total TEMPERATURE RANGE Specified Performance Typ TMIN to TMAX -55 With all digital inputs forced to VIO or GND as required. During the acquisition phase. 3 Dynamic power scaling duty cycle is 10%. 4 Calculated with the maximum supply differential and not the typical supply values. 1 2 Rev. A | Page 10 of 49 Data Sheet ADAQ7980/ADAQ7988 TIMING SPECIFICATIONS VDD = 3.5 V to 10 V, VIO = 1.7 V to 5.5 V, and TA = -55C to +125C, unless otherwise noted In addition to Figure 2 and Figure 3, see Figure 72, Figure 74, Figure 76, Figure 78, Figure 80, and Figure 82 for the additional timing diagrams detailed in Table 6. Table 6. Parameter CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE VIO Above 3.0 V (ADAQ7980) VIO Above 1.7 V (ADAQ7980) ADAQ7988 ACQUISITION PHASE 1 ADAQ7980 ADAQ7988 TIME BETWEEN CONVERSIONS VIO Above 3.0 V (ADAQ7980) VIO Above 1.7 V (ADAQ7980) VIO Above 1.7 V (ADAQ7988) CS MODE CNV Pulse Width SCK Period VIO Above 4.5 V VIO Above 3.0 V VIO Above 1.7 V CNV or SDI Low to SDO D15 MSB Valid VIO Above 3.0 V VIO Above 1.7 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance SDI Valid Hold Time from CNV Rising Edge VIO Above 3.0 V VIO Above 1.7 V CHAIN MODE SCK Period VIO Above 4.5 V VIO Above 3.0 V VIO Above 1.7 V SDI Valid Hold Time from CNV Rising Edge SCK Valid Setup Time from CNV Rising Edge SCK Valid Hold Time from CNV Rising Edge SDI Valid Setup Time from SCK Falling Edge SDI Valid Hold Time from SCK Falling Edge SDI High to SDO High (with Busy Indicator) VIO Above 3.0 V VIO Above 1.7 V SCK Low Time VIO Above 3.0 V VIO Above 1.7 V High Time VIO Above 3.0 V VIO Above 1.7 V Rev. A | Page 11 of 49 Symbol tCONV Min Max Unit 710 800 1200 290 800 ns ns ns ns ns ns 1000 1200 2000 ns ns ns 10 ns 10.5 12 22 ns ns ns 500 500 500 Typ tACQ tCYC tCNVH tSCK tEN 10 40 20 tDIS tHSDICNV ns ns ns 2 10 ns ns 11.5 13 23 0 5 5 2 3 ns ns ns ns ns ns ns ns tSCK tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 15 22 ns ns tSCKL 4.5 6 ns ns 4.5 6 ns ns tSCKH ADAQ7980/ADAQ7988 Data Sheet Parameter Falling Edge to Data Remains Valid Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3.0 V VIO Above 1.7 V SDI VALID SETUP TIME From CNV RISING EDGE Min 3 tSSDICNV Typ Max Unit ns 9.5 11 21 ns ns ns ns 5 The acquisition phase is the time available for the ADC sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1 MSPS. 500A IOL 1.4V TO SDO CL 20pF 500A 15060-002 IOH Figure 2. Load Circuit for Digital Interface Timing Y% VIO1 X% VIO1 tDELAY tDELAY VIH2 VIL2 VIH2 VIL2 1 FOR VIO 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30. 2 MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL SPECIFICATIONS IN TABLE 3 OR TABLE 5. Figure 3. Voltage Levels for Timing Rev. A | Page 12 of 49 15060-003 1 Symbol tHSDO tDSDO Data Sheet ADAQ7980/ADAQ7988 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 7. Thermal resistance values specified in Table 8 were calculated based on JEDEC specifications and must be used in compliance with JESD51-12. Because the product contains more than one silicon device, only the worst case junction temperature is reported. Parameter V+ to V- V+ to GND V- to GND VDD to GND REF_OUT/VIO to GND IN+/IN-/REF to GND AMP_OUT/ADCN to GND Differential Analog Input Voltage (IN+ - IN-) Digital Input1 Voltage to GND Digital Output2 Voltage to GND Input Current to Any Pin Except Supplies3, 4 Operating Temperature Range Storage Temperature Range Junction Temperature ESD Human Body Model (HBM) Field Induced Charged Device Model (FICDM) Rating 11 V -0.3 V to +11 V -11 V to +0.3 V -0.3 V to +24 V -0.3 V to +6 V V- - 0.7 V to V+ + 0.7 V -0.3 V to VREF + 0.3 V or 130 mA 1 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V 10 mA -55C to +125C -65C to +150C 150C 3500 V 1250 V The digital input pins include the following: CNV, SDI, and SCK. The digital output pin is SDO. 3 Transient currents of up to 100 mA do not cause SCR latch-up. 4 Condition applies when power is provided to the device. 1 2 Table 8. Thermal Resistance Package Type1, 2 CC-24-2 JA 65 JC TOP2 103 JT 12.6 Unit C/W These values represent the worst case die junction in the package. Table 8 values were calculated based on the standard JEDEC test conditions defined in Table 9, unless otherwise specified. 3 For JC test, 100 m thermal interface material (TIM) was used. TIM is assumed to be 3.6 W/mK. 1 2 Only use JA and JC TOP to compare thermal performance of the package of the device with other semiconductor packages when all test conditions listed are similar. One common mistake is to use JA and JC to estimate the junction temperature in the system environment. Instead, using JT is a more appropriate way to estimate the worst case junction temperature of the device in the system environment. First, take an accurate thermal measurement of the top center of the device (on the mold compound in this case) while the device operates in the system environment. This measurement is known in the following equation as TTOP. This equation can then be used to solve for the worst case TJ in that given environment as follows: TJ = JT x P + TTOP Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL DATA where: JT is the junction to top thermal characterization number as specified in data sheet. P refers to total power dissipation in the chip (W). TTOP refers to the package top temperature (C) and is measured at the top center of the package in the environment of the user. ESD CAUTION Absolute maximum ratings apply individually only, not in combination. The ADAQ7980/ADAQ7988 can be damaged when the junction temperature (TJ) limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature (TA) may have to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum TA can exceed the maximum limit as long as the junction temperature is within specification limits. The JA of the package is based on modeling and calculation using a 4-layer board. The JA is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The JA value may vary depending on PCB material, layout, and environmental conditions. Rev. A | Page 13 of 49 ADAQ7980/ADAQ7988 Data Sheet Table 9. Standard JEDEC Test Conditions Test Conditions Main Heat Transfer Mode Board Type Board Thickness Board Dimension Signal Traces Thickness PWR/GND Traces Thickness Thermal Vias Cold Plate JA Convection 2S2P 1.6 mm If package length is <27 mm, 76.2 mm x 114.3 mm; otherwise, 101.6 mm x 114.3 mm 0.07 mm 0.035 mm Use thermal vias with 0.3 mm diameter, 0.025 mm plating, and 1.2 mm pitch whenever a package has an exposed thermal pad; vias numbers are maximized to cover the area of the exposed paddle Not applicable JC Conduction 1S0P 1.6 mm If package length is <27 mm, 76.2 mm x 114.3 mm; otherwise, 101.6 mm x 114.3 mm 0.07 mm Not applicable Use thermal vias with 0.3 mm diameter, 0.025 mm plating, and 1.2 mm pitch whenever a package has an exposed thermal pad; vias numbers are maximized to cover the area of the exposed paddle Cold plate attaches to either package top or bottom depending on the path of least thermal resistance Rev. A | Page 14 of 49 JB Conduction 2S2P 1.6 mm If package length is <27 mm, 76.2 mm x 114.3 mm; otherwise, 101.6 mm x 114.3 mm 0.07 mm 0.035 mm Use thermal vias with 0.3 mm diameter, 0.025 mm plating, and 1.2 mm pitch whenever a package has an exposed thermal pad; vias numbers are maximized to cover the area of the exposed paddle Fluid cooled, ring style cold plate that clamps both sides of the test board such that heat flows from package radially in the plane of the test board Data Sheet ADAQ7980/ADAQ7988 20 19 18 4 TOP VIEW (Not to Scale) GND 5 6 7 8 9 10 11 12 LDO_OUT ADCN PD_AMP ADAQ7980/ ADAQ7988 GND 3 PD_REF AMP_OUT V- 2 GND 1 IN- GND IN+ 17 VIO 16 SDI 15 SCK 14 SDO 13 CNV 15060-004 21 GND 22 VDD V+ 23 PD_LDO REF 24 GND REF_OUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 5 to 7, 9, 18, 22 8 Mnemonic IN+ IN- AMP_OUT ADCN GND Type1 AI AI AI, AO AI P Description ADC Driver Noninverting Input. ADC Driver Inverting Input. ADC Driver Output and ADC Input Before Low-Pass Filter (LPF). Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. Ground. V- P 10 PD_REF DI 11 PD_AMP DI 12 LDO_OUT P 13 CNV DI 14 15 SDO SCK DO DI 16 SDI DI 17 VIO P 19 PD_LDO DI 20 VDD P Negative Power Supply Line for the ADC Driver. This pin requires a 100 nF capacitor to GND for best operation. Connect this pin to ground for single-supply operation. Active Low Power-Down Signal for Reference Buffer. When powered down, the reference buffer output enters a high impedance (high-Z) state. Active Low Power-Down Signal for ADC Driver. When powered down, the reference buffer output enters a high-Z state. Regulated 2.5 Output Voltage from On-Board LDO. An internal 2.2 F bypass capacitor to GND is provided. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, read the data when CNV is high. Serial Data Output. The conversion result is output on this pin. SDO synchronizes with SCK. Serial Data Clock Input. When the device is selected, the conversion result is shifted out onto SDO by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. When SDI is low during the CNV rising edge, chain mode is selected. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. When SDI is high during the CNV rising edge, CS mode is selected. In this mode, either SDI or CNV can enable the serial output signals when low; if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. VIO is nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Active Low Power-Down Signal for LDO. When powered down, the LDO output enters a high-Z state. For a continuously enabled state or for automatic startup, tie PD_LDO to the VDD pin (Pin 20). Regulator Input Supply. Bypass VDD to GND with a 2.2 F capacitor. Rev. A | Page 15 of 49 ADAQ7980/ADAQ7988 Pin No. 21 Mnemonic V+ Type1 P 23 REF AI 24 REF_OUT AO 1 Data Sheet Description Positive Power Supply Line for the ADC Driver and Reference Buffer. This pin can be tied to VDD as long as headroom for the reference buffer is maintained. This pin requires a 100 nF capacitor to GND for best operation. External Reference Signal. REF is the noninverting input of on-board reference buffer. Connect an external reference source to this pin. A low-pass filter may be required between the reference source and this pin to band limit noise generated by the reference source. Reference Buffer Output. This pin provides access to the buffered reference signal presented to the ADC. AI is analog input, AO is analog output, P is power, DI is digital input, and DO is digital output. Rev. A | Page 16 of 49 Data Sheet ADAQ7980/ADAQ7988 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3.5 V to 10 V, V+ = 6.3 V to 7.7 V, V- = -1.0 V to -2.5 V, VIO = 1.7 V to 5.5 V, VREF = 5 V, TA = 25C, ADC driver in a unity-gain buffer configuration, fSAMPLE = 1 MSPS (ADAQ7980), fSAMPLE = 500 kSPS (ADAQ7988), and fIN = 10 kHz, unless otherwise noted. 20 10 5 0 -5 -10 -20 0 10k 20k 30k 40k 50k 60k CODE 10 5 0 -5 -10 -15 -20 15060-105 -15 40k 50k 60k 20 10 5 0 -5 -10 22048 32048 42048 52048 62048 CODE Figure 6. Integral Nonlinearity vs. Code, V+ = VDD = 5 V, V- = 0 V, REF = 3.3 V POSITIVE DNL = 6.9ppm NEGATIVE DNL = -6.1ppm 10 5 0 -5 -10 -15 -20 2048 15060-106 12048 15 12048 22048 32048 42048 52048 62048 CODE 15060-109 POSITIVE INL = +7.8ppm NEGATIVE INL = -4.0ppm DIFFERENTIAL NONLINEARITY (ppm) INTEGRAL NONLINEARITY (ppm) 30k Figure 8. Differential Nonlinearity vs. Code, REF = 5 V -15 Figure 9. Differential Nonlinearity vs. Code, V+ = VDD = 5 V, V- = 0 V, REF = 3.3 V 0 0 SNR = 91.77dB SINAD = 91.56dB THD = -104.32dB SFDR = 105.08dBc -40 SNR = 86.87dB SINAD = 86.85dB THD = -110.10dB SFDR = 103.70dBc -20 AMPLITUDE (dB of FULL SCALE) -20 -60 -80 -100 -120 -140 -40 -60 -80 -100 -120 -140 -160 0 50k 100k 150k 200k 250k 300k 350k 400k 450k 500k FREQUENCY (Hz) 15060-107 AMPLITUDE (dB of FULL SCALE) 20k CODE 20 -20 2048 10k 0 Figure 5. Integral Nonlinearity vs. Code, REF = 5 V 15 POSITIVE DNL = 6.0ppm NEGATIVE DNL = -6.4ppm 15 Figure 7. FFT, REF = 5 V -160 0 50k 100k 150k 200k 250k 300k 350k 400k 450k 500k FREQUENCY (Hz) Figure 10. FFT, REF = 2.5 V Rev. A | Page 17 of 49 15060-110 INTEGRAL NONLINEARITY (ppm) DIFFERENTIAL NONLINEARITY (ppm) POSITIVE INL = +4.3ppm NEGATIVE INL = -5.8ppm 15 15060-108 20 ADAQ7980/ADAQ7988 180000 Data Sheet 100000 170828 TOTAL COUNT = 262144 TOTAL COUNT = 262144 160000 90000 140000 80000 70000 62761 COUNTS 100000 80000 52669 50000 40000 30000 21893 20580 20000 17 0 26242 426 ADC CODE Figure 11. Histogram of a DC Input at the Code Center, REF = 5 V Figure 14. Histogram of a DC Input at the Code Center, REF = 2.5 V 140000 -120 TOTAL COUNT = 262144 124157 -122 118166 120000 15060-114 3829 26238 349 26237 23 26236 1 26234 32785 32786 32787 32788 32789 32790 32791 32792 32793 ADC CODE 3857 0 26235 0 26232 0 26231 1 26230 454 15060-111 979 26240 10000 3 0 26233 20000 26241 37210 40000 26239 60000 60351 60000 26229 COUNTS 120000 0 88057 FFT SIZE = 65536 -124 NOISE FLOOR (dB) COUNTS 100000 80000 60000 40000 -126 -128 -130 -132 -134 -136 20000 10708 32790 32791 32792 32793 32794 ADC CODE -138 32795 76 0 32796 32797 -140 -10 -9 -7 -6 -5 -4 -2 -3 -1 0 INPUT LEVEL (dBFS) Figure 12. Histogram of a DC Input at the Code Transition, REF = 5 V 93 -8 15060-115 0 64 15060-112 8973 0 Figure 15. Noise Floor vs. Input Level 15.0 -95 115 -100 110 -105 105 -110 100 -115 95 92 14.8 14.5 89 14.4 14.3 88 SNR SINAD ENOB 87 86 2.4 14.2 14.0 2.9 3.4 3.9 4.4 4.9 REFERENCE (V) THD SFDR -120 90 14.1 -125 2.25 Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage 2.75 3.25 3.75 4.25 4.75 REFERENCE VOLTAGE (V) Figure 16. THD and SFDR vs. Reference Voltage Rev. A | Page 18 of 49 85 5.25 15060-116 90 THD (dB) 14.6 ENOB (Bits) 14.7 15060-113 SNR, SINAD (dB) 91 SFDR (dB) 14.9 ADAQ7980/ADAQ7988 -70 90 -80 85 -90 6 -100 80 SINAD THD 75 -110 10 100 FREQUENCY (kHz) Figure 17. SINAD and THD vs. Frequency -6 1 10 100 Figure 20. ADC Driver Small Signal Frequency Response for Various Gains 6 CLOSED-LOOP GAIN (dB) 91.5 91.0 90.5 3 0 -3 -6 -9 -15 5 25 45 65 85 105 125 TEMPERATURE (C) Figure 18. SNR and SINAD vs. Temperature V+ = +7V, V- = -2V V+ = +5V, V- = 0V -12 0.1 15060-118 -35 20mV p-p G = +1 1 10 100 FREQUENCY (MHz) 15060-123 SNR SINAD 92.0 Figure 21. ADC Driver Small Signal Frequency Response for Various Supply Voltages 3 -104.0 2V p-p G = +1 V+ = +7V V- = -2V -104.2 CLOSED-LOOP GAIN (dB) -104.4 -104.6 -104.8 -105.0 -105.2 -105.4 0 -3 -6 -105.8 -15 5 25 45 65 TEMPERATURE (C) Figure 19. THD vs. Temperature 85 105 125 15060-120 -35 -9 0.1 1 10 FREQUENCY (MHz) 100 15060-124 +125C +25C -40C -55C -105.6 -106.0 -55 G = +2 G = +1, RF = 0 G = -1 9 92.5 SNR, SINAD (dB) -3 FREQUENCY (MHz) 93.0 90.0 -55 0 -12 0.1 15060-117 1 3 -9 -120 70 V+ = +7V V- = -2V VOUT = 20mV p-p 15060-122 95 9 CLOSED-LOOP GAIN (dB) -60 THD (dB) 100 THD (dB) SINAD (dB) Data Sheet Figure 22. Large Signal Frequency Response for Various Temperatures Rev. A | Page 19 of 49 ADAQ7980/ADAQ7988 Data Sheet 5 9 CLOSED-LOOP GAIN (dB) 3 0 -3 +125C +85C +25C -40C -55C -9 -12 0.1 3 2 1 0 1 10 100 FREQUENCY (MHz) -1 0.1 20 V+ = +7V V- = -2V VOUT = 2V p-p 15 VOLTAGE NOISE (V) 10 0 -3 -6 5 0 -5 -10 G = +2 G = +1,RF = 0 G = -1 -12 0.1 1 -15 10 100 FREQUENCY (MHz) -20 0 1 5 6 7 8 9 10 800 G = +1 V+ = +7V V- = -2V V+ = +10V, V- = 0V V+ = +5V, V- = 0V QUIESCENT SUPPLY CURRENT (A) 750 3 0 -3 -6 20mV p-p 200mV p-p 500mV p-p 2V p-p 650 600 550 500 450 400 10 100 FREQUENCY (MHz) Figure 25. Frequency Response for Various Output Voltages 300 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 15060-130 1 700 350 15060-127 -12 0.1 4 Figure 27. 0.1 Hz to 10 Hz Voltage Noise 9 -9 3 TIME (Seconds) Figure 24. ADC Driver Large Signal Frequency Response for Various Gains 6 2 15060-227 -9 15060-126 CLOSED-LOOP GAIN (dB) 100 Figure 26. ADC Driver Small Signal 0.1 dB Bandwidth 6 CLOSED-LOOP GAIN (dB) 10 FREQUENCY (MHz) Figure 23. ADC Driver Small Signal Frequency Response for Various Temperatures 3 1 15060-128 -6 100mV p-p G = +1 V+ = 7V V- = -2V 4 15060-125 CLOSED-LOOP GAIN (dB) 6 20mV p-p G = +1 V+ = +7V V- = -2V Figure 28. ADC Driver and Reference Buffer Quiescent Supply Current vs. Temperature for Various Supplies Rev. A | Page 20 of 49 Data Sheet ADAQ7980/ADAQ7988 1200 ADC DRIVER DYNAMIC POWER SCALING TURN ON TIME (ns) 0.4 0.3 0.2 0.1 1 2 3 4 5 6 7 8 9 10 OVERLOAD DURATION (s) Figure 29. Recovery Time vs. Overload Duration -80 -100 PHASE -120 20 -140 0 10M SUPPLY CURRENT (A) 60 1M 8 9 V- = 0V V+ = 10V V+ = 5V V+ = 4V 400 300 200 -180 100M 0 0 1 2 3 4 6 Figure 33. Supply Current vs. ADC Driver and Reference Buffer Turn-Off Response Time for Various Supplies 800 V- = 0V VREF = 3.3V 700 100 800 600 400 V+ = 5V V- = 0V +125C +25C -40C fS = 100kSPS SUPPLY CURRENT (A) 1200 5 TIME (s) 1400 V+ = 10V V+ = 7V V+ = 5V 10 500 100 Figure 30. ADC Driver Open-Loop Gain and Phase vs. Frequency 600 500 400 300 200 100 200 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 125 0 15060-231 ADC DRIVER DYNAMIC POWER SCALING TURN-ON TIME (ns) 7 600 -160 FREQUENCY (Hz) 0 -55 6 SUPPLY (V) 700 -40 100k 5 4 -20 -60 10k 200 0 15060-132 OPEN-LOOP GAIN (dB) GAIN 1k 400 800 80 100 600 0 OPEN-LOOP PHASE (Degrees) 100 -20 10 800 Figure 32. ADC Driver Dynamic Power Scaling Turn On Time vs. Supply Voltage 120 40 V- = 0V VREF = 3.3V 1000 15060-242 0 15060-229 0 fS = 100kSPS Figure 31. ADC Driver Dynamic Power Scaling Turn-On Time vs. Temperature for Various Supply Voltages 0 1 2 3 TIME (s) 4 5 6 15060-235 RECOVERY TIME (s) G = +1 V+ = +7V V- = -2V 0.5 VIN = 10% OVERDRIVE 15060-233 0.6 Figure 34. Supply Current vs. ADC Driver and Reference Buffer Turn-Off Response Time for Various Temperatures Rev. A | Page 21 of 49 ADAQ7980/ADAQ7988 -40 -60 CMRR -80 +PSRR -100 -120 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 30 10 -10 -30 -50 -55 15060-138 -140 50 -15 5 25 45 65 85 105 125 TEMPERATURE (C) Figure 35. CMRR and PSRR vs. Frequency Figure 38. Reference Buffer Input Offset Voltage vs. Temperature 4.0 1.5 1.4 3.5 fSAMPLE = 0Hz 1.3 DEVICE ENABLED SUPPLY CURRENT (mA) POWER-DOWN THRESHOLD (V) -35 3.0 TA = +125C TA = +25C TA = -40C 2.5 2.0 1.5 DEVICE DISABLED 1.2 1.1 1.0 0.9 0.8 V+ = 10V V+ = 5V V+ = 3.8V 0.7 1.0 0.6 SUPPLY VOLTAGE FROM GROUND (V) 0.5 -55 15060-139 0.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 15060-142 CMRR, PSRR (dB) -20 70 15060-141 0 90 V+ = 5V, V- = 0V V+, VCM = 100mV p-p REFERENCE BUFFER OFFSET VOLTAGE (V) 20 Data Sheet Figure 39. ADC Driver and Reference Buffer Static Supply Current vs. Temperature for Various Supplies Figure 36. ADC Driver and Reference Buffer Power-Down Threshold vs. Supply Voltage from Ground for Various Temperatures 1.9 0.0025 1.7 0.0010 1.5 1.3 1.1 0.9 V+ = 10V V+ = 5V V+ = 3.8V 0.0005 0.7 0 -55 -35 -15 5 25 45 65 85 TEMPERATURE (C) Figure 37. Gain Error vs. Temperature 105 125 0.5 -55 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 125 15060-143 SUPPLY CURRENT (mA) 0.0015 15060-140 GAIN ERROR (% FS) 0.0020 Figure 40. ADC Driver and Reference Buffer Dynamic Supply Current vs. Temperature for Various Supplies Rev. A | Page 22 of 49 Data Sheet ADAQ7980/ADAQ7988 3.5 TOTAL OPERATING CURRENT (mA) fSAMPLE = 0Hz PD CURRENT (mA) 0.015 0.010 PD CURRENT 10V SUPPLY DELTA PD CURRENT 5V SUPPLY DELTA PD CURRENT 3.8V SUPPLY DELTA 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) Figure 41. Total ADC Driver and Reference Buffer Power-Down (PD) Current vs. Temperature 2.5 2.0 1.5 1.0 0.5 0 15060-144 0.005 V+ = 10V, V- = 0V V+ = 7.7V, V- = 0V V+ = 5V, V- = 0V V+ = 3.8V, V- = 0V 3.0 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k SAMPLE RATE (SPS) 15060-245 0.020 Figure 44. Total Operating Current vs. Sample Rate for Various Supplies 2.60 0.05 OFFSET ERROR V+ = +7V, V- = -2V OFFSET ERROR V+ = +5V, V- = 0V 0.03 LDO_OUT (V) OFFSET ERROR (mV) 2.55 0.01 -0.01 2.50 2.45 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 2.40 -55 15060-145 -0.05 -55 -35 -15 5 45 25 65 85 105 125 TEMPERATURE (C) 15060-148 -0.03 Figure 45. Output Voltage (LDO_OUT) vs. Temperature Figure 42. Offset Error vs. Temperature 2.55 1.6 1.4 2.53 LDO_OUT (V) LDO DYNAMIC CURRENT 10V INPUT LDO STATIC CURRENT 10V INPUT 1.0 0.8 0.6 2.51 2.49 0.4 2.47 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 2.45 0 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT (mA) Figure 46. Output Voltage (LDO_OUT) vs. Load Current (ILOAD) Figure 43. LDO Current vs. Temperature for Various Supplies Rev. A | Page 23 of 49 15060-149 0.2 15060-146 LDO CURRENT (mA) 1.2 ADAQ7980/ADAQ7988 Data Sheet 2.55 2.60 ILOAD = 100mA ILOAD = 10mA ILOAD = 1mA ILOAD = 100mA ILOAD = 10mA ILOAD = 1mA 2.55 2.53 LDO_OUT (V) LDO_OUT (V) 2.50 2.51 2.49 2.45 2.40 2.47 5 6 7 8 10 9 VDD (V) 2.30 2.50 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 VDD (V) Figure 47. Output Voltage (LDO_OUT) vs. VDD Figure 50. LDO_OUT vs. VDD in Dropout, LDO_OUT = 2.5 V -10 0.0020 fSAMPLE = 0Hz -20 VDD = 5V V+ = 5V V- = 0V VIN = 0.5 V p-p -30 0.0015 ISOLATION (dB) LDO PD CURRENT (mA) 2.55 15060-251 4 15060-248 2.45 2.35 0.0010 -40 -50 -60 -70 0.0005 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 0.20 LDO DROPOUT VOLTAGE (V) 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.01 ILOAD (mA) 0.1 15060-250 0.02 0.001 0.1 1 10 FREQUENCY (MHz) Figure 51. Forward/Off Isolation vs. Frequency Figure 48. LDO PD Current vs. Temperature 0 0.0001 -90 0.01 Figure 49. LDO Dropout Voltage vs. Load Current (ILOAD), LDO_OUT = 2.5 V Rev. A | Page 24 of 49 100 15060-154 0 -55 15060-151 -80 Data Sheet ADAQ7980/ADAQ7988 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. Calculate it as follows: Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels (dB). Zero Error The first transition occurs at a level 1/2 LSB above analog ground (38.1 V for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 ... 10 to 111 ... 11) occurs for an analog voltage 11/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINADdB - 1.76)/6.02 ENOB is expressed in bits. Noise Free Code Resolution = log2(2N/Peak to Peak Noise) Noise free code resolution is expressed in bits. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels (dB). It is measured with a signal at -60 dBFS to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels (dB). Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels (dB). Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. A | Page 25 of 49 ADAQ7980/ADAQ7988 Data Sheet THEORY OF OPERATION IN+ MSB LSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SW+ C REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C LSB SW- CNV 15060-055 MSB IN- Figure 52. ADC Simplified Schematic CIRCUIT INFORMATION The ADAQ7980/ADAQ7988 system in package (SiP) is a fast, low power, precise data acquisition (DAQ) signal chain that uses a SAR architecture. The Module data acquisition system contains a high bandwidth, analog-to-digital converter (ADC) driver, a low noise reference buffer, a low dropout regulator (LDO), and a 16-bit SAR ADC, along with critical passive components required to achieve optimal performance. All active components in the circuit are designed by Analog Devices, Inc. The ADAQ7980/ADAQ7988 are capable of converting 1,000,000 samples per second (1 MSPS) and 500,000 samples per second (500 kSPS), respectively. The ADC powers down between conversions; therefore, power consumption scales with sample rate. The ADC driver and reference buffer are capable of dynamic power scaling, where the power consumption of these components scales with sample rate. When operating at 1 kSPS, for example, the ADAQ7980/ADAQ7988 consume 2.9 mW typically, ideal for battery-powered applications. The ADAQ7980/ADAQ7988 offer a significant form factor reduction compared to traditional signal chains while still providing flexibility to adapt to a wide array of applications. All three signal pins of the ADC driver are available to the user, allowing various amplifier configurations. The devices house the LPF between the driver and the ADC, controlling the signal chain bandwidth and providing a bill of materials reduction. The ADAQ7980/ADAQ7988 do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. The ADAQ7980/ADAQ7988 house a reference buffer and the corresponding decoupling capacitor. The placement of this decoupling capacitor is vital to achieving peak conversion performance. Inclusion of this capacitor in the Module data acquisition system eliminates this performance hurdle. The reference buffer is configured for unity gain. By only including the reference buffer, the user has the flexibility to choose the reference buffer input voltage that matches the desired analog input range. The ADAQ7980/ADAQ7988 interface to any 1.8 V to 5 V digital logic family. They are housed in a tiny 24-lead LGA that provides significant space savings and allows flexible configurations. CONVERTER OPERATION The ADAQ7980/ADAQ7988 contain a successive approximation ADC based on a charge redistribution digital-to-analog converter (DAC). Figure 52 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via the internal switches (SW+ and SW-). All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the ADC inputs. When the acquisition phase is completed and the CNV input goes high, a conversion phase initiates. When the conversion phase begins, SW+ and SW- open first. The two capacitor arrays are then disconnected from the ADC input and connected to the GND input. Therefore, the differential voltage between the ADC input pins captured at the end of the acquisition phase are applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 ... VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the devices return to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator signaling the user that the conversion is complete. Because the ADAQ7980/ADAQ7988 have an on-board conversion clock, the serial clock (SCK) is not required for the conversion process. Rev. A | Page 26 of 49 Data Sheet ADAQ7980/ADAQ7988 Transfer Functions Table 11. Output Codes and Ideal Input Voltages The ideal transfer characteristics for the ADAQ7980/ADAQ7988 are shown in Figure 53 and Table 11. Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR 111 ... 110 111 ... 101 1 2 3 The ADAQ7980/ADAQ7988 ADC driver in the unity-gain buffer configuration. This is also the code for an overranged analog input (IN+ - IN- above VREF - VGND). This is also the code for an underranged analog input (IN+ - IN- below VGND). TYPICAL CONNECTION DIAGRAM 000 ... 010 Figure 54 shows an example of the recommended connection diagram for the ADAQ7980/ADAQ7988 when multiple supplies are available. 000 ... 001 -FSR -FSR + 1LSB -FSR + 0.5LSB +FSR - 1 LSB +FSR - 1.5 LSB ANALOG INPUT Figure 53. ADC Ideal Transfer Function POSITIVE SUPPLY 100nF 2.2F REF1 V+ REF REF_OUT LDO_OUT PD_REF 2 LDO 2.2F 10F 0V TO VREF IN+ 20 IN- VDD ADC PD_LDO 2 VIO 1.8V TO 5V SDI SCK 100nF SDO AMP_OUT CNV 1.8nF V- PD_AMP 2 ADCN GND 100nF NEGATIVE SUPPLY 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2POWER DOWN PINS CONNECTED TO EITHER DIGITAL HOST OR POSITIVE SUPPLY. Figure 54. Typical Application Diagram with Multiple Supplies Rev. A | Page 27 of 49 15060-057 000 ... 000 15060-056 ADC CODE (STRAIGHT BINARY) 111 ... 111 VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 V 0V Analog Input1 Digital Output Code (Hex) 0xFFFF2 0x8001 0x8000 0x7FFF 0x0001 0x00003 ADAQ7980/ADAQ7988 Data Sheet ADC DRIVER INPUT The ADC driver of the ADAQ7980/ADAQ7988 features a -3 dB bandwidth of 35 MHz and a slew rate of 110 V/s at G = +1 and VAMP_OUT = 2 V step. It features an input voltage noise of 5.9 nV/Hz .The driver can operate over a supply voltage range of 3.8 V to 10 V and consumes only 500 A of supply current at a supply difference of 5 V. The low end of the supply range allows -5% variation of a 4 V supply. The amplifier is unity-gain stable, and the input structure results in an extremely low input voltage noise 1/f corner. The ADC driver uses a slew enhancement architecture, as shown in Figure 55. The slew enhancement circuit detects the absolute difference between the two inputs. It then modulates the tail current, ITAIL, of the input stage to boost the slew rate. The architecture allows a higher slew rate and a faster settling time with a low quiescent current while maintaining low noise. The user has access to all three amplifier signal pins, providing flexibility to adapt to the desired application or configuration. SLEW ENHANCEMENT CIRCUIT ITAIL TO DETECT ABSOLUTE VALUE VIN- IN+ 15060-058 IN- INPUT STAGE The ESD clamps begin to conduct for input voltages that are more than 0.7 V above the positive supply and input voltages more than 0.7 V below the negative supply. If an overvoltage condition is expected, the input current must be limited to less than 10 mA. Along with the ADC driver inputs, protection is also provided on the ADC input. As shown in Figure 1, the ADAQ7980/ADAQ7988 house an RC filter between the ADC driver and the ADC. The series resistor in this low-pass filter acts to limit current in an overvoltage condition. The current sink capability of the reference buffer works to hold the reference node at its desired value when the ADC input protection diodes conduct due to an overvoltage event. Figure 57 shows an equivalent ADC analog input circuit of the ADAQ7980/ADAQ7988. The two diodes, D1 and D2, provide ESD protection for the ADC inputs. Take care to ensure that the ADC analog input signal never exceeds the reference value by more than 0.3 V or drops below ground by more than 0.3 V because this causes diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current greater than or equal to the short-circuit current of the ADC driver. For instance, these conditions can occur when the ADC driver positive supply is greater than the reference value. In such a case (for example, an input buffer with a short circuit), use the current limitation to protect the devices. V+ VIN+ External series input resistors that are sized appropriately for the expected differential overvoltage can provide the needed protection. Figure 55. ADC Driver Slew Enhancement Circuit REF INPUT PROTECTION V+ BIAS ESD ESD IN- ESD 15060-059 V- TO THE REST OF THE AMPLIFIER CPIN RIN CIN D2 GND Figure 57. Equivalent ADC Analog Input Circuit The analog input structure allows the sampling of the true differential signal between the ADC input pins. By using these differential inputs, signals common to both inputs are rejected. NOISE CONSIDERATIONS AND SIGNAL SETTLING ESD IN+ D1 IN+ OR IN- 15060-060 The amplifier is fully protected from ESD events, withstanding human body model ESD events of 4000 V and field induced charged device model events of 1250 V with no measured performance degradation. The precision input is protected with an ESD network between the power supplies and diode clamps across the input device pair, as shown in Figure 56. Figure 56. ADC Driver Input Stage and Protection Diodes For differential voltages more than approximately 1.2 V at room temperature and 0.8 V at 125C, the diode clamps begin to conduct. If large differential voltages must be sustained across the input terminals, the current through the input clamps must be limited to less than 10 mA. The ADC driver of the ADAQ7980/ADAQ7988 is ideal for driving the on-board high resolution SAR ADC. The low input voltage noise and rail-to-rail output stage of the driver helps to minimize distortion at large output levels. With its low power of 500 A, the amplifier consumes power that is compatible with the low power SAR ADC. Furthermore, the ADC driver supports a single-supply configuration; the input common-mode range extends to the negative supply, and 1.3 V below the positive supply. Rev. A | Page 28 of 49 Data Sheet ADAQ7980/ADAQ7988 1k Figure 58 illustrates the primary noise contributors for the typical gain configurations. The total output noise (vn_out) is the root sum square of all the noise contributions. vn_RG = 4kTRG + vn_out - in- 15060-061 RS vn_RS = 4kTRS in+ 100 10 SOURCE RESISTANCE = 47k SOURCE RESISTANCE = 2.6k Figure 58. Noise Sources in Typical Connection Calculate the output noise spectral density of the ADC driver by 1 100 vn _ out = 1k 10k 100k 1M SOURCE RESISTANCE () 2 [ ] Figure 59. RTI Noise vs. Source Resistance 2 R R 4kTRF + 1 + F 4kTRs + in + 2 RS 2 + vn2 + F 4kTRG + in -2 RF 2 RG RG where: k is the Boltzmann constant. T is the absolute temperature in degrees Kelvin. RF and RG are the feedback network resistances, as shown in Figure 58. RS is the source resistance, as shown in Figure 58. in+ and in- represent the amplifier input current noise spectral density in pA/Hz. vn is the amplifier input voltage noise spectral density in nV/Hz. For more information on these calculations, see MT-049 and MT-050. Source resistance noise, amplifier input voltage noise (vn), and the voltage noise from the amplifier input current noise (in+ x RS) are all subject to the noise gain term (1 + RF/RG). Figure 59 shows the total referred to input (RTI) noise due to the amplifier vs. the source resistance. Note that with a 5.9 nV/Hz input voltage noise and 0.6 pA/Hz input current noise, the noise contributions of the amplifier are relatively small for source resistances from approximately 2.6 k to 47 k. The Analog Devices, Inc., silicon germanium (SiGe) bipolar process makes it possible to achieve a low voltage noise. This noise is much improved compared to similar low power amplifiers with a supply current in the range of hundreds of microamperes. 15060-062 RG RTI NOISE (nV/Hz) vn_RF = 4kTRF RF vn TOTAL NOISE SOURCE RESISTANCE NOISE AMPLIFIER NOISE Keep the noise generated by the driver amplifier, and its associated passive components, as low as possible to preserve the SNR and transition noise performance of the ADAQ7980/ ADAQ7988. The analog input circuit of the ADAQ7980/ ADAQ7988 features a one-pole, low-pass filter to band limit the noise coming from the ADC driver. Because the typical noise of the ADAQ7980/ADAQ7988 is 44.4 V rms in the dual-supply typical configuration, the SNR degradation due to the amplifier is SNRLOSS 44.4 = 20 log 2 2 44.4 + f -3 dB (Ne N ) 2 where: f-3 dB is the cutoff frequency of the input filter (4.4 MHz). N is the noise gain of the amplifier (for example, 1 in a buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/Hz. For multichannel multiplexed applications, the analog input circuit of the ADAQ7980/ADAQ7988 must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm) within one conversion period. As shown in Figure 20, the bandwidth of the ADC driver changes with the gain setting implemented. The ADC driver must maintain a sufficient bandwidth to allow the ADC input to settle properly. The RC time constant of the low-pass filter of the ADAQ7980/ADAQ7988 has been set to settle the anticipated SAR ADC charge redistribution voltage step from a full-scale ADC input voltage transition within the minimum acquisition phase of the ADC. The maximum full-scale step is based upon the maximum reference input voltage of 5.1 V. The reference sets the maximum analog input range and subsequently the range of voltages that the ADC can quantize. Rev. A | Page 29 of 49 ADAQ7980/ADAQ7988 Data Sheet During the conversion process, the capacitive DAC of the SAR ADC disconnects from the ADC input. In a multiplexed application, the multiplexer input channel switches during the conversion time to provide the maximum settling time. At the end of the conversion time, the capacitive DAC then connects back to the input. During this time, the DAC is disconnected from the ADC input, and a voltage change occurs at the ADC input node. The voltage step observed at the ADC analog input resulting from capacitive charge redistribution attenuates due to the voltage divider created by the parallel combination of the capacitive DAC and the capacitor in the external low-pass filter. Calculate the voltage step by The method previously described assumes the multiplexer switches shortly after the conversion begins and that the amplifier and RC have a large enough bandwidth to sufficiently settle the lowpass filter capacitor before acquisition begins. During forward settling, approximately 11 time constants are required to settle a full-scale step to 16 bits. For the low-pass RC filter housed in the ADAQ7980/ADAQ7988, the forward settling time of the filter is 11 x 36 ns 400 ns, which is much less than the conversion time of 710 ns/1200 ns, respectively. To achieve an ADC driver forward settling time of less than 710 ns, maintain an ADC driver large signal bandwidth of 2.49 MHz. Calculate this as follows: VSTEP = (VREF x 30 pF)/(30 pF + 1800 pF) = VREF x 0.016 For a 5.0 V reference, this results in a maximum step size of 82 mV. To calculate the required filter and ADC driver bandwidth, determine the number of time constants required to settle this voltage step within the ADC acquisition phase as follows: With the number of time constants known, determine the RC time constant () by = 290 ns/NTC. The minimum acquisition phase of the ADC is 290 ns. Signals must be fully settled within this acquisition period. Calculate the filter bandwidth (BW) by BW = 1/(2 x ). The ADC driver small signal bandwidth must always remain greater than or equal to the bandwidth previously calculated. When the small signal bandwidth reduces, for example in the presence of a large voltage gain, increase the acquisition phase to increase the required system . An increase in acquisition phase results in a reduction of the maximum sample rate. Minimum ADC Driver Large Signal Bandwidth = 1/(2 x 64 ns) = 2.49 MHz The forward settling does not necessarily have to occur during the conversion time (before the capacitive DAC gets switched to the input), but the combined forward and reverse settling time must not exceed the required throughput rate. Forward settling is less important for low frequency inputs because the rate of change of the signal is much lower. The importance of which bandwidth specification of the ADC driver is used is dependent upon the type of input. Focus high frequency (>100 kHz) or multiplexed applications on the large signal bandwidth, and concentrate lower input frequency applications on the ADC driver small signal bandwidth when performing the previous calculations. ADC THROUGHPUT tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION MUX CHANNEL SWITCH POSITIVE FS ADC INPUT CAPACITIVE DAC SWITCH TO ACQUIRE NEGATIVE FS FORWARD SETTLING REVERSE SETTLING Figure 60. Multiplexed Application Timing Rev. A | Page 30 of 49 15060-063 N TC VSTEP = ln V REF 16 +1 2 ADC Driver Forward Settling Time Constant = 710 ns/ln(216) = 64 ns Data Sheet ADAQ7980/ADAQ7988 PD_AMP OPERATION DYNAMIC POWER SCALING (DPS) Figure 61 shows the ADC driver and reference buffer shutdown circuitry. To maintain a low supply current in shutdown mode, no internal pull-up circuitry exists; therefore, drive the PD_AMP pin high or low externally and do not leave it floating. Pulling the PD_AMP pin to 1 V below midsupply turns the device off, reducing the supply current to 2.9 A for a 5 V supply. When the amplifier powers down, its output enters a high impedance state. The output impedance decreases as frequency increases. In shutdown mode, a forward isolation of -62 dB can be achieved at 100 kHz (see Figure 51). One of the merits of a SAR ADC is that its power scales with the sampling rate. This power scaling makes SAR ADCs very power efficient, especially when running at lower sampling frequencies. Traditionally, the ADC driver associated with the SAR ADC consumes constant power, regardless of the sampling frequency. The ADC driver allows dynamic power scaling. This feature allows the user to provide a periodic signal to the powerdown pin of the ADC driver that is synchronized to the convert start signal, thus scaling the system power consumption with the sample rate. Figure 62 illustrates the method by which the sampling rate of the system dynamically scales the quiescent power of the ADC driver. By providing properly timed signals to the convert start (CNV) pin of the ADC and the PD_AMP pins of the ADC driver, both devices run at optimum efficiency. 2.2 1.1V ESD PD_AMP 1.8 TO ENABLE AMPLIFIER V- 15060-073 ESD V+ REF REF_OUT LDO_OUT VDD 10F LDO 2.2F PD_REF Figure 61. Shutdown Circuit ESD clamps protect the PD_AMP pin, as shown in Figure 61. Voltages beyond the power supplies cause these diodes to conduct. To protect the PD_AMP pin, ensure that the voltage to this pin does not exceed 0.7 V above the positive supply or 0.7 V below the negative supply. If expecting an overvoltage condition, limit the input current to less than 10 mA with a series resistor. Table 12 summarizes the threshold voltages for the powered down and enabled modes for various supplies. For any supply voltage, pulling the PD_AMP pin to 1 V below midsupply turns the device off. Table 12. Threshold Voltages for Powered Down and Enabled Modes Mode Enabled Powered Down +4 V/0 V >+1.4 V <+1.0 V V+/V- +5 V/0 V >+1.9 V <+1.5 V +7 V/-2 V >+1.9 V <+1.5 V 20 IN+ IN- ADC PD_LDO VIO SDI SCK SDO AMP_OUT 1.8nF CNV ADAQ7980/ ADAQ7988 V- PD_AMP ADCN GND TIMING GENERATOR 15060-065 V+ Figure 62. Power Management Circuitry Figure 63 illustrates the relative signal timing for power scaling the ADC driver and the ADC. To prevent degradation in the performance of the ADC, the ADC driver must have a fully settled output into the ADC before the activation of the CNV pin. In this example, the amplifier is switched to full power mode 3 s prior to the rising edge of the CNV signal. The PD_AMP pin of the ADC driver is pulled low when the ADC input is inactive in between samples. The quiescent current of the amplifier typically falls to 10% of the normal operating value within 0.9 s at a supply difference of 5 V. While in shutdown mode, the ADC driver output impedance is high. Rev. A | Page 31 of 49 ADAQ7980/ADAQ7988 Data Sheet SAMPLING FREQUENCY = 100kHz tS = 10s ACQUISITION ACQUISITION CONVERSION ACQUISITION CONVERSION CONVERSION ADC MODE CNV POWERED ON PD_AMP SHUTDOWN POWERED ON POWERED ON SHUTDOWN SHUTDOWN tAMP, ON MINIMUM POWERED ON TIME = 3s 3s 3s Vf3 Vf 1 Vf 2 tf1 tTURNOFF1 tf2 tTURNOFF2 tTURNOFF3 tf3 15060-066 ADC DRIVER OUTPUT Figure 63. Timing Waveforms PQ = IQ x VS With power scaling, the quiescent power becomes proportional to the ratio of the amplifier on time (tAMP, ON) and the sampling time (tS). PQ = IQ x VS x (tAMP, ON/tS) 1.2 PD_AMP ON TIME = 3s V+ = 5V V- = 0V 1.0 QUIESCENT CURRENT (mA) Figure 64 shows the quiescent power of the ADC driver with and without the power scaling. Without power scaling, the amplifier constantly consumes power regardless of the sampling frequency, as shown in the following equation. 0.8 0.6 AMP QUIESCENT CURRENT NO DPS AMP QUIESCENT CURRENT WITH DPS ADC CURRENT DRAW 0.4 Thus, by dynamically switching the driver between shutdown and full power modes during the sample period, the quiescent power of the driver scales with the sampling rate. 0 1 10 100 1k 10k SAMPLING FREQUENCY (fS) 100k 1M 15060-067 0.2 Figure 64. Quiescent Current of the ADC Driver vs. ADC Sampling Frequency Rev. A | Page 32 of 49 Data Sheet ADAQ7980/ADAQ7988 SLEW ENHANCEMENT VOLTAGE REFERENCE INPUT The ADC driver has an internal slew enhancement circuit that increases the slew rate as the feedback error voltage increases. This circuit improves the amplifier settling response for a large step, as shown in Figure 65. This improvement in settling response is useful in applications where the multiplexing of multiple input signals occurs. The ADAQ7980/ADAQ7988 voltage reference input (REF) is the noninverting node of the on-board low noise reference buffer. The reference buffer is included to optimally drive the dynamic input impedance of the SAR ADC reference node. Also housed in the ADAQ7980/ADAQ7988 is a 10 F decoupling capacitor that is ideally laid out within the devices. This decoupling capacitor is a required piece of the SAR architecture. The REF_OUT capacitor is not just a bypass capacitor. This capacitor is part of the SAR ADC that simply cannot fit on the silicon. 2.5 2V p-p 1V p-p 500mV p-p OUTPUT VOLTAGE (V) 2.0 During the bit decision process, because the bits are settled in a few 10s of nanoseconds or faster, the storage capacitor replenishes the charge of the internal capacitive DAC. As the binary bit weighted conversion is processed, small chunks of charge are taken from the 10 F capacitor. The internal capacitor array is a fraction of the size of the decoupling capacitor, but this large value storage capacitor is required to meet the SAR bit decision settling time. 1.5 1.0 0.5 -0.5 0 20 40 60 80 100 120 15060-266 0 140 TIME (ns) Figure 65. Step Response with Selected Output Steps EFFECT OF FEEDBACK RESISTOR ON FREQUENCY RESPONSE The amplifiers input capacitance and feedback resistor form a pole that, for larger value feedback resistors, can reduce phase margin and contribute to peaking in the frequency response. Figure 66 shows the peaking for 500 feedback resistors (RF) when the amplifier is configured in a gain of +2. Figure 66 also shows how peaking can mitigate with the addition of a small value capacitor placed across the feedback resistor of the amplifier. 9 G = +2 RF, RG = 500 VOUT = 200mV p-p 0pF 8pF CLOSED-LOOP GAIN (dB) 6 3 There is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF_OUT and GND pins. The reference value sets the maximum ADC input voltage that the SAR capacitor array can quantize. The reference buffer is set in the unity-gain configuration; therefore, the user sets the reference voltage value with the REF pin and observes this value at the REF_OUT pin. The user is responsible for selecting a reference voltage value that is appropriate for the system under design. Allowable reference values range from 2.4 V to 5.1 V; however, do not violate the input common-mode voltage range specification of the reference buffer. With the inclusion of the reference buffer, the user can implement a much lower power reference source than many traditional SAR ADC signal chains because the reference source drives a high impedance node instead of the dynamic load of the SAR capacitor array. Root sum square the reference buffer noise with the reference source noise to arrive at a total noise estimate. Generally, the reference buffer has a noise density much less than that of the reference source. 0 ADAQ7980 BUFFER -3 RG 1 10 100 FREQUENCY (MHz) OPTIONAL FILTER Figure 66. Peaking Mitigation in Small Signal Frequency Response ADC 15060-072 -6 0.1 15060-267 VOLTAGE REFERENCE Figure 67. Voltage Reference with RC Filtering As shown in Figure 67, place a passive, RC low-pass filter with a very low cutoff frequency between the reference source and the REF pin of the ADAQ7980/ADAQ7988 to band limit noise from the reference source. Rev. A | Page 33 of 49 ADAQ7980/ADAQ7988 Data Sheet ESD clamps protect the PD_REF pin, as shown in Figure 68. Voltages beyond the power supplies cause these diodes to conduct. To protect the PD_REF pin, ensure that the voltage to this pin does not exceed 0.7 V above the positive supply or 0.7 V below the negative supply. When expecting an overvoltage condition, limit the input current to less than 10 mA with a series resistor. Table 13 summarizes the threshold voltages for the powered down and enabled modes for various supplies. For any supply voltage, pulling the PD_REF pin to 1 V below midsupply turns the device off. This filtering can be useful, considering the voltage reference source is usually the dominant contributor to the noise of the reference input circuit. Filters with extremely low bandwidths can be used since the reference signal is a dc type signal. However, because with such low frequency cutoffs, the settling time at power on is quite large. For example, a single pole, lowpass filter with a -3 dB bandwidth of 20 Hz has a time constant of approximately 8 ms. Just like the ADC driver, the reference buffer features a PD_REF pin that allows the user to control the power consumption of the ADAQ7980/ADAQ7988. A timing scheme similar to Figure 63 can be implemented for the PD_REF pin. Also, use the PD_REF feature during long idle periods where extremely low power consumption is desired. Table 13. Threshold Voltages for Powered Down and Enabled Modes Mode Enabled Powered Down Figure 68 shows the reference buffer shutdown circuitry. To maintain very low supply current in shutdown mode, do not supply the internal pull-up resistor; therefore, the drive PD_REF pin high or low externally and do not leave it floating. Pulling the PD_REF pin to 1 V below midsupply turns the device off, reducing the supply current to 2.9 A for a 5 V supply. When the amplifier powers down, its output enters a high impedance state. The output impedance decreases as frequency increases. In shutdown mode, a forward isolation of -80 dB can be achieved at frequencies below 10 kHz (see Figure 51). The sample rate of each individual converter determines the number of ADAQ7980/ADAQ7988 references that can be chained together. Each ADAQ7980/ADAQ7988 SAR ADC reference consumes 330 A of load current at a reference input of 5 V and with the converter running at 1 MSPS. This current consumption scales linearly with sample rate. For example, reducing the sample rate to 100 kSPS reduces the reference current draw to 33 A. The active reference buffer must regulate the cumulative current draw well enough so that the reference voltage does not change by more than 1/2 of an LSB. An unperceived change in reference value manifests as a gain error. 2.2 ESD PD_REF ESD TO ENABLE AMPLIFIER 15060-064 V- Figure 68. Reference Buffer Shutdown Circuit ADAQ7980/ ADAQ7988 ADAQ7980/ ADAQ7988 ADAQ7980/ ADAQ7988 DEVICE 1 DEVICE 2 DEVICE 3 BUFFER BUFFER BUFFER RG RG RG VOLTAGE REFERENCE ADC OPTIONAL FILTER PD_REF 1 POWERED ON ADC PD_REF 2 POWERED OFF ADC PD_REF 3 POWERED OFF Figure 69. Reference Configuration for Multiple ADAQ7980/ADAQ7988 Devices Rev. A | Page 34 of 49 15060-074 1.8 +7 V/-2 V >+1.9 V <+1.5 V If more than one ADAQ7980/ADAQ7988 is used in a system, for example, in a daisy-chain configuration, it is possible to use the reference buffer of one ADAQ7980/ADAQ7988 to provide the REF_OUT signal for multiple ADAQ7980/ADAQ7988 devices. Enabling the PD_REF pin of the reference buffer places the reference buffer output in a high impedance state. The active reference buffer can drive the subsequent REF_OUT nodes. See Figure 69 for connection details. V+ 1.1V V+/V- +5 V/0 V >+1.9 V <+1.5 V +4 V/0 V >+1.4 V <+1.0 V Data Sheet ADAQ7980/ADAQ7988 POWER SUPPLY The recommended single-supply, power-down sequence follows: Power supply bypassing is a critical aspect in the performance of the ADC driver. A parallel connection of capacitors from each amplifier power supply pin (V+ and V-) to ground works best. Smaller value ceramic capacitors offer improved high frequency response, whereas larger value ceramic capacitors offer improved low frequency performance. 1. 2. 3. 4. The ADAQ7980/ADAQ7988 feature two other power supply pins: the input to the LDO regulator that supplies the ADC (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.0 V. The ADAQ7980/ ADAQ7988 are independent of power supply sequencing between VIO and VDD. It is recommended to provide power to VIO and VDD prior to V+ and V-. In addition, while not required, it is recommended to place the ADC driver and reference buffer in power-down by applying a logic low to the PD_AMP and PD_REF pins during the power-on sequence of the ADAQ7980/ ADAQ7988. The following are the recommended sequences for applying and removing power to the Module data acquisition systems. The recommended dual-supply, power-on sequence follows: 1. 2. 3. 4. 5. 6. Apply a logic low to PD_AMP, PD_REF, and PD_LDO. Apply a voltage to VIO. Apply a voltage to VDD. Apply a logic high to PD_LDO. Apply a voltage to V+ and V-. Apply a logic high to PD_AMP and PD_REF. The recommended single-supply, power-on sequence follows: 1. 2. 3. 4. 5. Apply a logic low to PD_AMP, PD_REF, and PD_LDO. Apply a voltage to VIO. Apply a voltage to VDD and V+. Apply a logic high to PD_LDO. Apply a logic high to PD_AMP and PD_REF. The recommended dual-supply, power-down sequence follows: 1. 2. 3. 4. 5. Apply a logic low to PD_AMP and PD_REF. Remove the voltage from V+ and V-. Apply a logic low to PD_LDO. Remove the voltage from VDD. Remove the voltage from VIO. 80 75 70 65 60 55 1 10 100 FREQUENCY (kHz) 1000 15060-075 Place the smallest value capacitor on the same side of the board as the ADAQ7980/ADAQ7988 and as close as possible to the amplifier power supply pins. Connect the ground end of the capacitor directly to the ground plane. Additionally, the ADAQ7980/ADAQ7988 are insensitive to power supply variations over a wide frequency range, as shown in Figure 70. PSRR (dB) Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided with a low ac impedance across a wide band of frequencies. Parralleling is important for minimizing the coupling of noise into the amplifier--especially when the amplifier PSRR begins to roll off--because the bypass capacitors can help lessen the degradation in PSRR performance. Apply a logic low to PD_AMP and PD_REF. Apply a logic low to PD_LDO. Remove the voltage from V+ and VDD. Remove the voltage from VIO. Figure 70. PSRR vs. Frequency The VDD input is the input of an on-board LDO regulator that supplies 2.5 V to the SAR ADC. By housing an LDO regulator, the ADAQ7980/ADAQ7988 provide a wide supply range to the user. When operating these devices in a single-supply configuration, tie the V+ and VDD pins together and connect the V- pin to ground. Refer to Table 4 for the full list of operating requirements associated with a single-supply system. The LDO regulator of the ADAQ7980/ADAQ7988 is a 2.5 V, low quiescent current, linear regulator that operates from 3.5 V to 10 V and provides up to 100 mA of output current. The LDO regulator draws a low 180 A of quiescent current (typical) at full load. The typical shutdown current consumption is less than 3 A at room temperature. Typical start-up time for the LDO regulator is 380 s. The ADAQ7980/ADAQ7988 require a small 2.2 F ceramic capacitor connected between the VDD pin and ground. Any quality ceramic capacitors can be used as long as they meet the minimum capacitance and maximum equivalent series resistance (ESR) requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V to 100 V are recommended. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. Rev. A | Page 35 of 49 ADAQ7980/ADAQ7988 Data Sheet Internally, the LDO regulator consists of a reference, an error amplifier, a feedback voltage divider, and a positive metal-oxide semiconductor (PMOS) pass transistor. The PMOS pass device, which is controlled by the error amplifier, delivers the output current. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device pulls lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device pulls higher, allowing less current to pass and decreasing the output voltage. Consider the case where a hard short circuit from LDO_OUT to ground occurs. At first, the LDO regulator limits the current threshold that can be conducted into the short circuit. If self heating of the junction is enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135C, the output turns on and conducts the current limit into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between the maximum current and 0 mA that continues as long as the short circuit remains at the output. The LDO regulator uses the PD_LDO pin to enable and disable the LDO_OUT pin under normal operating conditions. When PD_LDO is high, LDO_OUT turns on, and when PD_LDO is low, LDO_OUT turns off. For automatic startup, tie PD_LDO to VDD. Only apply a logic low to PD_LDO if a logic low is applied to PD_AMP and PD_REF as well. Current-limit and thermal limit protections protect the device against accidental overload conditions. For reliable operation, externally limit the power dissipation of the devices so that the junction temperature does not exceed 125C. LDO REGULATOR CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The current and thermal overload protection circuits protect the LDO regulator of the ADAQ7980/ADAQ7988 against damage due to excessive power dissipation. The LDO regulator current limits when the output load reaches 360 mA (typical). When the output load exceeds the current limit threshold, the output voltage reduces to maintain a constant current limit. Thermal overload protection is included, which limits the LDO regulator junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and/or high power dissipation), when the junction temperature starts to rise above 150C, the output turns off, reducing the output current to zero. When the junction temperature drops below 135C, the output turns on again, and the output current restores to its operating value. LDO REGULATOR THERMAL CONSIDERATIONS In applications with a low, input to output voltage differential, the LDO regulator does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough to cause the junction temperature of the die to exceed the specified junction temperature of 125C. When the junction temperature exceeds 150C, the LDO regulator enters thermal shutdown. It recovers only after the junction temperature decreases below 135C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions. To guarantee specified operation, the junction temperature of the LDO regulator must not exceed 125C. To ensure that the junction temperature stays below this value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds used and the amount of material used to solder the package GND pins to the PCB. Rev. A | Page 36 of 49 Data Sheet ADAQ7980/ADAQ7988 DIGITAL INTERFACE Though the ADAQ7980/ADAQ7988 have a reduced number of pins, they offer flexibility in their serial interface modes. The ADAQ7980/ADAQ7988, when in CS mode, are compatible with SPI, QSPITM, and digital hosts. This interface can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This independence is useful in low jitter sampling or simultaneous sampling applications. The ADAQ7980/ADAQ7988, when in chain mode, provide a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which these devices operate depends on the SDI level when the CNV rising edge occurs. To select CS mode, set SDI high, and to select chain mode, set SDI low. The SDI hold time is such that when SDI and CNV are connected together, chain mode is selected. In either mode, the ADAQ7980/ADAQ7988 offer the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator enables * * Rev. A | Page 37 of 49 In CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 74 and Figure 78). In chain mode if SCK is high during the CNV rising edge (see Figure 82). ADAQ7980/ADAQ7988 Data Sheet When CNV goes low, the MSB is output onto SDO. Then, the remaining data bits clock out by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture data, a digital host using the SCK falling edge allows a faster reading rate if it has an acceptable hold time. After the 16th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. 3-WIRE CS MODE WITHOUT THE BUSY INDICATOR To connect a single ADAQ7980/ADAQ7988 to an SPI-compatible digital host, use 3-wire CS mode without the busy indicator. Figure 71 shows the connection diagram, and Figure 72 shows the corresponding timing. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. After a conversion initiates, it continues until completion irrespective of the state of CNV, which is useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers. However, before the minimum conversion time elapses, return CNV high and then hold it high for the maximum conversion time to avoid the generation of a busy signal indicator. When the conversion completes, the ADAQ7980/ADAQ7988 enter the acquisition phase and power down. CONVERT DIGITAL HOST CNV VIO SDI ADAQ7980/ ADAQ7988 SDO DATA IN 15060-076 SCK CLK Figure 71. 3-Wire CS Mode Without the Busy Indicator Connection Diagram (SDI = 1, High) SDI = 1 tCYC tCNVH CNV tCONV ACQUISITION tACQ CONVERSION ACQUISITION tSCK tSCKL 2 3 14 tHSDO 16 tSCKH tEN SDO 15 tDSDO D15 D14 D13 tDIS D1 D0 Figure 72. 3-Wire CS Mode Without the Busy Indicator Serial Interface Timing (SDI = 1, High) Rev. A | Page 38 of 49 15060-077 1 SCK Data Sheet ADAQ7980/ADAQ7988 When the conversion completes, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, use this transition as an interrupt signal to initiate the data reading controlled by the digital host. The ADAQ7980/ADAQ7988 then enter the acquisition phase and power down. The data bits clock out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate if it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. 3-WIRE CS MODE WITH THE BUSY INDICATOR To connect a single ADAQ7980/ADAQ7988 to an SPI-compatible digital host that has an interrupt input, use 3-wire CS mode with the busy indicator. Figure 73 shows the connection diagram, and Figure 74 shows the corresponding timing. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. SDO stays in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, use CNV to select other SPI devices, such as analog multiplexers; however, return CNV to low before the minimum conversion time elapses and then hold it low for the maximum conversion time to guarantee the generation of the busy signal indicator. If selecting multiple ADAQ7980/ADAQ7988 devices at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. CONVERT VIO CNV SDI ADAQ7980/ ADAQ7988 SDO DIGITAL HOST 47k DATA IN SCK IRQ CLK 15060-078 VIO Figure 73. 3-Wire CS Mode with the Busy Indicator Connection Diagram (SDI = 1, High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO SDO D15 D14 D1 D0 Figure 74. 3-Wire CS Mode with the Busy Indicator Serial Interface Timing (SDI = 1, High) Rev. A | Page 39 of 49 15060-079 SCK ADAQ7980/ADAQ7988 Data Sheet When the conversion completes, the ADAQ7980/ADAQ7988 enter the acquisition phase and power down. Bringing the SDI input low reads each ADC result, which consequently outputs the MSB onto SDO. Then, the remaining data bits clock out by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate if it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another ADAQ7980/ADAQ7988 can be read. 4-WIRE CS MODE WITHOUT THE BUSY INDICATOR To connecting multiple ADAQ7980/ADAQ7988 devices to an SPI-compatible digital host, use 4-wire CS mode without the busy indicator. Figure 75 shows a connection diagram example using two ADAQ7980/ADAQ7988 devices, and Figure 76 shows the corresponding timing. With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, hold CNV high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, use SDI to select other SPI devices, such as analog multiplexers; however, return SDI to high before the minimum conversion time elapses and then hold it high for the maximum conversion time to avoid the generation of the busy signal indicator. CS2 CS1 CONVERT CNV SDI DIGITAL HOST ADAQ7980/ ADAQ7988 SDO SCK SCK 15060-080 SDI CNV ADAQ7980/ ADAQ7988 SDO DATA IN CLK Figure 75. 4-Wire CS Mode Without the Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL SCK 2 3 14 tHSDO SDO 15 16 17 18 30 31 32 tSCKH tEN tDIS tDSDO D15 D14 D13 D1 D0 D15 D14 Figure 76. 4-Wire CS Mode Without the Busy Indicator Serial Interface Timing Rev. A | Page 40 of 49 D1 D0 15060-081 1 Data Sheet ADAQ7980/ADAQ7988 With a pull-up resistor on the SDO line, use this transition as an interrupt signal to initiate the data readback controlled by the digital host. The ADAQ7980/ADAQ7988 then enter the acquisition phase and power down. The data bits clock out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate if it has an acceptable hold time. After the optional 17th SCK falling edge, or SDI going high, whichever is earlier, the SDO returns to high impedance. 4-WIRE CS MODE WITH THE BUSY INDICATOR To connect a single ADAQ7980/ADAQ7988 to an SPI-compatible digital host that has an interrupt input, and when keeping CNV, which samples the analog input, independent of the signal used to select the data reading, use 4-wire CS mode with the busy indicator. This requirement is particularly important in applications where low jitter on CNV is a requirement. Figure 77 shows the connection diagram, and Figure 78 shows the corresponding timing. With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, hold CNV high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, use SDI to select other SPI devices, such as analog multiplexers; however, return SDI low before the minimum conversion time elapses and then hold it low for the maximum conversion time to guarantee the generation of the busy signal indicator. When the conversion completes, SDO goes from high impedance to low impedance. CS1 CONVERT VIO CNV DIGITAL HOST 47k DATA IN SCK IRQ CLK Figure 77. 4-Wire CS Mode with the Busy Indicator Connection Diagram tCYC CNV tCONV ACQUISITION tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO tEN SDO D15 D14 D1 Figure 78. 4-Wire CS Mode with the Busy Indicator Serial Interface Timing Rev. A | Page 41 of 49 D0 15060-083 1 SCK 15060-082 SDI ADAQ7980/ ADAQ7988 SDO Data Sheet ADAQ7980/ADAQ7988 In this mode, hold CNV high during the conversion phase and the subsequent data readback. When the conversion completes, the MSB is output onto SDO, and the ADAQ7980/ADAQ7988 enter the acquisition phase and power down. The remaining data bits stored in the internal shift register clock out by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and it clocks out by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more ADAQ7980/ADAQ7988 devices in the chain, if the digital host has an acceptable hold time. The total readback time can reduce the maximum conversion rate. CHAIN MODE WITHOUT THE BUSY INDICATOR To daisy-chain multiple ADAQ7980/ADAQ7988 devices on a 3-wire serial interface, use chain mode without the busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. Figure 79 shows a connection diagram example using two ADAQ7980/ADAQ7988 devices, and Figure 80 shows the corresponding timing. When SDI and CNV are low, drive SDO low. With SCK low, a rising edge on CNV initiates a conversion, selects chain mode, and disables the busy indicator. CONVERT CNV ADAQ7980/ SDO ADAQ7988 SDI DIGITAL HOST ADAQ7980/ SDO ADAQ7988 A SCK DATA IN B SCK 15060-084 SDI CNV CLK Figure 79. Chain Mode Without the Busy Indicator Connection Diagram SDIA = 0 tCYC CNV tCONV ACQUISITION tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 2 3 15 tSSDISCK tHSCKCNV 16 17 18 30 31 32 DA 1 DA 0 tSCKH tHSDISCK tEN SDOA = SDIB 14 DA15 DA14 DA13 DA1 DA0 DB 1 DB0 tHSDO SDOB DB15 DB14 DB13 DA15 DA14 Figure 80. Chain Mode Without the Busy Indicator Serial Interface Timing Rev. A | Page 42 of 49 15060-085 tDSDO ADAQ7980/ADAQ7988 Data Sheet In this mode, hold CNV high during the conversion phase and the subsequent data readback. When all ADCs in the chain complete their conversions, drive the SDO pin of the ADC closest to the digital host (see the ADAQ7980/ADAQ7988 ADC labeled C in Figure 81) high. Use this transition on SDO as a busy indicator to trigger the data readback controlled by the digital host. The ADAQ7980/ ADAQ7988 then enter the acquisition phase and power down. The data bits stored in the internal shift register clock out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and clocks out by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 x N + 1 clocks are required to read back the N ADCs. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently, more ADAQ7980/ADAQ7988 devices in the chain, if the digital host has an acceptable hold time. CHAIN MODE WITH THE BUSY INDICATOR To daisy-chain multiple ADAQ7980/ADAQ7988 devices on a 3-wire serial interface while providing a busy indicator, use chain mode with the busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. Figure 81 shows a connection diagram example using three ADAQ7980/ADAQ7988 devices, and Figure 82 shows the corresponding timing. When SDI and CNV are low, drive SDO low. With SCK high, a rising edge on CNV initiates a conversion, selects chain mode, and enables the busy indicator feature. CONVERT SDI CNV SDI CNV ADAQ7980/ ADAQ7988 SDO SDI DIGITAL HOST ADAQ7980/ ADAQ7988 SDO A B C SCK SCK SCK DATA IN IRQ 15060-086 CNV ADAQ7980/ ADAQ7988 SDO CLK Figure 81. Chain Mode with the Busy Indicator Connection Diagram tCYC CNV = SDIA tCONV tACQ ACQUISITION CONVERSION ACQUISITION tSCK tSCKH SCK 1 tHSCKCNV 2 3 4 15 16 17 tSSDISCK DA15 SDOA = SDIB DA14 DA13 19 31 32 33 34 35 tSCKL tHSDISCK tEN 18 DA1 tDSDOSDI DB15 DB14 DB13 DB1 DB0 DA15 DA14 DA1 DA0 DC15 DC14 DC13 DC1 DC0 DB15 DB14 DB1 DB0 tDSDOSDI SDOC 49 DA0 tDSDO SDOB = SDIC 48 tDSDOSDI tHSDO tDSDOSDI 47 tDSDODSI Figure 82. Chain Mode with Busy Indicator Serial Interface Timing Rev. A | Page 43 of 49 DA15 DA14 DA1 DA0 15060-087 tSSCKCNV ADAQ7980/ADAQ7988 Data Sheet APPLICATION CIRCUITS Table 14 provides recommended component values at various gains and the corresponding slew rate, bandwidth, and noise of a given configuration. As shown in Figure 83, the noise gain, GN, of an op amp gain block is equal to its noninverting voltage gain, regardless of whether it is actually used for inverting or noninverting gain. Thus, Noninverting GN = RF/RG + 1 Inverting GN = RF/RG + 1 RS 1 RF 1k RG 249 + - RF 1k - RG 249 NONINVERTING G = -4 GN = +5 INVERTING 15060-088 + G = GN = +5 Figure 83. Noise Gain of Both Equals 5 With the ADC driver, a variety of trade-offs can be made to fine tune its dynamic performance. As with all high speed amplifiers, parasitic capacitance and inductance around the amplifier can affect its dynamic response. Often, the input capacitance (due to the op amp itself, as well as the PCB) has a significant effect. The feedback resistance, together with the input capacitance, can contribute to a loss of phase margin, thereby affecting the high frequency response. A capacitor (CF) in parallel with the feedback resistor can compensate for this phase loss. Additionally, any resistance in series with the source creates a pole with the input capacitance (as well as dampen high frequency resonance due to package and board inductance and capacitance). It must also be noted that increasing resistor values increases the overall noise of the amplifier and that reducing the feedback resistor value increases the load on the output stage, thus increasing distortion. The ADC driver, which has no crossover region, has a wide linear input range from 100 mV below ground to 1.3 V below positive rail. The amplifier, when configured as a follower, has a linear signal range from 150 mV above the negative supply voltage (limited by the output stage of the amplifier) to 1.3 V below the positive supply (limited by the amplifier input stage). If the supply differential between V+ and V- is less than 5 V, the linear range of the ADC driver is reduced from 150 mV above the negative supply voltage to 200 mV above the minus supply voltage. A 0 V to +4.096 V signal range can be accommodated with a positive supply as low as +5.4 V and a negative power supply of -0.2 V. If ground is used as the amplifier negative supply, at the low end of the input range close to ground, the ADC driver exhibits substantial nonlinearity, as with any railto-rail output amplifier. The amplifier drives a one-pole, low-pass filter. This filter limits the already very low noise contribution from the amplifier to the SAR ADC. Table 14. Recommended Component Values Noise Gain, Noninverting Gain 1 1.25 2 5 RS () 49.9 49.9 49.9 49.9 RF () 49.9 249 499 1k RG () Not applicable 1k 499 249 CF (pF) Not applicable 8 8 8 Table 15. ADAQ7980/ADAQ7988 Performance at Selected Input Frequency with 5 V Reference Value Input Frequency (kHz) 1 10 20 50 100 ADC Driver Gain 1 1 1 1 1 SNR (dB) 91.9 91.5 90.7 88.3 84.5 Rev. A | Page 44 of 49 THD (dB) -106.1 -105.0 -103.6 -99.7 -93.3 Results SINAD (dB) 91.5 91.0 90.1 87.6 83.3 ENOB 14.9 14.8 14.7 14.2 13.5 Data Sheet ADAQ7980/ADAQ7988 NONUNITY GAIN CONFIGURATIONS The total output voltage error is the sum of errors due to the amplifier offset voltage and input currents. Estimate the output error due to the offset voltage by the following: Figure 84 shows a typical connection diagram and the major dc error sources. The ideal transfer function (all error sources set to 0 and infinite dc gain) can be written as R R VOUT = 1 + F x VIP - F R G RG x VIN VOUTERROR = VCM VP - VPNOM VOUT RF + + VOFFSETNOM + x 1+ CMRR PSRR A RG (1) RF where: + VOS - which is measured with the input and output at midsupply. VCM is the common-mode voltage. VP is the power supply voltage. RS 15060-089 - VIP + VOFFSETNOM is the offset voltage at the specified supply voltage, + VOUT - IB- IB+ VpNOM is the specified power supply voltage. Figure 84. Typical ADC Driver Connection Diagram and DC Error Sources CMRR is the common-mode rejection ratio. PSRR is the power supply rejection ratio. A is the dc open-loop gain. This function reduces to the following familiar forms for noninverting and inverting op amp gain expressions. R VOUT = 1 + F xVIP R G Estimate the output error due to the input currents by the following: (2) VOUTERROR = (Noninverting gain, VIN = 0 V) xVIN R R (RF || RG ) x 1+ F I B- - RS x 1+ F x I B+ RG RG (3) (Inverting gain, VIP = 0 V) (5) Note that setting RS equal to RF||RG compensates for the voltage error due to the input bias current. Figure 85 shows the ADC driver noninverting gain connection. The circuit was tested with multiple gain settings and an output voltage of approximately 5 V p-p for optimum resolution and noise performance. POSITIVE SUPPLY REF V+ REF1 REF_OUT 100nF LDO_OUT - RF VOUT = RG PD_REF 2.2F LDO 2.2F 10F PD_LDO 49.9 50 49.9 VIO 1.8V TO 5V IN+ 20 IN- SDI SCK ADC AMP_OUT SDO RF 499 CNV 1.8nF ADAQ7980/ ADAQ7988 RG 499 OPTIONAL CF 100nF V- PD_AMP ADCN GND 100nF NEGATIVE SUPPLY Figure 85. Noninverting ADC Driver, Gain = 2 Rev. A | Page 45 of 49 15060-090 RG VDD - VIN + (4) ADAQ7980/ADAQ7988 Data Sheet Table 16. Typical Ambient Temperature Performance for the ADAQ7980/ADAQ7988 for Various Gain Configurations (fIN = 10 kHz) Gain (V/V) -1 -0.25 1 2 SNR (dB) 88.3 90.6 91.5 89.7 THD (dB) -103.4 -96.9 -105 -103.9 SINAD (dB) 88.0 90.2 91.0 89.3 The typical ambient temperature results are listed Table 16. INVERTING CONFIGURATION WITH LEVEL SHIFT Configuration of the ADAQ7980/ADAQ7988 to acquire bipolar inputs is possible. For example, the device configuration can be made such that 10 V signals can fit the 0 V to VREF volt input range. In this example, because a 20 V p-p signal is fit to a smaller peak-to-peak input range, an inverting configuration must be selected. Attenuation of the input signal requires an inverting configuration. This configuration results in an 180o phase shift due to the inversion. With the SAR ADC input range being unipolar, a level shift must be performed to fit a bipolar signal into the unipolar input of the ADC. This level shift is performed using a difference amplifier configuration. The resistor ratios selected for the difference amplifier depend upon the peak-to-peak voltage of the bipolar input signal and the reference voltage being used for the Module data acquisition sysem that sets the full scale of the ADC conversion range. R RT REF 1 F R R S T RG ENOB (Bits) 14.3 14.7 14.8 14.5 For both noninverting and inverting gain configurations, it is often useful to increase the RF value to decrease the load on the output. Increasing the RF value improves harmonic distortion at the expense of reducing the bandwidth of the amplifier. Note that as the gain increases, the small signal bandwidth decreases, as is expected from the gain bandwidth product relationship. In addition, the phase margin improves with higher gains, and the amplifier becomes more stable. As a result, the peaking in the frequency response is reduced. The PCB layout configuration and bond pads of the chip often contribute to stray capacitance. The stray capacitance at the inverting input forms a pole with the feedback and gain resistors. This additional pole adds phase shift and reduces phase margin in the closed-loop phase response, causing instability in the amplifier and peaking in the frequency response. To obtain the desired bandwidth, adjust the feedback resistor, RF. If RF cannot be adjusted, a small capacitor can be placed in parallel with RF to reduce peaking. The feedback capacitor, CF, forms a zero with the feedback resistor, which cancels out the pole formed by the input stray capacitance and the gain and feedback resistors. For the first pass in determining the CF value, use the following equation: VADCP RF Bipolar VIN RG SFDR (dB) 104.5 102.0 106.0 102.9 RG x CS = RF x CF REF where: RG is the gain resistor. CS is the input stray capacitance. RF is the feedback resistor. CF is the feedback capacitor. 10F BIPOLAR SOURCE RS RG IN+ 20 IN- 1.8nF RF AMP_OUT ADC 15060-091 RT Figure 86. Difference Amplifier Configuration Used to Fit Bipolar Signals to the ADAQ7980/ADAQ7988 Using this equation, the original closed-loop frequency response of the amplifier is restored, as if there is no stray input capacitance. Most often, however, the value of CF is determined empirically. See Table 14 for recommended values. Rev. A | Page 46 of 49 Data Sheet ADAQ7980/ADAQ7988 USING THE ADAQ7980/ADAQ7988 WITH ACTIVE FILTERS Table 17. Typical Component Values for Second-Order, Low-Pass Active Filter of Figure 87 The low noise and high gain bandwidth of the ADC driver make it an excellent choice in active filter circuits. Most active filter literature provides resistor and capacitor values for various filters but neglects the effect of the finite bandwidth of the op amp on filter performance; ideal filter response with infinite loop gain is implied. Unfortunately, real filters do not behave in this manner. Instead, they exhibit finite limits of attenuation, depending on the gain bandwidth of the active device. Optimal low-pass filter performance requires an op amp with high gain bandwidth for attenuation at high frequencies, and low noise and high dc gain for low frequency, pass-band performance. Gain 2 5 R2 () 215 365 RF () 499 365 RG () 499 90.9 C1 (nF) 10 10 C2 (nF) 10 10 Figure 88 is a network analyzer plot of the performance of this filter. 50 40 30 20 GAIN (dB) Figure 87 shows the schematic of a second-order, low-pass active filter and lists typical component values for filters having a Bessel type response with a gain of 2 and a gain of 5. R1 () 71.5 44.2 G=5 10 0 G=2 -10 -20 -30 C1 IN+ C2 IN- RG -50 AMP_OUT RF 15060-092 VIN R2 1k 10k 100k FREQUENCY (Hz) 1M 10M 15060-093 -40 R1 Figure 88. Frequency Response of the Filter Circuit of Figure 87 for Two Different Gains Figure 87. Schematic of a Second-Order, Low-Pass Active Filter Rev. A | Page 47 of 49 ADAQ7980/ADAQ7988 Data Sheet APPLICATIONS INFORMATION LAYOUT Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADAQ7980/ADAQ7988. However, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. When designing the PCB, separate and confine the analog and digital sections to certain areas of the PCB that houses the ADAQ7980/ADAQ7988. The ADAQ7980/ADAQ7988 pinouts with all their analog signals on the left side and all their digital signals on the right side eases this task. Avoid running digital lines under the devices because these couple noise onto the die, unless using a ground plane under the ADAQ7980/ADAQ7988 as a shield. Never run fast switching signals, such as CNV or clocks, near the analog signal paths. Avoid crossover of digital and analog signals. Use at least one ground plane, and it can be common or split between the digital and analog section. In the latter case, join the planes underneath the ADAQ7980/ADAQ7988 devices. Finally, decouple the power supplies (V+, V-, VDD, and VIO) of the ADAQ7980/ADAQ7988 with low ESR ceramic capacitors that are placed close to the ADAQ7980/ADAQ7988 and that are connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. Place the smallest value capacitor on the same side of the board as the ADAQ7980/ADAQ7988 and as close as possible to the amplifier power supply pins. Connect the ground end of the capacitor directly to the ground plane. See Figure 89 for an example layout of the ADAQ7980/ ADAQ7988 that can save 50% PCB area compared to similar designs using individual components for each section of the Module data acquisition system. EVALUATING THE PERFORMANCE OF THE ADAQ7980/ADAQ7988 The evaluation board (EVAL-ADAQ7980SDZ) user guide for the ADAQ7980/ADAQ7988 outlines the other recommended layouts for the ADAQ7980/ADAQ7988. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the separately purchased EVAL-SDP-CB1Z. PIN 1 15060-290 ADAQ7980/ ADAQ7988 Figure 89. Example Layout for the ADAQ7980/ADAQ7988 Rev. A | Page 48 of 49 Data Sheet ADAQ7980/ADAQ7988 OUTLINE DIMENSIONS 3.00 REF PIN 1 INDICATOR 18 24 17 4.10 4.00 3.90 1 2.00 REF 5 13 0.50 BSC TOP VIEW 0.30 0.25 0.20 SIDE VIEW 2.08 1.98 1.88 12 6 BOTTOM VIEW 0.45 0.40 0.35 0.10 REF 1.65 REF PKG-004990 0.362 0.332 0.302 09-11-2015-A PIN 1 CORNER AREA 5.10 5.00 4.90 Figure 90. 24-Lead Land Grid Array [LGA] 5 mm x 4 mm Body and 1.98 mm Package Height (CC-24-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADAQ7980BCCZ ADAQ7980BCCZ-RL7 ADAQ7988BCCZ ADAQ7988BCCZ-RL7 EVAL-ADAQ7980SDZ EVAL-SDP-CB1Z 1 Temperature Range -55C to +125C -55C to +125C -55C to +125C -55C to +125C Package Description 24-Lead Land Grid Array [LGA] 24-Lead Land Grid Array [LGA] 24-Lead Land Grid Array [LGA] 24-Lead Land Grid Array [LGA] Evaluation Board Evaluation Controller Board Z = RoHS Compliant Part. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15060-0-8/17(A) Rev. A | Page 49 of 49 Package Option CC-24-2 CC-24-2 CC-24-2 CC-24-2