Data Sheet ADAQ7980/ADAQ7988
Rev. A | Page 35 of 49
POWER SUPPLY
Power supply bypassing is a critical aspect in the performance
of the ADC driver. A parallel connection of capacitors from
each amplifier power supply pin (V+ and V−) to ground works
best. Smaller value ceramic capacitors offer improved high
frequency response, whereas larger value ceramic capacitors
offer improved low frequency performance.
Paralleling different values and sizes of capacitors helps to ensure
that the power supply pins are provided with a low ac impedance
across a wide band of frequencies. Parralleling is important for
minimizing the coupling of noise into the amplifier—especially
when the amplifier PSRR begins to roll off—because the bypass
capacitors can help lessen the degradation in PSRR
performance.
Place the smallest value capacitor on the same side of the board
as the ADAQ7980/ADAQ7988 and as close as possible to the
amplifier power supply pins. Connect the ground end of the
capacitor directly to the ground plane.
The ADAQ7980/ADAQ7988 feature two other power supply pins:
the input to the LDO regulator that supplies the ADC (VDD) and a
digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.0 V. The ADAQ7980/
ADAQ7988 are independent of power supply sequencing between
VIO and VDD. It is recommended to provide power to VIO and
VDD prior to V+ and V−. In addition, while not required, it is
recommended to place the ADC driver and reference buffer in
power-down by applying a logic low to the PD_AMP and
PD_REF pins during the power-on sequence of the ADAQ7980/
ADAQ7988. The following are the recommended sequences for
applying and removing power to the μModule data acquisition
systems.
The recommended dual-supply, power-on sequence follows:
1. Apply a logic low to PD_AMP, PD_REF, and PD_LDO.
2. Apply a voltage to VIO.
3. Apply a voltage to VDD.
4. Apply a logic high to PD_LDO.
5. Apply a voltage to V+ and V−.
6. Apply a logic high to PD_AMP and PD_REF.
The recommended single-supply, power-on sequence follows:
1. Apply a logic low to PD_AMP, PD_REF, and PD_LDO.
2. Apply a voltage to VIO.
3. Apply a voltage to VDD and V+.
4. Apply a logic high to PD_LDO.
5. Apply a logic high to PD_AMP and PD_REF.
The recommended dual-supply, power-down sequence follows:
1. Apply a logic low to PD_AMP and PD_REF.
2. Remove the voltage from V+ and V−.
3. Apply a logic low to PD_LDO.
4. Remove the voltage from VDD.
5. Remove the voltage from VIO.
The recommended single-supply, power-down sequence follows:
1. Apply a logic low to PD_AMP and PD_REF.
2. Apply a logic low to PD_LDO.
3. Remove the voltage from V+ and VDD.
4. Remove the voltage from VIO.
Additionally, the ADAQ7980/ADAQ7988 are insensitive to power
supply variations over a wide frequency range, as shown in
Figure 70.
80
55 11000
FRE QUENCY ( kHz )
PSRR ( dB)
10 100
75
70
65
60
15060-075
Figure 70. PSRR vs. Frequency
The VDD input is the input of an on-board LDO regulator that
supplies 2.5 V to the SAR ADC. By housing an LDO regulator,
the ADAQ7980/ADAQ7988 provide a wide supply range to the
user. When operating these devices in a single-supply
configuration, tie the V+ and VDD pins together and connect
the V− pin to ground. Refer to Table 4 for the full list of
operating requirements associated with a single-supply system.
The LDO regulator of the ADAQ7980/ADAQ7988 is a 2.5 V,
low quiescent current, linear regulator that operates from 3.5 V
to 10 V and provides up to 100 mA of output current. The LDO
regulator draws a low 180 µA of quiescent current (typical) at
full load. The typical shutdown current consumption is less than
3 µA at room temperature. Typical start-up time for the LDO
regulator is 380 µs.
The ADAQ7980/ADAQ7988 require a small 2.2 µF ceramic
capacitor connected between the VDD pin and ground. Any
quality ceramic capacitors can be used as long as they meet the
minimum capacitance and maximum equivalent series resistance
(ESR) requirements. Ceramic capacitors are manufactured with
a variety of dielectrics, each with different behavior over
temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or
X7R dielectrics with a voltage rating of 6.3 V to 100 V are
recommended. Y5V and Z5U dielectrics are not recommended
due to their poor temperature and dc bias characteristics.