SGLS148 – DECEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DQualification in Accordance With
AEC-Q100†
DQualified for Automotive Applications
DCustomer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
DESD Protection Exceeds 200 V Using
Machine Model (C = 200 pF, R = 0)
D500-mA Rated Collector Current
(Single Output)
DHigh-Voltage Outputs ...50 V
DOutput Clamp Diodes
DInputs Compatible With Various Types of
Logic
DRelay-Driver Applications
†Contact factory for details. Q100 qualification data available on
request.
description
The ULQ2003A-Q1 and ULQ2004A-Q1 are high-voltage, high-current Darlington transistor arrays. Each
consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes
for switching inductive loads. The collector-current rating of a single Darlington pair is 500 mA. The Darlington
pairs can be paralleled for higher current capability. Applications include relay drivers, hammer drivers, lamp
drivers, display drivers (LED and gas discharge), line drivers, and logic buffers.
The ULQ2003A-Q1 has a 2.7-kΩ series base resistor for each Darlington pair, for operation directly with TTL
or 5-V CMOS devices. The ULQ2004A-Q1 has a 10.5-kΩ series base resistor to allow operation directly from
CMOS devices that use supply voltages of 6 V to 15 V. The required input current of the ULQ2004A-Q1 is below
that of the ULQ2003A-Q1.
AVAILABLE OPTIONS
T
D PACKAGES{
TASMALL OUTLINE
40°C to 105°C
ULQ2003ATDQ1
ULQ2003ATDRQ1
–40°C to 105°CULQ2004ATDQ1}
ULQ2004ATDRQ1}
†The D package is available taped and reeled. Add the suffix R to
device type (e.g., ULQ2003TDADRQ1).
‡ULQ2004ATDQ1 and ULQ2004ATDRQ1 are Product Preview only.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2B
3B
4B
5B
6B
7B
E
1C
2C
3C
4C
5C
6C
7C
COM
SGLS148 – DECEMBER 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram
7C
6C
5C
4C
3C
2C
1C
COM
7
6
5
4
3
2
1
7B
6B
5B
4B
3B
2B
1B
10
11
12
13
14
15
16
9
schematics (each Darlington pair)
Output
C
COM
E
ULQ2003A-Q1, ULQ2004A-Q1
7.2 kΩ3 kΩ
RB
Input
B
ULQ2003A-Q1: RB = 2.7 kΩ
ULQ2004A-Q1: RB = 10.5 kΩ
All resistor values shown are nominal.
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)†
Collector-emitter voltage 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamp diode reverse voltage (see Note 1) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (see Note 1) 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak collector current (see Figure 14) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total emitter-terminal current –2.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2) 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA, –40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , an d
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SGLS148 – DECEMBER 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE
T
A
= 25°CDERATING FACTOR T
A
= 85°C T
A
= 105°C
PACKAGE
TA
=
25 C
POWER RATING
DERATING
FACTOR
ABOVE TA = 25°C
TA
=
85 C
POWER RATING
TA
=
105 C
POWER RATING
D950 mW 7.6 mW/°C494 mW 342 mW
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ULQ2003A-Q1 ULQ2004A-Q1
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
IC = 125 mA 5
IC = 200 mA 2.7 6
V
On state inp t oltage See Fig re 6
V2V
IC = 250 mA 2.9
V
VI(on) On-state input voltage, See Figure 6 VCE = 2 V IC = 275 mA 7V
IC = 300 mA 3
IC = 350 mA 8
C ll t itt t ti lt
II = 250 µA, IC = 100 mA 0.9 1.2 0.9 1.1
VCE
(
sat
)
Collector-emitter saturation voltage,
See Figure 5
II = 350 µA, IC = 200 mA 1 1.4 1 1.3 V
VCE(sat)
S
ee
Fi
gure
5
II = 500 µA, IC = 350 mA 1.2 1.7 1.2 1.6
V
I
Cll t tff t
VCE = 50 V, II = 0,
See Figure 1 100 50
A
ICEX Collector cutoff current V
CE
= 50 V, II = 0 100 µA
VCE
=
50
V
,
See Figure 2 VI = 1 V 500
VFClamp forward voltage,
See Figure 8 IF = 350 mA 1.7 2.2 1.7 2 V
I
Off state inp t c rrent See Fig re 3
V50V
I 500 A
30
65
50
65
A
II
(
off
)
Off-state input current, See Figure 3 VCE = 50 V, IC = 500 µA3065 50 65 µA
VI = 3.85 V 0.93 1.35
IIInput current, see Figure 4 VI = 5 V 0.35 0.5 mA
II
In ut
current,
see
Figure
4
VI = 12 V 1 1.45
mA
I
Clamp reverse current, VR = 50 V, TA = 25°C 100 50
A
IR
Clam
reverse
current
,
See Figure 7 VR = 50 V 100 100 µA
CiInput capacitance VI = 0, f = 1 MHz 15 25 15 25 pF
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS ULQ2003A-Q1,
ULQ2004A-Q1 UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
tPLH Propagation delay time, low-to-high level output See Figure 9 1 10 µs
tPHL Propagation delay time, high-to-low level output See Figure 9 1 10 µs
VOH High-level output voltage after switching VS = 50 V,
See Figure 10 IO ≈ 300 mA, VS–500 mV
SGLS148 – DECEMBER 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Open VCE
Open
ICEX
Figure 1. ICEX Test Circuit
Open VCE
VI
ICEX
Figure 2. ICEX Test Circuit
Open VCE
IC
II(off)
Figure 3. II(off) Test Circuit
Open
Open
II(on)
VI
Figure 4. II Test Circuit
Open
VCE IC
II
hFE = IC
II
NOTE: II is fixed for measuring VCE(sat), variable for
measuring hFE.
Figure 5. hFE, VCE
(
sat
)
Test Circuit
Open
VCE IC
VI(on)
Figure 6. VI(on) Test Circuit
VR
Open
IR
Figure 7. IR Test Circuit
IF
VF
Open
Figure 8. VF Test Circuit
SGLS148 – DECEMBER 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% 50%
50% 50%
tPHL
VOLTAGE W AVEFORMS
Input
Output
tPLH
Figure 9. Propagation Delay-Time Waveforms
Open
VS
200 Ω
Output
CL = 15 pF
(see Note B)
90% 90%
1.5 V 1.5 V
10% 10%
40 µs
≤10 ns
≤5 ns VIH
(see Note C)
0 V
VOH
VOL
Input
Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
1N3064 2 mH
Pulse
Generator
(see Note A) ULQ2003A-Q1
ULQ2004A-Q1
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. For testing the ULQ2003A-Q1, VIH = 3 V; for the ULQ2004A-Q1, VIH = 8 V.
Figure 10. Latch-Up Test Circuit and Voltage Waveforms
SGLS148 – DECEMBER 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
COLLECTOR-EMITTER SATURATION VOLTAGE
vs
COLLECTOR CURRENT
(ONE DARLINGTON)
0
IC – Collector Current – mA
2.5
800
0100 200 300 400 500 600 700
0.5
1
1.5
2
II = 350 µA
II = 500 µA
VCE(sat) – Collector-Emitter Saturation Voltage – V
VCE(sat)
TA = 25°C
II = 250 µA2
1.5
1
0.5
700600500400300200100
0800
2.5
IC(tot) – Total Collector Current – mA
0
COLLECTOR-EMITTER SATURATION VOLTAGE
vs
TOTAL COLLECTOR CURRENT
(TWO DARLINGTONS IN PARALLEL)
VCE(sat) – Collector-Emitter Saturation Voltage – VVCE(sat)
II = 250 µA
II = 350 µA
II = 500 µA
TA = 25°C
Figure 12
COLLECTOR CURRENT
vs
INPUT CURRENT
0
II – Input Current – µA
500
200
025 50 75 100 125 150 175
50
100
150
200
250
300
350
400
450
VS = 10 V
VS = 8 V
IC – Collector Current – mA
C
I
RL = 10 Ω
TA = 25°C
Figure 13
SGLS148 – DECEMBER 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
Figure 14
0
Duty Cycle – %
600
100
010 20 30 40 50 60 70 80 90
100
200
300
400
500
TA = 70°C
N = Number of Outputs
Conducting Simultaneously
N = 6
N = 7
MAXIMUM COLLECTOR CURRENT
vs
DUTY CYCLE
N = 5
N = 3
N = 2
N = 1
IC – Maximum Collector Current – mA
C
I
N = 4
SGLS148 – DECEMBER 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
ULQ2003A-Q1
Lamp
Test
TTL
Output
VCC V
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
7
Figure 15. TTL to Load
VDD V
ULQ2004A-Q1
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
CMOS
Output
7
Figure 16. Buffer for Higher Current Loads
VCC V
RP
ULQ2003A-Q1
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
TTL
Output
7
Figure 17. Use of Pullup Resistors
to Increase Drive Current
SGLS148 – DECEMBER 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
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Post Office Box 655303
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Copyright 2003, Texas Instruments Incorporated
