Preliminary: This document contains information on a new product. Specifications and information
contained herein are subject to change without notice.
HM5164800A Series
HM5165800A Series
8388608-word × 8-bit Dynamic Random Access Memory
ADE-203-595(Z)
Preliminary
Rev. 0.1
Jan. 22, 1997
Description
The Hitachi HM5164800A Series, HM5165800A Series are CMOS dynamic RAMs organized as 8,388,608-
word × 8-bit. They employ the most advanced CMOS technology for high performance and low power. The
HM5164800A Series, HM5165800A Series offer Fast Page Mode as a high speed access mode. They have
the package variations of standard 400-mil 32-pin plastic SOJ and standard 400-mil 32-pin plastic TSOPII.
Features
• Single 3.3 V (±0.3 V)
• High speed
Access time: 50 ns/60 ns/70 ns (max)
• Low power dissipation
Active mode : TBD/396 mW/342 mW (max) (HM5164800A Series)
: TBD/576 mW/504 mW (max) (HM5165800A Series)
Standby mode : 7.2 mW (max)
: TBD (L-version)
• Fast page mode capability
• Long refresh period
8192 RAS only refresh cycles : 64 ms (HM5164800A Series)
4096 CBR/Hidden refresh cycles : 64 ms
: 128 ms (L-version)
4096 RAS only refresh cycles : 64 ms (HM5165800A Series)
4096 CBR/Hidden refresh cycles : 64 ms
: 128 ms (L-version)
HM5164800A Series, HM5165800A Series
2
• 4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
• Battery backup operation (L-version)
Ordering Information
Type No. Access time Package
HM5164800AJ-5
HM5164800AJ-6
HM5164800AJ-7
50 ns
60 ns
70 ns
400-mil 32-pin plastic SOJ (CP-32DC)
HM5164800ALJ-5
HM5164800ALJ-6
HM5164800ALJ-7
50 ns
60 ns
70 ns
HM5165800AJ-5
HM5165800AJ-6
HM5165800AJ-7
50 ns
60 ns
70 ns
HM5165800ALJ-5
HM5165800ALJ-6
HM5165800ALJ-7
50 ns
60 ns
70 ns
HM5164800ATT-5
HM5164800ATT-6
HM5164800ATT-7
50 ns
60 ns
70 ns
400-mil 32-pin plastic TSOP II (TTP-32DC)
HM5164800ALTT-5
HM5164800ALTT-6
HM5164800ALTT-7
50 ns
60 ns
70 ns
HM5165800ATT-5
HM5165800ATT-6
HM5165800ATT-7
50 ns
60 ns
70 ns
HM5165800ALTT-5
HM5165800ALTT-6
HM5165800ALTT-7
50 ns
60 ns
70 ns
HM5164800A Series, HM5165800A Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HM5164800ATT/ALTT SeriesHM5164800AJ/ALJ Series
(Top view)(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
I/O0
I/O1
I/O2
I/O3
NC
V
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
CC
CC
V
I/O0
I/O1
I/O2
I/O3
NC
V
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
CC
CC
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
A12
A11
A10
A9
A8
A7
A6
V
SS
SS
SS
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
A12
A11
A10
A9
A8
A7
A6
V
SS
SS
SS
Pin Description
Pin name Function
A0 to A12 Address input
— Row/Refresh address A0 to A12
— Column address A0 to A9
I/O0 to I/O7 Data input/Data output
RAS Row address strobe
CAS Column address strobe
WE Read/Write enable
OE Output enable
VCC Power supply
VSS Ground
NC No connection
HM5164800A Series, HM5165800A Series
4
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HM5165800ATT/ALTT SeriesHM5165800AJ/ALJ Series
(Top view)(Top view)
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
NC
A11
A10
A9
A8
A7
A6
V
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
I/O0
I/O1
I/O2
I/O3
NC
V
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
CC
CC
V
I/O0
I/O1
I/O2
I/O3
NC
V
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
CC
CC
SS
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
NC
A11
A10
A9
A8
A7
A6
V
SS
SS
SS
Pin Description
Pin name Function
A0 to A11 Address input
— Row/Refresh address A0 to A11
— Column address A0 to A10
I/O0 to I/O7 Data input/Data output
RAS Row address strobe
CAS Column address strobe
WE Read/Write enable
OE Output enable
VCC Power supply
VSS Ground
NC No connection
HM5164800A Series, HM5165800A Series
5
Block Diagram (HM5164800A Series)
•
•
•
•
•
•
A0
A1
to
A9
Timing and control
Column
address
buffers
Row
address
buffers
I/O buffers I/O0
to
I/O7
RAS CAS WE OE
Column decoder
Row decoder
8M array
8M array
8M array
8M array
8M array
8M array
8M array
8M array
A10
to
A12
HM5164800A Series, HM5165800A Series
6
Block Diagram (HM5165800A Series)
•
•
•
•
•
•
A0
A1
to
A10
Timing and control
Column
address
buffers
Row
address
buffers
I/O buffers I/O0
to
I/O7
RAS CAS WE OE
Column decoder
Row decoder
A11
8M array
8M array
8M array
8M array
8M array
8M array
8M array
8M array
HM5164800A Series, HM5165800A Series
7
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to VSS VT–0.5 to VCC + 0.5 (≤ 4.6 V (max)) V
Supply voltage relative to VSS VCC –0.5 to +4.6 V
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Notes
Supply voltage VCC 3.0 3.3 3.6 V 1, 2
Input high voltage VIH 2.0 — VCC + 0.3 V 1
Input low voltage VIL –0.3 — 0.8 V 1
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins
must be on the same level.
HM5164800A Series, HM5165800A Series
8
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5164800A Series)
HM5164800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Test conditions
Operating current*1, *2ICC1 — TBD — 110 — 95 mA tRC = min
Standby current ICC2 — TBD — 2 — 2 mA TTL interface
RAS, CAS = VIH
Dout = High-Z
— TBD — 1 — 1 mA CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version) ICC2 — TBD — TBD — TBD µA CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2ICC3 — TBD — 110 — 95 mA tRC = min
Standby current*1ICC5 —TBD—5 —5 mARAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS refresh
current ICC6 — TBD — 140 — 120 mA tRC = min
Fast page mode current*1, *3ICC7 — TBD — 85 — 75 mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10 — TBD — TBD — TBD µA CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version) ICC11 — TBD — TBD — TBD µA CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current ILI TBD TBD –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC + 0.3 V
Output leakage current ILO TBD TBD –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC
Dout = disable
Output high voltage VOH TBD TBD 2.4 VCC 2.4 VCC V High Iout = –2 mA
Output low voltage VOL TBD TBD 0 0.4 0 0.4 V Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less within one page mode cycle tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
HM5164800A Series, HM5165800A Series
9
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5165800A Series)
HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Test conditions
Operating current*1, *2ICC1 — TBD — 160 — 140 mA tRC = min
Standby current ICC2 — TBD — 2 — 2 mA TTL interface
RAS, CAS = VIH
Dout = High-Z
— TBD — 1 — 1 mA CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version) ICC2 — TBD — TBD — TBD µA CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2ICC3 — TBD — 160 — 140 mA tRC = min
Standby current*1ICC5 —TBD—5 —5 mARAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS refresh
current ICC6 — TBD — 140 — 120 mA tRC = min
Fast page mode current*1, *3ICC7 — TBD — 100 — 90 mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10 — TBD — TBD — TBD µA CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version) ICC11 — TBD — TBD — TBD µA CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current ILI TBD TBD –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC + 0.3 V
Output leakage current ILO TBD TBD –10 10 –10 10 µA 0 V ≤ Vin ≤ VCC
Dout = disable
Output high voltage VOH TBD TBD 2.4 VCC 2.4 VCC V High Iout = –2 mA
Output low voltage VOL TBD TBD 0 0.4 0 0.4 V Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less within one page mode cycle tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
HM5164800A Series, HM5165800A Series
10
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter Symbol Typ Max Unit Notes
Input capacitance (Address) CI1 — 5 pF 1
Input capacitance (Clocks) CI2 — 7 pF 1
Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, CAS = VIH to disable Dout.
HM5164800A Series, HM5165800A Series
11
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *17
Test Conditions
• Input rise and fall time: 5 ns
• Input timing reference levels: 0.8 V, 2.0 V
• Output timing reference levels: 0.8 V, 2.0 V
• Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164800A/HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
Random read or write cycle time tRC TBD — 110 — 130 — ns
RAS precharge time tRP TBD — 40 — 50 — ns
CAS precharge time tCP TBD — 10 — 10 — ns
RAS pulse width tRAS TBD TBD 60 10000 70 10000 ns
CAS pulse width tCAS TBD TBD 15 10000 18 10000 ns
Row address setup time tASR TBD—0—0—ns
Row address hold time tRAH TBD — 10 — 10 — ns
Column address setup time tASC TBD—0—0—ns
Column address hold time tCAH TBD — 10 — 15 — ns
RAS to CAS delay time tRCD TBD TBD 20 45 20 52 ns 3
RAS to column address delay time tRAD TBD TBD 15 30 15 35 ns 4
RAS hold time tRSH TBD — 15 — 18 — ns
CAS hold time tCSH TBD — 60 — 70 — ns
CAS to RAS precharge time tCRP TBD—5—5—ns
OE to Din delay time tOED TBD — 15 — 18 — ns 5
OE delay time from Din tDZO TBD—0—0—ns6
CAS delay time from Din tDZC TBD—0—0—ns6
Transition time (rise and fall) tTTBD TBD 3 50 3 50 ns 7
HM5164800A Series, HM5165800A Series
12
Read Cycle
HM5164800A/HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
Access time from RAS tRAC — TBD — 60 — 70 ns 8, 9
Access time from CAS tCAC — TBD — 15 — 18 ns 9, 10, 16
Access time from address tAA — TBD — 30 — 35 ns 9, 11, 16
Access time from OE tOEA — TBD — 15 — 18 ns 9, 19
Read command setup time tRCS TBD—0—0—ns
Read command hold time to CAS tRCH TBD—0—0– ns12
Read command hold time to RAS tRRH TBD—5—5—ns12
Column address to RAS lead time tRAL TBD — 30 — 35 — ns
Column address to CAS lead time tCAL TBD — 30 — 35 — ns
CAS to output in low-Z tCLZ TBD—0—0—ns
Output data hold time tOH TBD—3—3—ns
Output data hold time from OE tOHO TBD—3—3—ns
Output buffer turn-off time tOFF — TBD — 15 — 15 ns 13
Output buffer turn-off to OE tOEZ — TBD — 15 — 15 ns 13
CAS to Din delay time tCDD TBD — 15 — 18 — ns 5
Write Cycle
HM5164800A/HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write command setup time tWCS TBD—0—0—ns14
Write command hold time tWCH TBD — 10 — 15 — ns
Write command pulse width tWP TBD — 10 — 10 — ns
Write command to RAS lead time tRWL TBD — 15 — 18 — ns
Write command to CAS lead time tCWL TBD — 15 — 18 — ns
Data-in setup time tDS TBD—0—0—ns
Data-in hold time tDH TBD — 10 — 15 — ns
HM5164800A Series, HM5165800A Series
13
Read-Modify-Write Cycle
HM5164800A/HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read-modify-write cycle time tRWC TBD — 155 — 181 — ns
RAS to WE delay time tRWD TBD — 85 — 98 — ns 14
CAS to WE delay time tCWD TBD — 40 — 46 — ns 14
Column address to WE delay time tAWD TBD — 55 — 63 — ns 14
OE hold time from WE tOEH TBD — 15 — 18 — ns
Refresh Cycle
HM5164800A/HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
CAS setup time (CBR refresh cycle) tCSR TBD—5—5—ns
CAS hold time (CBR refresh cycle) tCHR TBD — 10 — 10 — ns
WE setup time (CBR refresh cycle) tWRP TBD—0—0—ns
WE hold time (CBR refresh cycle) tWRH TBD — 10 — 10 — ns
RAS precharge to CAS hold time tRPC TBD—0—0—ns
Fast Page Mode Cycle
HM5164800A/HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
Fast page mode cycle time tPC TBD — 40 — 45 — ns
Fast page mode RAS pulse width tRASP — TBD — 100000 — 100000 ns 15
Access time from CAS precharge tCPA — TBD — 35 — 40 ns 9, 16
RAS hold time from CAS precharge tCPRH TBD — 35 — 40 — ns
HM5164800A Series, HM5165800A Series
14
Fast Page Mode Read-Modify-Write Cycle
HM5164800A/HM5165800A
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
Fast page mode read-modify-write
cycle time tPRWC TBD — 85 — 96 — ns
WE delay time from CAS precharge tCPW TBD — 60 — 68 — ns 14
Refresh (HM5164800A Series)
Parameter Symbol Max Unit Note
Refresh period tREF 64 ms 8192 cycles
Refresh period (L-version) tREF 128 ms 4096 cycles
Refresh (HM5165800A Series)
Parameter Symbol Max Unit Note
Refresh period tREF 64 ms 4096 cycles
Refresh period (L-version) tREF 128 ms 4096 cycles
Self Refresh Mode (L-version)
HM5164800AL/HM5165800AL
-5 -6 -7
Parameter Symbol Min Max Min Max Min Max Unit Notes
RAS pulse width (Self refresh) tRASS TBD — 100 — 100 — µs20
RAS precharge time (Self refresh) tRPS TBD — 110 — 130 — ns
CAS hold time (Self refresh) tCHS TBD — –50 — –50 — ns
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
HM5164800A Series, HM5165800A Series
15
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11.Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12.Either tRCH or tRRH must be satisfied for a read cycles.
13.tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and
are not referred to output voltage levels.
14.tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD
(min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW
(min), the cycle is a read-modify-write and the data output will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
15.tRASP defines RAS pulse width in fast page mode cycles.
16.Access time is determined by the longest among tAA, tCAC and tCPA.
17.All the VCC and VSS pins shall be supplied with the same voltages.
18.In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
19.When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS
line noise, which causes to degrade VIH min/VIL max level.
20.Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition
state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS precharge time
should use tRPS instead of tRP.
21.CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 µs interval should be
executed within 64 ms immediately after exiting from and before entering into the self refresh
mode.
22.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
23.XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
HM5164800A Series, HM5165800A Series
16
Timing Waveforms*23
Read Cycle
RAS
CAS
Address
WE
Dout
OE
Din
t
RC
t
RAS
t
RP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
T
t
RAD
t
RAL
t
CAL
t
ASC
t
CAH
t
ASR
Row Column
t
RAH
t
RCS
t
RCH
t
RRH
t
CDD
t
DZC
High-Z
Dout
t
DZO
t
OED
t
RAC
t
OEA
t
AA
t
CAC
t
CLZ
t
OH
t
OFF
t
OHO
t
OEZ
HM5164800A Series, HM5165800A Series
17
Early Write Cycle
RAS
CAS
Address
WE
Din
Dout
tRC
*
tRAS tRP
tCRP
tCSH
tRCD tRSH
tCAS
tT
tASR tRAH tASC tCAH
Row
tWCS tWCH
tDS tDH
Din
tWCS WCS(min)
High-Z*
t
Column
HM5164800A Series, HM5165800A Series
18
Delayed Write Cycle*18
Address
CAS
RAS
WE
Din
OE
Dout
tRC
tRAS tRP
tCSH
tRCD tRSH
tCAS
tCRP
tT
ColumnRow
tASR tRAH tASC tCAH
tRCS
tCWL
tRWL
tWP
tDZC tDS tDH
tDZO
tOED
tOEH
tCLZ
tOEZ
High-Z
Invalid Dout
Din
High-Z
HM5164800A Series, HM5165800A Series
19
Read-Modify-Write Cycle*18
!"
Address
RAS
Din
Dout
OE
WE
t
RWC
t
RAS
t
RP
t
CRP
t
CAS
t
RCD
t
T
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
ColumnRow
t
RCS
t
CWD
t
CWL
t
AWD
t
RWD
t
RWL
t
WP
t
DZC
t
DH
t
DS
Din
High-Z
t
DZO
t
OED
t
OEH
t
OEA
t
CAC
t
AA
t
RAC
t
OHO
t
OEZ
t
CLZ
Dout High-Z
CAS
HM5164800A Series, HM5165800A Series
20
RAS-Only Refresh Cycle
RAS
CAS
Address
Dout High-Z
Row
t
RC
t
RP
t
RAS
t
T
t
CRP
t
RPC
t
CRP
t
ASR
t
RAH
t
OFF
CAS-Before-RAS Refresh Cycle
$%*+,
RAS
CAS
WE
Dout
Address
t
RC
t
RP
t
RAS
t
RPC
t
CSR
t
CHR
t
RPC
t
CRP
t
CP
t
WRH
t
WRP
t
CP
t
T
t
OFF
High-Z
t
RP
HM5164800A Series, HM5165800A Series
21
Hidden Refresh Cycle
")0
Din
OE
Dout
WE
Address
CAS
RAS
tRC tRC tRC tRP
tRAS
tRP
tRAS
tRP
tRAS
tT
tRCD
tRSH tCHR tCRP
tRAD tRAL
tCAH
tASC
tRAH
tASR
tRCS
tCDD
tDZC
DZO
tOED
t
OEZ
t
OHO
t
OFF
t
OH
t
CAC
t
AA
t
RAC
t
CLZ
t
Dout
OEA
t
High-Z
tRRH
tRCH
ColumnRow
HM5164800A Series, HM5165800A Series
22
Fast Page Mode Read Cycle
!"(
,
+
WE
Din
OE
Dout
Address
RAS
tRASP tCPRH tRP
tTtCSH
tRCD tCAS tCP tCAS
tPC tRSH
tCP tCAS tCRP
tRAL
tCAL
tCAHASC
tt
ASC
ttCAL
tCAL
t
ASC
t
tRAD
t
ASR
tRAH
tt
RCH tRCH
tt t
RRH
tRCH
tCDD
High-Z
tDZC
tCDD
tDZC
tCDD
tDZC
High-ZHigh-Z
tDZO tOED tOED
tDZO tt
OED
tOH
tAA
tOH
tAA
tOH
tCPA
tCPA
tRAC tAA
tOEA tOEA tOEA tOHO
tOHO
tOHO
tCAC
tCLZ tOEZ
tOFF tCAC
tCLZ tOEZ
tOFF tCAC
tCLZ tOEZ
tOFF
Dout NDout 2Dout 1
Row Column 1 Column 2 Column N
CAH CAH
RCS RCS
RCS
DZO
CAS
HM5164800A Series, HM5165800A Series
23
Fast Page Mode Early Write Cycle
*tWCS WCS(min)
RAS
Address
WE
Din
Dout
tRASP tRP
tTtCSH tPC tRSH tCRP
tCAS
tCP
tCAS
tCP
tCAS
tRCD
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
tWCH
tWCS
tWCH
tWCS
tWCH
tWCS
tDH
tDS tDH
tDS tDH
tDS
Din 1 Din 2 Din N
High-Z*
t
Row Column 1 Column 2 Column N
CAS
HM5164800A Series, HM5165800A Series
24
Fast Page Mode Delayed Write Cycle*18
/0
"#)
WE
Din
OE
Dout
Address
RAS
tRASP
tRP
tCRP
tRSH
tCAS
tPCtCAS
tCAS
tCSH
tRCD
tTtCP tCP
tASC
tCAH
tASC
tCAH
tASC
tCAH
tRAD
tASR tRAH
tRCS tRCS tRCS
tRWL
tCWL
tCWL
tCWL
tWP
tWP
tWP
tDZC tDS tDZC tDS tDS
tDZC tDH
tDH
tDH
tDZO tOED
tDZO
tOED
tDZO
tOED
tOEH tOEH tOEH
tOEZ
tCLZ
tCLZ tOEZ
tCLZ tOEZ
Invalid Dout Invalid Dout Invalid Dout
Din
1Din
2Din
N
Column NColumn 2Column 1Row
High-Z
CAS
HM5164800A Series, HM5165800A Series
25
Fast Page Mode Read-Modify-Write Cycle*18
#)*
WE
Din
OE
Dout
Address
RAS
tRASP
tCRP
tCP
tPRWC
tT
tRCD tCAS
tCP
tCAS tCAS
tRAD
tASR tASC tASC tASC
tRAH tCAH tCAH tCAH
tCWL
tCPW
tCWL
tCPW
tCWL
tRWD
tAWD tAWD tAWD
tCWD
tRCS
tCWD
tRCS
tCWD
tRCS tWP tWP tWP
tDStDZC
tDStDZC
tDStDZC tDH
tDH
tDH
tDZO tDZO tDZO
tOEH tOEH tOEH
tAA
tRAC tOEZ
tCLZ
Dout NDout 2Dout 1
Din
1Din
2Din
N
Column NColumn 2Column 1
tRP
Row
tRWL
tOHO
tOEA
tCAC
tOEZ
tCLZ
tOHO
tOEA
tCAC
tCPA
tOEZ
tCLZ
tOHO
tOEA
tCAC
tCPA
High-Z
tOED tOED tOED
AA
tAA
t
tRSH
CAS
HM5164800A Series, HM5165800A Series
26
Self Refresh Cycle (L-version)*20, 21, 22
$%*+,
,
RAS
Dout
tRP tRASS tRPS
tRPC
tT
tCP tCSR tCHS
tCRP
tOFF
High-Z
CAS
WRP
tWRH
t
WE
HM5164800A Series, HM5165800A Series
27
Package Dimensions
HM5164800AJ/ALJ Series
HM5165800AJ/ALJ Series (CP-32DC) Unit: mm
20.95
21.38 Max
32 17
116
0.74
10.16 ± 0.12
11.18
3.50
1.27
0.10
0.43
0.64 Min
9.40 ± 0.25
2.55
+0.12
–0.13
+0.07
–0.04
+0.25
–0.24
HM5164800A Series, HM5165800A Series
28
HM5164800ATT/ALTT Series
HM5165800ATT/ALTT Series (TTP-32DC) Unit: mm
1.27
0.20 M
0.10
10.16
20.95
21.35 Max 17
16
32
1
1.20 Max
0 – 5°
0.08 Min
0.18 Max
0.68
11.76 ± 0.20
0.50 ± 0.10
1.15 Max
0.145
+0.03
–0.02
0.42
+0.08
–0.07
HM5164800A Series, HM5165800A Series
29
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 0628-585000
Fax: 0628-778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
HM5164800A Series, HM5165800A Series
30
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Jun. 3, 1996 Initial issue
