HM5164800A Series, HM5165800A Series
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5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11.Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12.Either tRCH or tRRH must be satisfied for a read cycles.
13.tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and
are not referred to output voltage levels.
14.tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD
(min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW
(min), the cycle is a read-modify-write and the data output will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
15.tRASP defines RAS pulse width in fast page mode cycles.
16.Access time is determined by the longest among tAA, tCAC and tCPA.
17.All the VCC and VSS pins shall be supplied with the same voltages.
18.In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
19.When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS
line noise, which causes to degrade VIH min/VIL max level.
20.Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition
state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS precharge time
should use tRPS instead of tRP.
21.CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 µs interval should be
executed within 64 ms immediately after exiting from and before entering into the self refresh
mode.
22.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
23.XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.