HM5164800A Series HM5165800A Series 8388608-word x 8-bit Dynamic Random Access Memory ADE-203-595(Z) Preliminary Rev. 0.1 Jan. 22, 1997 Description The Hitachi HM5164800A Series, HM5165800A Series are CMOS dynamic RAMs organized as 8,388,608word x 8-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5164800A Series, HM5165800A Series offer Fast Page Mode as a high speed access mode. They have the package variations of standard 400-mil 32-pin plastic SOJ and standard 400-mil 32-pin plastic TSOPII. Features * Single 3.3 V (0.3 V) * High speed Access time: 50 ns/60 ns/70 ns (max) * Low power dissipation Active mode : TBD/396 mW/342 mW (max) (HM5164800A Series) : TBD/576 mW/504 mW (max) (HM5165800A Series) Standby mode : 7.2 mW (max) : TBD (L-version) * Fast page mode capability * Long refresh period 8192 RAS only refresh cycles : 64 ms (HM5164800A Series) 4096 CBR/Hidden refresh cycles : 64 ms : 128 ms (L-version) 4096 RAS only refresh cycles : 64 ms (HM5165800A Series) 4096 CBR/Hidden refresh cycles : 64 ms : 128 ms (L-version) Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HM5164800A Series, HM5165800A Series * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version) Ordering Information Type No. Access time Package HM5164800AJ-5 HM5164800AJ-6 HM5164800AJ-7 50 ns 60 ns 70 ns 400-mil 32-pin plastic SOJ (CP-32DC) HM5164800ALJ-5 HM5164800ALJ-6 HM5164800ALJ-7 50 ns 60 ns 70 ns HM5165800AJ-5 HM5165800AJ-6 HM5165800AJ-7 50 ns 60 ns 70 ns HM5165800ALJ-5 HM5165800ALJ-6 HM5165800ALJ-7 50 ns 60 ns 70 ns HM5164800ATT-5 HM5164800ATT-6 HM5164800ATT-7 50 ns 60 ns 70 ns HM5164800ALTT-5 HM5164800ALTT-6 HM5164800ALTT-7 50 ns 60 ns 70 ns HM5165800ATT-5 HM5165800ATT-6 HM5165800ATT-7 50 ns 60 ns 70 ns HM5165800ALTT-5 HM5165800ALTT-6 HM5165800ALTT-7 50 ns 60 ns 70 ns 400-mil 32-pin plastic TSOP II (TTP-32DC) 2 HM5164800A Series, HM5165800A Series Pin Arrangement HM5164800AJ/ALJ Series VCC I/O0 I/O1 1 32 2 31 3 30 HM5164800ATT/ALTT Series V SS VCC 1 32 V SS I/O7 I/O0 2 31 I/O7 I/O6 I/O1 3 30 I/O6 4 29 I/O5 I/O2 4 29 I/O5 I/O2 I/O3 5 28 I/O4 I/O3 5 28 I/O4 NC 6 27 V SS NC 6 27 V SS V CC 7 26 CAS V CC 7 26 CAS WE 8 25 OE WE 8 25 OE RAS 9 24 A12 RAS 9 24 A12 A0 10 23 A11 A0 10 23 A11 A1 11 22 A10 A1 11 22 A10 A2 12 21 A9 A2 12 21 A9 A3 13 20 A8 A3 13 20 A8 A4 14 19 A7 A4 14 19 A7 A5 15 18 A6 A5 15 18 A6 VCC 16 17 V SS VCC 16 17 V SS (Top view) Pin Description Pin name Function A0 to A12 Address input -- Row/Refresh address A0 to A12 -- Column address A0 to A9 I/O0 to I/O7 Data input/Data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection 3 (Top view) HM5164800A Series, HM5165800A Series Pin Arrangement HM5165800AJ/ALJ Series HM5165800ATT/ALTT Series VCC 1 32 VSS VCC 1 32 VSS I/O0 2 31 I/O7 I/O0 2 31 I/O7 I/O1 3 30 I/O6 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O2 4 29 I/O5 I/O3 5 28 I/O4 I/O3 5 28 I/O4 NC 6 27 VSS NC 6 27 VSS VCC 7 26 CAS VCC 7 26 CAS WE 8 25 OE WE 8 25 OE RAS 9 24 NC RAS 9 24 NC A0 10 23 A11 A0 10 23 A11 A1 11 22 A10 A1 11 22 A10 A2 12 21 A9 A2 12 21 A9 A3 13 20 A8 A3 13 20 A8 A4 14 19 A7 A4 14 19 A7 A5 15 18 A6 A5 15 18 A6 VCC 16 17 V SS VCC 16 17 V SS (Top view) (Top view) Pin Description Pin name Function A0 to A11 Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A10 I/O0 to I/O7 Data input/Data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection 4 HM5164800A Series, HM5165800A Series Block Diagram (HM5164800A Series) RAS CAS WE OE Timing and control Column decoder A0 Column A1 to * * * 8M array address 8M array buffers A9 * * * Row address buffers A10 to A12 5 Row decoder 8M array 8M array 8M array 8M array 8M array 8M array I/O buffers I/O0 to I/O7 HM5164800A Series, HM5165800A Series Block Diagram (HM5165800A Series) RAS CAS WE OE Timing and control Column decoder A0 Column A1 to * * * 8M array address 8M array buffers A10 * * * Row address buffers Row decoder 8M array 8M array 8M array I/O buffers I/O0 to I/O7 8M array 8M array 8M array A11 6 HM5164800A Series, HM5165800A Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT -0.5 to VCC + 0.5 ( 4.6 V (max)) V Supply voltage relative to VSS VCC -0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 3.0 3.3 3.6 V 1, 2 Input high voltage VIH 2.0 -- VCC + 0.3 V 1 Input low voltage VIL -0.3 -- 0.8 V 1 Notes: 1. All voltage referred to VSS 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 7 HM5164800A Series, HM5165800A Series DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5164800A Series) HM5164800A -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 -- TBD -- 110 -- 95 mA t RC = min I CC2 -- TBD -- 2 -- 2 mA TTL interface RAS, CAS = VIH Dout = High-Z -- TBD -- 1 -- 1 mA CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z I CC2 -- TBD -- TBD -- TBD A CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z I CC3 -- TBD -- 110 -- 95 mA t RC = min Standby current* I CC5 -- TBD -- 5 -- 5 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 -- TBD -- 140 -- 120 mA t RC = min Fast page mode current*1, * 3 I CC7 -- TBD -- 85 -- 75 mA t PC = min 1, Operating current* * 2 Standby current Standby current (L-version) RAS-only refresh current*2 1 Battery backup current* (Standby with CBR refresh) (L-version) I CC10 -- TBD -- TBD -- TBD A CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s Self refresh mode current (L-version) I CC11 -- TBD -- TBD -- TBD A CMOS interface RAS, CAS 0.2 V Dout = High-Z Input leakage current I LI TBD TBD -10 10 -10 10 A 0 V Vin VCC + 0.3 V Output leakage current I LO TBD TBD -10 10 -10 10 A 0 V Vin VCC Dout = disable Output high voltage VOH TBD TBD 2.4 VCC 2.4 VCC V High Iout = -2 mA Output low voltage VOL TBD TBD 0 0.4 0 0.4 V Low Iout = 2 mA 4 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V. 8 HM5164800A Series, HM5165800A Series DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5165800A Series) HM5165800A -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 -- TBD -- 160 -- 140 mA t RC = min I CC2 -- TBD -- 2 -- 2 mA TTL interface RAS, CAS = VIH Dout = High-Z -- TBD -- 1 -- 1 mA CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z I CC2 -- TBD -- TBD -- TBD A CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z I CC3 -- TBD -- 160 -- 140 mA t RC = min Standby current* I CC5 -- TBD -- 5 -- 5 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 -- TBD -- 140 -- 120 mA t RC = min Fast page mode current*1, * 3 I CC7 -- TBD -- 100 -- 90 mA t PC = min 1, Operating current* * 2 Standby current Standby current (L-version) RAS-only refresh current*2 1 Battery backup current* (Standby with CBR refresh) (L-version) I CC10 -- TBD -- TBD -- TBD A CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s Self refresh mode current (L-version) I CC11 -- TBD -- TBD -- TBD A CMOS interface RAS, CAS 0.2 V Dout = High-Z Input leakage current I LI TBD TBD -10 10 -10 10 A 0 V Vin VCC + 0.3 V Output leakage current I LO TBD TBD -10 10 -10 10 A 0 V Vin VCC Dout = disable Output high voltage VOH TBD TBD 2.4 VCC 2.4 VCC V High Iout = -2 mA Output low voltage VOL TBD TBD 0 0.4 0 0.4 V Low Iout = 2 mA 4 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V. 9 HM5164800A Series, HM5165800A Series Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 -- 5 pF 1 Input capacitance (Clocks) CI2 -- 7 pF 1 Output capacitance (Data-in, Data-out) CI/O -- 7 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, CAS = VIH to disable Dout. 10 HM5164800A Series, HM5165800A Series AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *17 Test Conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5164800A/HM5165800A -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC TBD -- 110 -- 130 -- ns RAS precharge time t RP TBD -- 40 -- 50 -- ns CAS precharge time t CP TBD -- 10 -- 10 -- ns RAS pulse width t RAS TBD TBD 60 10000 70 10000 ns CAS pulse width t CAS TBD TBD 15 10000 18 10000 ns Row address setup time t ASR TBD -- 0 -- 0 -- ns Row address hold time t RAH TBD -- 10 -- 10 -- ns Column address setup time t ASC TBD -- 0 -- 0 -- ns Column address hold time t CAH TBD -- 10 -- 15 -- ns RAS to CAS delay time t RCD TBD TBD 20 45 20 52 ns 3 RAS to column address delay time t RAD TBD TBD 15 30 15 35 ns 4 RAS hold time t RSH TBD -- 15 -- 18 -- ns CAS hold time t CSH TBD -- 60 -- 70 -- ns CAS to RAS precharge time t CRP TBD -- 5 -- 5 -- ns OE to Din delay time t OED TBD -- 15 -- 18 -- ns 5 OE delay time from Din t DZO TBD -- 0 -- 0 -- ns 6 CAS delay time from Din t DZC TBD -- 0 -- 0 -- ns 6 Transition time (rise and fall) tT TBD TBD 3 50 3 50 ns 7 11 HM5164800A Series, HM5165800A Series Read Cycle HM5164800A/HM5165800A -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC -- TBD -- 60 -- 70 ns 8, 9 Access time from CAS t CAC -- TBD -- 15 -- 18 ns 9, 10, 16 Access time from address t AA -- TBD -- 30 -- 35 ns 9, 11, 16 Access time from OE t OEA -- TBD -- 15 -- 18 ns 9, 19 Read command setup time t RCS TBD -- 0 -- 0 -- ns Read command hold time to CAS t RCH TBD -- 0 -- 0 - ns 12 Read command hold time to RAS t RRH TBD -- 5 -- 5 -- ns 12 Column address to RAS lead time t RAL TBD -- 30 -- 35 -- ns Column address to CAS lead time t CAL TBD -- 30 -- 35 -- ns CAS to output in low-Z t CLZ TBD -- 0 -- 0 -- ns Output data hold time t OH TBD -- 3 -- 3 -- ns Output data hold time from OE t OHO TBD -- 3 -- 3 -- ns Output buffer turn-off time t OFF -- TBD -- 15 -- 15 ns 13 Output buffer turn-off to OE t OEZ -- TBD -- 15 -- 15 ns 13 CAS to Din delay time t CDD TBD -- 15 -- 18 -- ns 5 Write Cycle HM5164800A/HM5165800A -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS TBD -- 0 -- 0 -- ns Write command hold time t WCH TBD -- 10 -- 15 -- ns Write command pulse width t WP TBD -- 10 -- 10 -- ns Write command to RAS lead time t RWL TBD -- 15 -- 18 -- ns Write command to CAS lead time t CWL TBD -- 15 -- 18 -- ns Data-in setup time t DS TBD -- 0 -- 0 -- ns Data-in hold time t DH TBD -- 10 -- 15 -- ns 14 12 HM5164800A Series, HM5165800A Series Read-Modify-Write Cycle HM5164800A/HM5165800A -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC TBD -- 155 -- 181 -- ns RAS to WE delay time t RWD TBD -- 85 -- 98 -- ns 14 CAS to WE delay time t CWD TBD -- 40 -- 46 -- ns 14 Column address to WE delay time t AWD TBD -- 55 -- 63 -- ns 14 OE hold time from WE t OEH TBD -- 15 -- 18 -- ns Refresh Cycle HM5164800A/HM5165800A -5 Parameter Symbol Min -6 -7 Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR TBD -- 5 -- 5 -- ns CAS hold time (CBR refresh cycle) t CHR TBD -- 10 -- 10 -- ns WE setup time (CBR refresh cycle) t WRP TBD -- 0 -- 0 -- ns WE hold time (CBR refresh cycle) t WRH TBD -- 10 -- 10 -- ns RAS precharge to CAS hold time t RPC TBD -- 0 -- 0 -- ns Fast Page Mode Cycle HM5164800A/HM5165800A -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC TBD -- 40 -- 45 -- ns Fast page mode RAS pulse width t RASP -- TBD -- 100000 -- 100000 ns 15 Access time from CAS precharge t CPA -- TBD -- 35 -- 40 ns 9, 16 TBD -- 35 -- 40 -- ns RAS hold time from CAS precharge t CPRH 13 HM5164800A Series, HM5165800A Series Fast Page Mode Read-Modify-Write Cycle HM5164800A/HM5165800A -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write cycle time t PRWC TBD -- 85 -- 96 -- ns TBD -- 60 -- 68 -- ns WE delay time from CAS precharge t CPW 14 Refresh (HM5164800A Series) Parameter Symbol Max Unit Note Refresh period t REF 64 ms 8192 cycles Refresh period (L-version) t REF 128 ms 4096 cycles Parameter Symbol Max Unit Note Refresh period t REF 64 ms 4096 cycles Refresh period (L-version) t REF 128 ms 4096 cycles Refresh (HM5165800A Series) Self Refresh Mode (L-version) HM5164800AL/HM5165800AL -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes RAS pulse width (Self refresh) t RASS TBD -- 100 -- 100 -- s RAS precharge time (Self refresh) t RPS TBD -- 110 -- 130 -- ns CAS hold time (Self refresh) t CHS TBD -- -50 -- -50 -- ns 20 Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 14 HM5164800A Series, HM5165800A Series 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t RASP defines RAS pulse width in fast page mode cycles. 16. Access time is determined by the longest among t AA , t CAC and t CPA. 17. All the V CC and VSS pins shall be supplied with the same voltages. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 20. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use t RPS instead of tRP. 21. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into the self refresh mode. 22. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 23. XXX: H or L (H: V IH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL. 15 HM5164800A Series, HM5165800A Series Timing Waveforms*23 Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH t RAL t ASC t CAL t CAH Column Row t RRH t RCH t RCS WE t DZC t CDD High-Z Din t DZO t OEA t OED OE t OEZ t CAC t OHO t AA t OFF t RAC t CLZ Dout t OH Dout 16 HM5164800A Series, HM5165800A Series Early Write Cycle t RC t RP t RAS RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH WE t DS Din Dout t DH Din High-Z* * t WCS 17 t WCS (min) HM5164800A Series, HM5165800A Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t RAH t ASC Row t CAH Column t CWL t RWL t WP t RCS WE t DZC Din t DS High-Z t DH Din t DZO t OEH t OED OE t OEZ t CLZ High-Z Dout Invalid Dout 18 HM5164800A Series, HM5165800A Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR Address tRAH t ASC Row t CAH Column t RCS t CWD tCWL t AWD t RWL t RWD t WP WE t DZC t DH t DS High-Z Din Din t OED t DZO t OEH t OEA OE t CAC t OEZ t AA t RAC t OHO Dout Dout t CLZ 19 High-Z HM5164800A Series, HM5165800A Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP t RPC t CRP CAS t ASR Address t RAH Row t OFF High-Z Dout CAS-Before-RAS Refresh Cycle t RC t RAS t RP t RP RAS t RPC t CSR t CHR t RPC t CRP tT CAS t CP t WRP t WRH t CP WE Address t OFF Dout High-Z 20 HM5164800A Series, HM5165800A Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t RRH t RCH t RCS WE t DZC t CDD High-Z Din t DZO t OED t OEA OE t CAC t OEZ t OHO t AA t RAC t OFF t OH t CLZ Dout 21 Dout HM5164800A Series, HM5165800A Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CRP t CAS CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH t CAL t ASC t CAH t CAL t ASC t CAH Column 1 Column 2 Column N t RCS tRCS tRCH t RCS t RRH t RCH tRCH WE t DZC t DZC t CDD High-Z High-Z t CDD High-Z , Din t DZC t CDD t DZO t OED t DZO t OED t DZO t OED OE t RAC t AA t OH t OEA t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N 22 HM5164800A Series, HM5165800A Series Fast Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH Address Row t ASC t CAH t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS 23 t WCS (min) HM5164800A Series, HM5165800A Series Fast Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CP t CSH t RCD t CRP t CP t PC t CAS t RSH t CAS t CAS CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din Din 2 t DZO Din N t DZO # t DZO t DH t OED t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout Invalid Dout Invalid Dout 24 HM5164800A Series, HM5165800A Series Fast Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL Column N t CPW t AWD t CWL t AWD t CWD t RCS t CPW t AWD t RCS t CWD t CWL t RWL t CWD WE t RCS t WP t t DZC DS t WP t t DZC DS t WP t t DZC DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OED t DZO t OEH t OEH *# t OEH Din N OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t OEZ t CLZ t OHO t OEA t CAC t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 25 Dout 2 Dout N HM5164800A Series, HM5165800A Series Self Refresh Cycle (L-version)* 20, 21, 22 t RASS t RP t RPS RAS , tT $%*+, t RPC t CP t CSR t CRP t CHS CAS t WRP t WRH WE t OFF Dout High-Z 26 HM5164800A Series, HM5165800A Series Package Dimensions HM5164800AJ/ALJ Series HM5165800AJ/ALJ Series (CP-32DC) 0.43 +0.07 -0.04 2.55 0.64 Min +0.25 -0.24 1.27 0.10 27 11.18 16 0.74 3.50 1 +0.12 -0.13 17 10.16 0.12 32 20.95 21.38 Max Unit: mm 9.40 0.25 HM5164800A Series, HM5165800A Series HM5164800ATT/ALTT Series HM5165800ATT/ALTT Series (TTP-32DC) Unit: mm 20.95 21.35 Max 17 10.16 32 1 1.27 16 11.76 0.20 0 - 5 0.68 0.10 0.08 Min 0.18 Max M +0.03 -0.02 0.20 0.145 1.20 Max 0.42 +0.08 -0.07 1.15 Max 0.50 0.10 28 HM5164800A Series, HM5165800A Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 29 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 HM5164800A Series, HM5165800A Series Revision Record Rev. Date Contents of Modification 0.0 Jun. 3, 1996 Initial issue Drawn by Approved by 30